1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/notifier.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/spinlock.h>
16
17 /* EIC registers definition */
18 #define SPRD_EIC_DBNC_DATA 0x0
19 #define SPRD_EIC_DBNC_DMSK 0x4
20 #define SPRD_EIC_DBNC_IEV 0x14
21 #define SPRD_EIC_DBNC_IE 0x18
22 #define SPRD_EIC_DBNC_RIS 0x1c
23 #define SPRD_EIC_DBNC_MIS 0x20
24 #define SPRD_EIC_DBNC_IC 0x24
25 #define SPRD_EIC_DBNC_TRIG 0x28
26 #define SPRD_EIC_DBNC_CTRL0 0x40
27
28 #define SPRD_EIC_LATCH_INTEN 0x0
29 #define SPRD_EIC_LATCH_INTRAW 0x4
30 #define SPRD_EIC_LATCH_INTMSK 0x8
31 #define SPRD_EIC_LATCH_INTCLR 0xc
32 #define SPRD_EIC_LATCH_INTPOL 0x10
33 #define SPRD_EIC_LATCH_INTMODE 0x14
34
35 #define SPRD_EIC_ASYNC_INTIE 0x0
36 #define SPRD_EIC_ASYNC_INTRAW 0x4
37 #define SPRD_EIC_ASYNC_INTMSK 0x8
38 #define SPRD_EIC_ASYNC_INTCLR 0xc
39 #define SPRD_EIC_ASYNC_INTMODE 0x10
40 #define SPRD_EIC_ASYNC_INTBOTH 0x14
41 #define SPRD_EIC_ASYNC_INTPOL 0x18
42 #define SPRD_EIC_ASYNC_DATA 0x1c
43
44 #define SPRD_EIC_SYNC_INTIE 0x0
45 #define SPRD_EIC_SYNC_INTRAW 0x4
46 #define SPRD_EIC_SYNC_INTMSK 0x8
47 #define SPRD_EIC_SYNC_INTCLR 0xc
48 #define SPRD_EIC_SYNC_INTMODE 0x10
49 #define SPRD_EIC_SYNC_INTBOTH 0x14
50 #define SPRD_EIC_SYNC_INTPOL 0x18
51 #define SPRD_EIC_SYNC_DATA 0x1c
52
53 /*
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
55 * contains 8 EICs.
56 */
57 #define SPRD_EIC_MAX_BANK 3
58 #define SPRD_EIC_PER_BANK_NR 8
59 #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
61 #define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
62
63 /*
64 * The Spreadtrum EIC (external interrupt controller) can be used only in
65 * input mode to generate interrupts if detecting input signals.
66 *
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
69 *
70 * The debounce EIC is used to capture the input signals' stable status
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
73 * The debounce range is from 1ms to 4s with a step size of 1ms.
74 *
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
77 * to capture signals.
78 *
79 * The async EIC uses a 32k clock to capture the short signals (microsecond
80 * resolution) to generate interrupts by level or edge trigger.
81 *
82 * The EIC-sync is similar with GPIO's input function, which is a synchronized
83 * signal input register.
84 */
85 enum sprd_eic_type {
86 SPRD_EIC_DEBOUNCE,
87 SPRD_EIC_LATCH,
88 SPRD_EIC_ASYNC,
89 SPRD_EIC_SYNC,
90 SPRD_EIC_MAX,
91 };
92
93 struct sprd_eic {
94 struct gpio_chip chip;
95 struct notifier_block irq_nb;
96 void __iomem *base[SPRD_EIC_MAX_BANK];
97 enum sprd_eic_type type;
98 spinlock_t lock;
99 int irq;
100 };
101
102 static ATOMIC_NOTIFIER_HEAD(sprd_eic_irq_notifier);
103
to_sprd_eic(struct notifier_block * nb)104 static struct sprd_eic *to_sprd_eic(struct notifier_block *nb)
105 {
106 return container_of(nb, struct sprd_eic, irq_nb);
107 }
108
109 struct sprd_eic_variant_data {
110 enum sprd_eic_type type;
111 };
112
113 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
114 "eic-debounce", "eic-latch", "eic-async",
115 "eic-sync",
116 };
117
118 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
119 .type = SPRD_EIC_DEBOUNCE,
120 };
121
122 static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
123 .type = SPRD_EIC_LATCH,
124 };
125
126 static const struct sprd_eic_variant_data sc9860_eic_async_data = {
127 .type = SPRD_EIC_ASYNC,
128 };
129
130 static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
131 .type = SPRD_EIC_SYNC,
132 };
133
sprd_eic_offset_base(struct sprd_eic * sprd_eic,unsigned int bank)134 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
135 unsigned int bank)
136 {
137 if (bank >= SPRD_EIC_MAX_BANK)
138 return NULL;
139
140 return sprd_eic->base[bank];
141 }
142
sprd_eic_update(struct gpio_chip * chip,unsigned int offset,u16 reg,unsigned int val)143 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
144 u16 reg, unsigned int val)
145 {
146 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
147 void __iomem *base =
148 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
149 unsigned long flags;
150 u32 tmp;
151
152 spin_lock_irqsave(&sprd_eic->lock, flags);
153 tmp = readl_relaxed(base + reg);
154
155 if (val)
156 tmp |= BIT(SPRD_EIC_BIT(offset));
157 else
158 tmp &= ~BIT(SPRD_EIC_BIT(offset));
159
160 writel_relaxed(tmp, base + reg);
161 spin_unlock_irqrestore(&sprd_eic->lock, flags);
162 }
163
sprd_eic_read(struct gpio_chip * chip,unsigned int offset,u16 reg)164 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
165 {
166 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
167 void __iomem *base =
168 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
169
170 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
171 }
172
sprd_eic_request(struct gpio_chip * chip,unsigned int offset)173 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
174 {
175 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
176 return 0;
177 }
178
sprd_eic_free(struct gpio_chip * chip,unsigned int offset)179 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
180 {
181 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
182 }
183
sprd_eic_get(struct gpio_chip * chip,unsigned int offset)184 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
185 {
186 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
187
188 switch (sprd_eic->type) {
189 case SPRD_EIC_DEBOUNCE:
190 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
191 case SPRD_EIC_ASYNC:
192 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
193 case SPRD_EIC_SYNC:
194 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
195 default:
196 return -ENOTSUPP;
197 }
198 }
199
sprd_eic_direction_input(struct gpio_chip * chip,unsigned int offset)200 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
201 {
202 /* EICs are always input, nothing need to do here. */
203 return 0;
204 }
205
sprd_eic_set(struct gpio_chip * chip,unsigned int offset,int value)206 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
207 {
208 /* EICs are always input, nothing need to do here. */
209 }
210
sprd_eic_set_debounce(struct gpio_chip * chip,unsigned int offset,unsigned int debounce)211 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
212 unsigned int debounce)
213 {
214 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
215 void __iomem *base =
216 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
217 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
218 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
219
220 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
221 writel_relaxed(value, base + reg);
222
223 return 0;
224 }
225
sprd_eic_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)226 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
227 unsigned long config)
228 {
229 unsigned long param = pinconf_to_config_param(config);
230 u32 arg = pinconf_to_config_argument(config);
231
232 if (param == PIN_CONFIG_INPUT_DEBOUNCE)
233 return sprd_eic_set_debounce(chip, offset, arg);
234
235 return -ENOTSUPP;
236 }
237
sprd_eic_irq_mask(struct irq_data * data)238 static void sprd_eic_irq_mask(struct irq_data *data)
239 {
240 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
241 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
242 u32 offset = irqd_to_hwirq(data);
243
244 switch (sprd_eic->type) {
245 case SPRD_EIC_DEBOUNCE:
246 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
247 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
248 break;
249 case SPRD_EIC_LATCH:
250 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
251 break;
252 case SPRD_EIC_ASYNC:
253 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
254 break;
255 case SPRD_EIC_SYNC:
256 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
257 break;
258 default:
259 dev_err(chip->parent, "Unsupported EIC type.\n");
260 }
261
262 gpiochip_disable_irq(chip, offset);
263 }
264
sprd_eic_irq_unmask(struct irq_data * data)265 static void sprd_eic_irq_unmask(struct irq_data *data)
266 {
267 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
268 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
269 u32 offset = irqd_to_hwirq(data);
270
271 gpiochip_enable_irq(chip, offset);
272
273 switch (sprd_eic->type) {
274 case SPRD_EIC_DEBOUNCE:
275 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
276 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
277 break;
278 case SPRD_EIC_LATCH:
279 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
280 break;
281 case SPRD_EIC_ASYNC:
282 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
283 break;
284 case SPRD_EIC_SYNC:
285 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
286 break;
287 default:
288 dev_err(chip->parent, "Unsupported EIC type.\n");
289 }
290 }
291
sprd_eic_irq_ack(struct irq_data * data)292 static void sprd_eic_irq_ack(struct irq_data *data)
293 {
294 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
295 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
296 u32 offset = irqd_to_hwirq(data);
297
298 switch (sprd_eic->type) {
299 case SPRD_EIC_DEBOUNCE:
300 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
301 break;
302 case SPRD_EIC_LATCH:
303 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
304 break;
305 case SPRD_EIC_ASYNC:
306 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
307 break;
308 case SPRD_EIC_SYNC:
309 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
310 break;
311 default:
312 dev_err(chip->parent, "Unsupported EIC type.\n");
313 }
314 }
315
sprd_eic_irq_set_type(struct irq_data * data,unsigned int flow_type)316 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
317 {
318 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
319 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
320 u32 offset = irqd_to_hwirq(data);
321 int state;
322
323 switch (sprd_eic->type) {
324 case SPRD_EIC_DEBOUNCE:
325 switch (flow_type) {
326 case IRQ_TYPE_LEVEL_HIGH:
327 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
328 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
329 break;
330 case IRQ_TYPE_LEVEL_LOW:
331 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
332 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
333 break;
334 case IRQ_TYPE_EDGE_RISING:
335 case IRQ_TYPE_EDGE_FALLING:
336 case IRQ_TYPE_EDGE_BOTH:
337 state = sprd_eic_get(chip, offset);
338 if (state) {
339 sprd_eic_update(chip, offset,
340 SPRD_EIC_DBNC_IEV, 0);
341 sprd_eic_update(chip, offset,
342 SPRD_EIC_DBNC_IC, 1);
343 } else {
344 sprd_eic_update(chip, offset,
345 SPRD_EIC_DBNC_IEV, 1);
346 sprd_eic_update(chip, offset,
347 SPRD_EIC_DBNC_IC, 1);
348 }
349 break;
350 default:
351 return -ENOTSUPP;
352 }
353
354 irq_set_handler_locked(data, handle_level_irq);
355 break;
356 case SPRD_EIC_LATCH:
357 switch (flow_type) {
358 case IRQ_TYPE_LEVEL_HIGH:
359 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
360 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
361 break;
362 case IRQ_TYPE_LEVEL_LOW:
363 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
364 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
365 break;
366 case IRQ_TYPE_EDGE_RISING:
367 case IRQ_TYPE_EDGE_FALLING:
368 case IRQ_TYPE_EDGE_BOTH:
369 state = sprd_eic_get(chip, offset);
370 if (state) {
371 sprd_eic_update(chip, offset,
372 SPRD_EIC_LATCH_INTPOL, 0);
373 sprd_eic_update(chip, offset,
374 SPRD_EIC_LATCH_INTCLR, 1);
375 } else {
376 sprd_eic_update(chip, offset,
377 SPRD_EIC_LATCH_INTPOL, 1);
378 sprd_eic_update(chip, offset,
379 SPRD_EIC_LATCH_INTCLR, 1);
380 }
381 break;
382 default:
383 return -ENOTSUPP;
384 }
385
386 irq_set_handler_locked(data, handle_level_irq);
387 break;
388 case SPRD_EIC_ASYNC:
389 switch (flow_type) {
390 case IRQ_TYPE_EDGE_RISING:
391 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
392 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
395 irq_set_handler_locked(data, handle_edge_irq);
396 break;
397 case IRQ_TYPE_EDGE_FALLING:
398 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
400 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
401 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
402 irq_set_handler_locked(data, handle_edge_irq);
403 break;
404 case IRQ_TYPE_EDGE_BOTH:
405 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
408 irq_set_handler_locked(data, handle_edge_irq);
409 break;
410 case IRQ_TYPE_LEVEL_HIGH:
411 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
413 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
415 irq_set_handler_locked(data, handle_level_irq);
416 break;
417 case IRQ_TYPE_LEVEL_LOW:
418 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
419 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
420 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
421 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
422 irq_set_handler_locked(data, handle_level_irq);
423 break;
424 default:
425 return -ENOTSUPP;
426 }
427 break;
428 case SPRD_EIC_SYNC:
429 switch (flow_type) {
430 case IRQ_TYPE_EDGE_RISING:
431 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
432 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
433 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
435 irq_set_handler_locked(data, handle_edge_irq);
436 break;
437 case IRQ_TYPE_EDGE_FALLING:
438 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
440 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
441 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
442 irq_set_handler_locked(data, handle_edge_irq);
443 break;
444 case IRQ_TYPE_EDGE_BOTH:
445 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
448 irq_set_handler_locked(data, handle_edge_irq);
449 break;
450 case IRQ_TYPE_LEVEL_HIGH:
451 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
453 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
455 irq_set_handler_locked(data, handle_level_irq);
456 break;
457 case IRQ_TYPE_LEVEL_LOW:
458 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
459 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
460 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
461 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
462 irq_set_handler_locked(data, handle_level_irq);
463 break;
464 default:
465 return -ENOTSUPP;
466 }
467 break;
468 default:
469 dev_err(chip->parent, "Unsupported EIC type.\n");
470 return -ENOTSUPP;
471 }
472
473 return 0;
474 }
475
sprd_eic_toggle_trigger(struct gpio_chip * chip,unsigned int irq,unsigned int offset)476 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
477 unsigned int offset)
478 {
479 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
480 struct irq_data *data = irq_get_irq_data(irq);
481 u32 trigger = irqd_get_trigger_type(data);
482 int state, post_state;
483
484 /*
485 * The debounce EIC and latch EIC can only support level trigger, so we
486 * can toggle the level trigger to emulate the edge trigger.
487 */
488 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
489 sprd_eic->type != SPRD_EIC_LATCH) ||
490 !(trigger & IRQ_TYPE_EDGE_BOTH))
491 return;
492
493 sprd_eic_irq_mask(data);
494 state = sprd_eic_get(chip, offset);
495
496 retry:
497 switch (sprd_eic->type) {
498 case SPRD_EIC_DEBOUNCE:
499 if (state)
500 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
501 else
502 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
503 break;
504 case SPRD_EIC_LATCH:
505 if (state)
506 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
507 else
508 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
509 break;
510 default:
511 sprd_eic_irq_unmask(data);
512 return;
513 }
514
515 post_state = sprd_eic_get(chip, offset);
516 if (state != post_state) {
517 dev_warn(chip->parent, "EIC level was changed.\n");
518 state = post_state;
519 goto retry;
520 }
521
522 sprd_eic_irq_unmask(data);
523 }
524
sprd_eic_handle_one_type(struct gpio_chip * chip)525 static void sprd_eic_handle_one_type(struct gpio_chip *chip)
526 {
527 struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
528 u32 bank, n, girq;
529
530 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
531 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
532 unsigned long reg;
533
534 switch (sprd_eic->type) {
535 case SPRD_EIC_DEBOUNCE:
536 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
537 SPRD_EIC_DATA_MASK;
538 break;
539 case SPRD_EIC_LATCH:
540 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
541 SPRD_EIC_DATA_MASK;
542 break;
543 case SPRD_EIC_ASYNC:
544 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
545 SPRD_EIC_DATA_MASK;
546 break;
547 case SPRD_EIC_SYNC:
548 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
549 SPRD_EIC_DATA_MASK;
550 break;
551 default:
552 dev_err(chip->parent, "Unsupported EIC type.\n");
553 return;
554 }
555
556 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) {
557 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
558
559 girq = irq_find_mapping(chip->irq.domain, offset);
560
561 generic_handle_irq(girq);
562 sprd_eic_toggle_trigger(chip, girq, offset);
563 }
564 }
565 }
566
sprd_eic_irq_handler(struct irq_desc * desc)567 static void sprd_eic_irq_handler(struct irq_desc *desc)
568 {
569 struct irq_chip *ic = irq_desc_get_chip(desc);
570
571 chained_irq_enter(ic, desc);
572
573 /*
574 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
575 * and sync) share one same interrupt line, we should notify all of
576 * them to let them check if there are EIC interrupts were triggered.
577 */
578 atomic_notifier_call_chain(&sprd_eic_irq_notifier, 0, NULL);
579
580 chained_irq_exit(ic, desc);
581 }
582
sprd_eic_irq_notify(struct notifier_block * nb,unsigned long action,void * data)583 static int sprd_eic_irq_notify(struct notifier_block *nb, unsigned long action,
584 void *data)
585 {
586 struct sprd_eic *sprd_eic = to_sprd_eic(nb);
587
588 sprd_eic_handle_one_type(&sprd_eic->chip);
589
590 return NOTIFY_OK;
591 }
592
593 static const struct irq_chip sprd_eic_irq = {
594 .name = "sprd-eic",
595 .irq_ack = sprd_eic_irq_ack,
596 .irq_mask = sprd_eic_irq_mask,
597 .irq_unmask = sprd_eic_irq_unmask,
598 .irq_set_type = sprd_eic_irq_set_type,
599 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
600 GPIOCHIP_IRQ_RESOURCE_HELPERS,
601 };
602
sprd_eic_unregister_notifier(void * data)603 static void sprd_eic_unregister_notifier(void *data)
604 {
605 struct notifier_block *nb = data;
606
607 atomic_notifier_chain_unregister(&sprd_eic_irq_notifier, nb);
608 }
609
sprd_eic_probe(struct platform_device * pdev)610 static int sprd_eic_probe(struct platform_device *pdev)
611 {
612 const struct sprd_eic_variant_data *pdata;
613 struct device *dev = &pdev->dev;
614 struct gpio_irq_chip *irq;
615 struct sprd_eic *sprd_eic;
616 struct resource *res;
617 u16 num_banks = 0;
618 int ret, i;
619
620 pdata = of_device_get_match_data(dev);
621 if (!pdata) {
622 dev_err(dev, "No matching driver data found.\n");
623 return -EINVAL;
624 }
625
626 sprd_eic = devm_kzalloc(dev, sizeof(*sprd_eic), GFP_KERNEL);
627 if (!sprd_eic)
628 return -ENOMEM;
629
630 spin_lock_init(&sprd_eic->lock);
631 sprd_eic->type = pdata->type;
632
633 sprd_eic->irq = platform_get_irq(pdev, 0);
634 if (sprd_eic->irq < 0)
635 return sprd_eic->irq;
636
637 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
638 /*
639 * We can have maximum 3 banks EICs, and each EIC has
640 * its own base address. But some platform maybe only
641 * have one bank EIC, thus base[1] and base[2] can be
642 * optional.
643 */
644 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
645 if (!res)
646 break;
647
648 sprd_eic->base[i] = devm_ioremap_resource(dev, res);
649 if (IS_ERR(sprd_eic->base[i]))
650 return PTR_ERR(sprd_eic->base[i]);
651
652 num_banks++;
653 }
654
655 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
656 sprd_eic->chip.ngpio = num_banks * SPRD_EIC_PER_BANK_NR;
657 sprd_eic->chip.base = -1;
658 sprd_eic->chip.parent = dev;
659 sprd_eic->chip.direction_input = sprd_eic_direction_input;
660 switch (sprd_eic->type) {
661 case SPRD_EIC_DEBOUNCE:
662 sprd_eic->chip.request = sprd_eic_request;
663 sprd_eic->chip.free = sprd_eic_free;
664 sprd_eic->chip.set_config = sprd_eic_set_config;
665 sprd_eic->chip.set = sprd_eic_set;
666 fallthrough;
667 case SPRD_EIC_ASYNC:
668 case SPRD_EIC_SYNC:
669 sprd_eic->chip.get = sprd_eic_get;
670 break;
671 case SPRD_EIC_LATCH:
672 default:
673 break;
674 }
675
676 irq = &sprd_eic->chip.irq;
677 gpio_irq_chip_set_chip(irq, &sprd_eic_irq);
678 irq->handler = handle_bad_irq;
679 irq->default_type = IRQ_TYPE_NONE;
680 irq->parent_handler = sprd_eic_irq_handler;
681 irq->parent_handler_data = sprd_eic;
682 irq->num_parents = 1;
683 irq->parents = &sprd_eic->irq;
684
685 ret = devm_gpiochip_add_data(dev, &sprd_eic->chip, sprd_eic);
686 if (ret < 0) {
687 dev_err(dev, "Could not register gpiochip %d.\n", ret);
688 return ret;
689 }
690
691 sprd_eic->irq_nb.notifier_call = sprd_eic_irq_notify;
692 ret = atomic_notifier_chain_register(&sprd_eic_irq_notifier,
693 &sprd_eic->irq_nb);
694 if (ret)
695 return dev_err_probe(dev, ret,
696 "Failed to register with the interrupt notifier");
697
698 return devm_add_action_or_reset(dev, sprd_eic_unregister_notifier,
699 &sprd_eic->irq_nb);
700 }
701
702 static const struct of_device_id sprd_eic_of_match[] = {
703 {
704 .compatible = "sprd,sc9860-eic-debounce",
705 .data = &sc9860_eic_dbnc_data,
706 },
707 {
708 .compatible = "sprd,sc9860-eic-latch",
709 .data = &sc9860_eic_latch_data,
710 },
711 {
712 .compatible = "sprd,sc9860-eic-async",
713 .data = &sc9860_eic_async_data,
714 },
715 {
716 .compatible = "sprd,sc9860-eic-sync",
717 .data = &sc9860_eic_sync_data,
718 },
719 {
720 /* end of list */
721 }
722 };
723 MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
724
725 static struct platform_driver sprd_eic_driver = {
726 .probe = sprd_eic_probe,
727 .driver = {
728 .name = "sprd-eic",
729 .of_match_table = sprd_eic_of_match,
730 },
731 };
732
733 module_platform_driver(sprd_eic_driver);
734
735 MODULE_DESCRIPTION("Spreadtrum EIC driver");
736 MODULE_LICENSE("GPL v2");
737