1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Spreadtrum divider clock driver
4 //
5 // Copyright (C) 2017 Spreadtrum, Inc.
6 // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7
8 #include <linux/clk-provider.h>
9
10 #include "div.h"
11
sprd_div_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)12 static int sprd_div_determine_rate(struct clk_hw *hw,
13 struct clk_rate_request *req)
14 {
15 struct sprd_div *cd = hw_to_sprd_div(hw);
16
17 req->rate = divider_round_rate(&cd->common.hw, req->rate,
18 &req->best_parent_rate,
19 NULL, cd->div.width, 0);
20
21 return 0;
22 }
23
sprd_div_helper_recalc_rate(struct sprd_clk_common * common,const struct sprd_div_internal * div,unsigned long parent_rate)24 unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
25 const struct sprd_div_internal *div,
26 unsigned long parent_rate)
27 {
28 unsigned long val;
29 unsigned int reg;
30
31 regmap_read(common->regmap, common->reg + div->offset, ®);
32 val = reg >> div->shift;
33 val &= (1 << div->width) - 1;
34
35 return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0,
36 div->width);
37 }
38 EXPORT_SYMBOL_GPL(sprd_div_helper_recalc_rate);
39
sprd_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)40 static unsigned long sprd_div_recalc_rate(struct clk_hw *hw,
41 unsigned long parent_rate)
42 {
43 struct sprd_div *cd = hw_to_sprd_div(hw);
44
45 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate);
46 }
47
sprd_div_helper_set_rate(const struct sprd_clk_common * common,const struct sprd_div_internal * div,unsigned long rate,unsigned long parent_rate)48 int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
49 const struct sprd_div_internal *div,
50 unsigned long rate,
51 unsigned long parent_rate)
52 {
53 unsigned long val;
54 unsigned int reg;
55
56 val = divider_get_val(rate, parent_rate, NULL,
57 div->width, 0);
58
59 regmap_read(common->regmap, common->reg + div->offset, ®);
60 reg &= ~GENMASK(div->width + div->shift - 1, div->shift);
61
62 regmap_write(common->regmap, common->reg + div->offset,
63 reg | (val << div->shift));
64
65 return 0;
66
67 }
68 EXPORT_SYMBOL_GPL(sprd_div_helper_set_rate);
69
sprd_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)70 static int sprd_div_set_rate(struct clk_hw *hw, unsigned long rate,
71 unsigned long parent_rate)
72 {
73 struct sprd_div *cd = hw_to_sprd_div(hw);
74
75 return sprd_div_helper_set_rate(&cd->common, &cd->div,
76 rate, parent_rate);
77 }
78
79 const struct clk_ops sprd_div_ops = {
80 .recalc_rate = sprd_div_recalc_rate,
81 .determine_rate = sprd_div_determine_rate,
82 .set_rate = sprd_div_set_rate,
83 };
84 EXPORT_SYMBOL_GPL(sprd_div_ops);
85