xref: /linux/drivers/pinctrl/spear/pinctrl-spear320.c (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 /*
2  * Driver for the ST Microelectronics SPEAr320 pinmux
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Viresh Kumar <vireshk@kernel.org>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/platform_device.h>
16 #include "pinctrl-spear3xx.h"
17 
18 #define DRIVER_NAME "spear320-pinmux"
19 
20 /* addresses */
21 #define PMX_CONFIG_REG			0x0C
22 #define MODE_CONFIG_REG			0x10
23 #define MODE_EXT_CONFIG_REG		0x18
24 
25 /* modes */
26 #define AUTO_NET_SMII_MODE	(1 << 0)
27 #define AUTO_NET_MII_MODE	(1 << 1)
28 #define AUTO_EXP_MODE		(1 << 2)
29 #define SMALL_PRINTERS_MODE	(1 << 3)
30 #define EXTENDED_MODE		(1 << 4)
31 
32 static struct spear_pmx_mode pmx_mode_auto_net_smii = {
33 	.name = "Automation Networking SMII mode",
34 	.mode = AUTO_NET_SMII_MODE,
35 	.reg = MODE_CONFIG_REG,
36 	.mask = 0x00000007,
37 	.val = 0x0,
38 };
39 
40 static struct spear_pmx_mode pmx_mode_auto_net_mii = {
41 	.name = "Automation Networking MII mode",
42 	.mode = AUTO_NET_MII_MODE,
43 	.reg = MODE_CONFIG_REG,
44 	.mask = 0x00000007,
45 	.val = 0x1,
46 };
47 
48 static struct spear_pmx_mode pmx_mode_auto_exp = {
49 	.name = "Automation Expanded mode",
50 	.mode = AUTO_EXP_MODE,
51 	.reg = MODE_CONFIG_REG,
52 	.mask = 0x00000007,
53 	.val = 0x2,
54 };
55 
56 static struct spear_pmx_mode pmx_mode_small_printers = {
57 	.name = "Small Printers mode",
58 	.mode = SMALL_PRINTERS_MODE,
59 	.reg = MODE_CONFIG_REG,
60 	.mask = 0x00000007,
61 	.val = 0x3,
62 };
63 
64 static struct spear_pmx_mode pmx_mode_extended = {
65 	.name = "extended mode",
66 	.mode = EXTENDED_MODE,
67 	.reg = MODE_EXT_CONFIG_REG,
68 	.mask = 0x00000001,
69 	.val = 0x1,
70 };
71 
72 static struct spear_pmx_mode *spear320_pmx_modes[] = {
73 	&pmx_mode_auto_net_smii,
74 	&pmx_mode_auto_net_mii,
75 	&pmx_mode_auto_exp,
76 	&pmx_mode_small_printers,
77 	&pmx_mode_extended,
78 };
79 
80 /* Extended mode registers and their offsets */
81 #define EXT_CTRL_REG				0x0018
82 	#define MII_MDIO_MASK			(1 << 4)
83 	#define MII_MDIO_10_11_VAL		0
84 	#define MII_MDIO_81_VAL			(1 << 4)
85 	#define EMI_FSMC_DYNAMIC_MUX_MASK	(1 << 5)
86 	#define MAC_MODE_MII			0
87 	#define MAC_MODE_RMII			1
88 	#define MAC_MODE_SMII			2
89 	#define MAC_MODE_SS_SMII		3
90 	#define MAC_MODE_MASK			0x3
91 	#define MAC1_MODE_SHIFT			16
92 	#define MAC2_MODE_SHIFT			18
93 
94 #define IP_SEL_PAD_0_9_REG			0x00A4
95 	#define PMX_PL_0_1_MASK			(0x3F << 0)
96 	#define PMX_UART2_PL_0_1_VAL		0x0
97 	#define PMX_I2C2_PL_0_1_VAL		(0x4 | (0x4 << 3))
98 
99 	#define PMX_PL_2_3_MASK			(0x3F << 6)
100 	#define PMX_I2C2_PL_2_3_VAL		0x0
101 	#define PMX_UART6_PL_2_3_VAL		((0x1 << 6) | (0x1 << 9))
102 	#define PMX_UART1_ENH_PL_2_3_VAL	((0x4 << 6) | (0x4 << 9))
103 
104 	#define PMX_PL_4_5_MASK			(0x3F << 12)
105 	#define PMX_UART5_PL_4_5_VAL		((0x1 << 12) | (0x1 << 15))
106 	#define PMX_UART1_ENH_PL_4_5_VAL	((0x4 << 12) | (0x4 << 15))
107 	#define PMX_PL_5_MASK			(0x7 << 15)
108 	#define PMX_TOUCH_Y_PL_5_VAL		0x0
109 
110 	#define PMX_PL_6_7_MASK			(0x3F << 18)
111 	#define PMX_PL_6_MASK			(0x7 << 18)
112 	#define PMX_PL_7_MASK			(0x7 << 21)
113 	#define PMX_UART4_PL_6_7_VAL		((0x1 << 18) | (0x1 << 21))
114 	#define PMX_PWM_3_PL_6_VAL		(0x2 << 18)
115 	#define PMX_PWM_2_PL_7_VAL		(0x2 << 21)
116 	#define PMX_UART1_ENH_PL_6_7_VAL	((0x4 << 18) | (0x4 << 21))
117 
118 	#define PMX_PL_8_9_MASK			(0x3F << 24)
119 	#define PMX_UART3_PL_8_9_VAL		((0x1 << 24) | (0x1 << 27))
120 	#define PMX_PWM_0_1_PL_8_9_VAL		((0x2 << 24) | (0x2 << 27))
121 	#define PMX_I2C1_PL_8_9_VAL		((0x4 << 24) | (0x4 << 27))
122 
123 #define IP_SEL_PAD_10_19_REG			0x00A8
124 	#define PMX_PL_10_11_MASK		(0x3F << 0)
125 	#define PMX_SMII_PL_10_11_VAL		0
126 	#define PMX_RMII_PL_10_11_VAL		((0x4 << 0) | (0x4 << 3))
127 
128 	#define PMX_PL_12_MASK			(0x7 << 6)
129 	#define PMX_PWM3_PL_12_VAL		0
130 	#define PMX_SDHCI_CD_PL_12_VAL		(0x4 << 6)
131 
132 	#define PMX_PL_13_14_MASK		(0x3F << 9)
133 	#define PMX_PL_13_MASK			(0x7 << 9)
134 	#define PMX_PL_14_MASK			(0x7 << 12)
135 	#define PMX_SSP2_PL_13_14_15_16_VAL	0
136 	#define PMX_UART4_PL_13_14_VAL		((0x1 << 9) | (0x1 << 12))
137 	#define PMX_RMII_PL_13_14_VAL		((0x4 << 9) | (0x4 << 12))
138 	#define PMX_PWM2_PL_13_VAL		(0x2 << 9)
139 	#define PMX_PWM1_PL_14_VAL		(0x2 << 12)
140 
141 	#define PMX_PL_15_MASK			(0x7 << 15)
142 	#define PMX_PWM0_PL_15_VAL		(0x2 << 15)
143 	#define PMX_PL_15_16_MASK		(0x3F << 15)
144 	#define PMX_UART3_PL_15_16_VAL		((0x1 << 15) | (0x1 << 18))
145 	#define PMX_RMII_PL_15_16_VAL		((0x4 << 15) | (0x4 << 18))
146 
147 	#define PMX_PL_17_18_MASK		(0x3F << 21)
148 	#define PMX_SSP1_PL_17_18_19_20_VAL	0
149 	#define PMX_RMII_PL_17_18_VAL		((0x4 << 21) | (0x4 << 24))
150 
151 	#define PMX_PL_19_MASK			(0x7 << 27)
152 	#define PMX_I2C2_PL_19_VAL		(0x1 << 27)
153 	#define PMX_RMII_PL_19_VAL		(0x4 << 27)
154 
155 #define IP_SEL_PAD_20_29_REG			0x00AC
156 	#define PMX_PL_20_MASK			(0x7 << 0)
157 	#define PMX_I2C2_PL_20_VAL		(0x1 << 0)
158 	#define PMX_RMII_PL_20_VAL		(0x4 << 0)
159 
160 	#define PMX_PL_21_TO_27_MASK		(0x1FFFFF << 3)
161 	#define PMX_SMII_PL_21_TO_27_VAL	0
162 	#define PMX_RMII_PL_21_TO_27_VAL	((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
163 
164 	#define PMX_PL_28_29_MASK		(0x3F << 24)
165 	#define PMX_PL_28_MASK			(0x7 << 24)
166 	#define PMX_PL_29_MASK			(0x7 << 27)
167 	#define PMX_UART1_PL_28_29_VAL		0
168 	#define PMX_PWM_3_PL_28_VAL		(0x4 << 24)
169 	#define PMX_PWM_2_PL_29_VAL		(0x4 << 27)
170 
171 #define IP_SEL_PAD_30_39_REG			0x00B0
172 	#define PMX_PL_30_31_MASK		(0x3F << 0)
173 	#define PMX_CAN1_PL_30_31_VAL		(0)
174 	#define PMX_PL_30_MASK			(0x7 << 0)
175 	#define PMX_PL_31_MASK			(0x7 << 3)
176 	#define PMX_PWM1_EXT_PL_30_VAL		(0x4 << 0)
177 	#define PMX_PWM0_EXT_PL_31_VAL		(0x4 << 3)
178 	#define PMX_UART1_ENH_PL_31_VAL		(0x3 << 3)
179 
180 	#define PMX_PL_32_33_MASK		(0x3F << 6)
181 	#define PMX_CAN0_PL_32_33_VAL		0
182 	#define PMX_UART1_ENH_PL_32_33_VAL	((0x3 << 6) | (0x3 << 9))
183 	#define PMX_SSP2_PL_32_33_VAL		((0x4 << 6) | (0x4 << 9))
184 
185 	#define PMX_PL_34_MASK			(0x7 << 12)
186 	#define PMX_PWM2_PL_34_VAL		0
187 	#define PMX_UART1_ENH_PL_34_VAL		(0x2 << 12)
188 	#define PMX_SSP2_PL_34_VAL		(0x4 << 12)
189 
190 	#define PMX_PL_35_MASK			(0x7 << 15)
191 	#define PMX_I2S_REF_CLK_PL_35_VAL	0
192 	#define PMX_UART1_ENH_PL_35_VAL		(0x2 << 15)
193 	#define PMX_SSP2_PL_35_VAL		(0x4 << 15)
194 
195 	#define PMX_PL_36_MASK			(0x7 << 18)
196 	#define PMX_TOUCH_X_PL_36_VAL		0
197 	#define PMX_UART1_ENH_PL_36_VAL		(0x2 << 18)
198 	#define PMX_SSP1_PL_36_VAL		(0x4 << 18)
199 
200 	#define PMX_PL_37_38_MASK		(0x3F << 21)
201 	#define PMX_PWM0_1_PL_37_38_VAL		0
202 	#define PMX_UART5_PL_37_38_VAL		((0x2 << 21) | (0x2 << 24))
203 	#define PMX_SSP1_PL_37_38_VAL		((0x4 << 21) | (0x4 << 24))
204 
205 	#define PMX_PL_39_MASK			(0x7 << 27)
206 	#define PMX_I2S_PL_39_VAL		0
207 	#define PMX_UART4_PL_39_VAL		(0x2 << 27)
208 	#define PMX_SSP1_PL_39_VAL		(0x4 << 27)
209 
210 #define IP_SEL_PAD_40_49_REG			0x00B4
211 	#define PMX_PL_40_MASK			(0x7 << 0)
212 	#define PMX_I2S_PL_40_VAL		0
213 	#define PMX_UART4_PL_40_VAL		(0x2 << 0)
214 	#define PMX_PWM3_PL_40_VAL		(0x4 << 0)
215 
216 	#define PMX_PL_41_42_MASK		(0x3F << 3)
217 	#define PMX_PL_41_MASK			(0x7 << 3)
218 	#define PMX_PL_42_MASK			(0x7 << 6)
219 	#define PMX_I2S_PL_41_42_VAL		0
220 	#define PMX_UART3_PL_41_42_VAL		((0x2 << 3) | (0x2 << 6))
221 	#define PMX_PWM2_PL_41_VAL		(0x4 << 3)
222 	#define PMX_PWM1_PL_42_VAL		(0x4 << 6)
223 
224 	#define PMX_PL_43_MASK			(0x7 << 9)
225 	#define PMX_SDHCI_PL_43_VAL		0
226 	#define PMX_UART1_ENH_PL_43_VAL		(0x2 << 9)
227 	#define PMX_PWM0_PL_43_VAL		(0x4 << 9)
228 
229 	#define PMX_PL_44_45_MASK		(0x3F << 12)
230 	#define PMX_SDHCI_PL_44_45_VAL	0
231 	#define PMX_UART1_ENH_PL_44_45_VAL	((0x2 << 12) | (0x2 << 15))
232 	#define PMX_SSP2_PL_44_45_VAL		((0x4 << 12) | (0x4 << 15))
233 
234 	#define PMX_PL_46_47_MASK		(0x3F << 18)
235 	#define PMX_SDHCI_PL_46_47_VAL	0
236 	#define PMX_FSMC_EMI_PL_46_47_VAL	((0x2 << 18) | (0x2 << 21))
237 	#define PMX_SSP2_PL_46_47_VAL		((0x4 << 18) | (0x4 << 21))
238 
239 	#define PMX_PL_48_49_MASK		(0x3F << 24)
240 	#define PMX_SDHCI_PL_48_49_VAL	0
241 	#define PMX_FSMC_EMI_PL_48_49_VAL	((0x2 << 24) | (0x2 << 27))
242 	#define PMX_SSP1_PL_48_49_VAL		((0x4 << 24) | (0x4 << 27))
243 
244 #define IP_SEL_PAD_50_59_REG			0x00B8
245 	#define PMX_PL_50_51_MASK		(0x3F << 0)
246 	#define PMX_EMI_PL_50_51_VAL		((0x2 << 0) | (0x2 << 3))
247 	#define PMX_SSP1_PL_50_51_VAL		((0x4 << 0) | (0x4 << 3))
248 	#define PMX_PL_50_MASK			(0x7 << 0)
249 	#define PMX_PL_51_MASK			(0x7 << 3)
250 	#define PMX_SDHCI_PL_50_VAL		0
251 	#define PMX_SDHCI_CD_PL_51_VAL		0
252 
253 	#define PMX_PL_52_53_MASK		(0x3F << 6)
254 	#define PMX_FSMC_PL_52_53_VAL		0
255 	#define PMX_EMI_PL_52_53_VAL		((0x2 << 6) | (0x2 << 9))
256 	#define PMX_UART3_PL_52_53_VAL		((0x4 << 6) | (0x4 << 9))
257 
258 	#define PMX_PL_54_55_56_MASK		(0x1FF << 12)
259 	#define PMX_FSMC_EMI_PL_54_55_56_VAL	((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
260 
261 	#define PMX_PL_57_MASK			(0x7 << 21)
262 	#define PMX_FSMC_PL_57_VAL		0
263 	#define PMX_PWM3_PL_57_VAL		(0x4 << 21)
264 
265 	#define PMX_PL_58_59_MASK		(0x3F << 24)
266 	#define PMX_PL_58_MASK			(0x7 << 24)
267 	#define PMX_PL_59_MASK			(0x7 << 27)
268 	#define PMX_FSMC_EMI_PL_58_59_VAL	((0x2 << 24) | (0x2 << 27))
269 	#define PMX_PWM2_PL_58_VAL		(0x4 << 24)
270 	#define PMX_PWM1_PL_59_VAL		(0x4 << 27)
271 
272 #define IP_SEL_PAD_60_69_REG			0x00BC
273 	#define PMX_PL_60_MASK			(0x7 << 0)
274 	#define PMX_FSMC_PL_60_VAL		0
275 	#define PMX_PWM0_PL_60_VAL		(0x4 << 0)
276 
277 	#define PMX_PL_61_TO_64_MASK		(0xFFF << 3)
278 	#define PMX_FSMC_PL_61_TO_64_VAL	((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
279 	#define PMX_SSP2_PL_61_TO_64_VAL	((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
280 
281 	#define PMX_PL_65_TO_68_MASK		(0xFFF << 15)
282 	#define PMX_FSMC_PL_65_TO_68_VAL	((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
283 	#define PMX_SSP1_PL_65_TO_68_VAL	((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
284 
285 	#define PMX_PL_69_MASK			(0x7 << 27)
286 	#define PMX_CLCD_PL_69_VAL		(0)
287 	#define PMX_EMI_PL_69_VAL		(0x2 << 27)
288 	#define PMX_SPP_PL_69_VAL		(0x3 << 27)
289 	#define PMX_UART5_PL_69_VAL		(0x4 << 27)
290 
291 #define IP_SEL_PAD_70_79_REG			0x00C0
292 	#define PMX_PL_70_MASK			(0x7 << 0)
293 	#define PMX_CLCD_PL_70_VAL		(0)
294 	#define PMX_FSMC_EMI_PL_70_VAL		(0x2 << 0)
295 	#define PMX_SPP_PL_70_VAL		(0x3 << 0)
296 	#define PMX_UART5_PL_70_VAL		(0x4 << 0)
297 
298 	#define PMX_PL_71_72_MASK		(0x3F << 3)
299 	#define PMX_CLCD_PL_71_72_VAL		(0)
300 	#define PMX_FSMC_EMI_PL_71_72_VAL	((0x2 << 3) | (0x2 << 6))
301 	#define PMX_SPP_PL_71_72_VAL		((0x3 << 3) | (0x3 << 6))
302 	#define PMX_UART4_PL_71_72_VAL		((0x4 << 3) | (0x4 << 6))
303 
304 	#define PMX_PL_73_MASK			(0x7 << 9)
305 	#define PMX_CLCD_PL_73_VAL		(0)
306 	#define PMX_FSMC_EMI_PL_73_VAL		(0x2 << 9)
307 	#define PMX_SPP_PL_73_VAL		(0x3 << 9)
308 	#define PMX_UART3_PL_73_VAL		(0x4 << 9)
309 
310 	#define PMX_PL_74_MASK			(0x7 << 12)
311 	#define PMX_CLCD_PL_74_VAL		(0)
312 	#define PMX_EMI_PL_74_VAL		(0x2 << 12)
313 	#define PMX_SPP_PL_74_VAL		(0x3 << 12)
314 	#define PMX_UART3_PL_74_VAL		(0x4 << 12)
315 
316 	#define PMX_PL_75_76_MASK		(0x3F << 15)
317 	#define PMX_CLCD_PL_75_76_VAL		(0)
318 	#define PMX_EMI_PL_75_76_VAL		((0x2 << 15) | (0x2 << 18))
319 	#define PMX_SPP_PL_75_76_VAL		((0x3 << 15) | (0x3 << 18))
320 	#define PMX_I2C2_PL_75_76_VAL		((0x4 << 15) | (0x4 << 18))
321 
322 	#define PMX_PL_77_78_79_MASK		(0x1FF << 21)
323 	#define PMX_CLCD_PL_77_78_79_VAL	(0)
324 	#define PMX_EMI_PL_77_78_79_VAL		((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
325 	#define PMX_SPP_PL_77_78_79_VAL		((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
326 	#define PMX_RS485_PL_77_78_79_VAL	((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
327 
328 #define IP_SEL_PAD_80_89_REG			0x00C4
329 	#define PMX_PL_80_TO_85_MASK		(0x3FFFF << 0)
330 	#define PMX_CLCD_PL_80_TO_85_VAL	0
331 	#define PMX_MII2_PL_80_TO_85_VAL	((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
332 	#define PMX_EMI_PL_80_TO_85_VAL		((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
333 	#define PMX_SPP_PL_80_TO_85_VAL		((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
334 	#define PMX_UART1_ENH_PL_80_TO_85_VAL	((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
335 
336 	#define PMX_PL_86_87_MASK		(0x3F << 18)
337 	#define PMX_PL_86_MASK			(0x7 << 18)
338 	#define PMX_PL_87_MASK			(0x7 << 21)
339 	#define PMX_CLCD_PL_86_87_VAL		0
340 	#define PMX_MII2_PL_86_87_VAL		((0x1 << 18) | (0x1 << 21))
341 	#define PMX_EMI_PL_86_87_VAL		((0x2 << 18) | (0x2 << 21))
342 	#define PMX_PWM3_PL_86_VAL		(0x4 << 18)
343 	#define PMX_PWM2_PL_87_VAL		(0x4 << 21)
344 
345 	#define PMX_PL_88_89_MASK		(0x3F << 24)
346 	#define PMX_CLCD_PL_88_89_VAL		0
347 	#define PMX_MII2_PL_88_89_VAL		((0x1 << 24) | (0x1 << 27))
348 	#define PMX_EMI_PL_88_89_VAL		((0x2 << 24) | (0x2 << 27))
349 	#define PMX_UART6_PL_88_89_VAL		((0x3 << 24) | (0x3 << 27))
350 	#define PMX_PWM0_1_PL_88_89_VAL		((0x4 << 24) | (0x4 << 27))
351 
352 #define IP_SEL_PAD_90_99_REG			0x00C8
353 	#define PMX_PL_90_91_MASK		(0x3F << 0)
354 	#define PMX_CLCD_PL_90_91_VAL		0
355 	#define PMX_MII2_PL_90_91_VAL		((0x1 << 0) | (0x1 << 3))
356 	#define PMX_EMI1_PL_90_91_VAL		((0x2 << 0) | (0x2 << 3))
357 	#define PMX_UART5_PL_90_91_VAL		((0x3 << 0) | (0x3 << 3))
358 	#define PMX_SSP2_PL_90_91_VAL		((0x4 << 0) | (0x4 << 3))
359 
360 	#define PMX_PL_92_93_MASK		(0x3F << 6)
361 	#define PMX_CLCD_PL_92_93_VAL		0
362 	#define PMX_MII2_PL_92_93_VAL		((0x1 << 6) | (0x1 << 9))
363 	#define PMX_EMI1_PL_92_93_VAL		((0x2 << 6) | (0x2 << 9))
364 	#define PMX_UART4_PL_92_93_VAL		((0x3 << 6) | (0x3 << 9))
365 	#define PMX_SSP2_PL_92_93_VAL		((0x4 << 6) | (0x4 << 9))
366 
367 	#define PMX_PL_94_95_MASK		(0x3F << 12)
368 	#define PMX_CLCD_PL_94_95_VAL		0
369 	#define PMX_MII2_PL_94_95_VAL		((0x1 << 12) | (0x1 << 15))
370 	#define PMX_EMI1_PL_94_95_VAL		((0x2 << 12) | (0x2 << 15))
371 	#define PMX_UART3_PL_94_95_VAL		((0x3 << 12) | (0x3 << 15))
372 	#define PMX_SSP1_PL_94_95_VAL		((0x4 << 12) | (0x4 << 15))
373 
374 	#define PMX_PL_96_97_MASK		(0x3F << 18)
375 	#define PMX_CLCD_PL_96_97_VAL		0
376 	#define PMX_MII2_PL_96_97_VAL		((0x1 << 18) | (0x1 << 21))
377 	#define PMX_EMI1_PL_96_97_VAL		((0x2 << 18) | (0x2 << 21))
378 	#define PMX_I2C2_PL_96_97_VAL		((0x3 << 18) | (0x3 << 21))
379 	#define PMX_SSP1_PL_96_97_VAL		((0x4 << 18) | (0x4 << 21))
380 
381 	#define PMX_PL_98_MASK			(0x7 << 24)
382 	#define PMX_CLCD_PL_98_VAL		0
383 	#define PMX_I2C1_PL_98_VAL		(0x2 << 24)
384 	#define PMX_UART3_PL_98_VAL		(0x4 << 24)
385 
386 	#define PMX_PL_99_MASK			(0x7 << 27)
387 	#define PMX_SDHCI_PL_99_VAL		0
388 	#define PMX_I2C1_PL_99_VAL		(0x2 << 27)
389 	#define PMX_UART3_PL_99_VAL		(0x4 << 27)
390 
391 #define IP_SEL_MIX_PAD_REG			0x00CC
392 	#define PMX_PL_100_101_MASK		(0x3F << 0)
393 	#define PMX_SDHCI_PL_100_101_VAL	0
394 	#define PMX_UART4_PL_100_101_VAL	((0x4 << 0) | (0x4 << 3))
395 
396 	#define PMX_SSP1_PORT_SEL_MASK		(0x7 << 8)
397 	#define PMX_SSP1_PORT_94_TO_97_VAL	0
398 	#define PMX_SSP1_PORT_65_TO_68_VAL	(0x1 << 8)
399 	#define PMX_SSP1_PORT_48_TO_51_VAL	(0x2 << 8)
400 	#define PMX_SSP1_PORT_36_TO_39_VAL	(0x3 << 8)
401 	#define PMX_SSP1_PORT_17_TO_20_VAL	(0x4 << 8)
402 
403 	#define PMX_SSP2_PORT_SEL_MASK		(0x7 << 11)
404 	#define PMX_SSP2_PORT_90_TO_93_VAL	0
405 	#define PMX_SSP2_PORT_61_TO_64_VAL	(0x1 << 11)
406 	#define PMX_SSP2_PORT_44_TO_47_VAL	(0x2 << 11)
407 	#define PMX_SSP2_PORT_32_TO_35_VAL	(0x3 << 11)
408 	#define PMX_SSP2_PORT_13_TO_16_VAL	(0x4 << 11)
409 
410 	#define PMX_UART1_ENH_PORT_SEL_MASK		(0x3 << 14)
411 	#define PMX_UART1_ENH_PORT_81_TO_85_VAL		0
412 	#define PMX_UART1_ENH_PORT_44_45_34_36_VAL	(0x1 << 14)
413 	#define PMX_UART1_ENH_PORT_32_TO_34_36_VAL	(0x2 << 14)
414 	#define PMX_UART1_ENH_PORT_3_TO_5_7_VAL		(0x3 << 14)
415 
416 	#define PMX_UART3_PORT_SEL_MASK		(0x7 << 16)
417 	#define PMX_UART3_PORT_94_VAL		0
418 	#define PMX_UART3_PORT_73_VAL		(0x1 << 16)
419 	#define PMX_UART3_PORT_52_VAL		(0x2 << 16)
420 	#define PMX_UART3_PORT_41_VAL		(0x3 << 16)
421 	#define PMX_UART3_PORT_15_VAL		(0x4 << 16)
422 	#define PMX_UART3_PORT_8_VAL		(0x5 << 16)
423 	#define PMX_UART3_PORT_99_VAL		(0x6 << 16)
424 
425 	#define PMX_UART4_PORT_SEL_MASK		(0x7 << 19)
426 	#define PMX_UART4_PORT_92_VAL		0
427 	#define PMX_UART4_PORT_71_VAL		(0x1 << 19)
428 	#define PMX_UART4_PORT_39_VAL		(0x2 << 19)
429 	#define PMX_UART4_PORT_13_VAL		(0x3 << 19)
430 	#define PMX_UART4_PORT_6_VAL		(0x4 << 19)
431 	#define PMX_UART4_PORT_101_VAL		(0x5 << 19)
432 
433 	#define PMX_UART5_PORT_SEL_MASK		(0x3 << 22)
434 	#define PMX_UART5_PORT_90_VAL		0
435 	#define PMX_UART5_PORT_69_VAL		(0x1 << 22)
436 	#define PMX_UART5_PORT_37_VAL		(0x2 << 22)
437 	#define PMX_UART5_PORT_4_VAL		(0x3 << 22)
438 
439 	#define PMX_UART6_PORT_SEL_MASK		(0x1 << 24)
440 	#define PMX_UART6_PORT_88_VAL		0
441 	#define PMX_UART6_PORT_2_VAL		(0x1 << 24)
442 
443 	#define PMX_I2C1_PORT_SEL_MASK		(0x1 << 25)
444 	#define PMX_I2C1_PORT_8_9_VAL		0
445 	#define PMX_I2C1_PORT_98_99_VAL		(0x1 << 25)
446 
447 	#define PMX_I2C2_PORT_SEL_MASK		(0x3 << 26)
448 	#define PMX_I2C2_PORT_96_97_VAL		0
449 	#define PMX_I2C2_PORT_75_76_VAL		(0x1 << 26)
450 	#define PMX_I2C2_PORT_19_20_VAL		(0x2 << 26)
451 	#define PMX_I2C2_PORT_2_3_VAL		(0x3 << 26)
452 	#define PMX_I2C2_PORT_0_1_VAL		(0x4 << 26)
453 
454 	#define PMX_SDHCI_CD_PORT_SEL_MASK	(0x1 << 29)
455 	#define PMX_SDHCI_CD_PORT_12_VAL	0
456 	#define PMX_SDHCI_CD_PORT_51_VAL	(0x1 << 29)
457 
458 /* Pad multiplexing for CLCD device */
459 static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
460 	79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
461 	97 };
462 static struct spear_muxreg clcd_muxreg[] = {
463 	{
464 		.reg = IP_SEL_PAD_60_69_REG,
465 		.mask = PMX_PL_69_MASK,
466 		.val = PMX_CLCD_PL_69_VAL,
467 	}, {
468 		.reg = IP_SEL_PAD_70_79_REG,
469 		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
470 			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
471 			PMX_PL_77_78_79_MASK,
472 		.val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
473 			PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
474 			PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
475 	}, {
476 		.reg = IP_SEL_PAD_80_89_REG,
477 		.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
478 			PMX_PL_88_89_MASK,
479 		.val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
480 			PMX_CLCD_PL_88_89_VAL,
481 	}, {
482 		.reg = IP_SEL_PAD_90_99_REG,
483 		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
484 			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
485 		.val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
486 			PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
487 			PMX_CLCD_PL_98_VAL,
488 	},
489 };
490 
491 static struct spear_modemux clcd_modemux[] = {
492 	{
493 		.modes = EXTENDED_MODE,
494 		.muxregs = clcd_muxreg,
495 		.nmuxregs = ARRAY_SIZE(clcd_muxreg),
496 	},
497 };
498 
499 static struct spear_pingroup clcd_pingroup = {
500 	.name = "clcd_grp",
501 	.pins = clcd_pins,
502 	.npins = ARRAY_SIZE(clcd_pins),
503 	.modemuxs = clcd_modemux,
504 	.nmodemuxs = ARRAY_SIZE(clcd_modemux),
505 };
506 
507 static const char *const clcd_grps[] = { "clcd_grp" };
508 static struct spear_function clcd_function = {
509 	.name = "clcd",
510 	.groups = clcd_grps,
511 	.ngroups = ARRAY_SIZE(clcd_grps),
512 };
513 
514 /* Pad multiplexing for EMI (Parallel NOR flash) device */
515 static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
516 	57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
517 	75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
518 	93, 94, 95, 96, 97 };
519 static struct spear_muxreg emi_muxreg[] = {
520 	{
521 		.reg = PMX_CONFIG_REG,
522 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
523 		.val = 0,
524 	},
525 };
526 
527 static struct spear_muxreg emi_ext_muxreg[] = {
528 	{
529 		.reg = IP_SEL_PAD_40_49_REG,
530 		.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
531 		.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
532 	}, {
533 		.reg = IP_SEL_PAD_50_59_REG,
534 		.mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
535 			PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
536 		.val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
537 			PMX_FSMC_EMI_PL_54_55_56_VAL |
538 			PMX_FSMC_EMI_PL_58_59_VAL,
539 	}, {
540 		.reg = IP_SEL_PAD_60_69_REG,
541 		.mask = PMX_PL_69_MASK,
542 		.val = PMX_EMI_PL_69_VAL,
543 	}, {
544 		.reg = IP_SEL_PAD_70_79_REG,
545 		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
546 			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
547 			PMX_PL_77_78_79_MASK,
548 		.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
549 			PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
550 			PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
551 	}, {
552 		.reg = IP_SEL_PAD_80_89_REG,
553 		.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
554 			PMX_PL_88_89_MASK,
555 		.val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
556 			PMX_EMI_PL_88_89_VAL,
557 	}, {
558 		.reg = IP_SEL_PAD_90_99_REG,
559 		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
560 			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
561 		.val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
562 			PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
563 	}, {
564 		.reg = EXT_CTRL_REG,
565 		.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
566 		.val = EMI_FSMC_DYNAMIC_MUX_MASK,
567 	},
568 };
569 
570 static struct spear_modemux emi_modemux[] = {
571 	{
572 		.modes = AUTO_EXP_MODE | EXTENDED_MODE,
573 		.muxregs = emi_muxreg,
574 		.nmuxregs = ARRAY_SIZE(emi_muxreg),
575 	}, {
576 		.modes = EXTENDED_MODE,
577 		.muxregs = emi_ext_muxreg,
578 		.nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
579 	},
580 };
581 
582 static struct spear_pingroup emi_pingroup = {
583 	.name = "emi_grp",
584 	.pins = emi_pins,
585 	.npins = ARRAY_SIZE(emi_pins),
586 	.modemuxs = emi_modemux,
587 	.nmodemuxs = ARRAY_SIZE(emi_modemux),
588 };
589 
590 static const char *const emi_grps[] = { "emi_grp" };
591 static struct spear_function emi_function = {
592 	.name = "emi",
593 	.groups = emi_grps,
594 	.ngroups = ARRAY_SIZE(emi_grps),
595 };
596 
597 /* Pad multiplexing for FSMC (NAND flash) device */
598 static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
599 	61, 62, 63, 64, 65, 66, 67, 68 };
600 static struct spear_muxreg fsmc_8bit_muxreg[] = {
601 	{
602 		.reg = IP_SEL_PAD_50_59_REG,
603 		.mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
604 			PMX_PL_57_MASK | PMX_PL_58_59_MASK,
605 		.val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
606 			PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
607 	}, {
608 		.reg = IP_SEL_PAD_60_69_REG,
609 		.mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
610 			PMX_PL_65_TO_68_MASK,
611 		.val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
612 			PMX_FSMC_PL_65_TO_68_VAL,
613 	}, {
614 		.reg = EXT_CTRL_REG,
615 		.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
616 		.val = EMI_FSMC_DYNAMIC_MUX_MASK,
617 	},
618 };
619 
620 static struct spear_modemux fsmc_8bit_modemux[] = {
621 	{
622 		.modes = EXTENDED_MODE,
623 		.muxregs = fsmc_8bit_muxreg,
624 		.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
625 	},
626 };
627 
628 static struct spear_pingroup fsmc_8bit_pingroup = {
629 	.name = "fsmc_8bit_grp",
630 	.pins = fsmc_8bit_pins,
631 	.npins = ARRAY_SIZE(fsmc_8bit_pins),
632 	.modemuxs = fsmc_8bit_modemux,
633 	.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
634 };
635 
636 static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
637 	57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
638 static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
639 	{
640 		.reg = PMX_CONFIG_REG,
641 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
642 		.val = 0,
643 	},
644 };
645 
646 static struct spear_muxreg fsmc_16bit_muxreg[] = {
647 	{
648 		.reg = IP_SEL_PAD_40_49_REG,
649 		.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
650 		.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
651 	}, {
652 		.reg = IP_SEL_PAD_70_79_REG,
653 		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
654 		.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
655 			PMX_FSMC_EMI_PL_73_VAL,
656 	}
657 };
658 
659 static struct spear_modemux fsmc_16bit_modemux[] = {
660 	{
661 		.modes = EXTENDED_MODE,
662 		.muxregs = fsmc_8bit_muxreg,
663 		.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
664 	}, {
665 		.modes = AUTO_EXP_MODE | EXTENDED_MODE,
666 		.muxregs = fsmc_16bit_autoexp_muxreg,
667 		.nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
668 	}, {
669 		.modes = EXTENDED_MODE,
670 		.muxregs = fsmc_16bit_muxreg,
671 		.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
672 	},
673 };
674 
675 static struct spear_pingroup fsmc_16bit_pingroup = {
676 	.name = "fsmc_16bit_grp",
677 	.pins = fsmc_16bit_pins,
678 	.npins = ARRAY_SIZE(fsmc_16bit_pins),
679 	.modemuxs = fsmc_16bit_modemux,
680 	.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
681 };
682 
683 static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
684 static struct spear_function fsmc_function = {
685 	.name = "fsmc",
686 	.groups = fsmc_grps,
687 	.ngroups = ARRAY_SIZE(fsmc_grps),
688 };
689 
690 /* Pad multiplexing for SPP device */
691 static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
692 	80, 81, 82, 83, 84, 85 };
693 static struct spear_muxreg spp_muxreg[] = {
694 	{
695 		.reg = IP_SEL_PAD_60_69_REG,
696 		.mask = PMX_PL_69_MASK,
697 		.val = PMX_SPP_PL_69_VAL,
698 	}, {
699 		.reg = IP_SEL_PAD_70_79_REG,
700 		.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
701 			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
702 			PMX_PL_77_78_79_MASK,
703 		.val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
704 			PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
705 			PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
706 	}, {
707 		.reg = IP_SEL_PAD_80_89_REG,
708 		.mask = PMX_PL_80_TO_85_MASK,
709 		.val = PMX_SPP_PL_80_TO_85_VAL,
710 	},
711 };
712 
713 static struct spear_modemux spp_modemux[] = {
714 	{
715 		.modes = EXTENDED_MODE,
716 		.muxregs = spp_muxreg,
717 		.nmuxregs = ARRAY_SIZE(spp_muxreg),
718 	},
719 };
720 
721 static struct spear_pingroup spp_pingroup = {
722 	.name = "spp_grp",
723 	.pins = spp_pins,
724 	.npins = ARRAY_SIZE(spp_pins),
725 	.modemuxs = spp_modemux,
726 	.nmodemuxs = ARRAY_SIZE(spp_modemux),
727 };
728 
729 static const char *const spp_grps[] = { "spp_grp" };
730 static struct spear_function spp_function = {
731 	.name = "spp",
732 	.groups = spp_grps,
733 	.ngroups = ARRAY_SIZE(spp_grps),
734 };
735 
736 /* Pad multiplexing for SDHCI device */
737 static const unsigned sdhci_led_pins[] = { 34 };
738 static struct spear_muxreg sdhci_led_muxreg[] = {
739 	{
740 		.reg = PMX_CONFIG_REG,
741 		.mask = PMX_SSP_CS_MASK,
742 		.val = 0,
743 	},
744 };
745 
746 static struct spear_muxreg sdhci_led_ext_muxreg[] = {
747 	{
748 		.reg = IP_SEL_PAD_30_39_REG,
749 		.mask = PMX_PL_34_MASK,
750 		.val = PMX_PWM2_PL_34_VAL,
751 	},
752 };
753 
754 static struct spear_modemux sdhci_led_modemux[] = {
755 	{
756 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
757 		.muxregs = sdhci_led_muxreg,
758 		.nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
759 	}, {
760 		.modes = EXTENDED_MODE,
761 		.muxregs = sdhci_led_ext_muxreg,
762 		.nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
763 	},
764 };
765 
766 static struct spear_pingroup sdhci_led_pingroup = {
767 	.name = "sdhci_led_grp",
768 	.pins = sdhci_led_pins,
769 	.npins = ARRAY_SIZE(sdhci_led_pins),
770 	.modemuxs = sdhci_led_modemux,
771 	.nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
772 };
773 
774 static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
775 	50};
776 static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
777 };
778 static struct spear_muxreg sdhci_muxreg[] = {
779 	{
780 		.reg = PMX_CONFIG_REG,
781 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
782 		.val = 0,
783 	},
784 };
785 
786 static struct spear_muxreg sdhci_ext_muxreg[] = {
787 	{
788 		.reg = IP_SEL_PAD_40_49_REG,
789 		.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
790 			PMX_PL_48_49_MASK,
791 		.val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
792 			PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
793 	}, {
794 		.reg = IP_SEL_PAD_50_59_REG,
795 		.mask = PMX_PL_50_MASK,
796 		.val = PMX_SDHCI_PL_50_VAL,
797 	}, {
798 		.reg = IP_SEL_PAD_90_99_REG,
799 		.mask = PMX_PL_99_MASK,
800 		.val = PMX_SDHCI_PL_99_VAL,
801 	}, {
802 		.reg = IP_SEL_MIX_PAD_REG,
803 		.mask = PMX_PL_100_101_MASK,
804 		.val = PMX_SDHCI_PL_100_101_VAL,
805 	},
806 };
807 
808 static struct spear_muxreg sdhci_cd_12_muxreg[] = {
809 	{
810 		.reg = PMX_CONFIG_REG,
811 		.mask = PMX_MII_MASK,
812 		.val = 0,
813 	}, {
814 		.reg = IP_SEL_PAD_10_19_REG,
815 		.mask = PMX_PL_12_MASK,
816 		.val = PMX_SDHCI_CD_PL_12_VAL,
817 	}, {
818 		.reg = IP_SEL_MIX_PAD_REG,
819 		.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
820 		.val = PMX_SDHCI_CD_PORT_12_VAL,
821 	},
822 };
823 
824 static struct spear_muxreg sdhci_cd_51_muxreg[] = {
825 	{
826 		.reg = IP_SEL_PAD_50_59_REG,
827 		.mask = PMX_PL_51_MASK,
828 		.val = PMX_SDHCI_CD_PL_51_VAL,
829 	}, {
830 		.reg = IP_SEL_MIX_PAD_REG,
831 		.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
832 		.val = PMX_SDHCI_CD_PORT_51_VAL,
833 	},
834 };
835 
836 #define pmx_sdhci_common_modemux					\
837 	{								\
838 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |	\
839 			SMALL_PRINTERS_MODE | EXTENDED_MODE,		\
840 		.muxregs = sdhci_muxreg,				\
841 		.nmuxregs = ARRAY_SIZE(sdhci_muxreg),			\
842 	}, {								\
843 		.modes = EXTENDED_MODE,					\
844 		.muxregs = sdhci_ext_muxreg,				\
845 		.nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg),		\
846 	}
847 
848 static struct spear_modemux sdhci_modemux[][3] = {
849 	{
850 		/* select pin 12 for cd */
851 		pmx_sdhci_common_modemux,
852 		{
853 			.modes = EXTENDED_MODE,
854 			.muxregs = sdhci_cd_12_muxreg,
855 			.nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
856 		},
857 	}, {
858 		/* select pin 51 for cd */
859 		pmx_sdhci_common_modemux,
860 		{
861 			.modes = EXTENDED_MODE,
862 			.muxregs = sdhci_cd_51_muxreg,
863 			.nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
864 		},
865 	}
866 };
867 
868 static struct spear_pingroup sdhci_pingroup[] = {
869 	{
870 		.name = "sdhci_cd_12_grp",
871 		.pins = sdhci_cd_12_pins,
872 		.npins = ARRAY_SIZE(sdhci_cd_12_pins),
873 		.modemuxs = sdhci_modemux[0],
874 		.nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
875 	}, {
876 		.name = "sdhci_cd_51_grp",
877 		.pins = sdhci_cd_51_pins,
878 		.npins = ARRAY_SIZE(sdhci_cd_51_pins),
879 		.modemuxs = sdhci_modemux[1],
880 		.nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
881 	},
882 };
883 
884 static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
885 	"sdhci_led_grp" };
886 
887 static struct spear_function sdhci_function = {
888 	.name = "sdhci",
889 	.groups = sdhci_grps,
890 	.ngroups = ARRAY_SIZE(sdhci_grps),
891 };
892 
893 /* Pad multiplexing for I2S device */
894 static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
895 static struct spear_muxreg i2s_muxreg[] = {
896 	{
897 		.reg = PMX_CONFIG_REG,
898 		.mask = PMX_SSP_CS_MASK,
899 		.val = 0,
900 	}, {
901 		.reg = PMX_CONFIG_REG,
902 		.mask = PMX_UART0_MODEM_MASK,
903 		.val = 0,
904 	},
905 };
906 
907 static struct spear_muxreg i2s_ext_muxreg[] = {
908 	{
909 		.reg = IP_SEL_PAD_30_39_REG,
910 		.mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
911 		.val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
912 	}, {
913 		.reg = IP_SEL_PAD_40_49_REG,
914 		.mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
915 		.val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
916 	},
917 };
918 
919 static struct spear_modemux i2s_modemux[] = {
920 	{
921 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
922 		.muxregs = i2s_muxreg,
923 		.nmuxregs = ARRAY_SIZE(i2s_muxreg),
924 	}, {
925 		.modes = EXTENDED_MODE,
926 		.muxregs = i2s_ext_muxreg,
927 		.nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
928 	},
929 };
930 
931 static struct spear_pingroup i2s_pingroup = {
932 	.name = "i2s_grp",
933 	.pins = i2s_pins,
934 	.npins = ARRAY_SIZE(i2s_pins),
935 	.modemuxs = i2s_modemux,
936 	.nmodemuxs = ARRAY_SIZE(i2s_modemux),
937 };
938 
939 static const char *const i2s_grps[] = { "i2s_grp" };
940 static struct spear_function i2s_function = {
941 	.name = "i2s",
942 	.groups = i2s_grps,
943 	.ngroups = ARRAY_SIZE(i2s_grps),
944 };
945 
946 /* Pad multiplexing for UART1 device */
947 static const unsigned uart1_pins[] = { 28, 29 };
948 static struct spear_muxreg uart1_muxreg[] = {
949 	{
950 		.reg = PMX_CONFIG_REG,
951 		.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
952 		.val = 0,
953 	},
954 };
955 
956 static struct spear_muxreg uart1_ext_muxreg[] = {
957 	{
958 		.reg = IP_SEL_PAD_20_29_REG,
959 		.mask = PMX_PL_28_29_MASK,
960 		.val = PMX_UART1_PL_28_29_VAL,
961 	},
962 };
963 
964 static struct spear_modemux uart1_modemux[] = {
965 	{
966 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
967 			| SMALL_PRINTERS_MODE | EXTENDED_MODE,
968 		.muxregs = uart1_muxreg,
969 		.nmuxregs = ARRAY_SIZE(uart1_muxreg),
970 	}, {
971 		.modes = EXTENDED_MODE,
972 		.muxregs = uart1_ext_muxreg,
973 		.nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
974 	},
975 };
976 
977 static struct spear_pingroup uart1_pingroup = {
978 	.name = "uart1_grp",
979 	.pins = uart1_pins,
980 	.npins = ARRAY_SIZE(uart1_pins),
981 	.modemuxs = uart1_modemux,
982 	.nmodemuxs = ARRAY_SIZE(uart1_modemux),
983 };
984 
985 static const char *const uart1_grps[] = { "uart1_grp" };
986 static struct spear_function uart1_function = {
987 	.name = "uart1",
988 	.groups = uart1_grps,
989 	.ngroups = ARRAY_SIZE(uart1_grps),
990 };
991 
992 /* Pad multiplexing for UART1 Modem device */
993 static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
994 static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
995 static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
996 static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
997 
998 static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
999 	{
1000 		.reg = PMX_CONFIG_REG,
1001 		.mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1002 		.val = 0,
1003 	}, {
1004 		.reg = IP_SEL_PAD_0_9_REG,
1005 		.mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1006 		.val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1007 			PMX_UART1_ENH_PL_6_7_VAL,
1008 	}, {
1009 		.reg = IP_SEL_MIX_PAD_REG,
1010 		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1011 		.val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1012 	},
1013 };
1014 
1015 static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1016 	{
1017 		.reg = PMX_CONFIG_REG,
1018 		.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1019 			PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1020 		.val = 0,
1021 	},
1022 };
1023 
1024 static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1025 	{
1026 		.reg = IP_SEL_PAD_30_39_REG,
1027 		.mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1028 			PMX_PL_35_MASK | PMX_PL_36_MASK,
1029 		.val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1030 			PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1031 			PMX_UART1_ENH_PL_36_VAL,
1032 	}, {
1033 		.reg = IP_SEL_MIX_PAD_REG,
1034 		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1035 		.val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1036 	},
1037 };
1038 
1039 static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1040 	{
1041 		.reg = PMX_CONFIG_REG,
1042 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1043 			PMX_SSP_CS_MASK,
1044 		.val = 0,
1045 	},
1046 };
1047 
1048 static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1049 	{
1050 		.reg = IP_SEL_PAD_30_39_REG,
1051 		.mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1052 		.val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1053 			PMX_UART1_ENH_PL_36_VAL,
1054 	}, {
1055 		.reg = IP_SEL_PAD_40_49_REG,
1056 		.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1057 		.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1058 	}, {
1059 		.reg = IP_SEL_MIX_PAD_REG,
1060 		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1061 		.val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1062 	},
1063 };
1064 
1065 static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1066 	{
1067 		.reg = IP_SEL_PAD_80_89_REG,
1068 		.mask = PMX_PL_80_TO_85_MASK,
1069 		.val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1070 	}, {
1071 		.reg = IP_SEL_PAD_40_49_REG,
1072 		.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1073 		.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1074 	}, {
1075 		.reg = IP_SEL_MIX_PAD_REG,
1076 		.mask = PMX_UART1_ENH_PORT_SEL_MASK,
1077 		.val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1078 	},
1079 };
1080 
1081 static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1082 	{
1083 		.modes = EXTENDED_MODE,
1084 		.muxregs = uart1_modem_ext_2_to_7_muxreg,
1085 		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1086 	},
1087 };
1088 
1089 static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1090 	{
1091 		.modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1092 		.muxregs = uart1_modem_31_to_36_muxreg,
1093 		.nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1094 	}, {
1095 		.modes = EXTENDED_MODE,
1096 		.muxregs = uart1_modem_ext_31_to_36_muxreg,
1097 		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1098 	},
1099 };
1100 
1101 static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1102 	{
1103 		.modes = AUTO_EXP_MODE | EXTENDED_MODE,
1104 		.muxregs = uart1_modem_34_to_45_muxreg,
1105 		.nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1106 	}, {
1107 		.modes = EXTENDED_MODE,
1108 		.muxregs = uart1_modem_ext_34_to_45_muxreg,
1109 		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1110 	},
1111 };
1112 
1113 static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1114 	{
1115 		.modes = EXTENDED_MODE,
1116 		.muxregs = uart1_modem_ext_80_to_85_muxreg,
1117 		.nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1118 	},
1119 };
1120 
1121 static struct spear_pingroup uart1_modem_pingroup[] = {
1122 	{
1123 		.name = "uart1_modem_2_to_7_grp",
1124 		.pins = uart1_modem_2_to_7_pins,
1125 		.npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1126 		.modemuxs = uart1_modem_2_to_7_modemux,
1127 		.nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1128 	}, {
1129 		.name = "uart1_modem_31_to_36_grp",
1130 		.pins = uart1_modem_31_to_36_pins,
1131 		.npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1132 		.modemuxs = uart1_modem_31_to_36_modemux,
1133 		.nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1134 	}, {
1135 		.name = "uart1_modem_34_to_45_grp",
1136 		.pins = uart1_modem_34_to_45_pins,
1137 		.npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1138 		.modemuxs = uart1_modem_34_to_45_modemux,
1139 		.nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1140 	}, {
1141 		.name = "uart1_modem_80_to_85_grp",
1142 		.pins = uart1_modem_80_to_85_pins,
1143 		.npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1144 		.modemuxs = uart1_modem_80_to_85_modemux,
1145 		.nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1146 	},
1147 };
1148 
1149 static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1150 	"uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1151 	"uart1_modem_80_to_85_grp" };
1152 static struct spear_function uart1_modem_function = {
1153 	.name = "uart1_modem",
1154 	.groups = uart1_modem_grps,
1155 	.ngroups = ARRAY_SIZE(uart1_modem_grps),
1156 };
1157 
1158 /* Pad multiplexing for UART2 device */
1159 static const unsigned uart2_pins[] = { 0, 1 };
1160 static struct spear_muxreg uart2_muxreg[] = {
1161 	{
1162 		.reg = PMX_CONFIG_REG,
1163 		.mask = PMX_FIRDA_MASK,
1164 		.val = 0,
1165 	},
1166 };
1167 
1168 static struct spear_muxreg uart2_ext_muxreg[] = {
1169 	{
1170 		.reg = IP_SEL_PAD_0_9_REG,
1171 		.mask = PMX_PL_0_1_MASK,
1172 		.val = PMX_UART2_PL_0_1_VAL,
1173 	},
1174 };
1175 
1176 static struct spear_modemux uart2_modemux[] = {
1177 	{
1178 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1179 			| SMALL_PRINTERS_MODE | EXTENDED_MODE,
1180 		.muxregs = uart2_muxreg,
1181 		.nmuxregs = ARRAY_SIZE(uart2_muxreg),
1182 	}, {
1183 		.modes = EXTENDED_MODE,
1184 		.muxregs = uart2_ext_muxreg,
1185 		.nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1186 	},
1187 };
1188 
1189 static struct spear_pingroup uart2_pingroup = {
1190 	.name = "uart2_grp",
1191 	.pins = uart2_pins,
1192 	.npins = ARRAY_SIZE(uart2_pins),
1193 	.modemuxs = uart2_modemux,
1194 	.nmodemuxs = ARRAY_SIZE(uart2_modemux),
1195 };
1196 
1197 static const char *const uart2_grps[] = { "uart2_grp" };
1198 static struct spear_function uart2_function = {
1199 	.name = "uart2",
1200 	.groups = uart2_grps,
1201 	.ngroups = ARRAY_SIZE(uart2_grps),
1202 };
1203 
1204 /* Pad multiplexing for uart3 device */
1205 static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1206 	{ 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1207 
1208 static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1209 	{
1210 		.reg = PMX_CONFIG_REG,
1211 		.mask = PMX_SSP_MASK,
1212 		.val = 0,
1213 	}, {
1214 		.reg = IP_SEL_PAD_0_9_REG,
1215 		.mask = PMX_PL_8_9_MASK,
1216 		.val = PMX_UART3_PL_8_9_VAL,
1217 	}, {
1218 		.reg = IP_SEL_MIX_PAD_REG,
1219 		.mask = PMX_UART3_PORT_SEL_MASK,
1220 		.val = PMX_UART3_PORT_8_VAL,
1221 	},
1222 };
1223 
1224 static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1225 	{
1226 		.reg = PMX_CONFIG_REG,
1227 		.mask = PMX_MII_MASK,
1228 		.val = 0,
1229 	}, {
1230 		.reg = IP_SEL_PAD_10_19_REG,
1231 		.mask = PMX_PL_15_16_MASK,
1232 		.val = PMX_UART3_PL_15_16_VAL,
1233 	}, {
1234 		.reg = IP_SEL_MIX_PAD_REG,
1235 		.mask = PMX_UART3_PORT_SEL_MASK,
1236 		.val = PMX_UART3_PORT_15_VAL,
1237 	},
1238 };
1239 
1240 static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1241 	{
1242 		.reg = PMX_CONFIG_REG,
1243 		.mask = PMX_UART0_MODEM_MASK,
1244 		.val = 0,
1245 	}, {
1246 		.reg = IP_SEL_PAD_40_49_REG,
1247 		.mask = PMX_PL_41_42_MASK,
1248 		.val = PMX_UART3_PL_41_42_VAL,
1249 	}, {
1250 		.reg = IP_SEL_MIX_PAD_REG,
1251 		.mask = PMX_UART3_PORT_SEL_MASK,
1252 		.val = PMX_UART3_PORT_41_VAL,
1253 	},
1254 };
1255 
1256 static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1257 	{
1258 		.reg = IP_SEL_PAD_50_59_REG,
1259 		.mask = PMX_PL_52_53_MASK,
1260 		.val = PMX_UART3_PL_52_53_VAL,
1261 	}, {
1262 		.reg = IP_SEL_MIX_PAD_REG,
1263 		.mask = PMX_UART3_PORT_SEL_MASK,
1264 		.val = PMX_UART3_PORT_52_VAL,
1265 	},
1266 };
1267 
1268 static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1269 	{
1270 		.reg = IP_SEL_PAD_70_79_REG,
1271 		.mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1272 		.val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1273 	}, {
1274 		.reg = IP_SEL_MIX_PAD_REG,
1275 		.mask = PMX_UART3_PORT_SEL_MASK,
1276 		.val = PMX_UART3_PORT_73_VAL,
1277 	},
1278 };
1279 
1280 static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1281 	{
1282 		.reg = IP_SEL_PAD_90_99_REG,
1283 		.mask = PMX_PL_94_95_MASK,
1284 		.val = PMX_UART3_PL_94_95_VAL,
1285 	}, {
1286 		.reg = IP_SEL_MIX_PAD_REG,
1287 		.mask = PMX_UART3_PORT_SEL_MASK,
1288 		.val = PMX_UART3_PORT_94_VAL,
1289 	},
1290 };
1291 
1292 static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1293 	{
1294 		.reg = IP_SEL_PAD_90_99_REG,
1295 		.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1296 		.val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1297 	}, {
1298 		.reg = IP_SEL_MIX_PAD_REG,
1299 		.mask = PMX_UART3_PORT_SEL_MASK,
1300 		.val = PMX_UART3_PORT_99_VAL,
1301 	},
1302 };
1303 
1304 static struct spear_modemux uart3_modemux[][1] = {
1305 	{
1306 		/* Select signals on pins 8_9 */
1307 		{
1308 			.modes = EXTENDED_MODE,
1309 			.muxregs = uart3_ext_8_9_muxreg,
1310 			.nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1311 		},
1312 	}, {
1313 		/* Select signals on pins 15_16 */
1314 		{
1315 			.modes = EXTENDED_MODE,
1316 			.muxregs = uart3_ext_15_16_muxreg,
1317 			.nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1318 		},
1319 	}, {
1320 		/* Select signals on pins 41_42 */
1321 		{
1322 			.modes = EXTENDED_MODE,
1323 			.muxregs = uart3_ext_41_42_muxreg,
1324 			.nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1325 		},
1326 	}, {
1327 		/* Select signals on pins 52_53 */
1328 		{
1329 			.modes = EXTENDED_MODE,
1330 			.muxregs = uart3_ext_52_53_muxreg,
1331 			.nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1332 		},
1333 	}, {
1334 		/* Select signals on pins 73_74 */
1335 		{
1336 			.modes = EXTENDED_MODE,
1337 			.muxregs = uart3_ext_73_74_muxreg,
1338 			.nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1339 		},
1340 	}, {
1341 		/* Select signals on pins 94_95 */
1342 		{
1343 			.modes = EXTENDED_MODE,
1344 			.muxregs = uart3_ext_94_95_muxreg,
1345 			.nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1346 		},
1347 	}, {
1348 		/* Select signals on pins 98_99 */
1349 		{
1350 			.modes = EXTENDED_MODE,
1351 			.muxregs = uart3_ext_98_99_muxreg,
1352 			.nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1353 		},
1354 	},
1355 };
1356 
1357 static struct spear_pingroup uart3_pingroup[] = {
1358 	{
1359 		.name = "uart3_8_9_grp",
1360 		.pins = uart3_pins[0],
1361 		.npins = ARRAY_SIZE(uart3_pins[0]),
1362 		.modemuxs = uart3_modemux[0],
1363 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1364 	}, {
1365 		.name = "uart3_15_16_grp",
1366 		.pins = uart3_pins[1],
1367 		.npins = ARRAY_SIZE(uart3_pins[1]),
1368 		.modemuxs = uart3_modemux[1],
1369 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1370 	}, {
1371 		.name = "uart3_41_42_grp",
1372 		.pins = uart3_pins[2],
1373 		.npins = ARRAY_SIZE(uart3_pins[2]),
1374 		.modemuxs = uart3_modemux[2],
1375 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1376 	}, {
1377 		.name = "uart3_52_53_grp",
1378 		.pins = uart3_pins[3],
1379 		.npins = ARRAY_SIZE(uart3_pins[3]),
1380 		.modemuxs = uart3_modemux[3],
1381 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1382 	}, {
1383 		.name = "uart3_73_74_grp",
1384 		.pins = uart3_pins[4],
1385 		.npins = ARRAY_SIZE(uart3_pins[4]),
1386 		.modemuxs = uart3_modemux[4],
1387 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1388 	}, {
1389 		.name = "uart3_94_95_grp",
1390 		.pins = uart3_pins[5],
1391 		.npins = ARRAY_SIZE(uart3_pins[5]),
1392 		.modemuxs = uart3_modemux[5],
1393 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1394 	}, {
1395 		.name = "uart3_98_99_grp",
1396 		.pins = uart3_pins[6],
1397 		.npins = ARRAY_SIZE(uart3_pins[6]),
1398 		.modemuxs = uart3_modemux[6],
1399 		.nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1400 	},
1401 };
1402 
1403 static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1404 	"uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1405 	"uart3_94_95_grp", "uart3_98_99_grp" };
1406 
1407 static struct spear_function uart3_function = {
1408 	.name = "uart3",
1409 	.groups = uart3_grps,
1410 	.ngroups = ARRAY_SIZE(uart3_grps),
1411 };
1412 
1413 /* Pad multiplexing for uart4 device */
1414 static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1415 	{ 71, 72 }, { 92, 93 }, { 100, 101 } };
1416 
1417 static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1418 	{
1419 		.reg = PMX_CONFIG_REG,
1420 		.mask = PMX_SSP_MASK,
1421 		.val = 0,
1422 	}, {
1423 		.reg = IP_SEL_PAD_0_9_REG,
1424 		.mask = PMX_PL_6_7_MASK,
1425 		.val = PMX_UART4_PL_6_7_VAL,
1426 	}, {
1427 		.reg = IP_SEL_MIX_PAD_REG,
1428 		.mask = PMX_UART4_PORT_SEL_MASK,
1429 		.val = PMX_UART4_PORT_6_VAL,
1430 	},
1431 };
1432 
1433 static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1434 	{
1435 		.reg = PMX_CONFIG_REG,
1436 		.mask = PMX_MII_MASK,
1437 		.val = 0,
1438 	}, {
1439 		.reg = IP_SEL_PAD_10_19_REG,
1440 		.mask = PMX_PL_13_14_MASK,
1441 		.val = PMX_UART4_PL_13_14_VAL,
1442 	}, {
1443 		.reg = IP_SEL_MIX_PAD_REG,
1444 		.mask = PMX_UART4_PORT_SEL_MASK,
1445 		.val = PMX_UART4_PORT_13_VAL,
1446 	},
1447 };
1448 
1449 static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1450 	{
1451 		.reg = PMX_CONFIG_REG,
1452 		.mask = PMX_UART0_MODEM_MASK,
1453 		.val = 0,
1454 	}, {
1455 		.reg = IP_SEL_PAD_30_39_REG,
1456 		.mask = PMX_PL_39_MASK,
1457 		.val = PMX_UART4_PL_39_VAL,
1458 	}, {
1459 		.reg = IP_SEL_PAD_40_49_REG,
1460 		.mask = PMX_PL_40_MASK,
1461 		.val = PMX_UART4_PL_40_VAL,
1462 	}, {
1463 		.reg = IP_SEL_MIX_PAD_REG,
1464 		.mask = PMX_UART4_PORT_SEL_MASK,
1465 		.val = PMX_UART4_PORT_39_VAL,
1466 	},
1467 };
1468 
1469 static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1470 	{
1471 		.reg = IP_SEL_PAD_70_79_REG,
1472 		.mask = PMX_PL_71_72_MASK,
1473 		.val = PMX_UART4_PL_71_72_VAL,
1474 	}, {
1475 		.reg = IP_SEL_MIX_PAD_REG,
1476 		.mask = PMX_UART4_PORT_SEL_MASK,
1477 		.val = PMX_UART4_PORT_71_VAL,
1478 	},
1479 };
1480 
1481 static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1482 	{
1483 		.reg = IP_SEL_PAD_90_99_REG,
1484 		.mask = PMX_PL_92_93_MASK,
1485 		.val = PMX_UART4_PL_92_93_VAL,
1486 	}, {
1487 		.reg = IP_SEL_MIX_PAD_REG,
1488 		.mask = PMX_UART4_PORT_SEL_MASK,
1489 		.val = PMX_UART4_PORT_92_VAL,
1490 	},
1491 };
1492 
1493 static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1494 	{
1495 		.reg = IP_SEL_MIX_PAD_REG,
1496 		.mask = PMX_PL_100_101_MASK |
1497 			PMX_UART4_PORT_SEL_MASK,
1498 		.val = PMX_UART4_PL_100_101_VAL |
1499 			PMX_UART4_PORT_101_VAL,
1500 	},
1501 };
1502 
1503 static struct spear_modemux uart4_modemux[][1] = {
1504 	{
1505 		/* Select signals on pins 6_7 */
1506 		{
1507 			.modes = EXTENDED_MODE,
1508 			.muxregs = uart4_ext_6_7_muxreg,
1509 			.nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1510 		},
1511 	}, {
1512 		/* Select signals on pins 13_14 */
1513 		{
1514 			.modes = EXTENDED_MODE,
1515 			.muxregs = uart4_ext_13_14_muxreg,
1516 			.nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1517 		},
1518 	}, {
1519 		/* Select signals on pins 39_40 */
1520 		{
1521 			.modes = EXTENDED_MODE,
1522 			.muxregs = uart4_ext_39_40_muxreg,
1523 			.nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1524 		},
1525 	}, {
1526 		/* Select signals on pins 71_72 */
1527 		{
1528 			.modes = EXTENDED_MODE,
1529 			.muxregs = uart4_ext_71_72_muxreg,
1530 			.nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1531 		},
1532 	}, {
1533 		/* Select signals on pins 92_93 */
1534 		{
1535 			.modes = EXTENDED_MODE,
1536 			.muxregs = uart4_ext_92_93_muxreg,
1537 			.nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1538 		},
1539 	}, {
1540 		/* Select signals on pins 100_101_ */
1541 		{
1542 			.modes = EXTENDED_MODE,
1543 			.muxregs = uart4_ext_100_101_muxreg,
1544 			.nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1545 		},
1546 	},
1547 };
1548 
1549 static struct spear_pingroup uart4_pingroup[] = {
1550 	{
1551 		.name = "uart4_6_7_grp",
1552 		.pins = uart4_pins[0],
1553 		.npins = ARRAY_SIZE(uart4_pins[0]),
1554 		.modemuxs = uart4_modemux[0],
1555 		.nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1556 	}, {
1557 		.name = "uart4_13_14_grp",
1558 		.pins = uart4_pins[1],
1559 		.npins = ARRAY_SIZE(uart4_pins[1]),
1560 		.modemuxs = uart4_modemux[1],
1561 		.nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1562 	}, {
1563 		.name = "uart4_39_40_grp",
1564 		.pins = uart4_pins[2],
1565 		.npins = ARRAY_SIZE(uart4_pins[2]),
1566 		.modemuxs = uart4_modemux[2],
1567 		.nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1568 	}, {
1569 		.name = "uart4_71_72_grp",
1570 		.pins = uart4_pins[3],
1571 		.npins = ARRAY_SIZE(uart4_pins[3]),
1572 		.modemuxs = uart4_modemux[3],
1573 		.nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1574 	}, {
1575 		.name = "uart4_92_93_grp",
1576 		.pins = uart4_pins[4],
1577 		.npins = ARRAY_SIZE(uart4_pins[4]),
1578 		.modemuxs = uart4_modemux[4],
1579 		.nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1580 	}, {
1581 		.name = "uart4_100_101_grp",
1582 		.pins = uart4_pins[5],
1583 		.npins = ARRAY_SIZE(uart4_pins[5]),
1584 		.modemuxs = uart4_modemux[5],
1585 		.nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1586 	},
1587 };
1588 
1589 static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1590 	"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1591 	"uart4_100_101_grp" };
1592 
1593 static struct spear_function uart4_function = {
1594 	.name = "uart4",
1595 	.groups = uart4_grps,
1596 	.ngroups = ARRAY_SIZE(uart4_grps),
1597 };
1598 
1599 /* Pad multiplexing for uart5 device */
1600 static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1601 	{ 90, 91 } };
1602 
1603 static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1604 	{
1605 		.reg = PMX_CONFIG_REG,
1606 		.mask = PMX_I2C_MASK,
1607 		.val = 0,
1608 	}, {
1609 		.reg = IP_SEL_PAD_0_9_REG,
1610 		.mask = PMX_PL_4_5_MASK,
1611 		.val = PMX_UART5_PL_4_5_VAL,
1612 	}, {
1613 		.reg = IP_SEL_MIX_PAD_REG,
1614 		.mask = PMX_UART5_PORT_SEL_MASK,
1615 		.val = PMX_UART5_PORT_4_VAL,
1616 	},
1617 };
1618 
1619 static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1620 	{
1621 		.reg = PMX_CONFIG_REG,
1622 		.mask = PMX_UART0_MODEM_MASK,
1623 		.val = 0,
1624 	}, {
1625 		.reg = IP_SEL_PAD_30_39_REG,
1626 		.mask = PMX_PL_37_38_MASK,
1627 		.val = PMX_UART5_PL_37_38_VAL,
1628 	}, {
1629 		.reg = IP_SEL_MIX_PAD_REG,
1630 		.mask = PMX_UART5_PORT_SEL_MASK,
1631 		.val = PMX_UART5_PORT_37_VAL,
1632 	},
1633 };
1634 
1635 static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1636 	{
1637 		.reg = IP_SEL_PAD_60_69_REG,
1638 		.mask = PMX_PL_69_MASK,
1639 		.val = PMX_UART5_PL_69_VAL,
1640 	}, {
1641 		.reg = IP_SEL_PAD_70_79_REG,
1642 		.mask = PMX_PL_70_MASK,
1643 		.val = PMX_UART5_PL_70_VAL,
1644 	}, {
1645 		.reg = IP_SEL_MIX_PAD_REG,
1646 		.mask = PMX_UART5_PORT_SEL_MASK,
1647 		.val = PMX_UART5_PORT_69_VAL,
1648 	},
1649 };
1650 
1651 static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1652 	{
1653 		.reg = IP_SEL_PAD_90_99_REG,
1654 		.mask = PMX_PL_90_91_MASK,
1655 		.val = PMX_UART5_PL_90_91_VAL,
1656 	}, {
1657 		.reg = IP_SEL_MIX_PAD_REG,
1658 		.mask = PMX_UART5_PORT_SEL_MASK,
1659 		.val = PMX_UART5_PORT_90_VAL,
1660 	},
1661 };
1662 
1663 static struct spear_modemux uart5_modemux[][1] = {
1664 	{
1665 		/* Select signals on pins 4_5 */
1666 		{
1667 			.modes = EXTENDED_MODE,
1668 			.muxregs = uart5_ext_4_5_muxreg,
1669 			.nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1670 		},
1671 	}, {
1672 		/* Select signals on pins 37_38 */
1673 		{
1674 			.modes = EXTENDED_MODE,
1675 			.muxregs = uart5_ext_37_38_muxreg,
1676 			.nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1677 		},
1678 	}, {
1679 		/* Select signals on pins 69_70 */
1680 		{
1681 			.modes = EXTENDED_MODE,
1682 			.muxregs = uart5_ext_69_70_muxreg,
1683 			.nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1684 		},
1685 	}, {
1686 		/* Select signals on pins 90_91 */
1687 		{
1688 			.modes = EXTENDED_MODE,
1689 			.muxregs = uart5_ext_90_91_muxreg,
1690 			.nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1691 		},
1692 	},
1693 };
1694 
1695 static struct spear_pingroup uart5_pingroup[] = {
1696 	{
1697 		.name = "uart5_4_5_grp",
1698 		.pins = uart5_pins[0],
1699 		.npins = ARRAY_SIZE(uart5_pins[0]),
1700 		.modemuxs = uart5_modemux[0],
1701 		.nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1702 	}, {
1703 		.name = "uart5_37_38_grp",
1704 		.pins = uart5_pins[1],
1705 		.npins = ARRAY_SIZE(uart5_pins[1]),
1706 		.modemuxs = uart5_modemux[1],
1707 		.nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1708 	}, {
1709 		.name = "uart5_69_70_grp",
1710 		.pins = uart5_pins[2],
1711 		.npins = ARRAY_SIZE(uart5_pins[2]),
1712 		.modemuxs = uart5_modemux[2],
1713 		.nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1714 	}, {
1715 		.name = "uart5_90_91_grp",
1716 		.pins = uart5_pins[3],
1717 		.npins = ARRAY_SIZE(uart5_pins[3]),
1718 		.modemuxs = uart5_modemux[3],
1719 		.nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1720 	},
1721 };
1722 
1723 static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1724 	"uart5_69_70_grp", "uart5_90_91_grp" };
1725 static struct spear_function uart5_function = {
1726 	.name = "uart5",
1727 	.groups = uart5_grps,
1728 	.ngroups = ARRAY_SIZE(uart5_grps),
1729 };
1730 
1731 /* Pad multiplexing for uart6 device */
1732 static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1733 static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1734 	{
1735 		.reg = PMX_CONFIG_REG,
1736 		.mask = PMX_UART0_MASK,
1737 		.val = 0,
1738 	}, {
1739 		.reg = IP_SEL_PAD_0_9_REG,
1740 		.mask = PMX_PL_2_3_MASK,
1741 		.val = PMX_UART6_PL_2_3_VAL,
1742 	}, {
1743 		.reg = IP_SEL_MIX_PAD_REG,
1744 		.mask = PMX_UART6_PORT_SEL_MASK,
1745 		.val = PMX_UART6_PORT_2_VAL,
1746 	},
1747 };
1748 
1749 static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1750 	{
1751 		.reg = IP_SEL_PAD_80_89_REG,
1752 		.mask = PMX_PL_88_89_MASK,
1753 		.val = PMX_UART6_PL_88_89_VAL,
1754 	}, {
1755 		.reg = IP_SEL_MIX_PAD_REG,
1756 		.mask = PMX_UART6_PORT_SEL_MASK,
1757 		.val = PMX_UART6_PORT_88_VAL,
1758 	},
1759 };
1760 
1761 static struct spear_modemux uart6_modemux[][1] = {
1762 	{
1763 		/* Select signals on pins 2_3 */
1764 		{
1765 			.modes = EXTENDED_MODE,
1766 			.muxregs = uart6_ext_2_3_muxreg,
1767 			.nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1768 		},
1769 	}, {
1770 		/* Select signals on pins 88_89 */
1771 		{
1772 			.modes = EXTENDED_MODE,
1773 			.muxregs = uart6_ext_88_89_muxreg,
1774 			.nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1775 		},
1776 	},
1777 };
1778 
1779 static struct spear_pingroup uart6_pingroup[] = {
1780 	{
1781 		.name = "uart6_2_3_grp",
1782 		.pins = uart6_pins[0],
1783 		.npins = ARRAY_SIZE(uart6_pins[0]),
1784 		.modemuxs = uart6_modemux[0],
1785 		.nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1786 	}, {
1787 		.name = "uart6_88_89_grp",
1788 		.pins = uart6_pins[1],
1789 		.npins = ARRAY_SIZE(uart6_pins[1]),
1790 		.modemuxs = uart6_modemux[1],
1791 		.nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1792 	},
1793 };
1794 
1795 static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1796 static struct spear_function uart6_function = {
1797 	.name = "uart6",
1798 	.groups = uart6_grps,
1799 	.ngroups = ARRAY_SIZE(uart6_grps),
1800 };
1801 
1802 /* UART - RS485 pmx */
1803 static const unsigned rs485_pins[] = { 77, 78, 79 };
1804 static struct spear_muxreg rs485_muxreg[] = {
1805 	{
1806 		.reg = IP_SEL_PAD_70_79_REG,
1807 		.mask = PMX_PL_77_78_79_MASK,
1808 		.val = PMX_RS485_PL_77_78_79_VAL,
1809 	},
1810 };
1811 
1812 static struct spear_modemux rs485_modemux[] = {
1813 	{
1814 		.modes = EXTENDED_MODE,
1815 		.muxregs = rs485_muxreg,
1816 		.nmuxregs = ARRAY_SIZE(rs485_muxreg),
1817 	},
1818 };
1819 
1820 static struct spear_pingroup rs485_pingroup = {
1821 	.name = "rs485_grp",
1822 	.pins = rs485_pins,
1823 	.npins = ARRAY_SIZE(rs485_pins),
1824 	.modemuxs = rs485_modemux,
1825 	.nmodemuxs = ARRAY_SIZE(rs485_modemux),
1826 };
1827 
1828 static const char *const rs485_grps[] = { "rs485_grp" };
1829 static struct spear_function rs485_function = {
1830 	.name = "rs485",
1831 	.groups = rs485_grps,
1832 	.ngroups = ARRAY_SIZE(rs485_grps),
1833 };
1834 
1835 /* Pad multiplexing for Touchscreen device */
1836 static const unsigned touchscreen_pins[] = { 5, 36 };
1837 static struct spear_muxreg touchscreen_muxreg[] = {
1838 	{
1839 		.reg = PMX_CONFIG_REG,
1840 		.mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1841 		.val = 0,
1842 	},
1843 };
1844 
1845 static struct spear_muxreg touchscreen_ext_muxreg[] = {
1846 	{
1847 		.reg = IP_SEL_PAD_0_9_REG,
1848 		.mask = PMX_PL_5_MASK,
1849 		.val = PMX_TOUCH_Y_PL_5_VAL,
1850 	}, {
1851 		.reg = IP_SEL_PAD_30_39_REG,
1852 		.mask = PMX_PL_36_MASK,
1853 		.val = PMX_TOUCH_X_PL_36_VAL,
1854 	},
1855 };
1856 
1857 static struct spear_modemux touchscreen_modemux[] = {
1858 	{
1859 		.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1860 		.muxregs = touchscreen_muxreg,
1861 		.nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1862 	}, {
1863 		.modes = EXTENDED_MODE,
1864 		.muxregs = touchscreen_ext_muxreg,
1865 		.nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1866 	},
1867 };
1868 
1869 static struct spear_pingroup touchscreen_pingroup = {
1870 	.name = "touchscreen_grp",
1871 	.pins = touchscreen_pins,
1872 	.npins = ARRAY_SIZE(touchscreen_pins),
1873 	.modemuxs = touchscreen_modemux,
1874 	.nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1875 };
1876 
1877 static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1878 static struct spear_function touchscreen_function = {
1879 	.name = "touchscreen",
1880 	.groups = touchscreen_grps,
1881 	.ngroups = ARRAY_SIZE(touchscreen_grps),
1882 };
1883 
1884 /* Pad multiplexing for CAN device */
1885 static const unsigned can0_pins[] = { 32, 33 };
1886 static struct spear_muxreg can0_muxreg[] = {
1887 	{
1888 		.reg = PMX_CONFIG_REG,
1889 		.mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1890 		.val = 0,
1891 	},
1892 };
1893 
1894 static struct spear_muxreg can0_ext_muxreg[] = {
1895 	{
1896 		.reg = IP_SEL_PAD_30_39_REG,
1897 		.mask = PMX_PL_32_33_MASK,
1898 		.val = PMX_CAN0_PL_32_33_VAL,
1899 	},
1900 };
1901 
1902 static struct spear_modemux can0_modemux[] = {
1903 	{
1904 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1905 			| EXTENDED_MODE,
1906 		.muxregs = can0_muxreg,
1907 		.nmuxregs = ARRAY_SIZE(can0_muxreg),
1908 	}, {
1909 		.modes = EXTENDED_MODE,
1910 		.muxregs = can0_ext_muxreg,
1911 		.nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1912 	},
1913 };
1914 
1915 static struct spear_pingroup can0_pingroup = {
1916 	.name = "can0_grp",
1917 	.pins = can0_pins,
1918 	.npins = ARRAY_SIZE(can0_pins),
1919 	.modemuxs = can0_modemux,
1920 	.nmodemuxs = ARRAY_SIZE(can0_modemux),
1921 };
1922 
1923 static const char *const can0_grps[] = { "can0_grp" };
1924 static struct spear_function can0_function = {
1925 	.name = "can0",
1926 	.groups = can0_grps,
1927 	.ngroups = ARRAY_SIZE(can0_grps),
1928 };
1929 
1930 static const unsigned can1_pins[] = { 30, 31 };
1931 static struct spear_muxreg can1_muxreg[] = {
1932 	{
1933 		.reg = PMX_CONFIG_REG,
1934 		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1935 		.val = 0,
1936 	},
1937 };
1938 
1939 static struct spear_muxreg can1_ext_muxreg[] = {
1940 	{
1941 		.reg = IP_SEL_PAD_30_39_REG,
1942 		.mask = PMX_PL_30_31_MASK,
1943 		.val = PMX_CAN1_PL_30_31_VAL,
1944 	},
1945 };
1946 
1947 static struct spear_modemux can1_modemux[] = {
1948 	{
1949 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1950 			| EXTENDED_MODE,
1951 		.muxregs = can1_muxreg,
1952 		.nmuxregs = ARRAY_SIZE(can1_muxreg),
1953 	}, {
1954 		.modes = EXTENDED_MODE,
1955 		.muxregs = can1_ext_muxreg,
1956 		.nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1957 	},
1958 };
1959 
1960 static struct spear_pingroup can1_pingroup = {
1961 	.name = "can1_grp",
1962 	.pins = can1_pins,
1963 	.npins = ARRAY_SIZE(can1_pins),
1964 	.modemuxs = can1_modemux,
1965 	.nmodemuxs = ARRAY_SIZE(can1_modemux),
1966 };
1967 
1968 static const char *const can1_grps[] = { "can1_grp" };
1969 static struct spear_function can1_function = {
1970 	.name = "can1",
1971 	.groups = can1_grps,
1972 	.ngroups = ARRAY_SIZE(can1_grps),
1973 };
1974 
1975 /* Pad multiplexing for PWM0_1 device */
1976 static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1977 	{ 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1978 
1979 static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1980 	{
1981 		.reg = PMX_CONFIG_REG,
1982 		.mask = PMX_SSP_MASK,
1983 		.val = 0,
1984 	}, {
1985 		.reg = IP_SEL_PAD_0_9_REG,
1986 		.mask = PMX_PL_8_9_MASK,
1987 		.val = PMX_PWM_0_1_PL_8_9_VAL,
1988 	},
1989 };
1990 
1991 static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1992 	{
1993 		.reg = PMX_CONFIG_REG,
1994 		.mask = PMX_MII_MASK,
1995 		.val = 0,
1996 	},
1997 };
1998 
1999 static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2000 	{
2001 		.reg = IP_SEL_PAD_10_19_REG,
2002 		.mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2003 		.val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2004 	},
2005 };
2006 
2007 static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2008 	{
2009 		.reg = PMX_CONFIG_REG,
2010 		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2011 		.val = 0,
2012 	}, {
2013 		.reg = IP_SEL_PAD_30_39_REG,
2014 		.mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2015 		.val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2016 	},
2017 };
2018 
2019 static struct spear_muxreg pwm0_1_net_muxreg[] = {
2020 	{
2021 		.reg = PMX_CONFIG_REG,
2022 		.mask = PMX_UART0_MODEM_MASK,
2023 		.val = 0,
2024 	},
2025 };
2026 
2027 static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2028 	{
2029 		.reg = IP_SEL_PAD_30_39_REG,
2030 		.mask = PMX_PL_37_38_MASK,
2031 		.val = PMX_PWM0_1_PL_37_38_VAL,
2032 	},
2033 };
2034 
2035 static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2036 	{
2037 		.reg = PMX_CONFIG_REG,
2038 		.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2039 		.val = 0,
2040 	}, {
2041 		.reg = IP_SEL_PAD_40_49_REG,
2042 		.mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2043 		.val = PMX_PWM1_PL_42_VAL |
2044 			PMX_PWM0_PL_43_VAL,
2045 	},
2046 };
2047 
2048 static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2049 	{
2050 		.reg = IP_SEL_PAD_50_59_REG,
2051 		.mask = PMX_PL_59_MASK,
2052 		.val = PMX_PWM1_PL_59_VAL,
2053 	}, {
2054 		.reg = IP_SEL_PAD_60_69_REG,
2055 		.mask = PMX_PL_60_MASK,
2056 		.val = PMX_PWM0_PL_60_VAL,
2057 	},
2058 };
2059 
2060 static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2061 	{
2062 		.reg = IP_SEL_PAD_80_89_REG,
2063 		.mask = PMX_PL_88_89_MASK,
2064 		.val = PMX_PWM0_1_PL_88_89_VAL,
2065 	},
2066 };
2067 
2068 static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2069 	{
2070 		.modes = EXTENDED_MODE,
2071 		.muxregs = pwm0_1_pin_8_9_muxreg,
2072 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2073 	},
2074 };
2075 
2076 static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2077 	{
2078 		.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2079 		.muxregs = pwm0_1_autoexpsmallpri_muxreg,
2080 		.nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2081 	}, {
2082 		.modes = EXTENDED_MODE,
2083 		.muxregs = pwm0_1_pin_14_15_muxreg,
2084 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2085 	},
2086 };
2087 
2088 static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2089 	{
2090 		.modes = EXTENDED_MODE,
2091 		.muxregs = pwm0_1_pin_30_31_muxreg,
2092 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2093 	},
2094 };
2095 
2096 static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2097 	{
2098 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2099 		.muxregs = pwm0_1_net_muxreg,
2100 		.nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2101 	}, {
2102 		.modes = EXTENDED_MODE,
2103 		.muxregs = pwm0_1_pin_37_38_muxreg,
2104 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2105 	},
2106 };
2107 
2108 static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2109 	{
2110 		.modes = EXTENDED_MODE,
2111 		.muxregs = pwm0_1_pin_42_43_muxreg,
2112 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2113 	},
2114 };
2115 
2116 static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2117 	{
2118 		.modes = EXTENDED_MODE,
2119 		.muxregs = pwm0_1_pin_59_60_muxreg,
2120 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2121 	},
2122 };
2123 
2124 static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2125 	{
2126 		.modes = EXTENDED_MODE,
2127 		.muxregs = pwm0_1_pin_88_89_muxreg,
2128 		.nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2129 	},
2130 };
2131 
2132 static struct spear_pingroup pwm0_1_pingroup[] = {
2133 	{
2134 		.name = "pwm0_1_pin_8_9_grp",
2135 		.pins = pwm0_1_pins[0],
2136 		.npins = ARRAY_SIZE(pwm0_1_pins[0]),
2137 		.modemuxs = pwm0_1_pin_8_9_modemux,
2138 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2139 	}, {
2140 		.name = "pwm0_1_pin_14_15_grp",
2141 		.pins = pwm0_1_pins[1],
2142 		.npins = ARRAY_SIZE(pwm0_1_pins[1]),
2143 		.modemuxs = pwm0_1_pin_14_15_modemux,
2144 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2145 	}, {
2146 		.name = "pwm0_1_pin_30_31_grp",
2147 		.pins = pwm0_1_pins[2],
2148 		.npins = ARRAY_SIZE(pwm0_1_pins[2]),
2149 		.modemuxs = pwm0_1_pin_30_31_modemux,
2150 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2151 	}, {
2152 		.name = "pwm0_1_pin_37_38_grp",
2153 		.pins = pwm0_1_pins[3],
2154 		.npins = ARRAY_SIZE(pwm0_1_pins[3]),
2155 		.modemuxs = pwm0_1_pin_37_38_modemux,
2156 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2157 	}, {
2158 		.name = "pwm0_1_pin_42_43_grp",
2159 		.pins = pwm0_1_pins[4],
2160 		.npins = ARRAY_SIZE(pwm0_1_pins[4]),
2161 		.modemuxs = pwm0_1_pin_42_43_modemux,
2162 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2163 	}, {
2164 		.name = "pwm0_1_pin_59_60_grp",
2165 		.pins = pwm0_1_pins[5],
2166 		.npins = ARRAY_SIZE(pwm0_1_pins[5]),
2167 		.modemuxs = pwm0_1_pin_59_60_modemux,
2168 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2169 	}, {
2170 		.name = "pwm0_1_pin_88_89_grp",
2171 		.pins = pwm0_1_pins[6],
2172 		.npins = ARRAY_SIZE(pwm0_1_pins[6]),
2173 		.modemuxs = pwm0_1_pin_88_89_modemux,
2174 		.nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2175 	},
2176 };
2177 
2178 static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2179 	"pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2180 	"pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2181 };
2182 
2183 static struct spear_function pwm0_1_function = {
2184 	.name = "pwm0_1",
2185 	.groups = pwm0_1_grps,
2186 	.ngroups = ARRAY_SIZE(pwm0_1_grps),
2187 };
2188 
2189 /* Pad multiplexing for PWM2 device */
2190 static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2191 	{ 58 }, { 87 } };
2192 static struct spear_muxreg pwm2_net_muxreg[] = {
2193 	{
2194 		.reg = PMX_CONFIG_REG,
2195 		.mask = PMX_SSP_CS_MASK,
2196 		.val = 0,
2197 	},
2198 };
2199 
2200 static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2201 	{
2202 		.reg = IP_SEL_PAD_0_9_REG,
2203 		.mask = PMX_PL_7_MASK,
2204 		.val = PMX_PWM_2_PL_7_VAL,
2205 	},
2206 };
2207 
2208 static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2209 	{
2210 		.reg = PMX_CONFIG_REG,
2211 		.mask = PMX_MII_MASK,
2212 		.val = 0,
2213 	},
2214 };
2215 
2216 static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2217 	{
2218 		.reg = IP_SEL_PAD_10_19_REG,
2219 		.mask = PMX_PL_13_MASK,
2220 		.val = PMX_PWM2_PL_13_VAL,
2221 	},
2222 };
2223 
2224 static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2225 	{
2226 		.reg = PMX_CONFIG_REG,
2227 		.mask = PMX_GPIO_PIN1_MASK,
2228 		.val = 0,
2229 	}, {
2230 		.reg = IP_SEL_PAD_20_29_REG,
2231 		.mask = PMX_PL_29_MASK,
2232 		.val = PMX_PWM_2_PL_29_VAL,
2233 	},
2234 };
2235 
2236 static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2237 	{
2238 		.reg = PMX_CONFIG_REG,
2239 		.mask = PMX_SSP_CS_MASK,
2240 		.val = 0,
2241 	}, {
2242 		.reg = MODE_CONFIG_REG,
2243 		.mask = PMX_PWM_MASK,
2244 		.val = PMX_PWM_MASK,
2245 	}, {
2246 		.reg = IP_SEL_PAD_30_39_REG,
2247 		.mask = PMX_PL_34_MASK,
2248 		.val = PMX_PWM2_PL_34_VAL,
2249 	},
2250 };
2251 
2252 static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2253 	{
2254 		.reg = PMX_CONFIG_REG,
2255 		.mask = PMX_UART0_MODEM_MASK,
2256 		.val = 0,
2257 	}, {
2258 		.reg = IP_SEL_PAD_40_49_REG,
2259 		.mask = PMX_PL_41_MASK,
2260 		.val = PMX_PWM2_PL_41_VAL,
2261 	},
2262 };
2263 
2264 static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2265 	{
2266 		.reg = IP_SEL_PAD_50_59_REG,
2267 		.mask = PMX_PL_58_MASK,
2268 		.val = PMX_PWM2_PL_58_VAL,
2269 	},
2270 };
2271 
2272 static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2273 	{
2274 		.reg = IP_SEL_PAD_80_89_REG,
2275 		.mask = PMX_PL_87_MASK,
2276 		.val = PMX_PWM2_PL_87_VAL,
2277 	},
2278 };
2279 
2280 static struct spear_modemux pwm2_pin_7_modemux[] = {
2281 	{
2282 		.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2283 		.muxregs = pwm2_net_muxreg,
2284 		.nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2285 	}, {
2286 		.modes = EXTENDED_MODE,
2287 		.muxregs = pwm2_pin_7_muxreg,
2288 		.nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2289 	},
2290 };
2291 static struct spear_modemux pwm2_pin_13_modemux[] = {
2292 	{
2293 		.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2294 		.muxregs = pwm2_autoexpsmallpri_muxreg,
2295 		.nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2296 	}, {
2297 		.modes = EXTENDED_MODE,
2298 		.muxregs = pwm2_pin_13_muxreg,
2299 		.nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2300 	},
2301 };
2302 static struct spear_modemux pwm2_pin_29_modemux[] = {
2303 	{
2304 		.modes = EXTENDED_MODE,
2305 		.muxregs = pwm2_pin_29_muxreg,
2306 		.nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2307 	},
2308 };
2309 static struct spear_modemux pwm2_pin_34_modemux[] = {
2310 	{
2311 		.modes = EXTENDED_MODE,
2312 		.muxregs = pwm2_pin_34_muxreg,
2313 		.nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2314 	},
2315 };
2316 
2317 static struct spear_modemux pwm2_pin_41_modemux[] = {
2318 	{
2319 		.modes = EXTENDED_MODE,
2320 		.muxregs = pwm2_pin_41_muxreg,
2321 		.nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2322 	},
2323 };
2324 
2325 static struct spear_modemux pwm2_pin_58_modemux[] = {
2326 	{
2327 		.modes = EXTENDED_MODE,
2328 		.muxregs = pwm2_pin_58_muxreg,
2329 		.nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2330 	},
2331 };
2332 
2333 static struct spear_modemux pwm2_pin_87_modemux[] = {
2334 	{
2335 		.modes = EXTENDED_MODE,
2336 		.muxregs = pwm2_pin_87_muxreg,
2337 		.nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2338 	},
2339 };
2340 
2341 static struct spear_pingroup pwm2_pingroup[] = {
2342 	{
2343 		.name = "pwm2_pin_7_grp",
2344 		.pins = pwm2_pins[0],
2345 		.npins = ARRAY_SIZE(pwm2_pins[0]),
2346 		.modemuxs = pwm2_pin_7_modemux,
2347 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2348 	}, {
2349 		.name = "pwm2_pin_13_grp",
2350 		.pins = pwm2_pins[1],
2351 		.npins = ARRAY_SIZE(pwm2_pins[1]),
2352 		.modemuxs = pwm2_pin_13_modemux,
2353 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2354 	}, {
2355 		.name = "pwm2_pin_29_grp",
2356 		.pins = pwm2_pins[2],
2357 		.npins = ARRAY_SIZE(pwm2_pins[2]),
2358 		.modemuxs = pwm2_pin_29_modemux,
2359 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2360 	}, {
2361 		.name = "pwm2_pin_34_grp",
2362 		.pins = pwm2_pins[3],
2363 		.npins = ARRAY_SIZE(pwm2_pins[3]),
2364 		.modemuxs = pwm2_pin_34_modemux,
2365 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2366 	}, {
2367 		.name = "pwm2_pin_41_grp",
2368 		.pins = pwm2_pins[4],
2369 		.npins = ARRAY_SIZE(pwm2_pins[4]),
2370 		.modemuxs = pwm2_pin_41_modemux,
2371 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2372 	}, {
2373 		.name = "pwm2_pin_58_grp",
2374 		.pins = pwm2_pins[5],
2375 		.npins = ARRAY_SIZE(pwm2_pins[5]),
2376 		.modemuxs = pwm2_pin_58_modemux,
2377 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2378 	}, {
2379 		.name = "pwm2_pin_87_grp",
2380 		.pins = pwm2_pins[6],
2381 		.npins = ARRAY_SIZE(pwm2_pins[6]),
2382 		.modemuxs = pwm2_pin_87_modemux,
2383 		.nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2384 	},
2385 };
2386 
2387 static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2388 	"pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2389 	"pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2390 static struct spear_function pwm2_function = {
2391 	.name = "pwm2",
2392 	.groups = pwm2_grps,
2393 	.ngroups = ARRAY_SIZE(pwm2_grps),
2394 };
2395 
2396 /* Pad multiplexing for PWM3 device */
2397 static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2398 	{ 86 } };
2399 static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2400 	{
2401 		.reg = PMX_CONFIG_REG,
2402 		.mask = PMX_SSP_MASK,
2403 		.val = 0,
2404 	}, {
2405 		.reg = IP_SEL_PAD_0_9_REG,
2406 		.mask = PMX_PL_6_MASK,
2407 		.val = PMX_PWM_3_PL_6_VAL,
2408 	},
2409 };
2410 
2411 static struct spear_muxreg pwm3_muxreg[] = {
2412 	{
2413 		.reg = PMX_CONFIG_REG,
2414 		.mask = PMX_MII_MASK,
2415 		.val = 0,
2416 	},
2417 };
2418 
2419 static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2420 	{
2421 		.reg = IP_SEL_PAD_10_19_REG,
2422 		.mask = PMX_PL_12_MASK,
2423 		.val = PMX_PWM3_PL_12_VAL,
2424 	},
2425 };
2426 
2427 static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2428 	{
2429 		.reg = PMX_CONFIG_REG,
2430 		.mask = PMX_GPIO_PIN0_MASK,
2431 		.val = 0,
2432 	}, {
2433 		.reg = IP_SEL_PAD_20_29_REG,
2434 		.mask = PMX_PL_28_MASK,
2435 		.val = PMX_PWM_3_PL_28_VAL,
2436 	},
2437 };
2438 
2439 static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2440 	{
2441 		.reg = PMX_CONFIG_REG,
2442 		.mask = PMX_UART0_MODEM_MASK,
2443 		.val = 0,
2444 	}, {
2445 		.reg = IP_SEL_PAD_40_49_REG,
2446 		.mask = PMX_PL_40_MASK,
2447 		.val = PMX_PWM3_PL_40_VAL,
2448 	},
2449 };
2450 
2451 static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2452 	{
2453 		.reg = IP_SEL_PAD_50_59_REG,
2454 		.mask = PMX_PL_57_MASK,
2455 		.val = PMX_PWM3_PL_57_VAL,
2456 	},
2457 };
2458 
2459 static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2460 	{
2461 		.reg = IP_SEL_PAD_80_89_REG,
2462 		.mask = PMX_PL_86_MASK,
2463 		.val = PMX_PWM3_PL_86_VAL,
2464 	},
2465 };
2466 
2467 static struct spear_modemux pwm3_pin_6_modemux[] = {
2468 	{
2469 		.modes = EXTENDED_MODE,
2470 		.muxregs = pwm3_pin_6_muxreg,
2471 		.nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2472 	},
2473 };
2474 
2475 static struct spear_modemux pwm3_pin_12_modemux[] = {
2476 	{
2477 		.modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2478 			AUTO_NET_SMII_MODE | EXTENDED_MODE,
2479 		.muxregs = pwm3_muxreg,
2480 		.nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2481 	}, {
2482 		.modes = EXTENDED_MODE,
2483 		.muxregs = pwm3_pin_12_muxreg,
2484 		.nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2485 	},
2486 };
2487 
2488 static struct spear_modemux pwm3_pin_28_modemux[] = {
2489 	{
2490 		.modes = EXTENDED_MODE,
2491 		.muxregs = pwm3_pin_28_muxreg,
2492 		.nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2493 	},
2494 };
2495 
2496 static struct spear_modemux pwm3_pin_40_modemux[] = {
2497 	{
2498 		.modes = EXTENDED_MODE,
2499 		.muxregs = pwm3_pin_40_muxreg,
2500 		.nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2501 	},
2502 };
2503 
2504 static struct spear_modemux pwm3_pin_57_modemux[] = {
2505 	{
2506 		.modes = EXTENDED_MODE,
2507 		.muxregs = pwm3_pin_57_muxreg,
2508 		.nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2509 	},
2510 };
2511 
2512 static struct spear_modemux pwm3_pin_86_modemux[] = {
2513 	{
2514 		.modes = EXTENDED_MODE,
2515 		.muxregs = pwm3_pin_86_muxreg,
2516 		.nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2517 	},
2518 };
2519 
2520 static struct spear_pingroup pwm3_pingroup[] = {
2521 	{
2522 		.name = "pwm3_pin_6_grp",
2523 		.pins = pwm3_pins[0],
2524 		.npins = ARRAY_SIZE(pwm3_pins[0]),
2525 		.modemuxs = pwm3_pin_6_modemux,
2526 		.nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2527 	}, {
2528 		.name = "pwm3_pin_12_grp",
2529 		.pins = pwm3_pins[1],
2530 		.npins = ARRAY_SIZE(pwm3_pins[1]),
2531 		.modemuxs = pwm3_pin_12_modemux,
2532 		.nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2533 	}, {
2534 		.name = "pwm3_pin_28_grp",
2535 		.pins = pwm3_pins[2],
2536 		.npins = ARRAY_SIZE(pwm3_pins[2]),
2537 		.modemuxs = pwm3_pin_28_modemux,
2538 		.nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2539 	}, {
2540 		.name = "pwm3_pin_40_grp",
2541 		.pins = pwm3_pins[3],
2542 		.npins = ARRAY_SIZE(pwm3_pins[3]),
2543 		.modemuxs = pwm3_pin_40_modemux,
2544 		.nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2545 	}, {
2546 		.name = "pwm3_pin_57_grp",
2547 		.pins = pwm3_pins[4],
2548 		.npins = ARRAY_SIZE(pwm3_pins[4]),
2549 		.modemuxs = pwm3_pin_57_modemux,
2550 		.nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2551 	}, {
2552 		.name = "pwm3_pin_86_grp",
2553 		.pins = pwm3_pins[5],
2554 		.npins = ARRAY_SIZE(pwm3_pins[5]),
2555 		.modemuxs = pwm3_pin_86_modemux,
2556 		.nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2557 	},
2558 };
2559 
2560 static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2561 	"pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2562 	"pwm3_pin_86_grp" };
2563 static struct spear_function pwm3_function = {
2564 	.name = "pwm3",
2565 	.groups = pwm3_grps,
2566 	.ngroups = ARRAY_SIZE(pwm3_grps),
2567 };
2568 
2569 /* Pad multiplexing for SSP1 device */
2570 static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2571 	{ 65, 68 }, { 94, 97 } };
2572 static struct spear_muxreg ssp1_muxreg[] = {
2573 	{
2574 		.reg = PMX_CONFIG_REG,
2575 		.mask = PMX_MII_MASK,
2576 		.val = 0,
2577 	},
2578 };
2579 
2580 static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2581 	{
2582 		.reg = IP_SEL_PAD_10_19_REG,
2583 		.mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2584 		.val = PMX_SSP1_PL_17_18_19_20_VAL,
2585 	}, {
2586 		.reg = IP_SEL_PAD_20_29_REG,
2587 		.mask = PMX_PL_20_MASK,
2588 		.val = PMX_SSP1_PL_17_18_19_20_VAL,
2589 	}, {
2590 		.reg = IP_SEL_MIX_PAD_REG,
2591 		.mask = PMX_SSP1_PORT_SEL_MASK,
2592 		.val = PMX_SSP1_PORT_17_TO_20_VAL,
2593 	},
2594 };
2595 
2596 static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2597 	{
2598 		.reg = PMX_CONFIG_REG,
2599 		.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2600 		.val = 0,
2601 	}, {
2602 		.reg = IP_SEL_PAD_30_39_REG,
2603 		.mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2604 		.val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2605 			PMX_SSP1_PL_39_VAL,
2606 	}, {
2607 		.reg = IP_SEL_MIX_PAD_REG,
2608 		.mask = PMX_SSP1_PORT_SEL_MASK,
2609 		.val = PMX_SSP1_PORT_36_TO_39_VAL,
2610 	},
2611 };
2612 
2613 static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2614 	{
2615 		.reg = PMX_CONFIG_REG,
2616 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2617 		.val = 0,
2618 	}, {
2619 		.reg = IP_SEL_PAD_40_49_REG,
2620 		.mask = PMX_PL_48_49_MASK,
2621 		.val = PMX_SSP1_PL_48_49_VAL,
2622 	}, {
2623 		.reg = IP_SEL_PAD_50_59_REG,
2624 		.mask = PMX_PL_50_51_MASK,
2625 		.val = PMX_SSP1_PL_50_51_VAL,
2626 	}, {
2627 		.reg = IP_SEL_MIX_PAD_REG,
2628 		.mask = PMX_SSP1_PORT_SEL_MASK,
2629 		.val = PMX_SSP1_PORT_48_TO_51_VAL,
2630 	},
2631 };
2632 
2633 static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2634 	{
2635 		.reg = IP_SEL_PAD_60_69_REG,
2636 		.mask = PMX_PL_65_TO_68_MASK,
2637 		.val = PMX_SSP1_PL_65_TO_68_VAL,
2638 	}, {
2639 		.reg = IP_SEL_MIX_PAD_REG,
2640 		.mask = PMX_SSP1_PORT_SEL_MASK,
2641 		.val = PMX_SSP1_PORT_65_TO_68_VAL,
2642 	},
2643 };
2644 
2645 static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2646 	{
2647 		.reg = IP_SEL_PAD_90_99_REG,
2648 		.mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2649 		.val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2650 	}, {
2651 		.reg = IP_SEL_MIX_PAD_REG,
2652 		.mask = PMX_SSP1_PORT_SEL_MASK,
2653 		.val = PMX_SSP1_PORT_94_TO_97_VAL,
2654 	},
2655 };
2656 
2657 static struct spear_modemux ssp1_17_20_modemux[] = {
2658 	{
2659 		.modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2660 			EXTENDED_MODE,
2661 		.muxregs = ssp1_muxreg,
2662 		.nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2663 	}, {
2664 		.modes = EXTENDED_MODE,
2665 		.muxregs = ssp1_ext_17_20_muxreg,
2666 		.nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2667 	},
2668 };
2669 
2670 static struct spear_modemux ssp1_36_39_modemux[] = {
2671 	{
2672 		.modes = EXTENDED_MODE,
2673 		.muxregs = ssp1_ext_36_39_muxreg,
2674 		.nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2675 	},
2676 };
2677 
2678 static struct spear_modemux ssp1_48_51_modemux[] = {
2679 	{
2680 		.modes = EXTENDED_MODE,
2681 		.muxregs = ssp1_ext_48_51_muxreg,
2682 		.nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2683 	},
2684 };
2685 static struct spear_modemux ssp1_65_68_modemux[] = {
2686 	{
2687 		.modes = EXTENDED_MODE,
2688 		.muxregs = ssp1_ext_65_68_muxreg,
2689 		.nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2690 	},
2691 };
2692 
2693 static struct spear_modemux ssp1_94_97_modemux[] = {
2694 	{
2695 		.modes = EXTENDED_MODE,
2696 		.muxregs = ssp1_ext_94_97_muxreg,
2697 		.nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2698 	},
2699 };
2700 
2701 static struct spear_pingroup ssp1_pingroup[] = {
2702 	{
2703 		.name = "ssp1_17_20_grp",
2704 		.pins = ssp1_pins[0],
2705 		.npins = ARRAY_SIZE(ssp1_pins[0]),
2706 		.modemuxs = ssp1_17_20_modemux,
2707 		.nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2708 	}, {
2709 		.name = "ssp1_36_39_grp",
2710 		.pins = ssp1_pins[1],
2711 		.npins = ARRAY_SIZE(ssp1_pins[1]),
2712 		.modemuxs = ssp1_36_39_modemux,
2713 		.nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2714 	}, {
2715 		.name = "ssp1_48_51_grp",
2716 		.pins = ssp1_pins[2],
2717 		.npins = ARRAY_SIZE(ssp1_pins[2]),
2718 		.modemuxs = ssp1_48_51_modemux,
2719 		.nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2720 	}, {
2721 		.name = "ssp1_65_68_grp",
2722 		.pins = ssp1_pins[3],
2723 		.npins = ARRAY_SIZE(ssp1_pins[3]),
2724 		.modemuxs = ssp1_65_68_modemux,
2725 		.nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2726 	}, {
2727 		.name = "ssp1_94_97_grp",
2728 		.pins = ssp1_pins[4],
2729 		.npins = ARRAY_SIZE(ssp1_pins[4]),
2730 		.modemuxs = ssp1_94_97_modemux,
2731 		.nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2732 	},
2733 };
2734 
2735 static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2736 	"ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2737 };
2738 static struct spear_function ssp1_function = {
2739 	.name = "ssp1",
2740 	.groups = ssp1_grps,
2741 	.ngroups = ARRAY_SIZE(ssp1_grps),
2742 };
2743 
2744 /* Pad multiplexing for SSP2 device */
2745 static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2746 	{ 61, 64 }, { 90, 93 } };
2747 static struct spear_muxreg ssp2_muxreg[] = {
2748 	{
2749 		.reg = PMX_CONFIG_REG,
2750 		.mask = PMX_MII_MASK,
2751 		.val = 0,
2752 	},
2753 };
2754 
2755 static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2756 	{
2757 		.reg = IP_SEL_PAD_10_19_REG,
2758 		.mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2759 		.val = PMX_SSP2_PL_13_14_15_16_VAL,
2760 	}, {
2761 		.reg = IP_SEL_MIX_PAD_REG,
2762 		.mask = PMX_SSP2_PORT_SEL_MASK,
2763 		.val = PMX_SSP2_PORT_13_TO_16_VAL,
2764 	},
2765 };
2766 
2767 static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2768 	{
2769 		.reg = PMX_CONFIG_REG,
2770 		.mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2771 			PMX_GPIO_PIN5_MASK,
2772 		.val = 0,
2773 	}, {
2774 		.reg = IP_SEL_PAD_30_39_REG,
2775 		.mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2776 		.val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2777 			PMX_SSP2_PL_35_VAL,
2778 	}, {
2779 		.reg = IP_SEL_MIX_PAD_REG,
2780 		.mask = PMX_SSP2_PORT_SEL_MASK,
2781 		.val = PMX_SSP2_PORT_32_TO_35_VAL,
2782 	},
2783 };
2784 
2785 static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2786 	{
2787 		.reg = PMX_CONFIG_REG,
2788 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2789 		.val = 0,
2790 	}, {
2791 		.reg = IP_SEL_PAD_40_49_REG,
2792 		.mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2793 		.val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2794 	}, {
2795 		.reg = IP_SEL_MIX_PAD_REG,
2796 		.mask = PMX_SSP2_PORT_SEL_MASK,
2797 		.val = PMX_SSP2_PORT_44_TO_47_VAL,
2798 	},
2799 };
2800 
2801 static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2802 	{
2803 		.reg = IP_SEL_PAD_60_69_REG,
2804 		.mask = PMX_PL_61_TO_64_MASK,
2805 		.val = PMX_SSP2_PL_61_TO_64_VAL,
2806 	}, {
2807 		.reg = IP_SEL_MIX_PAD_REG,
2808 		.mask = PMX_SSP2_PORT_SEL_MASK,
2809 		.val = PMX_SSP2_PORT_61_TO_64_VAL,
2810 	},
2811 };
2812 
2813 static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2814 	{
2815 		.reg = IP_SEL_PAD_90_99_REG,
2816 		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2817 		.val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2818 	}, {
2819 		.reg = IP_SEL_MIX_PAD_REG,
2820 		.mask = PMX_SSP2_PORT_SEL_MASK,
2821 		.val = PMX_SSP2_PORT_90_TO_93_VAL,
2822 	},
2823 };
2824 
2825 static struct spear_modemux ssp2_13_16_modemux[] = {
2826 	{
2827 		.modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2828 		.muxregs = ssp2_muxreg,
2829 		.nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2830 	}, {
2831 		.modes = EXTENDED_MODE,
2832 		.muxregs = ssp2_ext_13_16_muxreg,
2833 		.nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2834 	},
2835 };
2836 
2837 static struct spear_modemux ssp2_32_35_modemux[] = {
2838 	{
2839 		.modes = EXTENDED_MODE,
2840 		.muxregs = ssp2_ext_32_35_muxreg,
2841 		.nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2842 	},
2843 };
2844 
2845 static struct spear_modemux ssp2_44_47_modemux[] = {
2846 	{
2847 		.modes = EXTENDED_MODE,
2848 		.muxregs = ssp2_ext_44_47_muxreg,
2849 		.nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2850 	},
2851 };
2852 
2853 static struct spear_modemux ssp2_61_64_modemux[] = {
2854 	{
2855 		.modes = EXTENDED_MODE,
2856 		.muxregs = ssp2_ext_61_64_muxreg,
2857 		.nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2858 	},
2859 };
2860 
2861 static struct spear_modemux ssp2_90_93_modemux[] = {
2862 	{
2863 		.modes = EXTENDED_MODE,
2864 		.muxregs = ssp2_ext_90_93_muxreg,
2865 		.nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2866 	},
2867 };
2868 
2869 static struct spear_pingroup ssp2_pingroup[] = {
2870 	{
2871 		.name = "ssp2_13_16_grp",
2872 		.pins = ssp2_pins[0],
2873 		.npins = ARRAY_SIZE(ssp2_pins[0]),
2874 		.modemuxs = ssp2_13_16_modemux,
2875 		.nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2876 	}, {
2877 		.name = "ssp2_32_35_grp",
2878 		.pins = ssp2_pins[1],
2879 		.npins = ARRAY_SIZE(ssp2_pins[1]),
2880 		.modemuxs = ssp2_32_35_modemux,
2881 		.nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2882 	}, {
2883 		.name = "ssp2_44_47_grp",
2884 		.pins = ssp2_pins[2],
2885 		.npins = ARRAY_SIZE(ssp2_pins[2]),
2886 		.modemuxs = ssp2_44_47_modemux,
2887 		.nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2888 	}, {
2889 		.name = "ssp2_61_64_grp",
2890 		.pins = ssp2_pins[3],
2891 		.npins = ARRAY_SIZE(ssp2_pins[3]),
2892 		.modemuxs = ssp2_61_64_modemux,
2893 		.nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2894 	}, {
2895 		.name = "ssp2_90_93_grp",
2896 		.pins = ssp2_pins[4],
2897 		.npins = ARRAY_SIZE(ssp2_pins[4]),
2898 		.modemuxs = ssp2_90_93_modemux,
2899 		.nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2900 	},
2901 };
2902 
2903 static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2904 	"ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2905 static struct spear_function ssp2_function = {
2906 	.name = "ssp2",
2907 	.groups = ssp2_grps,
2908 	.ngroups = ARRAY_SIZE(ssp2_grps),
2909 };
2910 
2911 /* Pad multiplexing for cadence mii2 as mii device */
2912 static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2913 	90, 91, 92, 93, 94, 95, 96, 97 };
2914 static struct spear_muxreg mii2_muxreg[] = {
2915 	{
2916 		.reg = IP_SEL_PAD_80_89_REG,
2917 		.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2918 			PMX_PL_88_89_MASK,
2919 		.val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2920 			PMX_MII2_PL_88_89_VAL,
2921 	}, {
2922 		.reg = IP_SEL_PAD_90_99_REG,
2923 		.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2924 			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2925 		.val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2926 			PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2927 	}, {
2928 		.reg = EXT_CTRL_REG,
2929 		.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2930 			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2931 			MII_MDIO_MASK,
2932 		.val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2933 			(MAC_MODE_MII << MAC1_MODE_SHIFT) |
2934 			MII_MDIO_81_VAL,
2935 	},
2936 };
2937 
2938 static struct spear_modemux mii2_modemux[] = {
2939 	{
2940 		.modes = EXTENDED_MODE,
2941 		.muxregs = mii2_muxreg,
2942 		.nmuxregs = ARRAY_SIZE(mii2_muxreg),
2943 	},
2944 };
2945 
2946 static struct spear_pingroup mii2_pingroup = {
2947 	.name = "mii2_grp",
2948 	.pins = mii2_pins,
2949 	.npins = ARRAY_SIZE(mii2_pins),
2950 	.modemuxs = mii2_modemux,
2951 	.nmodemuxs = ARRAY_SIZE(mii2_modemux),
2952 };
2953 
2954 static const char *const mii2_grps[] = { "mii2_grp" };
2955 static struct spear_function mii2_function = {
2956 	.name = "mii2",
2957 	.groups = mii2_grps,
2958 	.ngroups = ARRAY_SIZE(mii2_grps),
2959 };
2960 
2961 /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2962 static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2963 	21, 22, 23, 24, 25, 26, 27 };
2964 static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2965 static struct spear_muxreg mii0_1_muxreg[] = {
2966 	{
2967 		.reg = PMX_CONFIG_REG,
2968 		.mask = PMX_MII_MASK,
2969 		.val = 0,
2970 	},
2971 };
2972 
2973 static struct spear_muxreg smii0_1_ext_muxreg[] = {
2974 	{
2975 		.reg = IP_SEL_PAD_10_19_REG,
2976 		.mask = PMX_PL_10_11_MASK,
2977 		.val = PMX_SMII_PL_10_11_VAL,
2978 	}, {
2979 		.reg = IP_SEL_PAD_20_29_REG,
2980 		.mask = PMX_PL_21_TO_27_MASK,
2981 		.val = PMX_SMII_PL_21_TO_27_VAL,
2982 	}, {
2983 		.reg = EXT_CTRL_REG,
2984 		.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2985 			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2986 			MII_MDIO_MASK,
2987 		.val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2988 			| (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2989 			| MII_MDIO_10_11_VAL,
2990 	},
2991 };
2992 
2993 static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2994 	{
2995 		.reg = IP_SEL_PAD_10_19_REG,
2996 		.mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2997 			PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2998 		.val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
2999 			PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
3000 			PMX_RMII_PL_19_VAL,
3001 	}, {
3002 		.reg = IP_SEL_PAD_20_29_REG,
3003 		.mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3004 		.val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3005 	}, {
3006 		.reg = EXT_CTRL_REG,
3007 		.mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3008 			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3009 			MII_MDIO_MASK,
3010 		.val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3011 			| (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3012 			| MII_MDIO_10_11_VAL,
3013 	},
3014 };
3015 
3016 static struct spear_modemux mii0_1_modemux[][2] = {
3017 	{
3018 		/* configure as smii */
3019 		{
3020 			.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3021 				SMALL_PRINTERS_MODE | EXTENDED_MODE,
3022 			.muxregs = mii0_1_muxreg,
3023 			.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3024 		}, {
3025 			.modes = EXTENDED_MODE,
3026 			.muxregs = smii0_1_ext_muxreg,
3027 			.nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3028 		},
3029 	}, {
3030 		/* configure as rmii */
3031 		{
3032 			.modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3033 				SMALL_PRINTERS_MODE | EXTENDED_MODE,
3034 			.muxregs = mii0_1_muxreg,
3035 			.nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3036 		}, {
3037 			.modes = EXTENDED_MODE,
3038 			.muxregs = rmii0_1_ext_muxreg,
3039 			.nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3040 		},
3041 	},
3042 };
3043 
3044 static struct spear_pingroup mii0_1_pingroup[] = {
3045 	{
3046 		.name = "smii0_1_grp",
3047 		.pins = smii0_1_pins,
3048 		.npins = ARRAY_SIZE(smii0_1_pins),
3049 		.modemuxs = mii0_1_modemux[0],
3050 		.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3051 	}, {
3052 		.name = "rmii0_1_grp",
3053 		.pins = rmii0_1_pins,
3054 		.npins = ARRAY_SIZE(rmii0_1_pins),
3055 		.modemuxs = mii0_1_modemux[1],
3056 		.nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3057 	},
3058 };
3059 
3060 static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3061 static struct spear_function mii0_1_function = {
3062 	.name = "mii0_1",
3063 	.groups = mii0_1_grps,
3064 	.ngroups = ARRAY_SIZE(mii0_1_grps),
3065 };
3066 
3067 /* Pad multiplexing for i2c1 device */
3068 static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3069 static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3070 	{
3071 		.reg = PMX_CONFIG_REG,
3072 		.mask = PMX_SSP_CS_MASK,
3073 		.val = 0,
3074 	}, {
3075 		.reg = IP_SEL_PAD_0_9_REG,
3076 		.mask = PMX_PL_8_9_MASK,
3077 		.val = PMX_I2C1_PL_8_9_VAL,
3078 	}, {
3079 		.reg = IP_SEL_MIX_PAD_REG,
3080 		.mask = PMX_I2C1_PORT_SEL_MASK,
3081 		.val = PMX_I2C1_PORT_8_9_VAL,
3082 	},
3083 };
3084 
3085 static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3086 	{
3087 		.reg = IP_SEL_PAD_90_99_REG,
3088 		.mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3089 		.val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3090 	}, {
3091 		.reg = IP_SEL_MIX_PAD_REG,
3092 		.mask = PMX_I2C1_PORT_SEL_MASK,
3093 		.val = PMX_I2C1_PORT_98_99_VAL,
3094 	},
3095 };
3096 
3097 static struct spear_modemux i2c1_modemux[][1] = {
3098 	{
3099 		/* Select signals on pins 8-9 */
3100 		{
3101 			.modes = EXTENDED_MODE,
3102 			.muxregs = i2c1_ext_8_9_muxreg,
3103 			.nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3104 		},
3105 	}, {
3106 		/* Select signals on pins 98-99 */
3107 		{
3108 			.modes = EXTENDED_MODE,
3109 			.muxregs = i2c1_ext_98_99_muxreg,
3110 			.nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3111 		},
3112 	},
3113 };
3114 
3115 static struct spear_pingroup i2c1_pingroup[] = {
3116 	{
3117 		.name = "i2c1_8_9_grp",
3118 		.pins = i2c1_pins[0],
3119 		.npins = ARRAY_SIZE(i2c1_pins[0]),
3120 		.modemuxs = i2c1_modemux[0],
3121 		.nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3122 	}, {
3123 		.name = "i2c1_98_99_grp",
3124 		.pins = i2c1_pins[1],
3125 		.npins = ARRAY_SIZE(i2c1_pins[1]),
3126 		.modemuxs = i2c1_modemux[1],
3127 		.nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3128 	},
3129 };
3130 
3131 static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3132 static struct spear_function i2c1_function = {
3133 	.name = "i2c1",
3134 	.groups = i2c1_grps,
3135 	.ngroups = ARRAY_SIZE(i2c1_grps),
3136 };
3137 
3138 /* Pad multiplexing for i2c2 device */
3139 static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3140 	{ 75, 76 }, { 96, 97 } };
3141 static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3142 	{
3143 		.reg = PMX_CONFIG_REG,
3144 		.mask = PMX_FIRDA_MASK,
3145 		.val = 0,
3146 	}, {
3147 		.reg = IP_SEL_PAD_0_9_REG,
3148 		.mask = PMX_PL_0_1_MASK,
3149 		.val = PMX_I2C2_PL_0_1_VAL,
3150 	}, {
3151 		.reg = IP_SEL_MIX_PAD_REG,
3152 		.mask = PMX_I2C2_PORT_SEL_MASK,
3153 		.val = PMX_I2C2_PORT_0_1_VAL,
3154 	},
3155 };
3156 
3157 static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3158 	{
3159 		.reg = PMX_CONFIG_REG,
3160 		.mask = PMX_UART0_MASK,
3161 		.val = 0,
3162 	}, {
3163 		.reg = IP_SEL_PAD_0_9_REG,
3164 		.mask = PMX_PL_2_3_MASK,
3165 		.val = PMX_I2C2_PL_2_3_VAL,
3166 	}, {
3167 		.reg = IP_SEL_MIX_PAD_REG,
3168 		.mask = PMX_I2C2_PORT_SEL_MASK,
3169 		.val = PMX_I2C2_PORT_2_3_VAL,
3170 	},
3171 };
3172 
3173 static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3174 	{
3175 		.reg = PMX_CONFIG_REG,
3176 		.mask = PMX_MII_MASK,
3177 		.val = 0,
3178 	}, {
3179 		.reg = IP_SEL_PAD_10_19_REG,
3180 		.mask = PMX_PL_19_MASK,
3181 		.val = PMX_I2C2_PL_19_VAL,
3182 	}, {
3183 		.reg = IP_SEL_PAD_20_29_REG,
3184 		.mask = PMX_PL_20_MASK,
3185 		.val = PMX_I2C2_PL_20_VAL,
3186 	}, {
3187 		.reg = IP_SEL_MIX_PAD_REG,
3188 		.mask = PMX_I2C2_PORT_SEL_MASK,
3189 		.val = PMX_I2C2_PORT_19_20_VAL,
3190 	},
3191 };
3192 
3193 static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3194 	{
3195 		.reg = IP_SEL_PAD_70_79_REG,
3196 		.mask = PMX_PL_75_76_MASK,
3197 		.val = PMX_I2C2_PL_75_76_VAL,
3198 	}, {
3199 		.reg = IP_SEL_MIX_PAD_REG,
3200 		.mask = PMX_I2C2_PORT_SEL_MASK,
3201 		.val = PMX_I2C2_PORT_75_76_VAL,
3202 	},
3203 };
3204 
3205 static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3206 	{
3207 		.reg = IP_SEL_PAD_90_99_REG,
3208 		.mask = PMX_PL_96_97_MASK,
3209 		.val = PMX_I2C2_PL_96_97_VAL,
3210 	}, {
3211 		.reg = IP_SEL_MIX_PAD_REG,
3212 		.mask = PMX_I2C2_PORT_SEL_MASK,
3213 		.val = PMX_I2C2_PORT_96_97_VAL,
3214 	},
3215 };
3216 
3217 static struct spear_modemux i2c2_modemux[][1] = {
3218 	{
3219 		/* Select signals on pins 0_1 */
3220 		{
3221 			.modes = EXTENDED_MODE,
3222 			.muxregs = i2c2_ext_0_1_muxreg,
3223 			.nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3224 		},
3225 	}, {
3226 		/* Select signals on pins 2_3 */
3227 		{
3228 			.modes = EXTENDED_MODE,
3229 			.muxregs = i2c2_ext_2_3_muxreg,
3230 			.nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3231 		},
3232 	}, {
3233 		/* Select signals on pins 19_20 */
3234 		{
3235 			.modes = EXTENDED_MODE,
3236 			.muxregs = i2c2_ext_19_20_muxreg,
3237 			.nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3238 		},
3239 	}, {
3240 		/* Select signals on pins 75_76 */
3241 		{
3242 			.modes = EXTENDED_MODE,
3243 			.muxregs = i2c2_ext_75_76_muxreg,
3244 			.nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3245 		},
3246 	}, {
3247 		/* Select signals on pins 96_97 */
3248 		{
3249 			.modes = EXTENDED_MODE,
3250 			.muxregs = i2c2_ext_96_97_muxreg,
3251 			.nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3252 		},
3253 	},
3254 };
3255 
3256 static struct spear_pingroup i2c2_pingroup[] = {
3257 	{
3258 		.name = "i2c2_0_1_grp",
3259 		.pins = i2c2_pins[0],
3260 		.npins = ARRAY_SIZE(i2c2_pins[0]),
3261 		.modemuxs = i2c2_modemux[0],
3262 		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3263 	}, {
3264 		.name = "i2c2_2_3_grp",
3265 		.pins = i2c2_pins[1],
3266 		.npins = ARRAY_SIZE(i2c2_pins[1]),
3267 		.modemuxs = i2c2_modemux[1],
3268 		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3269 	}, {
3270 		.name = "i2c2_19_20_grp",
3271 		.pins = i2c2_pins[2],
3272 		.npins = ARRAY_SIZE(i2c2_pins[2]),
3273 		.modemuxs = i2c2_modemux[2],
3274 		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3275 	}, {
3276 		.name = "i2c2_75_76_grp",
3277 		.pins = i2c2_pins[3],
3278 		.npins = ARRAY_SIZE(i2c2_pins[3]),
3279 		.modemuxs = i2c2_modemux[3],
3280 		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3281 	}, {
3282 		.name = "i2c2_96_97_grp",
3283 		.pins = i2c2_pins[4],
3284 		.npins = ARRAY_SIZE(i2c2_pins[4]),
3285 		.modemuxs = i2c2_modemux[4],
3286 		.nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3287 	},
3288 };
3289 
3290 static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3291 	"i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3292 static struct spear_function i2c2_function = {
3293 	.name = "i2c2",
3294 	.groups = i2c2_grps,
3295 	.ngroups = ARRAY_SIZE(i2c2_grps),
3296 };
3297 
3298 /* pingroups */
3299 static struct spear_pingroup *spear320_pingroups[] = {
3300 	SPEAR3XX_COMMON_PINGROUPS,
3301 	&clcd_pingroup,
3302 	&emi_pingroup,
3303 	&fsmc_8bit_pingroup,
3304 	&fsmc_16bit_pingroup,
3305 	&spp_pingroup,
3306 	&sdhci_led_pingroup,
3307 	&sdhci_pingroup[0],
3308 	&sdhci_pingroup[1],
3309 	&i2s_pingroup,
3310 	&uart1_pingroup,
3311 	&uart1_modem_pingroup[0],
3312 	&uart1_modem_pingroup[1],
3313 	&uart1_modem_pingroup[2],
3314 	&uart1_modem_pingroup[3],
3315 	&uart2_pingroup,
3316 	&uart3_pingroup[0],
3317 	&uart3_pingroup[1],
3318 	&uart3_pingroup[2],
3319 	&uart3_pingroup[3],
3320 	&uart3_pingroup[4],
3321 	&uart3_pingroup[5],
3322 	&uart3_pingroup[6],
3323 	&uart4_pingroup[0],
3324 	&uart4_pingroup[1],
3325 	&uart4_pingroup[2],
3326 	&uart4_pingroup[3],
3327 	&uart4_pingroup[4],
3328 	&uart4_pingroup[5],
3329 	&uart5_pingroup[0],
3330 	&uart5_pingroup[1],
3331 	&uart5_pingroup[2],
3332 	&uart5_pingroup[3],
3333 	&uart6_pingroup[0],
3334 	&uart6_pingroup[1],
3335 	&rs485_pingroup,
3336 	&touchscreen_pingroup,
3337 	&can0_pingroup,
3338 	&can1_pingroup,
3339 	&pwm0_1_pingroup[0],
3340 	&pwm0_1_pingroup[1],
3341 	&pwm0_1_pingroup[2],
3342 	&pwm0_1_pingroup[3],
3343 	&pwm0_1_pingroup[4],
3344 	&pwm0_1_pingroup[5],
3345 	&pwm0_1_pingroup[6],
3346 	&pwm2_pingroup[0],
3347 	&pwm2_pingroup[1],
3348 	&pwm2_pingroup[2],
3349 	&pwm2_pingroup[3],
3350 	&pwm2_pingroup[4],
3351 	&pwm2_pingroup[5],
3352 	&pwm2_pingroup[6],
3353 	&pwm3_pingroup[0],
3354 	&pwm3_pingroup[1],
3355 	&pwm3_pingroup[2],
3356 	&pwm3_pingroup[3],
3357 	&pwm3_pingroup[4],
3358 	&pwm3_pingroup[5],
3359 	&ssp1_pingroup[0],
3360 	&ssp1_pingroup[1],
3361 	&ssp1_pingroup[2],
3362 	&ssp1_pingroup[3],
3363 	&ssp1_pingroup[4],
3364 	&ssp2_pingroup[0],
3365 	&ssp2_pingroup[1],
3366 	&ssp2_pingroup[2],
3367 	&ssp2_pingroup[3],
3368 	&ssp2_pingroup[4],
3369 	&mii2_pingroup,
3370 	&mii0_1_pingroup[0],
3371 	&mii0_1_pingroup[1],
3372 	&i2c1_pingroup[0],
3373 	&i2c1_pingroup[1],
3374 	&i2c2_pingroup[0],
3375 	&i2c2_pingroup[1],
3376 	&i2c2_pingroup[2],
3377 	&i2c2_pingroup[3],
3378 	&i2c2_pingroup[4],
3379 };
3380 
3381 /* functions */
3382 static struct spear_function *spear320_functions[] = {
3383 	SPEAR3XX_COMMON_FUNCTIONS,
3384 	&clcd_function,
3385 	&emi_function,
3386 	&fsmc_function,
3387 	&spp_function,
3388 	&sdhci_function,
3389 	&i2s_function,
3390 	&uart1_function,
3391 	&uart1_modem_function,
3392 	&uart2_function,
3393 	&uart3_function,
3394 	&uart4_function,
3395 	&uart5_function,
3396 	&uart6_function,
3397 	&rs485_function,
3398 	&touchscreen_function,
3399 	&can0_function,
3400 	&can1_function,
3401 	&pwm0_1_function,
3402 	&pwm2_function,
3403 	&pwm3_function,
3404 	&ssp1_function,
3405 	&ssp2_function,
3406 	&mii2_function,
3407 	&mii0_1_function,
3408 	&i2c1_function,
3409 	&i2c2_function,
3410 };
3411 
3412 static const struct of_device_id spear320_pinctrl_of_match[] = {
3413 	{
3414 		.compatible = "st,spear320-pinmux",
3415 	},
3416 	{},
3417 };
3418 
spear320_pinctrl_probe(struct platform_device * pdev)3419 static int spear320_pinctrl_probe(struct platform_device *pdev)
3420 {
3421 	spear3xx_machdata.groups = spear320_pingroups;
3422 	spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3423 	spear3xx_machdata.functions = spear320_functions;
3424 	spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3425 
3426 	spear3xx_machdata.modes_supported = true;
3427 	spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3428 	spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3429 
3430 	pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3431 	pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
3432 			spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
3433 
3434 	return spear_pinctrl_probe(pdev, &spear3xx_machdata);
3435 }
3436 
3437 static struct platform_driver spear320_pinctrl_driver = {
3438 	.driver = {
3439 		.name = DRIVER_NAME,
3440 		.of_match_table = spear320_pinctrl_of_match,
3441 	},
3442 	.probe = spear320_pinctrl_probe,
3443 };
3444 
spear320_pinctrl_init(void)3445 static int __init spear320_pinctrl_init(void)
3446 {
3447 	return platform_driver_register(&spear320_pinctrl_driver);
3448 }
3449 arch_initcall(spear320_pinctrl_init);
3450