xref: /linux/sound/soc/codecs/lpass-wsa-macro.c (revision 05a54fa773284d1a7923cdfdd8f0c8dabb98bd26)
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3 
4 #include <linux/cleanup.h>
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/clk.h>
11 #include <linux/of_clk.h>
12 #include <linux/clk-provider.h>
13 #include <sound/soc.h>
14 #include <sound/soc-dapm.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/of_platform.h>
17 #include <sound/tlv.h>
18 
19 #include "lpass-macro-common.h"
20 #include "lpass-wsa-macro.h"
21 
22 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL	(0x0000)
23 #define CDC_WSA_MCLK_EN_MASK			BIT(0)
24 #define CDC_WSA_MCLK_ENABLE			BIT(0)
25 #define CDC_WSA_MCLK_DISABLE			0
26 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL	(0x0004)
27 #define CDC_WSA_FS_CNT_EN_MASK			BIT(0)
28 #define CDC_WSA_FS_CNT_ENABLE			BIT(0)
29 #define CDC_WSA_FS_CNT_DISABLE			0
30 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL	(0x0008)
31 #define CDC_WSA_SWR_CLK_EN_MASK			BIT(0)
32 #define CDC_WSA_SWR_CLK_ENABLE			BIT(0)
33 #define CDC_WSA_SWR_RST_EN_MASK			BIT(1)
34 #define CDC_WSA_SWR_RST_ENABLE			BIT(1)
35 #define CDC_WSA_SWR_RST_DISABLE			0
36 #define CDC_WSA_TOP_TOP_CFG0			(0x0080)
37 #define CDC_WSA_TOP_TOP_CFG1			(0x0084)
38 #define CDC_WSA_TOP_FREQ_MCLK			(0x0088)
39 #define CDC_WSA_TOP_DEBUG_BUS_SEL		(0x008C)
40 #define CDC_WSA_TOP_DEBUG_EN0			(0x0090)
41 #define CDC_WSA_TOP_DEBUG_EN1			(0x0094)
42 #define CDC_WSA_TOP_DEBUG_DSM_LB		(0x0098)
43 #define CDC_WSA_TOP_RX_I2S_CTL			(0x009C)
44 #define CDC_WSA_TOP_TX_I2S_CTL			(0x00A0)
45 #define CDC_WSA_TOP_I2S_CLK			(0x00A4)
46 #define CDC_WSA_TOP_I2S_RESET			(0x00A8)
47 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0		(0x0100)
48 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1		(0x0104)
49 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0		(0x0108)
50 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1		(0x010C)
51 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0		(0x0110)
52 #define CDC_WSA_RX_MIX_TX1_SEL_MASK		GENMASK(5, 3)
53 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT		3
54 #define CDC_WSA_RX_MIX_TX0_SEL_MASK		GENMASK(2, 0)
55 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0		(0x0114)
56 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0	(0x0118)
57 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL		(0x0244)
58 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK		BIT(5)
59 #define CDC_WSA_TX_SPKR_PROT_RESET		BIT(5)
60 #define CDC_WSA_TX_SPKR_PROT_NO_RESET		0
61 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK	BIT(4)
62 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE		BIT(4)
63 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE	0
64 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK	GENMASK(3, 0)
65 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K	0
66 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K	1
67 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K	2
68 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K	3
69 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K	4
70 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0		(0x0248)
71 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL		(0x0264)
72 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0		(0x0268)
73 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL		(0x0284)
74 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0		(0x0288)
75 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL		(0x02A4)
76 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0		(0x02A8)
77 #define CDC_WSA_INTR_CTRL_CFG			(0x0340)
78 #define CDC_WSA_INTR_CTRL_CLR_COMMIT		(0x0344)
79 #define CDC_WSA_INTR_CTRL_PIN1_MASK0		(0x0360)
80 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0		(0x0368)
81 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0		(0x0370)
82 #define CDC_WSA_INTR_CTRL_PIN2_MASK0		(0x0380)
83 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0		(0x0388)
84 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0		(0x0390)
85 #define CDC_WSA_INTR_CTRL_LEVEL0		(0x03C0)
86 #define CDC_WSA_INTR_CTRL_BYPASS0		(0x03C8)
87 #define CDC_WSA_INTR_CTRL_SET0			(0x03D0)
88 #define CDC_WSA_RX0_RX_PATH_CTL			(0x0400)
89 #define CDC_WSA_RX_PATH_CLK_EN_MASK		BIT(5)
90 #define CDC_WSA_RX_PATH_CLK_ENABLE		BIT(5)
91 #define CDC_WSA_RX_PATH_CLK_DISABLE		0
92 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK	BIT(4)
93 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE		BIT(4)
94 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE	0
95 #define CDC_WSA_RX0_RX_PATH_CFG0		(0x0404)
96 #define CDC_WSA_RX_PATH_COMP_EN_MASK		BIT(1)
97 #define CDC_WSA_RX_PATH_COMP_ENABLE		BIT(1)
98 #define CDC_WSA_RX_PATH_HD2_EN_MASK		BIT(2)
99 #define CDC_WSA_RX_PATH_HD2_ENABLE		BIT(2)
100 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK		BIT(3)
101 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072	BIT(3)
102 #define CDC_WSA_RX0_RX_PATH_CFG1		(0x0408)
103 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK	BIT(0)
104 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE	BIT(0)
105 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE	0
106 #define CDC_WSA_RX0_RX_PATH_CFG2		(0x040C)
107 #define CDC_WSA_RX0_RX_PATH_CFG3		(0x0410)
108 #define CDC_WSA_RX_DC_DCOEFF_MASK		GENMASK(1, 0)
109 #define CDC_WSA_RX0_RX_VOL_CTL			(0x0414)
110 #define CDC_WSA_RX0_RX_PATH_MIX_CTL		(0x0418)
111 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK		BIT(5)
112 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE		BIT(5)
113 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE		0
114 #define CDC_WSA_RX0_RX_PATH_MIX_CFG		(0x041C)
115 #define CDC_WSA_RX0_RX_VOL_MIX_CTL		(0x0420)
116 #define CDC_WSA_RX0_RX_PATH_SEC0		(0x0424)
117 #define CDC_WSA_RX0_RX_PATH_SEC1		(0x0428)
118 #define CDC_WSA_RX_PGA_HALF_DB_MASK		BIT(0)
119 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE		BIT(0)
120 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE		0
121 #define CDC_WSA_RX0_RX_PATH_SEC2		(0x042C)
122 #define CDC_WSA_RX0_RX_PATH_SEC3		(0x0430)
123 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK		GENMASK(1, 0)
124 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK		GENMASK(5, 2)
125 #define CDC_WSA_RX0_RX_PATH_SEC5		(0x0438)
126 #define CDC_WSA_RX0_RX_PATH_SEC6		(0x043C)
127 #define CDC_WSA_RX0_RX_PATH_SEC7		(0x0440)
128 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0		(0x0444)
129 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1		(0x0448)
130 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL		(0x044C)
131 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK		BIT(0)
132 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE		BIT(0)
133 #define CDC_WSA_RX1_RX_PATH_CTL			(0x0480)
134 #define CDC_WSA_RX1_RX_PATH_CFG0		(0x0484)
135 #define CDC_WSA_RX1_RX_PATH_CFG1		(0x0488)
136 #define CDC_WSA_RX1_RX_PATH_CFG2		(0x048C)
137 #define CDC_WSA_RX1_RX_PATH_CFG3		(0x0490)
138 #define CDC_WSA_RX1_RX_VOL_CTL			(0x0494)
139 #define CDC_WSA_RX1_RX_PATH_MIX_CTL		(0x0498)
140 #define CDC_WSA_RX1_RX_PATH_MIX_CFG		(0x049C)
141 #define CDC_WSA_RX1_RX_VOL_MIX_CTL		(0x04A0)
142 #define CDC_WSA_RX1_RX_PATH_SEC0		(0x04A4)
143 #define CDC_WSA_RX1_RX_PATH_SEC1		(0x04A8)
144 #define CDC_WSA_RX1_RX_PATH_SEC2		(0x04AC)
145 #define CDC_WSA_RX1_RX_PATH_SEC3		(0x04B0)
146 #define CDC_WSA_RX1_RX_PATH_SEC5		(0x04B8)
147 #define CDC_WSA_RX1_RX_PATH_SEC6		(0x04BC)
148 #define CDC_WSA_RX1_RX_PATH_SEC7		(0x04C0)
149 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0		(0x04C4)
150 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1		(0x04C8)
151 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL		(0x04CC)
152 #define CDC_WSA_BOOST0_BOOST_PATH_CTL		(0x0500)
153 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK		BIT(4)
154 #define CDC_WSA_BOOST_PATH_CLK_ENABLE		BIT(4)
155 #define CDC_WSA_BOOST_PATH_CLK_DISABLE		0
156 #define CDC_WSA_BOOST0_BOOST_CTL		(0x0504)
157 #define CDC_WSA_BOOST0_BOOST_CFG1		(0x0508)
158 #define CDC_WSA_BOOST0_BOOST_CFG2		(0x050C)
159 #define CDC_WSA_BOOST1_BOOST_PATH_CTL		(0x0540)
160 #define CDC_WSA_BOOST1_BOOST_CTL		(0x0544)
161 #define CDC_WSA_BOOST1_BOOST_CFG1		(0x0548)
162 #define CDC_WSA_BOOST1_BOOST_CFG2		(0x054C)
163 #define CDC_WSA_COMPANDER0_CTL0			(0x0580)
164 #define CDC_WSA_COMPANDER_CLK_EN_MASK		BIT(0)
165 #define CDC_WSA_COMPANDER_CLK_ENABLE		BIT(0)
166 #define CDC_WSA_COMPANDER_SOFT_RST_MASK		BIT(1)
167 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE	BIT(1)
168 #define CDC_WSA_COMPANDER_HALT_MASK		BIT(2)
169 #define CDC_WSA_COMPANDER_HALT			BIT(2)
170 #define CDC_WSA_COMPANDER0_CTL1			(0x0584)
171 #define CDC_WSA_COMPANDER0_CTL2			(0x0588)
172 #define CDC_WSA_COMPANDER0_CTL3			(0x058C)
173 #define CDC_WSA_COMPANDER0_CTL4			(0x0590)
174 #define CDC_WSA_COMPANDER0_CTL5			(0x0594)
175 #define CDC_WSA_COMPANDER0_CTL6			(0x0598)
176 #define CDC_WSA_COMPANDER0_CTL7			(0x059C)
177 /* CDC_WSA_COMPANDER1_CTLx and CDC_WSA_SOFTCLIPx differ per LPASS codec versions */
178 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL	(0x0680)
179 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK		BIT(0)
180 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE		BIT(0)
181 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0		(0x0684)
182 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK	GENMASK(4, 1)
183 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K	BIT(3)
184 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL	(0x06C0)
185 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0		(0x06C4)
186 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL	(0x0700)
187 #define CDC_WSA_SPLINE_ASRC0_CTL0		(0x0704)
188 #define CDC_WSA_SPLINE_ASRC0_CTL1		(0x0708)
189 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL		(0x070C)
190 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB	(0x0710)
191 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB	(0x0714)
192 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB	(0x0718)
193 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB	(0x071C)
194 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO		(0x0720)
195 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL		(0x0740)
196 #define CDC_WSA_SPLINE_ASRC1_CTL0		(0x0744)
197 #define CDC_WSA_SPLINE_ASRC1_CTL1		(0x0748)
198 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL		(0x074C)
199 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750)
200 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754)
201 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758)
202 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C)
203 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO	(0x0760)
204 #define WSA_MAX_OFFSET				(0x0760)
205 
206 /* LPASS codec version <=2.4 register offsets */
207 #define CDC_WSA_COMPANDER1_CTL0			(0x05C0)
208 #define CDC_WSA_COMPANDER1_CTL1			(0x05C4)
209 #define CDC_WSA_COMPANDER1_CTL2			(0x05C8)
210 #define CDC_WSA_COMPANDER1_CTL3			(0x05CC)
211 #define CDC_WSA_COMPANDER1_CTL4			(0x05D0)
212 #define CDC_WSA_COMPANDER1_CTL5			(0x05D4)
213 #define CDC_WSA_COMPANDER1_CTL6			(0x05D8)
214 #define CDC_WSA_COMPANDER1_CTL7			(0x05DC)
215 #define CDC_WSA_SOFTCLIP0_CRC			(0x0600)
216 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK		BIT(0)
217 #define CDC_WSA_SOFTCLIP_CLK_ENABLE		BIT(0)
218 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL		(0x0604)
219 #define CDC_WSA_SOFTCLIP_EN_MASK		BIT(0)
220 #define CDC_WSA_SOFTCLIP_ENABLE			BIT(0)
221 #define CDC_WSA_SOFTCLIP1_CRC			(0x0640)
222 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL		(0x0644)
223 
224 /* LPASS codec version >=2.5 register offsets */
225 #define CDC_WSA_TOP_FS_UNGATE			(0x00AC)
226 #define CDC_WSA_TOP_GRP_SEL			(0x00B0)
227 #define CDC_WSA_TOP_FS_UNGATE2			(0x00DC)
228 #define CDC_2_5_WSA_COMPANDER0_CTL8		(0x05A0)
229 #define CDC_2_5_WSA_COMPANDER0_CTL9		(0x05A4)
230 #define CDC_2_5_WSA_COMPANDER0_CTL10		(0x05A8)
231 #define CDC_2_5_WSA_COMPANDER0_CTL11		(0x05AC)
232 #define CDC_2_5_WSA_COMPANDER0_CTL12		(0x05B0)
233 #define CDC_2_5_WSA_COMPANDER0_CTL13		(0x05B4)
234 #define CDC_2_5_WSA_COMPANDER0_CTL14		(0x05B8)
235 #define CDC_2_5_WSA_COMPANDER0_CTL15		(0x05BC)
236 #define CDC_2_5_WSA_COMPANDER0_CTL16		(0x05C0)
237 #define CDC_2_5_WSA_COMPANDER0_CTL17		(0x05C4)
238 #define CDC_2_5_WSA_COMPANDER0_CTL18		(0x05C8)
239 #define CDC_2_5_WSA_COMPANDER0_CTL19		(0x05CC)
240 #define CDC_2_5_WSA_COMPANDER1_CTL0		(0x05E0)
241 #define CDC_2_5_WSA_COMPANDER1_CTL1		(0x05E4)
242 #define CDC_2_5_WSA_COMPANDER1_CTL2		(0x05E8)
243 #define CDC_2_5_WSA_COMPANDER1_CTL3		(0x05EC)
244 #define CDC_2_5_WSA_COMPANDER1_CTL4		(0x05F0)
245 #define CDC_2_5_WSA_COMPANDER1_CTL5		(0x05F4)
246 #define CDC_2_5_WSA_COMPANDER1_CTL6		(0x05F8)
247 #define CDC_2_5_WSA_COMPANDER1_CTL7		(0x05FC)
248 #define CDC_2_5_WSA_COMPANDER1_CTL8		(0x0600)
249 #define CDC_2_5_WSA_COMPANDER1_CTL9		(0x0604)
250 #define CDC_2_5_WSA_COMPANDER1_CTL10		(0x0608)
251 #define CDC_2_5_WSA_COMPANDER1_CTL11		(0x060C)
252 #define CDC_2_5_WSA_COMPANDER1_CTL12		(0x0610)
253 #define CDC_2_5_WSA_COMPANDER1_CTL13		(0x0614)
254 #define CDC_2_5_WSA_COMPANDER1_CTL14		(0x0618)
255 #define CDC_2_5_WSA_COMPANDER1_CTL15		(0x061C)
256 #define CDC_2_5_WSA_COMPANDER1_CTL16		(0x0620)
257 #define CDC_2_5_WSA_COMPANDER1_CTL17		(0x0624)
258 #define CDC_2_5_WSA_COMPANDER1_CTL18		(0x0628)
259 #define CDC_2_5_WSA_COMPANDER1_CTL19		(0x062C)
260 #define CDC_2_5_WSA_SOFTCLIP0_CRC		(0x0640)
261 #define CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL	(0x0644)
262 #define CDC_2_5_WSA_SOFTCLIP1_CRC		(0x0660)
263 #define CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL	(0x0664)
264 
265 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
266 			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
267 			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
268 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
269 			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
270 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
271 		SNDRV_PCM_FMTBIT_S24_LE |\
272 		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
273 
274 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
275 			SNDRV_PCM_RATE_48000)
276 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
277 		SNDRV_PCM_FMTBIT_S24_LE |\
278 		SNDRV_PCM_FMTBIT_S24_3LE)
279 
280 #define NUM_INTERPOLATORS 2
281 #define WSA_NUM_CLKS_MAX	5
282 #define WSA_MACRO_MCLK_FREQ 19200000
283 #define WSA_MACRO_MUX_CFG_OFFSET 0x8
284 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4
285 #define WSA_MACRO_RX_PATH_OFFSET 0x80
286 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10
287 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
288 #define WSA_MACRO_FS_RATE_MASK 0x0F
289 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03
290 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18
291 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2
292 
293 enum {
294 	WSA_MACRO_GAIN_OFFSET_M1P5_DB,
295 	WSA_MACRO_GAIN_OFFSET_0_DB,
296 };
297 enum {
298 	WSA_MACRO_RX0 = 0,
299 	WSA_MACRO_RX1,
300 	WSA_MACRO_RX_MIX,
301 	WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX,
302 	WSA_MACRO_RX_MIX1,
303 	WSA_MACRO_RX_MAX,
304 };
305 
306 enum {
307 	WSA_MACRO_TX0 = 0,
308 	WSA_MACRO_TX1,
309 	WSA_MACRO_TX_MAX,
310 };
311 
312 enum {
313 	WSA_MACRO_EC0_MUX = 0,
314 	WSA_MACRO_EC1_MUX,
315 	WSA_MACRO_EC_MUX_MAX,
316 };
317 
318 enum {
319 	WSA_MACRO_COMP1, /* SPK_L */
320 	WSA_MACRO_COMP2, /* SPK_R */
321 	WSA_MACRO_COMP_MAX
322 };
323 
324 enum {
325 	WSA_MACRO_SOFTCLIP0, /* RX0 */
326 	WSA_MACRO_SOFTCLIP1, /* RX1 */
327 	WSA_MACRO_SOFTCLIP_MAX
328 };
329 
330 enum {
331 	INTn_1_INP_SEL_ZERO = 0,
332 	INTn_1_INP_SEL_RX0,
333 	INTn_1_INP_SEL_RX1,
334 	INTn_1_INP_SEL_RX2,
335 	INTn_1_INP_SEL_RX3,
336 	INTn_1_INP_SEL_DEC0,
337 	INTn_1_INP_SEL_DEC1,
338 };
339 
340 enum {
341 	INTn_2_INP_SEL_ZERO = 0,
342 	INTn_2_INP_SEL_RX0,
343 	INTn_2_INP_SEL_RX1,
344 	INTn_2_INP_SEL_RX2,
345 	INTn_2_INP_SEL_RX3,
346 };
347 
348 struct interp_sample_rate {
349 	int sample_rate;
350 	int rate_val;
351 };
352 
353 static struct interp_sample_rate int_prim_sample_rate_val[] = {
354 	{8000, 0x0},	/* 8K */
355 	{16000, 0x1},	/* 16K */
356 	{24000, -EINVAL},/* 24K */
357 	{32000, 0x3},	/* 32K */
358 	{48000, 0x4},	/* 48K */
359 	{96000, 0x5},	/* 96K */
360 	{192000, 0x6},	/* 192K */
361 	{384000, 0x7},	/* 384K */
362 	{44100, 0x8}, /* 44.1K */
363 };
364 
365 static struct interp_sample_rate int_mix_sample_rate_val[] = {
366 	{48000, 0x4},	/* 48K */
367 	{96000, 0x5},	/* 96K */
368 	{192000, 0x6},	/* 192K */
369 };
370 
371 /* Matches also rx_mux_text */
372 enum {
373 	WSA_MACRO_AIF1_PB,
374 	WSA_MACRO_AIF_MIX1_PB,
375 	WSA_MACRO_AIF_VI,
376 	WSA_MACRO_AIF_ECHO,
377 	WSA_MACRO_MAX_DAIS,
378 };
379 
380 /**
381  * struct wsa_reg_layout - Register layout differences
382  * @rx_intx_1_mix_inp0_sel_mask: register mask for RX_INTX_1_MIX_INP0_SEL_MASK
383  * @rx_intx_1_mix_inp1_sel_mask: register mask for RX_INTX_1_MIX_INP1_SEL_MASK
384  * @rx_intx_1_mix_inp2_sel_mask: register mask for RX_INTX_1_MIX_INP2_SEL_MASK
385  * @rx_intx_2_sel_mask: register mask for RX_INTX_2_SEL_MASK
386  * @compander1_reg_offset: offset between compander registers (compander1 - compander0)
387  * @softclip0_reg_base: base address of softclip0 register
388  * @softclip1_reg_offset: offset between compander registers (softclip1 - softclip0)
389  */
390 struct wsa_reg_layout {
391 	unsigned int rx_intx_1_mix_inp0_sel_mask;
392 	unsigned int rx_intx_1_mix_inp1_sel_mask;
393 	unsigned int rx_intx_1_mix_inp2_sel_mask;
394 	unsigned int rx_intx_2_sel_mask;
395 	unsigned int compander1_reg_offset;
396 	unsigned int softclip0_reg_base;
397 	unsigned int softclip1_reg_offset;
398 };
399 
400 struct wsa_macro {
401 	struct device *dev;
402 	int comp_enabled[WSA_MACRO_COMP_MAX];
403 	int ec_hq[WSA_MACRO_RX1 + 1];
404 	u16 prim_int_users[WSA_MACRO_RX1 + 1];
405 	u16 wsa_mclk_users;
406 	enum lpass_codec_version codec_version;
407 	const struct wsa_reg_layout *reg_layout;
408 	unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS];
409 	unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS];
410 	int rx_port_value[WSA_MACRO_RX_MAX];
411 	int ear_spkr_gain;
412 	int spkr_gain_offset;
413 	int spkr_mode;
414 	u32 pcm_rate_vi;
415 	int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
416 	int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
417 	struct regmap *regmap;
418 	struct clk *mclk;
419 	struct clk *npl;
420 	struct clk *macro;
421 	struct clk *dcodec;
422 	struct clk *fsgen;
423 	struct clk_hw hw;
424 };
425 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw)
426 
427 static const struct wsa_reg_layout wsa_codec_v2_1 = {
428 	.rx_intx_1_mix_inp0_sel_mask		= GENMASK(2, 0),
429 	.rx_intx_1_mix_inp1_sel_mask		= GENMASK(5, 3),
430 	.rx_intx_1_mix_inp2_sel_mask		= GENMASK(5, 3),
431 	.rx_intx_2_sel_mask			= GENMASK(2, 0),
432 	.compander1_reg_offset			= 0x40,
433 	.softclip0_reg_base			= 0x600,
434 	.softclip1_reg_offset			= 0x40,
435 };
436 
437 static const struct wsa_reg_layout wsa_codec_v2_5 = {
438 	.rx_intx_1_mix_inp0_sel_mask		= GENMASK(3, 0),
439 	.rx_intx_1_mix_inp1_sel_mask		= GENMASK(7, 4),
440 	.rx_intx_1_mix_inp2_sel_mask		= GENMASK(7, 4),
441 	.rx_intx_2_sel_mask			= GENMASK(3, 0),
442 	.compander1_reg_offset			= 0x60,
443 	.softclip0_reg_base			= 0x640,
444 	.softclip1_reg_offset			= 0x20,
445 };
446 
447 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
448 
449 static const char *const rx_text_v2_1[] = {
450 	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
451 };
452 
453 static const char *const rx_text_v2_5[] = {
454 	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "RX6", "RX7", "RX8", "DEC0", "DEC1"
455 };
456 
457 static const char *const rx_mix_text_v2_1[] = {
458 	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
459 };
460 
461 static const char *const rx_mix_text_v2_5[] = {
462 	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "RX6", "RX7", "RX8"
463 };
464 
465 static const char *const rx_mix_ec_text[] = {
466 	"ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
467 };
468 
469 /* Order must match WSA_MACRO_MAX_DAIS enum (offset by 1) */
470 static const char *const rx_mux_text[] = {
471 	"ZERO", "AIF1_PB", "AIF_MIX1_PB"
472 };
473 
474 static const char *const rx_sidetone_mix_text[] = {
475 	"ZERO", "SRC0"
476 };
477 
478 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
479 	"G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
480 	"G_4_DB", "G_5_DB", "G_6_DB"
481 };
482 
483 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
484 				wsa_macro_ear_spkr_pa_gain_text);
485 
486 /* RX INT0 */
487 static const struct soc_enum rx0_prim_inp0_chain_enum_v2_1 =
488 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
489 		0, 7, rx_text_v2_1);
490 
491 static const struct soc_enum rx0_prim_inp1_chain_enum_v2_1 =
492 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
493 		3, 7, rx_text_v2_1);
494 
495 static const struct soc_enum rx0_prim_inp2_chain_enum_v2_1 =
496 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
497 		3, 7, rx_text_v2_1);
498 
499 static const struct soc_enum rx0_mix_chain_enum_v2_1 =
500 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
501 		0, 5, rx_mix_text_v2_1);
502 
503 static const struct soc_enum rx0_prim_inp0_chain_enum_v2_5 =
504 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
505 		0, 12, rx_text_v2_5);
506 
507 static const struct soc_enum rx0_prim_inp1_chain_enum_v2_5 =
508 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
509 		4, 12, rx_text_v2_5);
510 
511 static const struct soc_enum rx0_prim_inp2_chain_enum_v2_5 =
512 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
513 		4, 12, rx_text_v2_5);
514 
515 static const struct soc_enum rx0_mix_chain_enum_v2_5 =
516 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
517 		0, 10, rx_mix_text_v2_5);
518 
519 static const struct soc_enum rx0_sidetone_mix_enum =
520 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
521 
522 static const struct snd_kcontrol_new rx0_prim_inp0_mux_v2_1 =
523 	SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum_v2_1);
524 
525 static const struct snd_kcontrol_new rx0_prim_inp1_mux_v2_1 =
526 	SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum_v2_1);
527 
528 static const struct snd_kcontrol_new rx0_prim_inp2_mux_v2_1 =
529 	SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum_v2_1);
530 
531 static const struct snd_kcontrol_new rx0_mix_mux_v2_1 =
532 	SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum_v2_1);
533 
534 static const struct snd_kcontrol_new rx0_prim_inp0_mux_v2_5 =
535 	SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum_v2_5);
536 
537 static const struct snd_kcontrol_new rx0_prim_inp1_mux_v2_5 =
538 	SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum_v2_5);
539 
540 static const struct snd_kcontrol_new rx0_prim_inp2_mux_v2_5 =
541 	SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum_v2_5);
542 
543 static const struct snd_kcontrol_new rx0_mix_mux_v2_5 =
544 	SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum_v2_5);
545 
546 static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
547 	SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
548 
549 /* RX INT1 */
550 static const struct soc_enum rx1_prim_inp0_chain_enum_v2_1 =
551 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
552 		0, 7, rx_text_v2_1);
553 
554 static const struct soc_enum rx1_prim_inp1_chain_enum_v2_1 =
555 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
556 		3, 7, rx_text_v2_1);
557 
558 static const struct soc_enum rx1_prim_inp2_chain_enum_v2_1 =
559 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
560 		3, 7, rx_text_v2_1);
561 
562 static const struct soc_enum rx1_mix_chain_enum_v2_1 =
563 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
564 		0, 5, rx_mix_text_v2_1);
565 
566 static const struct soc_enum rx1_prim_inp0_chain_enum_v2_5 =
567 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
568 		0, 12, rx_text_v2_5);
569 
570 static const struct soc_enum rx1_prim_inp1_chain_enum_v2_5 =
571 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
572 		4, 12, rx_text_v2_5);
573 
574 static const struct soc_enum rx1_prim_inp2_chain_enum_v2_5 =
575 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
576 		4, 12, rx_text_v2_5);
577 
578 static const struct soc_enum rx1_mix_chain_enum_v2_5 =
579 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
580 		0, 10, rx_mix_text_v2_5);
581 
582 static const struct snd_kcontrol_new rx1_prim_inp0_mux_v2_1 =
583 	SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum_v2_1);
584 
585 static const struct snd_kcontrol_new rx1_prim_inp1_mux_v2_1 =
586 	SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum_v2_1);
587 
588 static const struct snd_kcontrol_new rx1_prim_inp2_mux_v2_1 =
589 	SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum_v2_1);
590 
591 static const struct snd_kcontrol_new rx1_mix_mux_v2_1 =
592 	SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum_v2_1);
593 
594 static const struct snd_kcontrol_new rx1_prim_inp0_mux_v2_5 =
595 	SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum_v2_5);
596 
597 static const struct snd_kcontrol_new rx1_prim_inp1_mux_v2_5 =
598 	SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum_v2_5);
599 
600 static const struct snd_kcontrol_new rx1_prim_inp2_mux_v2_5 =
601 	SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum_v2_5);
602 
603 static const struct snd_kcontrol_new rx1_mix_mux_v2_5 =
604 	SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum_v2_5);
605 
606 static const struct soc_enum rx_mix_ec0_enum =
607 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
608 		0, 3, rx_mix_ec_text);
609 
610 static const struct soc_enum rx_mix_ec1_enum =
611 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
612 		3, 3, rx_mix_ec_text);
613 
614 static const struct snd_kcontrol_new rx_mix_ec0_mux =
615 	SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
616 
617 static const struct snd_kcontrol_new rx_mix_ec1_mux =
618 	SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
619 
620 static const struct reg_default wsa_defaults[] = {
621 	/* WSA Macro */
622 	{ CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
623 	{ CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
624 	{ CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
625 	{ CDC_WSA_TOP_TOP_CFG0, 0x00},
626 	{ CDC_WSA_TOP_TOP_CFG1, 0x00},
627 	{ CDC_WSA_TOP_FREQ_MCLK, 0x00},
628 	{ CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
629 	{ CDC_WSA_TOP_DEBUG_EN0, 0x00},
630 	{ CDC_WSA_TOP_DEBUG_EN1, 0x00},
631 	{ CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
632 	{ CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
633 	{ CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
634 	{ CDC_WSA_TOP_I2S_CLK, 0x02},
635 	{ CDC_WSA_TOP_I2S_RESET, 0x00},
636 	{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
637 	{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
638 	{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
639 	{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
640 	{ CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
641 	{ CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
642 	{ CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
643 	{ CDC_WSA_INTR_CTRL_CFG, 0x00},
644 	{ CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
645 	{ CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
646 	{ CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
647 	{ CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
648 	{ CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
649 	{ CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
650 	{ CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
651 	{ CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
652 	{ CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
653 	{ CDC_WSA_INTR_CTRL_SET0, 0x00},
654 	{ CDC_WSA_RX0_RX_PATH_CTL, 0x04},
655 	{ CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
656 	{ CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
657 	{ CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
658 	{ CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
659 	{ CDC_WSA_RX0_RX_VOL_CTL, 0x00},
660 	{ CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
661 	{ CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
662 	{ CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
663 	{ CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
664 	{ CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
665 	{ CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
666 	{ CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
667 	{ CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
668 	{ CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
669 	{ CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
670 	{ CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
671 	{ CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
672 	{ CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
673 	{ CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
674 	{ CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
675 	{ CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
676 	{ CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
677 	{ CDC_WSA_RX1_RX_VOL_CTL, 0x00},
678 	{ CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
679 	{ CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
680 	{ CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
681 	{ CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
682 	{ CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
683 	{ CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
684 	{ CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
685 	{ CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
686 	{ CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
687 	{ CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
688 	{ CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
689 	{ CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
690 	{ CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
691 	{ CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
692 	{ CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
693 	{ CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
694 	{ CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
695 	{ CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
696 	{ CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
697 	{ CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
698 	{ CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
699 	{ CDC_WSA_COMPANDER0_CTL0, 0x60},
700 	{ CDC_WSA_COMPANDER0_CTL1, 0xDB},
701 	{ CDC_WSA_COMPANDER0_CTL2, 0xFF},
702 	{ CDC_WSA_COMPANDER0_CTL3, 0x35},
703 	{ CDC_WSA_COMPANDER0_CTL4, 0xFF},
704 	{ CDC_WSA_COMPANDER0_CTL5, 0x00},
705 	{ CDC_WSA_COMPANDER0_CTL6, 0x01},
706 	{ CDC_WSA_COMPANDER0_CTL7, 0x28},
707 	{ CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
708 	{ CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
709 	{ CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
710 	{ CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
711 	{ CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
712 	{ CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
713 	{ CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
714 	{ CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
715 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
716 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
717 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
718 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
719 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
720 	{ CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
721 	{ CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
722 	{ CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
723 	{ CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
724 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
725 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
726 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
727 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
728 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
729 };
730 
731 static const struct reg_default wsa_defaults_v2_1[] = {
732 	{ CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
733 	{ CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
734 	{ CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
735 	{ CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
736 	{ CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
737 	{ CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
738 	{ CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
739 	{ CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
740 	{ CDC_WSA_COMPANDER1_CTL0, 0x60},
741 	{ CDC_WSA_COMPANDER1_CTL1, 0xDB},
742 	{ CDC_WSA_COMPANDER1_CTL2, 0xFF},
743 	{ CDC_WSA_COMPANDER1_CTL3, 0x35},
744 	{ CDC_WSA_COMPANDER1_CTL4, 0xFF},
745 	{ CDC_WSA_COMPANDER1_CTL5, 0x00},
746 	{ CDC_WSA_COMPANDER1_CTL6, 0x01},
747 	{ CDC_WSA_COMPANDER1_CTL7, 0x28},
748 	{ CDC_WSA_SOFTCLIP0_CRC, 0x00},
749 	{ CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
750 	{ CDC_WSA_SOFTCLIP1_CRC, 0x00},
751 	{ CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
752 };
753 
754 static const struct reg_default wsa_defaults_v2_5[] = {
755 	{ CDC_WSA_TOP_FS_UNGATE, 0xFF},
756 	{ CDC_WSA_TOP_GRP_SEL, 0x08},
757 	{ CDC_WSA_TOP_FS_UNGATE2, 0x1F},
758 	{ CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x04},
759 	{ CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x02},
760 	{ CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x04},
761 	{ CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x02},
762 	{ CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x04},
763 	{ CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x02},
764 	{ CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x04},
765 	{ CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x02},
766 	{ CDC_2_5_WSA_COMPANDER0_CTL8, 0x00},
767 	{ CDC_2_5_WSA_COMPANDER0_CTL9, 0x00},
768 	{ CDC_2_5_WSA_COMPANDER0_CTL10, 0x06},
769 	{ CDC_2_5_WSA_COMPANDER0_CTL11, 0x12},
770 	{ CDC_2_5_WSA_COMPANDER0_CTL12, 0x1E},
771 	{ CDC_2_5_WSA_COMPANDER0_CTL13, 0x24},
772 	{ CDC_2_5_WSA_COMPANDER0_CTL14, 0x24},
773 	{ CDC_2_5_WSA_COMPANDER0_CTL15, 0x24},
774 	{ CDC_2_5_WSA_COMPANDER0_CTL16, 0x00},
775 	{ CDC_2_5_WSA_COMPANDER0_CTL17, 0x24},
776 	{ CDC_2_5_WSA_COMPANDER0_CTL18, 0x2A},
777 	{ CDC_2_5_WSA_COMPANDER0_CTL19, 0x16},
778 	{ CDC_2_5_WSA_COMPANDER1_CTL0, 0x60},
779 	{ CDC_2_5_WSA_COMPANDER1_CTL1, 0xDB},
780 	{ CDC_2_5_WSA_COMPANDER1_CTL2, 0xFF},
781 	{ CDC_2_5_WSA_COMPANDER1_CTL3, 0x35},
782 	{ CDC_2_5_WSA_COMPANDER1_CTL4, 0xFF},
783 	{ CDC_2_5_WSA_COMPANDER1_CTL5, 0x00},
784 	{ CDC_2_5_WSA_COMPANDER1_CTL6, 0x01},
785 	{ CDC_2_5_WSA_COMPANDER1_CTL7, 0x28},
786 	{ CDC_2_5_WSA_COMPANDER1_CTL8, 0x00},
787 	{ CDC_2_5_WSA_COMPANDER1_CTL9, 0x00},
788 	{ CDC_2_5_WSA_COMPANDER1_CTL10, 0x06},
789 	{ CDC_2_5_WSA_COMPANDER1_CTL11, 0x12},
790 	{ CDC_2_5_WSA_COMPANDER1_CTL12, 0x1E},
791 	{ CDC_2_5_WSA_COMPANDER1_CTL13, 0x24},
792 	{ CDC_2_5_WSA_COMPANDER1_CTL14, 0x24},
793 	{ CDC_2_5_WSA_COMPANDER1_CTL15, 0x24},
794 	{ CDC_2_5_WSA_COMPANDER1_CTL16, 0x00},
795 	{ CDC_2_5_WSA_COMPANDER1_CTL17, 0x24},
796 	{ CDC_2_5_WSA_COMPANDER1_CTL18, 0x2A},
797 	{ CDC_2_5_WSA_COMPANDER1_CTL19, 0x16},
798 	{ CDC_2_5_WSA_SOFTCLIP0_CRC, 0x00},
799 	{ CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
800 	{ CDC_2_5_WSA_SOFTCLIP1_CRC, 0x00},
801 	{ CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
802 };
803 
804 static bool wsa_is_wronly_register(struct device *dev,
805 					unsigned int reg)
806 {
807 	switch (reg) {
808 	case CDC_WSA_INTR_CTRL_CLR_COMMIT:
809 	case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
810 	case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
811 		return true;
812 	}
813 
814 	return false;
815 }
816 
817 static bool wsa_is_rw_register_v2_1(struct device *dev, unsigned int reg)
818 {
819 	switch (reg) {
820 	case CDC_WSA_COMPANDER1_CTL0:
821 	case CDC_WSA_COMPANDER1_CTL1:
822 	case CDC_WSA_COMPANDER1_CTL2:
823 	case CDC_WSA_COMPANDER1_CTL3:
824 	case CDC_WSA_COMPANDER1_CTL4:
825 	case CDC_WSA_COMPANDER1_CTL5:
826 	case CDC_WSA_COMPANDER1_CTL7:
827 	case CDC_WSA_SOFTCLIP0_CRC:
828 	case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
829 	case CDC_WSA_SOFTCLIP1_CRC:
830 	case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
831 		return true;
832 	}
833 
834 	return false;
835 }
836 
837 static bool wsa_is_rw_register_v2_5(struct device *dev, unsigned int reg)
838 {
839 	switch (reg) {
840 	case CDC_WSA_TOP_FS_UNGATE:
841 	case CDC_WSA_TOP_GRP_SEL:
842 	case CDC_WSA_TOP_FS_UNGATE2:
843 	case CDC_2_5_WSA_COMPANDER0_CTL8:
844 	case CDC_2_5_WSA_COMPANDER0_CTL9:
845 	case CDC_2_5_WSA_COMPANDER0_CTL10:
846 	case CDC_2_5_WSA_COMPANDER0_CTL11:
847 	case CDC_2_5_WSA_COMPANDER0_CTL12:
848 	case CDC_2_5_WSA_COMPANDER0_CTL13:
849 	case CDC_2_5_WSA_COMPANDER0_CTL14:
850 	case CDC_2_5_WSA_COMPANDER0_CTL15:
851 	case CDC_2_5_WSA_COMPANDER0_CTL16:
852 	case CDC_2_5_WSA_COMPANDER0_CTL17:
853 	case CDC_2_5_WSA_COMPANDER0_CTL18:
854 	case CDC_2_5_WSA_COMPANDER0_CTL19:
855 	case CDC_2_5_WSA_COMPANDER1_CTL0:
856 	case CDC_2_5_WSA_COMPANDER1_CTL1:
857 	case CDC_2_5_WSA_COMPANDER1_CTL2:
858 	case CDC_2_5_WSA_COMPANDER1_CTL3:
859 	case CDC_2_5_WSA_COMPANDER1_CTL4:
860 	case CDC_2_5_WSA_COMPANDER1_CTL5:
861 	case CDC_2_5_WSA_COMPANDER1_CTL7:
862 	case CDC_2_5_WSA_COMPANDER1_CTL8:
863 	case CDC_2_5_WSA_COMPANDER1_CTL9:
864 	case CDC_2_5_WSA_COMPANDER1_CTL10:
865 	case CDC_2_5_WSA_COMPANDER1_CTL11:
866 	case CDC_2_5_WSA_COMPANDER1_CTL12:
867 	case CDC_2_5_WSA_COMPANDER1_CTL13:
868 	case CDC_2_5_WSA_COMPANDER1_CTL14:
869 	case CDC_2_5_WSA_COMPANDER1_CTL15:
870 	case CDC_2_5_WSA_COMPANDER1_CTL16:
871 	case CDC_2_5_WSA_COMPANDER1_CTL17:
872 	case CDC_2_5_WSA_COMPANDER1_CTL18:
873 	case CDC_2_5_WSA_COMPANDER1_CTL19:
874 	case CDC_2_5_WSA_SOFTCLIP0_CRC:
875 	case CDC_2_5_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
876 	case CDC_2_5_WSA_SOFTCLIP1_CRC:
877 	case CDC_2_5_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
878 		return true;
879 	}
880 
881 	return false;
882 }
883 
884 static bool wsa_is_rw_register(struct device *dev, unsigned int reg)
885 {
886 	struct wsa_macro *wsa = dev_get_drvdata(dev);
887 
888 	switch (reg) {
889 	case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL:
890 	case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL:
891 	case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL:
892 	case CDC_WSA_TOP_TOP_CFG0:
893 	case CDC_WSA_TOP_TOP_CFG1:
894 	case CDC_WSA_TOP_FREQ_MCLK:
895 	case CDC_WSA_TOP_DEBUG_BUS_SEL:
896 	case CDC_WSA_TOP_DEBUG_EN0:
897 	case CDC_WSA_TOP_DEBUG_EN1:
898 	case CDC_WSA_TOP_DEBUG_DSM_LB:
899 	case CDC_WSA_TOP_RX_I2S_CTL:
900 	case CDC_WSA_TOP_TX_I2S_CTL:
901 	case CDC_WSA_TOP_I2S_CLK:
902 	case CDC_WSA_TOP_I2S_RESET:
903 	case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0:
904 	case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1:
905 	case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0:
906 	case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1:
907 	case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0:
908 	case CDC_WSA_RX_INP_MUX_RX_EC_CFG0:
909 	case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0:
910 	case CDC_WSA_TX0_SPKR_PROT_PATH_CTL:
911 	case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0:
912 	case CDC_WSA_TX1_SPKR_PROT_PATH_CTL:
913 	case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0:
914 	case CDC_WSA_TX2_SPKR_PROT_PATH_CTL:
915 	case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0:
916 	case CDC_WSA_TX3_SPKR_PROT_PATH_CTL:
917 	case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0:
918 	case CDC_WSA_INTR_CTRL_CFG:
919 	case CDC_WSA_INTR_CTRL_PIN1_MASK0:
920 	case CDC_WSA_INTR_CTRL_PIN2_MASK0:
921 	case CDC_WSA_INTR_CTRL_LEVEL0:
922 	case CDC_WSA_INTR_CTRL_BYPASS0:
923 	case CDC_WSA_INTR_CTRL_SET0:
924 	case CDC_WSA_RX0_RX_PATH_CTL:
925 	case CDC_WSA_RX0_RX_PATH_CFG0:
926 	case CDC_WSA_RX0_RX_PATH_CFG1:
927 	case CDC_WSA_RX0_RX_PATH_CFG2:
928 	case CDC_WSA_RX0_RX_PATH_CFG3:
929 	case CDC_WSA_RX0_RX_VOL_CTL:
930 	case CDC_WSA_RX0_RX_PATH_MIX_CTL:
931 	case CDC_WSA_RX0_RX_PATH_MIX_CFG:
932 	case CDC_WSA_RX0_RX_VOL_MIX_CTL:
933 	case CDC_WSA_RX0_RX_PATH_SEC0:
934 	case CDC_WSA_RX0_RX_PATH_SEC1:
935 	case CDC_WSA_RX0_RX_PATH_SEC2:
936 	case CDC_WSA_RX0_RX_PATH_SEC3:
937 	case CDC_WSA_RX0_RX_PATH_SEC5:
938 	case CDC_WSA_RX0_RX_PATH_SEC6:
939 	case CDC_WSA_RX0_RX_PATH_SEC7:
940 	case CDC_WSA_RX0_RX_PATH_MIX_SEC0:
941 	case CDC_WSA_RX0_RX_PATH_MIX_SEC1:
942 	case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL:
943 	case CDC_WSA_RX1_RX_PATH_CTL:
944 	case CDC_WSA_RX1_RX_PATH_CFG0:
945 	case CDC_WSA_RX1_RX_PATH_CFG1:
946 	case CDC_WSA_RX1_RX_PATH_CFG2:
947 	case CDC_WSA_RX1_RX_PATH_CFG3:
948 	case CDC_WSA_RX1_RX_VOL_CTL:
949 	case CDC_WSA_RX1_RX_PATH_MIX_CTL:
950 	case CDC_WSA_RX1_RX_PATH_MIX_CFG:
951 	case CDC_WSA_RX1_RX_VOL_MIX_CTL:
952 	case CDC_WSA_RX1_RX_PATH_SEC0:
953 	case CDC_WSA_RX1_RX_PATH_SEC1:
954 	case CDC_WSA_RX1_RX_PATH_SEC2:
955 	case CDC_WSA_RX1_RX_PATH_SEC3:
956 	case CDC_WSA_RX1_RX_PATH_SEC5:
957 	case CDC_WSA_RX1_RX_PATH_SEC6:
958 	case CDC_WSA_RX1_RX_PATH_SEC7:
959 	case CDC_WSA_RX1_RX_PATH_MIX_SEC0:
960 	case CDC_WSA_RX1_RX_PATH_MIX_SEC1:
961 	case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL:
962 	case CDC_WSA_BOOST0_BOOST_PATH_CTL:
963 	case CDC_WSA_BOOST0_BOOST_CTL:
964 	case CDC_WSA_BOOST0_BOOST_CFG1:
965 	case CDC_WSA_BOOST0_BOOST_CFG2:
966 	case CDC_WSA_BOOST1_BOOST_PATH_CTL:
967 	case CDC_WSA_BOOST1_BOOST_CTL:
968 	case CDC_WSA_BOOST1_BOOST_CFG1:
969 	case CDC_WSA_BOOST1_BOOST_CFG2:
970 	case CDC_WSA_COMPANDER0_CTL0:
971 	case CDC_WSA_COMPANDER0_CTL1:
972 	case CDC_WSA_COMPANDER0_CTL2:
973 	case CDC_WSA_COMPANDER0_CTL3:
974 	case CDC_WSA_COMPANDER0_CTL4:
975 	case CDC_WSA_COMPANDER0_CTL5:
976 	case CDC_WSA_COMPANDER0_CTL7:
977 	case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL:
978 	case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0:
979 	case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL:
980 	case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0:
981 	case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL:
982 	case CDC_WSA_SPLINE_ASRC0_CTL0:
983 	case CDC_WSA_SPLINE_ASRC0_CTL1:
984 	case CDC_WSA_SPLINE_ASRC0_FIFO_CTL:
985 	case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL:
986 	case CDC_WSA_SPLINE_ASRC1_CTL0:
987 	case CDC_WSA_SPLINE_ASRC1_CTL1:
988 	case CDC_WSA_SPLINE_ASRC1_FIFO_CTL:
989 		return true;
990 	}
991 
992 	if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5)
993 		return wsa_is_rw_register_v2_5(dev, reg);
994 
995 	return wsa_is_rw_register_v2_1(dev, reg);
996 }
997 
998 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg)
999 {
1000 	bool ret;
1001 
1002 	ret = wsa_is_rw_register(dev, reg);
1003 	if (!ret)
1004 		return wsa_is_wronly_register(dev, reg);
1005 
1006 	return ret;
1007 }
1008 
1009 static bool wsa_is_readable_register_v2_1(struct device *dev, unsigned int reg)
1010 {
1011 	switch (reg) {
1012 	case CDC_WSA_COMPANDER1_CTL6:
1013 		return true;
1014 	}
1015 
1016 	return wsa_is_rw_register(dev, reg);
1017 }
1018 
1019 static bool wsa_is_readable_register_v2_5(struct device *dev, unsigned int reg)
1020 {
1021 	switch (reg) {
1022 	case CDC_2_5_WSA_COMPANDER1_CTL6:
1023 		return true;
1024 	}
1025 
1026 	return wsa_is_rw_register(dev, reg);
1027 }
1028 
1029 static bool wsa_is_readable_register(struct device *dev, unsigned int reg)
1030 {
1031 	struct wsa_macro *wsa = dev_get_drvdata(dev);
1032 
1033 	switch (reg) {
1034 	case CDC_WSA_INTR_CTRL_CLR_COMMIT:
1035 	case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
1036 	case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
1037 	case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
1038 	case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
1039 	case CDC_WSA_COMPANDER0_CTL6:
1040 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
1041 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
1042 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
1043 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
1044 	case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
1045 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
1046 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
1047 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
1048 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
1049 	case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
1050 		return true;
1051 	}
1052 
1053 	if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5)
1054 		return wsa_is_readable_register_v2_5(dev, reg);
1055 
1056 	return wsa_is_readable_register_v2_1(dev, reg);
1057 }
1058 
1059 static bool wsa_is_volatile_register_v2_1(struct device *dev, unsigned int reg)
1060 {
1061 	switch (reg) {
1062 	case CDC_WSA_COMPANDER1_CTL6:
1063 		return true;
1064 	}
1065 
1066 	return false;
1067 }
1068 
1069 static bool wsa_is_volatile_register_v2_5(struct device *dev, unsigned int reg)
1070 {
1071 	switch (reg) {
1072 	case CDC_2_5_WSA_COMPANDER1_CTL6:
1073 		return true;
1074 	}
1075 
1076 	return false;
1077 }
1078 
1079 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)
1080 {
1081 	struct wsa_macro *wsa = dev_get_drvdata(dev);
1082 
1083 	/* Update volatile list for rx/tx macros */
1084 	switch (reg) {
1085 	case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
1086 	case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
1087 	case CDC_WSA_COMPANDER0_CTL6:
1088 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
1089 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
1090 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
1091 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
1092 	case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
1093 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
1094 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
1095 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
1096 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
1097 	case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
1098 		return true;
1099 	}
1100 
1101 	if (wsa->codec_version >= LPASS_CODEC_VERSION_2_5)
1102 		return wsa_is_volatile_register_v2_5(dev, reg);
1103 
1104 	return wsa_is_volatile_register_v2_1(dev, reg);
1105 }
1106 
1107 static const struct regmap_config wsa_regmap_config = {
1108 	.name = "wsa_macro",
1109 	.reg_bits = 16,
1110 	.val_bits = 32, /* 8 but with 32 bit read/write */
1111 	.reg_stride = 4,
1112 	.cache_type = REGCACHE_FLAT,
1113 	/* .reg_defaults and .num_reg_defaults set in probe() */
1114 	.max_register = WSA_MAX_OFFSET,
1115 	.writeable_reg = wsa_is_writeable_register,
1116 	.volatile_reg = wsa_is_volatile_register,
1117 	.readable_reg = wsa_is_readable_register,
1118 };
1119 
1120 /**
1121  * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost
1122  * settings based on speaker mode.
1123  *
1124  * @component: codec instance
1125  * @mode: Indicates speaker configuration mode.
1126  *
1127  * Returns 0 on success or -EINVAL on error.
1128  */
1129 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode)
1130 {
1131 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1132 
1133 	wsa->spkr_mode = mode;
1134 
1135 	switch (mode) {
1136 	case WSA_MACRO_SPKR_MODE_1:
1137 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00);
1138 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00);
1139 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
1140 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00);
1141 		snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44);
1142 		snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44);
1143 		break;
1144 	default:
1145 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
1146 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80);
1147 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
1148 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01);
1149 		snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58);
1150 		snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58);
1151 		break;
1152 	}
1153 	return 0;
1154 }
1155 EXPORT_SYMBOL(wsa_macro_set_spkr_mode);
1156 
1157 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1158 						u8 int_prim_fs_rate_reg_val,
1159 						u32 sample_rate)
1160 {
1161 	u8 int_1_mix1_inp;
1162 	u32 j, port;
1163 	u16 int_mux_cfg0, int_mux_cfg1;
1164 	u16 int_fs_reg;
1165 	u8 inp0_sel, inp1_sel, inp2_sel;
1166 	struct snd_soc_component *component = dai->component;
1167 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1168 
1169 	for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
1170 		int_1_mix1_inp = port;
1171 		if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) {
1172 			dev_err(component->dev,	"%s: Invalid RX port, Dai ID is %d\n",
1173 				__func__, dai->id);
1174 			return -EINVAL;
1175 		}
1176 
1177 		int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0;
1178 
1179 		/*
1180 		 * Loop through all interpolator MUX inputs and find out
1181 		 * to which interpolator input, the cdc_dma rx port
1182 		 * is connected
1183 		 */
1184 		for (j = 0; j < NUM_INTERPOLATORS; j++) {
1185 			int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;
1186 			inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1187 								wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask);
1188 			inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1189 								wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask);
1190 			inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
1191 								wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask);
1192 
1193 			if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1194 			    (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1195 			    (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1196 				int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL +
1197 					     WSA_MACRO_RX_PATH_OFFSET * j;
1198 				/* sample_rate is in Hz */
1199 				snd_soc_component_update_bits(component, int_fs_reg,
1200 							      WSA_MACRO_FS_RATE_MASK,
1201 							      int_prim_fs_rate_reg_val);
1202 			}
1203 			int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET;
1204 		}
1205 	}
1206 
1207 	return 0;
1208 }
1209 
1210 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1211 					       u8 int_mix_fs_rate_reg_val,
1212 					       u32 sample_rate)
1213 {
1214 	u8 int_2_inp;
1215 	u32 j, port;
1216 	u16 int_mux_cfg1, int_fs_reg;
1217 	u8 int_mux_cfg1_val;
1218 	struct snd_soc_component *component = dai->component;
1219 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1220 
1221 	for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
1222 		int_2_inp = port;
1223 		if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) {
1224 			dev_err(component->dev,	"%s: Invalid RX port, Dai ID is %d\n",
1225 				__func__, dai->id);
1226 			return -EINVAL;
1227 		}
1228 
1229 		int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
1230 		for (j = 0; j < NUM_INTERPOLATORS; j++) {
1231 			int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
1232 									wsa->reg_layout->rx_intx_2_sel_mask);
1233 
1234 			if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1235 				int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +
1236 					WSA_MACRO_RX_PATH_OFFSET * j;
1237 
1238 				snd_soc_component_update_bits(component,
1239 						      int_fs_reg,
1240 						      WSA_MACRO_FS_RATE_MASK,
1241 						      int_mix_fs_rate_reg_val);
1242 			}
1243 			int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET;
1244 		}
1245 	}
1246 	return 0;
1247 }
1248 
1249 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1250 					   u32 sample_rate)
1251 {
1252 	int rate_val = 0;
1253 	int i, ret;
1254 
1255 	/* set mixing path rate */
1256 	for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
1257 		if (sample_rate == int_mix_sample_rate_val[i].sample_rate) {
1258 			rate_val = int_mix_sample_rate_val[i].rate_val;
1259 			break;
1260 		}
1261 	}
1262 	if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0))
1263 		goto prim_rate;
1264 
1265 	ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate);
1266 	if (ret < 0)
1267 		return ret;
1268 prim_rate:
1269 	/* set primary path sample rate */
1270 	for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
1271 		if (sample_rate == int_prim_sample_rate_val[i].sample_rate) {
1272 			rate_val = int_prim_sample_rate_val[i].rate_val;
1273 			break;
1274 		}
1275 	}
1276 	if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0))
1277 		return -EINVAL;
1278 
1279 	ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate);
1280 
1281 	return ret;
1282 }
1283 
1284 static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
1285 			       struct snd_pcm_hw_params *params,
1286 			       struct snd_soc_dai *dai)
1287 {
1288 	struct snd_soc_component *component = dai->component;
1289 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1290 	int ret;
1291 
1292 	switch (substream->stream) {
1293 	case SNDRV_PCM_STREAM_PLAYBACK:
1294 		ret = wsa_macro_set_interpolator_rate(dai, params_rate(params));
1295 		if (ret) {
1296 			dev_err(component->dev,
1297 				"%s: cannot set sample rate: %u\n",
1298 				__func__, params_rate(params));
1299 			return ret;
1300 		}
1301 		break;
1302 	case SNDRV_PCM_STREAM_CAPTURE:
1303 		if (dai->id == WSA_MACRO_AIF_VI)
1304 			wsa->pcm_rate_vi = params_rate(params);
1305 
1306 		break;
1307 	default:
1308 		break;
1309 	}
1310 	return 0;
1311 }
1312 
1313 static int wsa_macro_get_channel_map(const struct snd_soc_dai *dai,
1314 				     unsigned int *tx_num, unsigned int *tx_slot,
1315 				     unsigned int *rx_num, unsigned int *rx_slot)
1316 {
1317 	struct snd_soc_component *component = dai->component;
1318 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1319 	u16 val, mask = 0, cnt = 0, temp;
1320 
1321 	switch (dai->id) {
1322 	case WSA_MACRO_AIF_VI:
1323 		*tx_slot = wsa->active_ch_mask[dai->id];
1324 		*tx_num = wsa->active_ch_cnt[dai->id];
1325 		break;
1326 	case WSA_MACRO_AIF1_PB:
1327 	case WSA_MACRO_AIF_MIX1_PB:
1328 		for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
1329 					WSA_MACRO_RX_MAX) {
1330 			mask |= (1 << temp);
1331 			if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT)
1332 				break;
1333 		}
1334 		if (mask & 0x0C)
1335 			mask = mask >> 0x2;
1336 		*rx_slot = mask;
1337 		*rx_num = cnt;
1338 		break;
1339 	case WSA_MACRO_AIF_ECHO:
1340 		val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1341 		if (val & WSA_MACRO_EC_MIX_TX1_MASK) {
1342 			mask |= 0x2;
1343 			cnt++;
1344 		}
1345 		if (val & WSA_MACRO_EC_MIX_TX0_MASK) {
1346 			mask |= 0x1;
1347 			cnt++;
1348 		}
1349 		*tx_slot = mask;
1350 		*tx_num = cnt;
1351 		break;
1352 	default:
1353 		dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1354 		break;
1355 	}
1356 	return 0;
1357 }
1358 
1359 static const struct snd_soc_dai_ops wsa_macro_dai_ops = {
1360 	.hw_params = wsa_macro_hw_params,
1361 	.get_channel_map = wsa_macro_get_channel_map,
1362 };
1363 
1364 static struct snd_soc_dai_driver wsa_macro_dai[] = {
1365 	{
1366 		.name = "wsa_macro_rx1",
1367 		.id = WSA_MACRO_AIF1_PB,
1368 		.playback = {
1369 			.stream_name = "WSA_AIF1 Playback",
1370 			.rates = WSA_MACRO_RX_RATES,
1371 			.formats = WSA_MACRO_RX_FORMATS,
1372 			.rate_max = 384000,
1373 			.rate_min = 8000,
1374 			.channels_min = 1,
1375 			.channels_max = 2,
1376 		},
1377 		.ops = &wsa_macro_dai_ops,
1378 	},
1379 	{
1380 		.name = "wsa_macro_rx_mix",
1381 		.id = WSA_MACRO_AIF_MIX1_PB,
1382 		.playback = {
1383 			.stream_name = "WSA_AIF_MIX1 Playback",
1384 			.rates = WSA_MACRO_RX_MIX_RATES,
1385 			.formats = WSA_MACRO_RX_FORMATS,
1386 			.rate_max = 192000,
1387 			.rate_min = 48000,
1388 			.channels_min = 1,
1389 			.channels_max = 2,
1390 		},
1391 		.ops = &wsa_macro_dai_ops,
1392 	},
1393 	{
1394 		.name = "wsa_macro_vifeedback",
1395 		.id = WSA_MACRO_AIF_VI,
1396 		.capture = {
1397 			.stream_name = "WSA_AIF_VI Capture",
1398 			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
1399 			.formats = WSA_MACRO_RX_FORMATS,
1400 			.rate_max = 48000,
1401 			.rate_min = 8000,
1402 			.channels_min = 1,
1403 			.channels_max = 4,
1404 		},
1405 		.ops = &wsa_macro_dai_ops,
1406 	},
1407 	{
1408 		.name = "wsa_macro_echo",
1409 		.id = WSA_MACRO_AIF_ECHO,
1410 		.capture = {
1411 			.stream_name = "WSA_AIF_ECHO Capture",
1412 			.rates = WSA_MACRO_ECHO_RATES,
1413 			.formats = WSA_MACRO_ECHO_FORMATS,
1414 			.rate_max = 48000,
1415 			.rate_min = 8000,
1416 			.channels_min = 1,
1417 			.channels_max = 2,
1418 		},
1419 		.ops = &wsa_macro_dai_ops,
1420 	},
1421 };
1422 
1423 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
1424 {
1425 	struct regmap *regmap = wsa->regmap;
1426 
1427 	if (mclk_enable) {
1428 		if (wsa->wsa_mclk_users == 0) {
1429 			regcache_mark_dirty(regmap);
1430 			regcache_sync(regmap);
1431 			/* 9.6MHz MCLK, set value 0x00 if other frequency */
1432 			regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01);
1433 			regmap_update_bits(regmap,
1434 					   CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1435 					   CDC_WSA_MCLK_EN_MASK,
1436 					   CDC_WSA_MCLK_ENABLE);
1437 			regmap_update_bits(regmap,
1438 					   CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1439 					   CDC_WSA_FS_CNT_EN_MASK,
1440 					   CDC_WSA_FS_CNT_ENABLE);
1441 		}
1442 		wsa->wsa_mclk_users++;
1443 	} else {
1444 		if (wsa->wsa_mclk_users <= 0) {
1445 			dev_err(wsa->dev, "clock already disabled\n");
1446 			wsa->wsa_mclk_users = 0;
1447 			return;
1448 		}
1449 		wsa->wsa_mclk_users--;
1450 		if (wsa->wsa_mclk_users == 0) {
1451 			regmap_update_bits(regmap,
1452 					   CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1453 					   CDC_WSA_FS_CNT_EN_MASK,
1454 					   CDC_WSA_FS_CNT_DISABLE);
1455 			regmap_update_bits(regmap,
1456 					   CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1457 					   CDC_WSA_MCLK_EN_MASK,
1458 					   CDC_WSA_MCLK_DISABLE);
1459 		}
1460 	}
1461 }
1462 
1463 static void wsa_macro_enable_disable_vi_sense(struct snd_soc_component *component, bool enable,
1464 						u32 tx_reg0, u32 tx_reg1, u32 val)
1465 {
1466 	if (enable) {
1467 		/* Enable V&I sensing */
1468 		snd_soc_component_update_bits(component, tx_reg0,
1469 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1470 					      CDC_WSA_TX_SPKR_PROT_RESET);
1471 		snd_soc_component_update_bits(component, tx_reg1,
1472 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1473 					      CDC_WSA_TX_SPKR_PROT_RESET);
1474 		snd_soc_component_update_bits(component, tx_reg0,
1475 					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1476 					      val);
1477 		snd_soc_component_update_bits(component, tx_reg1,
1478 					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1479 					      val);
1480 		snd_soc_component_update_bits(component, tx_reg0,
1481 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1482 					      CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1483 		snd_soc_component_update_bits(component, tx_reg1,
1484 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1485 					      CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1486 		snd_soc_component_update_bits(component, tx_reg0,
1487 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1488 					      CDC_WSA_TX_SPKR_PROT_NO_RESET);
1489 		snd_soc_component_update_bits(component, tx_reg1,
1490 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1491 					      CDC_WSA_TX_SPKR_PROT_NO_RESET);
1492 	} else {
1493 		snd_soc_component_update_bits(component, tx_reg0,
1494 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1495 					      CDC_WSA_TX_SPKR_PROT_RESET);
1496 		snd_soc_component_update_bits(component, tx_reg1,
1497 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1498 					      CDC_WSA_TX_SPKR_PROT_RESET);
1499 		snd_soc_component_update_bits(component, tx_reg0,
1500 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1501 					      CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1502 		snd_soc_component_update_bits(component, tx_reg1,
1503 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1504 					      CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1505 	}
1506 }
1507 
1508 static void wsa_macro_enable_disable_vi_feedback(struct snd_soc_component *component,
1509 						 bool enable, u32 rate)
1510 {
1511 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1512 
1513 	if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1514 		wsa_macro_enable_disable_vi_sense(component, enable,
1515 				CDC_WSA_TX0_SPKR_PROT_PATH_CTL,
1516 				CDC_WSA_TX1_SPKR_PROT_PATH_CTL, rate);
1517 
1518 	if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1519 		wsa_macro_enable_disable_vi_sense(component, enable,
1520 				CDC_WSA_TX2_SPKR_PROT_PATH_CTL,
1521 				CDC_WSA_TX3_SPKR_PROT_PATH_CTL, rate);
1522 }
1523 
1524 static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
1525 				struct snd_kcontrol *kcontrol, int event)
1526 {
1527 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1528 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1529 
1530 	wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
1531 	return 0;
1532 }
1533 
1534 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
1535 					struct snd_kcontrol *kcontrol,
1536 					int event)
1537 {
1538 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1539 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1540 	u32 rate_val;
1541 
1542 	switch (wsa->pcm_rate_vi) {
1543 	case 8000:
1544 		rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K;
1545 		break;
1546 	case 16000:
1547 		rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K;
1548 		break;
1549 	case 24000:
1550 		rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K;
1551 		break;
1552 	case 32000:
1553 		rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K;
1554 		break;
1555 	case 48000:
1556 		rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K;
1557 		break;
1558 	default:
1559 		rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K;
1560 		break;
1561 	}
1562 
1563 	switch (event) {
1564 	case SND_SOC_DAPM_POST_PMU:
1565 		/* Enable V&I sensing */
1566 		wsa_macro_enable_disable_vi_feedback(component, true, rate_val);
1567 		break;
1568 	case SND_SOC_DAPM_POST_PMD:
1569 		/* Disable V&I sensing */
1570 		wsa_macro_enable_disable_vi_feedback(component, false, rate_val);
1571 		break;
1572 	}
1573 
1574 	return 0;
1575 }
1576 
1577 static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
1578 				     struct snd_kcontrol *kcontrol, int event)
1579 {
1580 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1581 	u16 path_reg, gain_reg;
1582 	int val;
1583 
1584 	switch (w->shift) {
1585 	case WSA_MACRO_RX_MIX0:
1586 		path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL;
1587 		gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
1588 		break;
1589 	case WSA_MACRO_RX_MIX1:
1590 		path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL;
1591 		gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
1592 		break;
1593 	default:
1594 		return 0;
1595 	}
1596 
1597 	switch (event) {
1598 	case SND_SOC_DAPM_POST_PMU:
1599 		val = snd_soc_component_read(component, gain_reg);
1600 		snd_soc_component_write(component, gain_reg, val);
1601 		break;
1602 	case SND_SOC_DAPM_POST_PMD:
1603 		snd_soc_component_update_bits(component, path_reg,
1604 					      CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
1605 					      CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
1606 		break;
1607 	}
1608 
1609 	return 0;
1610 }
1611 
1612 static void wsa_macro_hd2_control(struct snd_soc_component *component,
1613 				  u16 reg, int event)
1614 {
1615 	u16 hd2_scale_reg;
1616 	u16 hd2_enable_reg;
1617 
1618 	if (reg == CDC_WSA_RX0_RX_PATH_CTL) {
1619 		hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3;
1620 		hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0;
1621 	}
1622 	if (reg == CDC_WSA_RX1_RX_PATH_CTL) {
1623 		hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3;
1624 		hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0;
1625 	}
1626 
1627 	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
1628 		snd_soc_component_update_bits(component, hd2_scale_reg,
1629 					      CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1630 					      0x10);
1631 		snd_soc_component_update_bits(component, hd2_scale_reg,
1632 					      CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1633 					      0x1);
1634 		snd_soc_component_update_bits(component, hd2_enable_reg,
1635 					      CDC_WSA_RX_PATH_HD2_EN_MASK,
1636 					      CDC_WSA_RX_PATH_HD2_ENABLE);
1637 	}
1638 
1639 	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
1640 		snd_soc_component_update_bits(component, hd2_enable_reg,
1641 					      CDC_WSA_RX_PATH_HD2_EN_MASK, 0);
1642 		snd_soc_component_update_bits(component, hd2_scale_reg,
1643 					      CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1644 					      0);
1645 		snd_soc_component_update_bits(component, hd2_scale_reg,
1646 					      CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1647 					      0);
1648 	}
1649 }
1650 
1651 static int wsa_macro_config_compander(struct snd_soc_component *component,
1652 				      int comp, int event)
1653 {
1654 	u16 comp_ctl0_reg, rx_path_cfg0_reg;
1655 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1656 
1657 	if (!wsa->comp_enabled[comp])
1658 		return 0;
1659 
1660 	comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 +
1661 					(comp * wsa->reg_layout->compander1_reg_offset);
1662 	rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 +
1663 					(comp * WSA_MACRO_RX_PATH_OFFSET);
1664 
1665 	if (SND_SOC_DAPM_EVENT_ON(event)) {
1666 		/* Enable Compander Clock */
1667 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1668 					      CDC_WSA_COMPANDER_CLK_EN_MASK,
1669 					      CDC_WSA_COMPANDER_CLK_ENABLE);
1670 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1671 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1672 					      CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1673 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1674 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1675 					      0);
1676 		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1677 					      CDC_WSA_RX_PATH_COMP_EN_MASK,
1678 					      CDC_WSA_RX_PATH_COMP_ENABLE);
1679 	}
1680 
1681 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
1682 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1683 					      CDC_WSA_COMPANDER_HALT_MASK,
1684 					      CDC_WSA_COMPANDER_HALT);
1685 		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1686 					      CDC_WSA_RX_PATH_COMP_EN_MASK, 0);
1687 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1688 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1689 					      CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1690 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1691 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1692 					      0);
1693 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1694 					      CDC_WSA_COMPANDER_CLK_EN_MASK, 0);
1695 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1696 					      CDC_WSA_COMPANDER_HALT_MASK, 0);
1697 	}
1698 
1699 	return 0;
1700 }
1701 
1702 static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component,
1703 					 struct wsa_macro *wsa,
1704 					 int path,
1705 					 bool enable)
1706 {
1707 	u16 softclip_clk_reg = wsa->reg_layout->softclip0_reg_base +
1708 			(path * wsa->reg_layout->softclip1_reg_offset);
1709 	u8 softclip_mux_mask = (1 << path);
1710 	u8 softclip_mux_value = (1 << path);
1711 
1712 	if (enable) {
1713 		if (wsa->softclip_clk_users[path] == 0) {
1714 			snd_soc_component_update_bits(component,
1715 						softclip_clk_reg,
1716 						CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1717 						CDC_WSA_SOFTCLIP_CLK_ENABLE);
1718 			snd_soc_component_update_bits(component,
1719 				CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1720 				softclip_mux_mask, softclip_mux_value);
1721 		}
1722 		wsa->softclip_clk_users[path]++;
1723 	} else {
1724 		wsa->softclip_clk_users[path]--;
1725 		if (wsa->softclip_clk_users[path] == 0) {
1726 			snd_soc_component_update_bits(component,
1727 						softclip_clk_reg,
1728 						CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1729 						0);
1730 			snd_soc_component_update_bits(component,
1731 				CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1732 				softclip_mux_mask, 0x00);
1733 		}
1734 	}
1735 }
1736 
1737 static int wsa_macro_config_softclip(struct snd_soc_component *component,
1738 				     int path, int event)
1739 {
1740 	u16 softclip_ctrl_reg;
1741 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1742 	int softclip_path = 0;
1743 
1744 	if (path == WSA_MACRO_COMP1)
1745 		softclip_path = WSA_MACRO_SOFTCLIP0;
1746 	else if (path == WSA_MACRO_COMP2)
1747 		softclip_path = WSA_MACRO_SOFTCLIP1;
1748 
1749 	if (!wsa->is_softclip_on[softclip_path])
1750 		return 0;
1751 
1752 	softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL +
1753 				(softclip_path * wsa->reg_layout->softclip1_reg_offset);
1754 
1755 	if (SND_SOC_DAPM_EVENT_ON(event)) {
1756 		/* Enable Softclip clock and mux */
1757 		wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1758 					      true);
1759 		/* Enable Softclip control */
1760 		snd_soc_component_update_bits(component, softclip_ctrl_reg,
1761 					      CDC_WSA_SOFTCLIP_EN_MASK,
1762 					      CDC_WSA_SOFTCLIP_ENABLE);
1763 	}
1764 
1765 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
1766 		snd_soc_component_update_bits(component, softclip_ctrl_reg,
1767 					      CDC_WSA_SOFTCLIP_EN_MASK, 0);
1768 		wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1769 					      false);
1770 	}
1771 
1772 	return 0;
1773 }
1774 
1775 static bool wsa_macro_adie_lb(struct snd_soc_component *component,
1776 			      int interp_idx)
1777 {
1778 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1779 	u16 int_mux_cfg0,  int_mux_cfg1;
1780 	u8 int_n_inp0, int_n_inp1, int_n_inp2;
1781 
1782 	int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1783 	int_mux_cfg1 = int_mux_cfg0 + 4;
1784 
1785 	int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
1786 						  wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask);
1787 	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1788 		int_n_inp0 == INTn_1_INP_SEL_DEC1)
1789 		return true;
1790 
1791 	int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
1792 						  wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask);
1793 	if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1794 		int_n_inp1 == INTn_1_INP_SEL_DEC1)
1795 		return true;
1796 
1797 	int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
1798 						  wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask);
1799 	if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1800 		int_n_inp2 == INTn_1_INP_SEL_DEC1)
1801 		return true;
1802 
1803 	return false;
1804 }
1805 
1806 static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1807 				      struct snd_kcontrol *kcontrol,
1808 				      int event)
1809 {
1810 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1811 	u16 reg;
1812 
1813 	reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift;
1814 	switch (event) {
1815 	case SND_SOC_DAPM_PRE_PMU:
1816 		if (wsa_macro_adie_lb(component, w->shift)) {
1817 			snd_soc_component_update_bits(component, reg,
1818 					     CDC_WSA_RX_PATH_CLK_EN_MASK,
1819 					     CDC_WSA_RX_PATH_CLK_ENABLE);
1820 		}
1821 		break;
1822 	default:
1823 		break;
1824 	}
1825 	return 0;
1826 }
1827 
1828 static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind)
1829 {
1830 	u16 prim_int_reg = 0;
1831 
1832 	switch (reg) {
1833 	case CDC_WSA_RX0_RX_PATH_CTL:
1834 	case CDC_WSA_RX0_RX_PATH_MIX_CTL:
1835 		prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL;
1836 		*ind = 0;
1837 		break;
1838 	case CDC_WSA_RX1_RX_PATH_CTL:
1839 	case CDC_WSA_RX1_RX_PATH_MIX_CTL:
1840 		prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL;
1841 		*ind = 1;
1842 		break;
1843 	}
1844 
1845 	return prim_int_reg;
1846 }
1847 
1848 static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component,
1849 					      u16 reg, int event)
1850 {
1851 	u16 prim_int_reg;
1852 	u16 ind = 0;
1853 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1854 
1855 	prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind);
1856 
1857 	switch (event) {
1858 	case SND_SOC_DAPM_PRE_PMU:
1859 		wsa->prim_int_users[ind]++;
1860 		if (wsa->prim_int_users[ind] == 1) {
1861 			snd_soc_component_update_bits(component,
1862 						      prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET,
1863 						      CDC_WSA_RX_DC_DCOEFF_MASK,
1864 						      0x3);
1865 			snd_soc_component_update_bits(component, prim_int_reg,
1866 					CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK,
1867 					CDC_WSA_RX_PATH_PGA_MUTE_ENABLE);
1868 			wsa_macro_hd2_control(component, prim_int_reg, event);
1869 			snd_soc_component_update_bits(component,
1870 				prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1871 				CDC_WSA_RX_DSMDEM_CLK_EN_MASK,
1872 				CDC_WSA_RX_DSMDEM_CLK_ENABLE);
1873 		}
1874 		if ((reg != prim_int_reg) &&
1875 		    ((snd_soc_component_read(
1876 				component, prim_int_reg)) & 0x10))
1877 			snd_soc_component_update_bits(component, reg,
1878 					0x10, 0x10);
1879 		break;
1880 	case SND_SOC_DAPM_POST_PMD:
1881 		wsa->prim_int_users[ind]--;
1882 		if (wsa->prim_int_users[ind] == 0) {
1883 			snd_soc_component_update_bits(component,
1884 				prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1885 				CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0);
1886 			wsa_macro_hd2_control(component, prim_int_reg, event);
1887 		}
1888 		break;
1889 	}
1890 
1891 	return 0;
1892 }
1893 
1894 static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
1895 					  struct wsa_macro *wsa,
1896 					  int event, int gain_reg)
1897 {
1898 	int comp_gain_offset, val;
1899 
1900 	switch (wsa->spkr_mode) {
1901 	/* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */
1902 	case WSA_MACRO_SPKR_MODE_1:
1903 		comp_gain_offset = -12;
1904 		break;
1905 	/* Default case compander gain is 15 dB */
1906 	default:
1907 		comp_gain_offset = -15;
1908 		break;
1909 	}
1910 
1911 	switch (event) {
1912 	case SND_SOC_DAPM_POST_PMU:
1913 		/* Apply ear spkr gain only if compander is enabled */
1914 		if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1915 		    (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1916 		    (wsa->ear_spkr_gain != 0)) {
1917 			/* For example, val is -8(-12+5-1) for 4dB of gain */
1918 			val = comp_gain_offset + wsa->ear_spkr_gain - 1;
1919 			snd_soc_component_write(component, gain_reg, val);
1920 		}
1921 		break;
1922 	case SND_SOC_DAPM_POST_PMD:
1923 		/*
1924 		 * Reset RX0 volume to 0 dB if compander is enabled and
1925 		 * ear_spkr_gain is non-zero.
1926 		 */
1927 		if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1928 		    (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1929 		    (wsa->ear_spkr_gain != 0)) {
1930 			snd_soc_component_write(component, gain_reg, 0x0);
1931 		}
1932 		break;
1933 	}
1934 
1935 	return 0;
1936 }
1937 
1938 static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
1939 					 struct snd_kcontrol *kcontrol,
1940 					 int event)
1941 {
1942 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1943 	u16 gain_reg;
1944 	u16 reg;
1945 	int val;
1946 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1947 
1948 	if (w->shift == WSA_MACRO_COMP1) {
1949 		reg = CDC_WSA_RX0_RX_PATH_CTL;
1950 		gain_reg = CDC_WSA_RX0_RX_VOL_CTL;
1951 	} else if (w->shift == WSA_MACRO_COMP2) {
1952 		reg = CDC_WSA_RX1_RX_PATH_CTL;
1953 		gain_reg = CDC_WSA_RX1_RX_VOL_CTL;
1954 	}
1955 
1956 	switch (event) {
1957 	case SND_SOC_DAPM_PRE_PMU:
1958 		/* Reset if needed */
1959 		wsa_macro_enable_prim_interpolator(component, reg, event);
1960 		break;
1961 	case SND_SOC_DAPM_POST_PMU:
1962 		wsa_macro_config_compander(component, w->shift, event);
1963 		wsa_macro_config_softclip(component, w->shift, event);
1964 		/* apply gain after int clk is enabled */
1965 		if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1966 		    (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1967 		     wsa->comp_enabled[WSA_MACRO_COMP2])) {
1968 			snd_soc_component_update_bits(component,
1969 					CDC_WSA_RX0_RX_PATH_SEC1,
1970 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1971 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1972 			snd_soc_component_update_bits(component,
1973 					CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1974 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1975 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1976 			snd_soc_component_update_bits(component,
1977 					CDC_WSA_RX1_RX_PATH_SEC1,
1978 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1979 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1980 			snd_soc_component_update_bits(component,
1981 					CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1982 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1983 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1984 		}
1985 		val = snd_soc_component_read(component, gain_reg);
1986 		snd_soc_component_write(component, gain_reg, val);
1987 		wsa_macro_config_ear_spkr_gain(component, wsa,
1988 						event, gain_reg);
1989 		break;
1990 	case SND_SOC_DAPM_POST_PMD:
1991 		wsa_macro_config_compander(component, w->shift, event);
1992 		wsa_macro_config_softclip(component, w->shift, event);
1993 		wsa_macro_enable_prim_interpolator(component, reg, event);
1994 		if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1995 		    (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1996 		     wsa->comp_enabled[WSA_MACRO_COMP2])) {
1997 			snd_soc_component_update_bits(component,
1998 					CDC_WSA_RX0_RX_PATH_SEC1,
1999 					CDC_WSA_RX_PGA_HALF_DB_MASK,
2000 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
2001 			snd_soc_component_update_bits(component,
2002 					CDC_WSA_RX0_RX_PATH_MIX_SEC0,
2003 					CDC_WSA_RX_PGA_HALF_DB_MASK,
2004 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
2005 			snd_soc_component_update_bits(component,
2006 					CDC_WSA_RX1_RX_PATH_SEC1,
2007 					CDC_WSA_RX_PGA_HALF_DB_MASK,
2008 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
2009 			snd_soc_component_update_bits(component,
2010 					CDC_WSA_RX1_RX_PATH_MIX_SEC0,
2011 					CDC_WSA_RX_PGA_HALF_DB_MASK,
2012 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
2013 		}
2014 		wsa_macro_config_ear_spkr_gain(component, wsa,
2015 						event, gain_reg);
2016 		break;
2017 	}
2018 
2019 	return 0;
2020 }
2021 
2022 static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
2023 				     struct snd_kcontrol *kcontrol,
2024 				     int event)
2025 {
2026 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2027 	u16 boost_path_ctl, boost_path_cfg1;
2028 	u16 reg, reg_mix;
2029 
2030 	if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT0 CHAIN")) {
2031 		boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL;
2032 		boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1;
2033 		reg = CDC_WSA_RX0_RX_PATH_CTL;
2034 		reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL;
2035 	} else if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT1 CHAIN")) {
2036 		boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL;
2037 		boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1;
2038 		reg = CDC_WSA_RX1_RX_PATH_CTL;
2039 		reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL;
2040 	} else {
2041 		dev_warn(component->dev, "Incorrect widget name in the driver\n");
2042 		return -EINVAL;
2043 	}
2044 
2045 	switch (event) {
2046 	case SND_SOC_DAPM_PRE_PMU:
2047 		snd_soc_component_update_bits(component, boost_path_cfg1,
2048 					      CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
2049 					      CDC_WSA_RX_PATH_SMART_BST_ENABLE);
2050 		snd_soc_component_update_bits(component, boost_path_ctl,
2051 					      CDC_WSA_BOOST_PATH_CLK_EN_MASK,
2052 					      CDC_WSA_BOOST_PATH_CLK_ENABLE);
2053 		if ((snd_soc_component_read(component, reg_mix)) & 0x10)
2054 			snd_soc_component_update_bits(component, reg_mix,
2055 						0x10, 0x00);
2056 		break;
2057 	case SND_SOC_DAPM_POST_PMU:
2058 		snd_soc_component_update_bits(component, reg, 0x10, 0x00);
2059 		break;
2060 	case SND_SOC_DAPM_POST_PMD:
2061 		snd_soc_component_update_bits(component, boost_path_ctl,
2062 					      CDC_WSA_BOOST_PATH_CLK_EN_MASK,
2063 					      CDC_WSA_BOOST_PATH_CLK_DISABLE);
2064 		snd_soc_component_update_bits(component, boost_path_cfg1,
2065 					      CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
2066 					      CDC_WSA_RX_PATH_SMART_BST_DISABLE);
2067 		break;
2068 	}
2069 
2070 	return 0;
2071 }
2072 
2073 static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
2074 				 struct snd_kcontrol *kcontrol,
2075 				 int event)
2076 {
2077 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2078 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2079 	u16 val, ec_tx, ec_hq_reg;
2080 
2081 	val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
2082 
2083 	switch (w->shift) {
2084 	case WSA_MACRO_EC0_MUX:
2085 		val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK;
2086 		ec_tx = val - 1;
2087 		break;
2088 	case WSA_MACRO_EC1_MUX:
2089 		val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK;
2090 		ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1;
2091 		break;
2092 	default:
2093 		dev_err(component->dev,	"%s: Invalid shift %u\n",
2094 			__func__, w->shift);
2095 		return -EINVAL;
2096 	}
2097 
2098 	if (wsa->ec_hq[ec_tx]) {
2099 		ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL +	0x40 * ec_tx;
2100 		snd_soc_component_update_bits(component, ec_hq_reg,
2101 					     CDC_WSA_EC_HQ_EC_CLK_EN_MASK,
2102 					     CDC_WSA_EC_HQ_EC_CLK_ENABLE);
2103 		ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx;
2104 		/* default set to 48k */
2105 		snd_soc_component_update_bits(component, ec_hq_reg,
2106 				      CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK,
2107 				      CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K);
2108 	}
2109 
2110 	return 0;
2111 }
2112 
2113 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
2114 			       struct snd_ctl_elem_value *ucontrol)
2115 {
2116 
2117 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2118 	int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2119 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2120 
2121 	ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];
2122 
2123 	return 0;
2124 }
2125 
2126 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
2127 			       struct snd_ctl_elem_value *ucontrol)
2128 {
2129 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2130 	int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2131 	int value = ucontrol->value.integer.value[0];
2132 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2133 
2134 	wsa->ec_hq[ec_tx] = value;
2135 
2136 	return 0;
2137 }
2138 
2139 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol,
2140 				   struct snd_ctl_elem_value *ucontrol)
2141 {
2142 
2143 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2144 	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2145 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2146 
2147 	ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
2148 	return 0;
2149 }
2150 
2151 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol,
2152 				   struct snd_ctl_elem_value *ucontrol)
2153 {
2154 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2155 	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2156 	int value = ucontrol->value.integer.value[0];
2157 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2158 
2159 	wsa->comp_enabled[comp] = value;
2160 
2161 	return 0;
2162 }
2163 
2164 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
2165 					  struct snd_ctl_elem_value *ucontrol)
2166 {
2167 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2168 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2169 
2170 	ucontrol->value.integer.value[0] = wsa->ear_spkr_gain;
2171 
2172 	return 0;
2173 }
2174 
2175 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
2176 					  struct snd_ctl_elem_value *ucontrol)
2177 {
2178 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2179 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2180 
2181 	wsa->ear_spkr_gain =  ucontrol->value.integer.value[0];
2182 
2183 	return 0;
2184 }
2185 
2186 static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
2187 				struct snd_ctl_elem_value *ucontrol)
2188 {
2189 	struct snd_soc_dapm_widget *widget =
2190 		snd_soc_dapm_kcontrol_widget(kcontrol);
2191 	struct snd_soc_component *component =
2192 				snd_soc_dapm_to_component(widget->dapm);
2193 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2194 
2195 	ucontrol->value.integer.value[0] =
2196 			wsa->rx_port_value[widget->shift];
2197 	return 0;
2198 }
2199 
2200 static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
2201 				struct snd_ctl_elem_value *ucontrol)
2202 {
2203 	struct snd_soc_dapm_widget *widget =
2204 		snd_soc_dapm_kcontrol_widget(kcontrol);
2205 	struct snd_soc_component *component =
2206 				snd_soc_dapm_to_component(widget->dapm);
2207 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2208 	struct snd_soc_dapm_update *update = NULL;
2209 	u32 rx_port_value = ucontrol->value.integer.value[0];
2210 	u32 bit_input;
2211 	u32 aif_rst;
2212 	unsigned int dai_id;
2213 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2214 
2215 	aif_rst = wsa->rx_port_value[widget->shift];
2216 	if (!rx_port_value) {
2217 		if (aif_rst == 0)
2218 			return 0;
2219 		if (aif_rst >= WSA_MACRO_RX_MAX) {
2220 			dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2221 			return 0;
2222 		}
2223 	}
2224 	wsa->rx_port_value[widget->shift] = rx_port_value;
2225 
2226 	bit_input = widget->shift;
2227 
2228 	switch (rx_port_value) {
2229 	case 0:
2230 		/*
2231 		 * active_ch_cnt and active_ch_mask use DAI IDs (WSA_MACRO_MAX_DAIS).
2232 		 * active_ch_cnt == 0 was tested in if() above.
2233 		 */
2234 		dai_id = aif_rst - 1;
2235 		if (wsa->active_ch_cnt[dai_id]) {
2236 			clear_bit(bit_input, &wsa->active_ch_mask[dai_id]);
2237 			wsa->active_ch_cnt[dai_id]--;
2238 		}
2239 		break;
2240 	case 1:
2241 	case 2:
2242 		/* active_ch_cnt and active_ch_mask use DAI IDs (WSA_MACRO_MAX_DAIS). */
2243 		dai_id = rx_port_value - 1;
2244 		set_bit(bit_input, &wsa->active_ch_mask[dai_id]);
2245 		wsa->active_ch_cnt[dai_id]++;
2246 		break;
2247 	default:
2248 		dev_err(component->dev,
2249 			"%s: Invalid AIF_ID for WSA RX MUX %d\n",
2250 			__func__, rx_port_value);
2251 		return -EINVAL;
2252 	}
2253 
2254 	snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2255 					rx_port_value, e, update);
2256 	return 0;
2257 }
2258 
2259 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2260 					  struct snd_ctl_elem_value *ucontrol)
2261 {
2262 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2263 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2264 	int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift;
2265 
2266 	ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];
2267 
2268 	return 0;
2269 }
2270 
2271 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2272 					  struct snd_ctl_elem_value *ucontrol)
2273 {
2274 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2275 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2276 	int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2277 
2278 	wsa->is_softclip_on[path] =  ucontrol->value.integer.value[0];
2279 
2280 	return 0;
2281 }
2282 
2283 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = {
2284 	SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum,
2285 		     wsa_macro_ear_spkr_pa_gain_get,
2286 		     wsa_macro_ear_spkr_pa_gain_put),
2287 	SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
2288 			WSA_MACRO_SOFTCLIP0, 1, 0,
2289 			wsa_macro_soft_clip_enable_get,
2290 			wsa_macro_soft_clip_enable_put),
2291 	SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM,
2292 			WSA_MACRO_SOFTCLIP1, 1, 0,
2293 			wsa_macro_soft_clip_enable_get,
2294 			wsa_macro_soft_clip_enable_put),
2295 
2296 	SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL,
2297 			  -84, 40, digital_gain),
2298 	SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL,
2299 			  -84, 40, digital_gain),
2300 
2301 	SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0),
2302 	SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0),
2303 	SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4,
2304 		   1, 0),
2305 	SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4,
2306 		   1, 0),
2307 	SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0,
2308 		       wsa_macro_get_compander, wsa_macro_set_compander),
2309 	SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0,
2310 		       wsa_macro_get_compander, wsa_macro_set_compander),
2311 	SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0,
2312 		       wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
2313 	SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0,
2314 		       wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
2315 };
2316 
2317 static const struct soc_enum rx_mux_enum =
2318 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);
2319 
2320 static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = {
2321 	SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
2322 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2323 	SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
2324 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2325 	SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
2326 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2327 	SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
2328 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
2329 };
2330 
2331 static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
2332 				       struct snd_ctl_elem_value *ucontrol)
2333 {
2334 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2335 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2336 	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2337 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2338 	u32 spk_tx_id = mixer->shift;
2339 	u32 dai_id = widget->shift;
2340 
2341 	if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
2342 		ucontrol->value.integer.value[0] = 1;
2343 	else
2344 		ucontrol->value.integer.value[0] = 0;
2345 
2346 	return 0;
2347 }
2348 
2349 static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
2350 				       struct snd_ctl_elem_value *ucontrol)
2351 {
2352 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2353 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2354 	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2355 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
2356 	u32 enable = ucontrol->value.integer.value[0];
2357 	u32 spk_tx_id = mixer->shift;
2358 	u32 dai_id = widget->shift;
2359 
2360 	if (enable) {
2361 		if (spk_tx_id == WSA_MACRO_TX0 &&
2362 			!test_bit(WSA_MACRO_TX0,
2363 				&wsa->active_ch_mask[dai_id])) {
2364 			set_bit(WSA_MACRO_TX0,
2365 				&wsa->active_ch_mask[dai_id]);
2366 			wsa->active_ch_cnt[dai_id]++;
2367 		}
2368 		if (spk_tx_id == WSA_MACRO_TX1 &&
2369 			!test_bit(WSA_MACRO_TX1,
2370 				&wsa->active_ch_mask[dai_id])) {
2371 			set_bit(WSA_MACRO_TX1,
2372 				&wsa->active_ch_mask[dai_id]);
2373 			wsa->active_ch_cnt[dai_id]++;
2374 		}
2375 	} else {
2376 		if (spk_tx_id == WSA_MACRO_TX0 &&
2377 			test_bit(WSA_MACRO_TX0,
2378 				&wsa->active_ch_mask[dai_id])) {
2379 			clear_bit(WSA_MACRO_TX0,
2380 				&wsa->active_ch_mask[dai_id]);
2381 			wsa->active_ch_cnt[dai_id]--;
2382 		}
2383 		if (spk_tx_id == WSA_MACRO_TX1 &&
2384 			test_bit(WSA_MACRO_TX1,
2385 				&wsa->active_ch_mask[dai_id])) {
2386 			clear_bit(WSA_MACRO_TX1,
2387 				&wsa->active_ch_mask[dai_id]);
2388 			wsa->active_ch_cnt[dai_id]--;
2389 		}
2390 	}
2391 	snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
2392 
2393 	return 0;
2394 }
2395 
2396 static const struct snd_kcontrol_new aif_vi_mixer[] = {
2397 	SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0,
2398 			wsa_macro_vi_feed_mixer_get,
2399 			wsa_macro_vi_feed_mixer_put),
2400 	SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0,
2401 			wsa_macro_vi_feed_mixer_get,
2402 			wsa_macro_vi_feed_mixer_put),
2403 };
2404 
2405 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = {
2406 	SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
2407 			    SND_SOC_NOPM, 0, 0),
2408 	SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
2409 			    SND_SOC_NOPM, 0, 0),
2410 
2411 	SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
2412 			       SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0,
2413 			       wsa_macro_enable_vi_feedback,
2414 			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2415 	SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
2416 			     SND_SOC_NOPM, 0, 0),
2417 
2418 	SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI,
2419 			   0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
2420 	SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
2421 			   WSA_MACRO_EC0_MUX, 0,
2422 			   &rx_mix_ec0_mux, wsa_macro_enable_echo,
2423 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2424 	SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
2425 			   WSA_MACRO_EC1_MUX, 0,
2426 			   &rx_mix_ec1_mux, wsa_macro_enable_echo,
2427 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2428 
2429 	SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
2430 			 &rx_mux[WSA_MACRO_RX0]),
2431 	SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
2432 			 &rx_mux[WSA_MACRO_RX1]),
2433 	SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
2434 			 &rx_mux[WSA_MACRO_RX_MIX0]),
2435 	SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
2436 			 &rx_mux[WSA_MACRO_RX_MIX1]),
2437 
2438 	SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2439 	SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2440 	SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2441 	SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2442 
2443 	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0,
2444 			     wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
2445 	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0,
2446 			     wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
2447 
2448 	SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2449 	SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2450 
2451 	SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1,
2452 			 4, 0, &rx0_sidetone_mix_mux),
2453 
2454 	SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
2455 	SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"),
2456 	SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"),
2457 
2458 	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM,
2459 			     WSA_MACRO_COMP1, 0, NULL, 0,
2460 			     wsa_macro_enable_interpolator,
2461 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2462 			     SND_SOC_DAPM_POST_PMD),
2463 
2464 	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM,
2465 			     WSA_MACRO_COMP2, 0, NULL, 0,
2466 			     wsa_macro_enable_interpolator,
2467 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2468 			     SND_SOC_DAPM_POST_PMD),
2469 
2470 	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
2471 			     NULL, 0, wsa_macro_spk_boost_event,
2472 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2473 			     SND_SOC_DAPM_POST_PMD),
2474 
2475 	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
2476 			     NULL, 0, wsa_macro_spk_boost_event,
2477 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2478 			     SND_SOC_DAPM_POST_PMD),
2479 
2480 	SND_SOC_DAPM_INPUT("VIINPUT_WSA"),
2481 	SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"),
2482 	SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"),
2483 
2484 	SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0),
2485 	SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0),
2486 	SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2487 	SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2488 	SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0,
2489 			      wsa_macro_mclk_event,
2490 			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2491 };
2492 
2493 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets_v2_1[] = {
2494 	SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux_v2_1),
2495 	SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux_v2_1),
2496 	SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux_v2_1),
2497 	SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
2498 			   0, &rx0_mix_mux_v2_1, wsa_macro_enable_mix_path,
2499 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2500 	SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux_v2_1),
2501 	SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux_v2_1),
2502 	SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux_v2_1),
2503 	SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
2504 			   0, &rx1_mix_mux_v2_1, wsa_macro_enable_mix_path,
2505 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2506 };
2507 
2508 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets_v2_5[] = {
2509 	SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux_v2_5),
2510 	SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux_v2_5),
2511 	SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux_v2_5),
2512 	SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
2513 			   0, &rx0_mix_mux_v2_5, wsa_macro_enable_mix_path,
2514 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2515 	SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux_v2_5),
2516 	SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux_v2_5),
2517 	SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux_v2_5),
2518 	SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
2519 			   0, &rx1_mix_mux_v2_5, wsa_macro_enable_mix_path,
2520 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2521 };
2522 
2523 static const struct snd_soc_dapm_route wsa_audio_map[] = {
2524 	/* VI Feedback */
2525 	{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"},
2526 	{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"},
2527 	{"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
2528 	{"WSA AIF_VI", NULL, "WSA_MCLK"},
2529 
2530 	{"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2531 	{"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2532 	{"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2533 	{"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2534 	{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
2535 	{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
2536 	{"WSA AIF_ECHO", NULL, "WSA_MCLK"},
2537 
2538 	{"WSA AIF1 PB", NULL, "WSA_MCLK"},
2539 	{"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},
2540 
2541 	{"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2542 	{"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2543 	{"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2544 	{"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2545 
2546 	{"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2547 	{"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2548 	{"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2549 	{"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2550 
2551 	{"WSA RX0", NULL, "WSA RX0 MUX"},
2552 	{"WSA RX1", NULL, "WSA RX1 MUX"},
2553 	{"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
2554 	{"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},
2555 
2556 	{"WSA RX0", NULL, "WSA_RX0_CLK"},
2557 	{"WSA RX1", NULL, "WSA_RX1_CLK"},
2558 	{"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"},
2559 	{"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"},
2560 
2561 	{"WSA_RX0 INP0", "RX0", "WSA RX0"},
2562 	{"WSA_RX0 INP0", "RX1", "WSA RX1"},
2563 	{"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
2564 	{"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
2565 	{"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"},
2566 	{"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"},
2567 	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"},
2568 
2569 	{"WSA_RX0 INP1", "RX0", "WSA RX0"},
2570 	{"WSA_RX0 INP1", "RX1", "WSA RX1"},
2571 	{"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
2572 	{"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
2573 	{"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"},
2574 	{"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"},
2575 	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"},
2576 
2577 	{"WSA_RX0 INP2", "RX0", "WSA RX0"},
2578 	{"WSA_RX0 INP2", "RX1", "WSA RX1"},
2579 	{"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
2580 	{"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
2581 	{"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"},
2582 	{"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"},
2583 	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"},
2584 
2585 	{"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
2586 	{"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
2587 	{"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2588 	{"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2589 	{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"},
2590 
2591 	{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"},
2592 	{"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"},
2593 	{"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
2594 	{"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"},
2595 	{"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"},
2596 
2597 	{"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"},
2598 	{"WSA_SPK1 OUT", NULL, "WSA_MCLK"},
2599 
2600 	{"WSA_RX1 INP0", "RX0", "WSA RX0"},
2601 	{"WSA_RX1 INP0", "RX1", "WSA RX1"},
2602 	{"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
2603 	{"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
2604 	{"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"},
2605 	{"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"},
2606 	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"},
2607 
2608 	{"WSA_RX1 INP1", "RX0", "WSA RX0"},
2609 	{"WSA_RX1 INP1", "RX1", "WSA RX1"},
2610 	{"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
2611 	{"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
2612 	{"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"},
2613 	{"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"},
2614 	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"},
2615 
2616 	{"WSA_RX1 INP2", "RX0", "WSA RX0"},
2617 	{"WSA_RX1 INP2", "RX1", "WSA RX1"},
2618 	{"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
2619 	{"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
2620 	{"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"},
2621 	{"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"},
2622 	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"},
2623 
2624 	{"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
2625 	{"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
2626 	{"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2627 	{"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2628 	{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"},
2629 
2630 	{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"},
2631 	{"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"},
2632 
2633 	{"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"},
2634 	{"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"},
2635 	{"WSA_SPK2 OUT", NULL, "WSA_MCLK"},
2636 };
2637 
2638 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
2639 {
2640 	struct regmap *regmap = wsa->regmap;
2641 
2642 	if (enable) {
2643 		int ret;
2644 
2645 		ret = clk_prepare_enable(wsa->mclk);
2646 		if (ret) {
2647 			dev_err(wsa->dev, "failed to enable mclk\n");
2648 			return ret;
2649 		}
2650 		wsa_macro_mclk_enable(wsa, true);
2651 
2652 		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2653 				   CDC_WSA_SWR_CLK_EN_MASK,
2654 				   CDC_WSA_SWR_CLK_ENABLE);
2655 
2656 	} else {
2657 		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2658 				   CDC_WSA_SWR_CLK_EN_MASK, 0);
2659 		wsa_macro_mclk_enable(wsa, false);
2660 		clk_disable_unprepare(wsa->mclk);
2661 	}
2662 
2663 	return 0;
2664 }
2665 
2666 static int wsa_macro_component_probe(struct snd_soc_component *comp)
2667 {
2668 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(comp);
2669 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);
2670 	const struct snd_soc_dapm_widget *widgets;
2671 	unsigned int num_widgets;
2672 
2673 	snd_soc_component_init_regmap(comp, wsa->regmap);
2674 
2675 	wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;
2676 
2677 	/* set SPKR rate to FS_2P4_3P072 */
2678 	snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,
2679 				CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2680 				CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2681 
2682 	snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,
2683 				CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2684 				CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2685 
2686 	wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);
2687 
2688 	switch (wsa->codec_version) {
2689 	case LPASS_CODEC_VERSION_1_0:
2690 	case LPASS_CODEC_VERSION_1_1:
2691 	case LPASS_CODEC_VERSION_1_2:
2692 	case LPASS_CODEC_VERSION_2_0:
2693 	case LPASS_CODEC_VERSION_2_1:
2694 		widgets = wsa_macro_dapm_widgets_v2_1;
2695 		num_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets_v2_1);
2696 		break;
2697 	case LPASS_CODEC_VERSION_2_5:
2698 	case LPASS_CODEC_VERSION_2_6:
2699 	case LPASS_CODEC_VERSION_2_7:
2700 	case LPASS_CODEC_VERSION_2_8:
2701 	case LPASS_CODEC_VERSION_2_9:
2702 		widgets = wsa_macro_dapm_widgets_v2_5;
2703 		num_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets_v2_5);
2704 		break;
2705 	default:
2706 		return -EINVAL;
2707 	}
2708 
2709 	return snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
2710 }
2711 
2712 static int swclk_gate_enable(struct clk_hw *hw)
2713 {
2714 	return wsa_swrm_clock(to_wsa_macro(hw), true);
2715 }
2716 
2717 static void swclk_gate_disable(struct clk_hw *hw)
2718 {
2719 	wsa_swrm_clock(to_wsa_macro(hw), false);
2720 }
2721 
2722 static int swclk_gate_is_enabled(struct clk_hw *hw)
2723 {
2724 	struct wsa_macro *wsa = to_wsa_macro(hw);
2725 	int ret, val;
2726 
2727 	regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
2728 	ret = val & BIT(0);
2729 
2730 	return ret;
2731 }
2732 
2733 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2734 				       unsigned long parent_rate)
2735 {
2736 	return parent_rate / 2;
2737 }
2738 
2739 static const struct clk_ops swclk_gate_ops = {
2740 	.prepare = swclk_gate_enable,
2741 	.unprepare = swclk_gate_disable,
2742 	.is_enabled = swclk_gate_is_enabled,
2743 	.recalc_rate = swclk_recalc_rate,
2744 };
2745 
2746 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
2747 {
2748 	struct device *dev = wsa->dev;
2749 	const char *parent_clk_name;
2750 	struct clk_hw *hw;
2751 	struct clk_init_data init;
2752 	int ret;
2753 
2754 	if (wsa->npl)
2755 		parent_clk_name = __clk_get_name(wsa->npl);
2756 	else
2757 		parent_clk_name = __clk_get_name(wsa->mclk);
2758 
2759 	init.name = "mclk";
2760 	of_property_read_string(dev_of_node(dev), "clock-output-names",
2761 				&init.name);
2762 	init.ops = &swclk_gate_ops;
2763 	init.flags = 0;
2764 	init.parent_names = &parent_clk_name;
2765 	init.num_parents = 1;
2766 	wsa->hw.init = &init;
2767 	hw = &wsa->hw;
2768 	ret = clk_hw_register(wsa->dev, hw);
2769 	if (ret)
2770 		return ret;
2771 
2772 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2773 }
2774 
2775 static const struct snd_soc_component_driver wsa_macro_component_drv = {
2776 	.name = "WSA MACRO",
2777 	.probe = wsa_macro_component_probe,
2778 	.controls = wsa_macro_snd_controls,
2779 	.num_controls = ARRAY_SIZE(wsa_macro_snd_controls),
2780 	.dapm_widgets = wsa_macro_dapm_widgets,
2781 	.num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets),
2782 	.dapm_routes = wsa_audio_map,
2783 	.num_dapm_routes = ARRAY_SIZE(wsa_audio_map),
2784 };
2785 
2786 static int wsa_macro_probe(struct platform_device *pdev)
2787 {
2788 	struct device *dev = &pdev->dev;
2789 	struct wsa_macro *wsa;
2790 	kernel_ulong_t flags;
2791 	void __iomem *base;
2792 	int ret, def_count;
2793 
2794 	flags = (kernel_ulong_t)device_get_match_data(dev);
2795 
2796 	wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
2797 	if (!wsa)
2798 		return -ENOMEM;
2799 
2800 	wsa->macro = devm_clk_get_optional(dev, "macro");
2801 	if (IS_ERR(wsa->macro))
2802 		return dev_err_probe(dev, PTR_ERR(wsa->macro), "unable to get macro clock\n");
2803 
2804 	wsa->dcodec = devm_clk_get_optional(dev, "dcodec");
2805 	if (IS_ERR(wsa->dcodec))
2806 		return dev_err_probe(dev, PTR_ERR(wsa->dcodec), "unable to get dcodec clock\n");
2807 
2808 	wsa->mclk = devm_clk_get(dev, "mclk");
2809 	if (IS_ERR(wsa->mclk))
2810 		return dev_err_probe(dev, PTR_ERR(wsa->mclk), "unable to get mclk clock\n");
2811 
2812 	if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
2813 		wsa->npl = devm_clk_get(dev, "npl");
2814 		if (IS_ERR(wsa->npl))
2815 			return dev_err_probe(dev, PTR_ERR(wsa->npl), "unable to get npl clock\n");
2816 	}
2817 
2818 	wsa->fsgen = devm_clk_get(dev, "fsgen");
2819 	if (IS_ERR(wsa->fsgen))
2820 		return dev_err_probe(dev, PTR_ERR(wsa->fsgen), "unable to get fsgen clock\n");
2821 
2822 	base = devm_platform_ioremap_resource(pdev, 0);
2823 	if (IS_ERR(base))
2824 		return PTR_ERR(base);
2825 
2826 	wsa->codec_version = lpass_macro_get_codec_version();
2827 	struct reg_default *reg_defaults __free(kfree) = NULL;
2828 
2829 	switch (wsa->codec_version) {
2830 	case LPASS_CODEC_VERSION_1_0:
2831 	case LPASS_CODEC_VERSION_1_1:
2832 	case LPASS_CODEC_VERSION_1_2:
2833 	case LPASS_CODEC_VERSION_2_0:
2834 	case LPASS_CODEC_VERSION_2_1:
2835 		wsa->reg_layout = &wsa_codec_v2_1;
2836 		def_count = ARRAY_SIZE(wsa_defaults) + ARRAY_SIZE(wsa_defaults_v2_1);
2837 		reg_defaults = kmalloc_array(def_count, sizeof(*reg_defaults),
2838 					     GFP_KERNEL);
2839 		if (!reg_defaults)
2840 			return -ENOMEM;
2841 		memcpy(&reg_defaults[0], wsa_defaults, sizeof(wsa_defaults));
2842 		memcpy(&reg_defaults[ARRAY_SIZE(wsa_defaults)],
2843 		       wsa_defaults_v2_1, sizeof(wsa_defaults_v2_1));
2844 		break;
2845 
2846 	case LPASS_CODEC_VERSION_2_5:
2847 	case LPASS_CODEC_VERSION_2_6:
2848 	case LPASS_CODEC_VERSION_2_7:
2849 	case LPASS_CODEC_VERSION_2_8:
2850 	case LPASS_CODEC_VERSION_2_9:
2851 		wsa->reg_layout = &wsa_codec_v2_5;
2852 		def_count = ARRAY_SIZE(wsa_defaults) + ARRAY_SIZE(wsa_defaults_v2_5);
2853 		reg_defaults = kmalloc_array(def_count, sizeof(*reg_defaults),
2854 					     GFP_KERNEL);
2855 		if (!reg_defaults)
2856 			return -ENOMEM;
2857 		memcpy(&reg_defaults[0], wsa_defaults, sizeof(wsa_defaults));
2858 		memcpy(&reg_defaults[ARRAY_SIZE(wsa_defaults)],
2859 		       wsa_defaults_v2_5, sizeof(wsa_defaults_v2_5));
2860 		break;
2861 
2862 	default:
2863 		dev_err(dev, "Unsupported Codec version (%d)\n", wsa->codec_version);
2864 		return -EINVAL;
2865 	}
2866 
2867 	struct regmap_config *reg_config __free(kfree) = kmemdup(&wsa_regmap_config,
2868 								 sizeof(*reg_config),
2869 								 GFP_KERNEL);
2870 	if (!reg_config)
2871 		return -ENOMEM;
2872 
2873 	reg_config->reg_defaults = reg_defaults;
2874 	reg_config->num_reg_defaults = def_count;
2875 
2876 	wsa->regmap = devm_regmap_init_mmio(dev, base, reg_config);
2877 	if (IS_ERR(wsa->regmap))
2878 		return PTR_ERR(wsa->regmap);
2879 
2880 	dev_set_drvdata(dev, wsa);
2881 
2882 	wsa->dev = dev;
2883 
2884 	/* set MCLK and NPL rates */
2885 	clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ);
2886 	clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ);
2887 
2888 	ret = clk_prepare_enable(wsa->macro);
2889 	if (ret)
2890 		goto err;
2891 
2892 	ret = clk_prepare_enable(wsa->dcodec);
2893 	if (ret)
2894 		goto err_dcodec;
2895 
2896 	ret = clk_prepare_enable(wsa->mclk);
2897 	if (ret)
2898 		goto err_mclk;
2899 
2900 	ret = clk_prepare_enable(wsa->npl);
2901 	if (ret)
2902 		goto err_npl;
2903 
2904 	ret = clk_prepare_enable(wsa->fsgen);
2905 	if (ret)
2906 		goto err_fsgen;
2907 
2908 	/* reset swr ip */
2909 	regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2910 			   CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE);
2911 
2912 	regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2913 			   CDC_WSA_SWR_CLK_EN_MASK, CDC_WSA_SWR_CLK_ENABLE);
2914 
2915 	/* Bring out of reset */
2916 	regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2917 			   CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE);
2918 
2919 	ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
2920 					      wsa_macro_dai,
2921 					      ARRAY_SIZE(wsa_macro_dai));
2922 	if (ret)
2923 		goto err_clkout;
2924 
2925 	pm_runtime_set_autosuspend_delay(dev, 3000);
2926 	pm_runtime_use_autosuspend(dev);
2927 	pm_runtime_mark_last_busy(dev);
2928 	pm_runtime_set_active(dev);
2929 	pm_runtime_enable(dev);
2930 
2931 	ret = wsa_macro_register_mclk_output(wsa);
2932 	if (ret)
2933 		goto err_clkout;
2934 
2935 	return 0;
2936 
2937 err_clkout:
2938 	clk_disable_unprepare(wsa->fsgen);
2939 err_fsgen:
2940 	clk_disable_unprepare(wsa->npl);
2941 err_npl:
2942 	clk_disable_unprepare(wsa->mclk);
2943 err_mclk:
2944 	clk_disable_unprepare(wsa->dcodec);
2945 err_dcodec:
2946 	clk_disable_unprepare(wsa->macro);
2947 err:
2948 	return ret;
2949 
2950 }
2951 
2952 static void wsa_macro_remove(struct platform_device *pdev)
2953 {
2954 	struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev);
2955 
2956 	clk_disable_unprepare(wsa->macro);
2957 	clk_disable_unprepare(wsa->dcodec);
2958 	clk_disable_unprepare(wsa->mclk);
2959 	clk_disable_unprepare(wsa->npl);
2960 	clk_disable_unprepare(wsa->fsgen);
2961 }
2962 
2963 static int wsa_macro_runtime_suspend(struct device *dev)
2964 {
2965 	struct wsa_macro *wsa = dev_get_drvdata(dev);
2966 
2967 	regcache_cache_only(wsa->regmap, true);
2968 	regcache_mark_dirty(wsa->regmap);
2969 
2970 	clk_disable_unprepare(wsa->fsgen);
2971 	clk_disable_unprepare(wsa->npl);
2972 	clk_disable_unprepare(wsa->mclk);
2973 
2974 	return 0;
2975 }
2976 
2977 static int wsa_macro_runtime_resume(struct device *dev)
2978 {
2979 	struct wsa_macro *wsa = dev_get_drvdata(dev);
2980 	int ret;
2981 
2982 	ret = clk_prepare_enable(wsa->mclk);
2983 	if (ret) {
2984 		dev_err(dev, "unable to prepare mclk\n");
2985 		return ret;
2986 	}
2987 
2988 	ret = clk_prepare_enable(wsa->npl);
2989 	if (ret) {
2990 		dev_err(dev, "unable to prepare mclkx2\n");
2991 		goto err_npl;
2992 	}
2993 
2994 	ret = clk_prepare_enable(wsa->fsgen);
2995 	if (ret) {
2996 		dev_err(dev, "unable to prepare fsgen\n");
2997 		goto err_fsgen;
2998 	}
2999 
3000 	regcache_cache_only(wsa->regmap, false);
3001 	regcache_sync(wsa->regmap);
3002 
3003 	return 0;
3004 err_fsgen:
3005 	clk_disable_unprepare(wsa->npl);
3006 err_npl:
3007 	clk_disable_unprepare(wsa->mclk);
3008 
3009 	return ret;
3010 }
3011 
3012 static const struct dev_pm_ops wsa_macro_pm_ops = {
3013 	RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL)
3014 };
3015 
3016 static const struct of_device_id wsa_macro_dt_match[] = {
3017 	{
3018 		.compatible = "qcom,sc7280-lpass-wsa-macro",
3019 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3020 	}, {
3021 		.compatible = "qcom,sm8250-lpass-wsa-macro",
3022 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3023 	}, {
3024 		.compatible = "qcom,sm8450-lpass-wsa-macro",
3025 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3026 	}, {
3027 		.compatible = "qcom,sm8550-lpass-wsa-macro",
3028 	}, {
3029 		.compatible = "qcom,sc8280xp-lpass-wsa-macro",
3030 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3031 	},
3032 	{}
3033 };
3034 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match);
3035 
3036 static struct platform_driver wsa_macro_driver = {
3037 	.driver = {
3038 		.name = "wsa_macro",
3039 		.of_match_table = wsa_macro_dt_match,
3040 		.pm = pm_ptr(&wsa_macro_pm_ops),
3041 	},
3042 	.probe = wsa_macro_probe,
3043 	.remove = wsa_macro_remove,
3044 };
3045 
3046 module_platform_driver(wsa_macro_driver);
3047 MODULE_DESCRIPTION("WSA macro driver");
3048 MODULE_LICENSE("GPL");
3049