1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * SPI_PPC4XX SPI controller driver.
4 *
5 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
6 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
8 *
9 * Based in part on drivers/spi/spi_s3c24xx.c
10 *
11 * Copyright (c) 2006 Ben Dooks
12 * Copyright (c) 2006 Simtec Electronics
13 * Ben Dooks <ben@simtec.co.uk>
14 */
15
16 /*
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
19 * This driver allows platforms to reduce the interrupt load on the CPU
20 * during SPI transfers by setting max_speed_hz via the device tree.
21 */
22
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/wait.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
37
38 #include <asm/dcr.h>
39 #include <asm/dcr-regs.h>
40
41 /* bits in mode register - bit 0 is MSb */
42
43 /*
44 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
45 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
46 * Note: This is the inverse of CPHA.
47 */
48 #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
49
50 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
51 #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
52
53 /*
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
56 * Note: This is identical to SPI_LSB_FIRST.
57 */
58 #define SPI_PPC4XX_MODE_RD (0x80 >> 5)
59
60 /*
61 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
62 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
63 * Note: This is identical to CPOL.
64 */
65 #define SPI_PPC4XX_MODE_CI (0x80 >> 6)
66
67 /*
68 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
69 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
70 */
71 #define SPI_PPC4XX_MODE_IL (0x80 >> 7)
72
73 /* bits in control register */
74 /* starts a transfer when set */
75 #define SPI_PPC4XX_CR_STR (0x80 >> 7)
76
77 /* bits in status register */
78 /* port is busy with a transfer */
79 #define SPI_PPC4XX_SR_BSY (0x80 >> 6)
80 /* RxD ready */
81 #define SPI_PPC4XX_SR_RBR (0x80 >> 7)
82
83 /* clock settings (SCP and CI) for various SPI modes */
84 #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
85 #define SPI_CLK_MODE1 (0 | 0)
86 #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
87 #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
88
89 #define DRIVER_NAME "spi_ppc4xx_of"
90
91 struct spi_ppc4xx_regs {
92 u8 mode;
93 u8 rxd;
94 u8 txd;
95 u8 cr;
96 u8 sr;
97 u8 dummy;
98 /*
99 * Clock divisor modulus register
100 * This uses the following formula:
101 * SCPClkOut = OPBCLK/(4(CDM + 1))
102 * or
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
104 * bit 0 is the MSb!
105 */
106 u8 cdm;
107 };
108
109 /* SPI Controller driver's private data. */
110 struct ppc4xx_spi {
111 /* bitbang has to be first */
112 struct spi_bitbang bitbang;
113 struct completion done;
114
115 u64 mapbase;
116 u64 mapsize;
117 int irqnum;
118 /* need this to set the SPI clock */
119 unsigned int opb_freq;
120
121 /* for transfers */
122 int len;
123 int count;
124 /* data buffers */
125 const unsigned char *tx;
126 unsigned char *rx;
127
128 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
129 struct spi_controller *host;
130 struct device *dev;
131 };
132
133 /* need this so we can set the clock in the chipselect routine */
134 struct spi_ppc4xx_cs {
135 u8 mode;
136 };
137
spi_ppc4xx_txrx(struct spi_device * spi,struct spi_transfer * t)138 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
139 {
140 struct ppc4xx_spi *hw;
141 u8 data;
142
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
144 t->tx_buf, t->rx_buf, t->len);
145
146 hw = spi_controller_get_devdata(spi->controller);
147
148 hw->tx = t->tx_buf;
149 hw->rx = t->rx_buf;
150 hw->len = t->len;
151 hw->count = 0;
152
153 /* send the first byte */
154 data = hw->tx ? hw->tx[0] : 0;
155 out_8(&hw->regs->txd, data);
156 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
157 wait_for_completion(&hw->done);
158
159 return hw->count;
160 }
161
spi_ppc4xx_setupxfer(struct spi_device * spi,struct spi_transfer * t)162 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
163 {
164 struct ppc4xx_spi *hw = spi_controller_get_devdata(spi->controller);
165 struct spi_ppc4xx_cs *cs = spi->controller_state;
166 int scr;
167 u8 cdm = 0;
168 u32 speed;
169
170 /* Start with the generic configuration for this device. */
171 speed = spi->max_speed_hz;
172
173 /*
174 * Modify the configuration if the transfer overrides it. Do not allow
175 * the transfer to overwrite the generic configuration with zeros.
176 */
177 if (t) {
178 if (t->speed_hz)
179 speed = min(t->speed_hz, spi->max_speed_hz);
180 }
181
182 if (!speed || (speed > spi->max_speed_hz)) {
183 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
184 return -EINVAL;
185 }
186
187 /* Write new configuration */
188 out_8(&hw->regs->mode, cs->mode);
189
190 /* Set the clock */
191 /* opb_freq was already divided by 4 */
192 scr = (hw->opb_freq / speed) - 1;
193 if (scr > 0)
194 cdm = min(scr, 0xff);
195
196 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
197
198 if (in_8(&hw->regs->cdm) != cdm)
199 out_8(&hw->regs->cdm, cdm);
200
201 mutex_lock(&hw->bitbang.lock);
202 if (!hw->bitbang.busy) {
203 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
204 /* Need to ndelay here? */
205 }
206 mutex_unlock(&hw->bitbang.lock);
207
208 return 0;
209 }
210
spi_ppc4xx_setup(struct spi_device * spi)211 static int spi_ppc4xx_setup(struct spi_device *spi)
212 {
213 struct spi_ppc4xx_cs *cs = spi->controller_state;
214
215 if (!spi->max_speed_hz) {
216 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
217 return -EINVAL;
218 }
219
220 if (cs == NULL) {
221 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
222 if (!cs)
223 return -ENOMEM;
224 spi->controller_state = cs;
225 }
226
227 /*
228 * We set all bits of the SPI0_MODE register, so,
229 * no need to read-modify-write
230 */
231 cs->mode = SPI_PPC4XX_MODE_SPE;
232
233 switch (spi->mode & SPI_MODE_X_MASK) {
234 case SPI_MODE_0:
235 cs->mode |= SPI_CLK_MODE0;
236 break;
237 case SPI_MODE_1:
238 cs->mode |= SPI_CLK_MODE1;
239 break;
240 case SPI_MODE_2:
241 cs->mode |= SPI_CLK_MODE2;
242 break;
243 case SPI_MODE_3:
244 cs->mode |= SPI_CLK_MODE3;
245 break;
246 }
247
248 if (spi->mode & SPI_LSB_FIRST)
249 cs->mode |= SPI_PPC4XX_MODE_RD;
250
251 return 0;
252 }
253
spi_ppc4xx_int(int irq,void * dev_id)254 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
255 {
256 struct ppc4xx_spi *hw;
257 u8 status;
258 u8 data;
259 unsigned int count;
260
261 hw = (struct ppc4xx_spi *)dev_id;
262
263 status = in_8(&hw->regs->sr);
264 if (!status)
265 return IRQ_NONE;
266
267 /*
268 * BSY de-asserts one cycle after the transfer is complete. The
269 * interrupt is asserted after the transfer is complete. The exact
270 * relationship is not documented, hence this code.
271 */
272
273 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
274 u8 lstatus;
275 int cnt = 0;
276
277 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
278 do {
279 ndelay(10);
280 lstatus = in_8(&hw->regs->sr);
281 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
282
283 if (cnt >= 100) {
284 dev_err(hw->dev, "busywait: too many loops!\n");
285 complete(&hw->done);
286 return IRQ_HANDLED;
287 } else {
288 /* status is always 1 (RBR) here */
289 status = in_8(&hw->regs->sr);
290 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
291 }
292 }
293
294 count = hw->count;
295 hw->count++;
296
297 /* RBR triggered this interrupt. Therefore, data must be ready. */
298 data = in_8(&hw->regs->rxd);
299 if (hw->rx)
300 hw->rx[count] = data;
301
302 count++;
303
304 if (count < hw->len) {
305 data = hw->tx ? hw->tx[count] : 0;
306 out_8(&hw->regs->txd, data);
307 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
308 } else {
309 complete(&hw->done);
310 }
311
312 return IRQ_HANDLED;
313 }
314
spi_ppc4xx_cleanup(struct spi_device * spi)315 static void spi_ppc4xx_cleanup(struct spi_device *spi)
316 {
317 kfree(spi->controller_state);
318 }
319
spi_ppc4xx_enable(struct ppc4xx_spi * hw)320 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
321 {
322 /*
323 * On all 4xx PPC's the SPI bus is shared/multiplexed with
324 * the 2nd I2C bus. We need to enable the SPI bus before
325 * using it.
326 */
327
328 /* need to clear bit 14 to enable SPC */
329 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
330 }
331
332 /*
333 * platform_device layer stuff...
334 */
spi_ppc4xx_of_probe(struct platform_device * op)335 static int spi_ppc4xx_of_probe(struct platform_device *op)
336 {
337 struct ppc4xx_spi *hw;
338 struct spi_controller *host;
339 struct spi_bitbang *bbp;
340 struct resource resource;
341 struct device_node *np = op->dev.of_node;
342 struct device *dev = &op->dev;
343 struct device_node *opbnp;
344 int ret;
345 const unsigned int *clk;
346
347 host = spi_alloc_host(dev, sizeof(*hw));
348 if (host == NULL)
349 return -ENOMEM;
350 host->dev.of_node = np;
351 platform_set_drvdata(op, host);
352 hw = spi_controller_get_devdata(host);
353 hw->host = host;
354 hw->dev = dev;
355
356 init_completion(&hw->done);
357
358 /* Setup the state for the bitbang driver */
359 bbp = &hw->bitbang;
360 bbp->ctlr = hw->host;
361 bbp->setup_transfer = spi_ppc4xx_setupxfer;
362 bbp->txrx_bufs = spi_ppc4xx_txrx;
363 bbp->use_dma = 0;
364 bbp->ctlr->setup = spi_ppc4xx_setup;
365 bbp->ctlr->cleanup = spi_ppc4xx_cleanup;
366 bbp->ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
367 bbp->ctlr->use_gpio_descriptors = true;
368 /*
369 * The SPI core will count the number of GPIO descriptors to figure
370 * out the number of chip selects available on the platform.
371 */
372 bbp->ctlr->num_chipselect = 0;
373
374 /* the spi->mode bits understood by this driver: */
375 bbp->ctlr->mode_bits =
376 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
377
378 /* Get the clock for the OPB */
379 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
380 if (opbnp == NULL) {
381 dev_err(dev, "OPB: cannot find node\n");
382 ret = -ENODEV;
383 goto free_host;
384 }
385 /* Get the clock (Hz) for the OPB */
386 clk = of_get_property(opbnp, "clock-frequency", NULL);
387 if (clk == NULL) {
388 dev_err(dev, "OPB: no clock-frequency property set\n");
389 of_node_put(opbnp);
390 ret = -ENODEV;
391 goto free_host;
392 }
393 hw->opb_freq = *clk;
394 hw->opb_freq >>= 2;
395 of_node_put(opbnp);
396
397 ret = of_address_to_resource(np, 0, &resource);
398 if (ret) {
399 dev_err(dev, "error while parsing device node resource\n");
400 goto free_host;
401 }
402 hw->mapbase = resource.start;
403 hw->mapsize = resource_size(&resource);
404
405 /* Sanity check */
406 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
407 dev_err(dev, "too small to map registers\n");
408 ret = -EINVAL;
409 goto free_host;
410 }
411
412 /* Request IRQ */
413 ret = platform_get_irq(op, 0);
414 if (ret < 0)
415 goto free_host;
416 hw->irqnum = ret;
417
418 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
419 0, "spi_ppc4xx_of", (void *)hw);
420 if (ret) {
421 dev_err(dev, "unable to allocate interrupt\n");
422 goto free_host;
423 }
424
425 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
426 dev_err(dev, "resource unavailable\n");
427 ret = -EBUSY;
428 goto request_mem_error;
429 }
430
431 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
432
433 if (!hw->regs) {
434 dev_err(dev, "unable to memory map registers\n");
435 ret = -ENXIO;
436 goto map_io_error;
437 }
438
439 spi_ppc4xx_enable(hw);
440
441 /* Finally register our spi controller */
442 dev->dma_mask = 0;
443 ret = spi_bitbang_start(bbp);
444 if (ret) {
445 dev_err(dev, "failed to register SPI host\n");
446 goto unmap_regs;
447 }
448
449 dev_info(dev, "driver initialized\n");
450
451 return 0;
452
453 unmap_regs:
454 iounmap(hw->regs);
455 map_io_error:
456 release_mem_region(hw->mapbase, hw->mapsize);
457 request_mem_error:
458 free_irq(hw->irqnum, hw);
459 free_host:
460 spi_controller_put(host);
461
462 dev_err(dev, "initialization failed\n");
463 return ret;
464 }
465
spi_ppc4xx_of_remove(struct platform_device * op)466 static void spi_ppc4xx_of_remove(struct platform_device *op)
467 {
468 struct spi_controller *host = platform_get_drvdata(op);
469 struct ppc4xx_spi *hw = spi_controller_get_devdata(host);
470
471 spi_bitbang_stop(&hw->bitbang);
472 release_mem_region(hw->mapbase, hw->mapsize);
473 free_irq(hw->irqnum, hw);
474 iounmap(hw->regs);
475 spi_controller_put(host);
476 }
477
478 static const struct of_device_id spi_ppc4xx_of_match[] = {
479 { .compatible = "ibm,ppc4xx-spi", },
480 {},
481 };
482
483 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
484
485 static struct platform_driver spi_ppc4xx_of_driver = {
486 .probe = spi_ppc4xx_of_probe,
487 .remove = spi_ppc4xx_of_remove,
488 .driver = {
489 .name = DRIVER_NAME,
490 .of_match_table = spi_ppc4xx_of_match,
491 },
492 };
493 module_platform_driver(spi_ppc4xx_of_driver);
494
495 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
496 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
497 MODULE_LICENSE("GPL");
498