1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface framework 4 * 5 * Author: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/iopoll.h> 10 #include <linux/interrupt.h> 11 #include <linux/mdio.h> 12 #include <linux/phy.h> 13 #include <linux/oa_tc6.h> 14 15 /* Control command header */ 16 #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) 17 #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) 18 #define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24) 19 #define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8) 20 #define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1) 21 #define OA_TC6_CTRL_HEADER_PARITY BIT(0) 22 23 /* Data header */ 24 #define OA_TC6_DATA_HEADER_DATA_NOT_CTRL BIT(31) 25 #define OA_TC6_DATA_HEADER_DATA_VALID BIT(21) 26 #define OA_TC6_DATA_HEADER_START_VALID BIT(20) 27 #define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) 28 #define OA_TC6_DATA_HEADER_END_VALID BIT(14) 29 #define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) 30 #define OA_TC6_DATA_HEADER_PARITY BIT(0) 31 32 /* Data footer */ 33 #define OA_TC6_DATA_FOOTER_EXTENDED_STS BIT(31) 34 #define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD BIT(30) 35 #define OA_TC6_DATA_FOOTER_CONFIG_SYNC BIT(29) 36 #define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24) 37 #define OA_TC6_DATA_FOOTER_DATA_VALID BIT(21) 38 #define OA_TC6_DATA_FOOTER_START_VALID BIT(20) 39 #define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) 40 #define OA_TC6_DATA_FOOTER_END_VALID BIT(14) 41 #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) 42 #define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) 43 44 #define OA_TC6_CTRL_PROT_REPLY_SIZE 4 45 #define OA_TC6_CTRL_HEADER_SIZE 4 46 #define OA_TC6_CTRL_REG_VALUE_SIZE 4 47 #define OA_TC6_CTRL_IGNORED_SIZE 4 48 #define OA_TC6_CTRL_MAX_REGISTERS 128 49 #define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ 50 (OA_TC6_CTRL_MAX_REGISTERS *\ 51 (OA_TC6_CTRL_REG_VALUE_SIZE +\ 52 OA_TC6_CTRL_PROT_REPLY_SIZE)) +\ 53 OA_TC6_CTRL_IGNORED_SIZE) 54 55 #define OA_TC6_CHUNK_PAYLOAD_SIZE 64 56 #define OA_TC6_DATA_HEADER_SIZE 4 57 #define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ 58 OA_TC6_CHUNK_PAYLOAD_SIZE) 59 #define OA_TC6_MAX_TX_CHUNKS 48 60 #define OA_TC6_SPI_DATA_BUF_SIZE (OA_TC6_MAX_TX_CHUNKS *\ 61 OA_TC6_CHUNK_SIZE) 62 #define STATUS0_RESETC_POLL_DELAY 1000 63 #define STATUS0_RESETC_POLL_TIMEOUT 1000000 64 65 #define OA_TC6_REG_MMS_MASK GENMASK(19, 16) 66 67 /* Internal structure for MAC-PHY drivers */ 68 struct oa_tc6 { 69 struct net_device *netdev; 70 struct phy_device *phydev; 71 struct mii_bus *mdiobus; 72 struct spi_device *spi; 73 struct mutex spi_ctrl_lock; /* Protects spi control transfer */ 74 spinlock_t tx_skb_lock; /* Protects tx skb handling */ 75 void *spi_ctrl_tx_buf; 76 void *spi_ctrl_rx_buf; 77 void *spi_data_tx_buf; 78 void *spi_data_rx_buf; 79 struct sk_buff *ongoing_tx_skb; 80 struct sk_buff *waiting_tx_skb; 81 struct sk_buff *rx_skb; 82 u16 tx_skb_offset; 83 u16 spi_data_tx_buf_offset; 84 u16 tx_credits; 85 u8 rx_chunks_available; 86 bool wait_until_start_valid; 87 bool int_flag; 88 bool disable_traffic; 89 bool prot_ctrl; 90 enum oa_tc6_quirk_flag quirk_flags; 91 }; 92 93 enum oa_tc6_header_type { 94 OA_TC6_CTRL_HEADER, 95 OA_TC6_DATA_HEADER, 96 }; 97 98 enum oa_tc6_register_op { 99 OA_TC6_CTRL_REG_READ = 0, 100 OA_TC6_CTRL_REG_WRITE = 1, 101 }; 102 103 enum oa_tc6_data_valid_info { 104 OA_TC6_DATA_INVALID, 105 OA_TC6_DATA_VALID, 106 }; 107 108 enum oa_tc6_data_start_valid_info { 109 OA_TC6_DATA_START_INVALID, 110 OA_TC6_DATA_START_VALID, 111 }; 112 113 enum oa_tc6_data_end_valid_info { 114 OA_TC6_DATA_END_INVALID, 115 OA_TC6_DATA_END_VALID, 116 }; 117 118 static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, 119 enum oa_tc6_header_type header_type, u16 length) 120 { 121 struct spi_transfer xfer = { 0 }; 122 struct spi_message msg; 123 124 if (header_type == OA_TC6_DATA_HEADER) { 125 xfer.tx_buf = tc6->spi_data_tx_buf; 126 xfer.rx_buf = tc6->spi_data_rx_buf; 127 } else { 128 xfer.tx_buf = tc6->spi_ctrl_tx_buf; 129 xfer.rx_buf = tc6->spi_ctrl_rx_buf; 130 } 131 xfer.len = length; 132 133 spi_message_init(&msg); 134 spi_message_add_tail(&xfer, &msg); 135 136 return spi_sync(tc6->spi, &msg); 137 } 138 139 static int oa_tc6_get_parity(u32 p) 140 { 141 /* Public domain code snippet, lifted from 142 * http://www-graphics.stanford.edu/~seander/bithacks.html 143 */ 144 p ^= p >> 1; 145 p ^= p >> 2; 146 p = (p & 0x11111111U) * 0x11111111U; 147 148 /* Odd parity is used here */ 149 return !((p >> 28) & 1); 150 } 151 152 static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, 153 enum oa_tc6_register_op reg_op) 154 { 155 u32 header; 156 157 header = FIELD_PREP(OA_TC6_CTRL_HEADER_DATA_NOT_CTRL, 158 OA_TC6_CTRL_HEADER) | 159 FIELD_PREP(OA_TC6_CTRL_HEADER_WRITE_NOT_READ, reg_op) | 160 FIELD_PREP(OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR, addr >> 16) | 161 FIELD_PREP(OA_TC6_CTRL_HEADER_ADDR, addr) | 162 FIELD_PREP(OA_TC6_CTRL_HEADER_LENGTH, length - 1); 163 header |= FIELD_PREP(OA_TC6_CTRL_HEADER_PARITY, 164 oa_tc6_get_parity(header)); 165 166 return cpu_to_be32(header); 167 } 168 169 static void oa_tc6_update_ctrl_write_data(struct oa_tc6 *tc6, u32 value[], 170 u8 length) 171 { 172 __be32 *tx_buf = tc6->spi_ctrl_tx_buf + OA_TC6_CTRL_HEADER_SIZE; 173 174 for (int i = 0; i < length; i++) { 175 *tx_buf++ = cpu_to_be32(value[i]); 176 if (tc6->prot_ctrl) 177 *tx_buf++ = cpu_to_be32(~value[i]); 178 } 179 } 180 181 static u16 oa_tc6_calculate_ctrl_buf_size(u8 length, bool ctrl_prot) 182 { 183 u32 reply_size = OA_TC6_CTRL_REG_VALUE_SIZE; 184 185 if (ctrl_prot) 186 reply_size += OA_TC6_CTRL_PROT_REPLY_SIZE; 187 188 /* Control command consists 4 bytes header + 4 bytes register value for 189 * each register (+ 4 bytes for the register value complement in case 190 * protected mode is used) + 4 bytes ignored value. 191 */ 192 return OA_TC6_CTRL_HEADER_SIZE + reply_size * length + 193 OA_TC6_CTRL_IGNORED_SIZE; 194 } 195 196 static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address, 197 u32 value[], u8 length, 198 enum oa_tc6_register_op reg_op, 199 u16 buf_size) 200 { 201 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 202 203 memset(tx_buf, 0, buf_size); 204 *tx_buf = oa_tc6_prepare_ctrl_header(address, length, reg_op); 205 206 if (reg_op == OA_TC6_CTRL_REG_WRITE) 207 oa_tc6_update_ctrl_write_data(tc6, value, length); 208 } 209 210 static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size) 211 { 212 u8 *tx_buf = tc6->spi_ctrl_tx_buf; 213 u8 *rx_buf = tc6->spi_ctrl_rx_buf; 214 215 rx_buf += OA_TC6_CTRL_IGNORED_SIZE; 216 217 /* The echoed control write must match with the one that was 218 * transmitted. 219 */ 220 if (memcmp(tx_buf, rx_buf, size - OA_TC6_CTRL_IGNORED_SIZE)) 221 return -EPROTO; 222 223 return 0; 224 } 225 226 static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 length) 227 { 228 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE; 229 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 230 u32 complement; 231 u32 reply; 232 233 /* The echoed control read header must match with the one that was 234 * transmitted. 235 */ 236 if (*tx_buf != *rx_buf) 237 return -EPROTO; 238 239 if (tc6->prot_ctrl) { 240 /* Skip past the echoed header to the value/complement pairs */ 241 rx_buf += 1; 242 for (int i = 0; i < length; i++) { 243 reply = be32_to_cpu(rx_buf[0]); 244 complement = be32_to_cpu(rx_buf[1]); 245 246 if (complement != ~reply) 247 return -EPROTO; 248 249 rx_buf += 2; 250 } 251 } 252 253 return 0; 254 } 255 256 static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *tc6, u32 value[], 257 u8 length) 258 { 259 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE + 260 OA_TC6_CTRL_HEADER_SIZE; 261 262 for (int i = 0; i < length; i++) { 263 value[i] = be32_to_cpu(*rx_buf++); 264 265 /* skip complement word */ 266 if (tc6->prot_ctrl) 267 rx_buf++; 268 } 269 } 270 271 static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[], 272 u8 length, enum oa_tc6_register_op reg_op) 273 { 274 u16 size; 275 int ret; 276 277 size = oa_tc6_calculate_ctrl_buf_size(length, tc6->prot_ctrl); 278 279 /* Prepare control command and copy to SPI control buffer */ 280 oa_tc6_prepare_ctrl_spi_buf(tc6, address, value, length, reg_op, size); 281 282 /* Perform SPI transfer */ 283 ret = oa_tc6_spi_transfer(tc6, OA_TC6_CTRL_HEADER, size); 284 if (ret) { 285 dev_err(&tc6->spi->dev, "SPI transfer failed for control: %d\n", 286 ret); 287 return ret; 288 } 289 290 /* Check echoed/received control write command reply for errors */ 291 if (reg_op == OA_TC6_CTRL_REG_WRITE) 292 return oa_tc6_check_ctrl_write_reply(tc6, size); 293 294 /* Check echoed/received control read command reply for errors */ 295 ret = oa_tc6_check_ctrl_read_reply(tc6, length); 296 if (ret) 297 return ret; 298 299 oa_tc6_copy_ctrl_read_data(tc6, value, length); 300 301 return 0; 302 } 303 304 /** 305 * oa_tc6_read_registers - function for reading multiple consecutive registers. 306 * @tc6: oa_tc6 struct. 307 * @address: address of the first register to be read in the MAC-PHY. 308 * @value: values to be read from the starting register address @address. 309 * @length: number of consecutive registers to be read from @address. 310 * 311 * Maximum of 128 consecutive registers can be read starting at @address. 312 * 313 * Return: 0 on success otherwise failed. 314 */ 315 int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 316 u8 length) 317 { 318 int ret; 319 320 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 321 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 322 return -EINVAL; 323 } 324 325 mutex_lock(&tc6->spi_ctrl_lock); 326 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 327 OA_TC6_CTRL_REG_READ); 328 mutex_unlock(&tc6->spi_ctrl_lock); 329 330 return ret; 331 } 332 EXPORT_SYMBOL_GPL(oa_tc6_read_registers); 333 334 /** 335 * oa_tc6_read_register - function for reading a MAC-PHY register. 336 * @tc6: oa_tc6 struct. 337 * @address: register address of the MAC-PHY to be read. 338 * @value: value read from the @address register address of the MAC-PHY. 339 * 340 * Return: 0 on success otherwise failed. 341 */ 342 int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value) 343 { 344 return oa_tc6_read_registers(tc6, address, value, 1); 345 } 346 EXPORT_SYMBOL_GPL(oa_tc6_read_register); 347 348 /** 349 * oa_tc6_read_register_mms - function for reading a MAC-PHY register in a 350 * specified memory map. 351 * @tc6: oa_tc6 struct. 352 * @mms: Memory map selector for the register. 353 * @address: register address of the MAC-PHY to be read. 354 * @value: value read from the @address register address of the MAC-PHY. 355 * 356 * Return: 0 on success or a negative error code on failure. 357 */ 358 int oa_tc6_read_register_mms(struct oa_tc6 *tc6, u8 mms, u16 address, 359 u32 *value) 360 { 361 u32 mms_reg; 362 363 mms_reg = FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | address; 364 365 return oa_tc6_read_registers(tc6, mms_reg, value, 1); 366 } 367 EXPORT_SYMBOL_GPL(oa_tc6_read_register_mms); 368 369 /** 370 * oa_tc6_write_registers - function for writing multiple consecutive registers. 371 * @tc6: oa_tc6 struct. 372 * @address: address of the first register to be written in the MAC-PHY. 373 * @value: values to be written from the starting register address @address. 374 * @length: number of consecutive registers to be written from @address. 375 * 376 * Maximum of 128 consecutive registers can be written starting at @address. 377 * 378 * Return: 0 on success otherwise failed. 379 */ 380 int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 381 u8 length) 382 { 383 int ret; 384 385 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 386 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 387 return -EINVAL; 388 } 389 390 mutex_lock(&tc6->spi_ctrl_lock); 391 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 392 OA_TC6_CTRL_REG_WRITE); 393 mutex_unlock(&tc6->spi_ctrl_lock); 394 395 return ret; 396 } 397 EXPORT_SYMBOL_GPL(oa_tc6_write_registers); 398 399 /** 400 * oa_tc6_write_register - function for writing a MAC-PHY register. 401 * @tc6: oa_tc6 struct. 402 * @address: register address of the MAC-PHY to be written. 403 * @value: value to be written in the @address register address of the MAC-PHY. 404 * 405 * Return: 0 on success otherwise failed. 406 */ 407 int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value) 408 { 409 return oa_tc6_write_registers(tc6, address, &value, 1); 410 } 411 EXPORT_SYMBOL_GPL(oa_tc6_write_register); 412 413 /** 414 * oa_tc6_write_register_mms - function for writing a MAC-PHY register in a 415 * specified memory map. 416 * @tc6: oa_tc6 struct. 417 * @mms: Memory map selector for the register. 418 * @address: register address of the MAC-PHY to be written. 419 * @value: value to be written in the @address register address of the MAC-PHY. 420 * 421 * Return: 0 on success or a negative error code on failure. 422 */ 423 int oa_tc6_write_register_mms(struct oa_tc6 *tc6, u8 mms, u16 address, 424 u32 value) 425 { 426 u32 mms_reg; 427 428 mms_reg = FIELD_PREP(OA_TC6_REG_MMS_MASK, mms) | address; 429 430 return oa_tc6_write_registers(tc6, mms_reg, &value, 1); 431 } 432 EXPORT_SYMBOL_GPL(oa_tc6_write_register_mms); 433 434 static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6) 435 { 436 u32 regval; 437 int ret; 438 439 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STDCAP, ®val); 440 if (ret) 441 return ret; 442 443 if (!(regval & OA_TC6_STDCAP_DIRECT_PHY_REG_ACCESS)) 444 return -ENODEV; 445 446 return 0; 447 } 448 449 static void oa_tc6_handle_link_change(struct net_device *netdev) 450 { 451 phy_print_status(netdev->phydev); 452 } 453 454 static int oa_tc6_mdiobus_read(struct mii_bus *bus, int addr, int regnum) 455 { 456 struct oa_tc6 *tc6 = bus->priv; 457 u32 regval; 458 int ret; 459 460 ret = oa_tc6_read_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 461 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 462 ®val); 463 if (ret) 464 return ret; 465 466 return regval; 467 } 468 469 static int oa_tc6_mdiobus_write(struct mii_bus *bus, int addr, int regnum, 470 u16 val) 471 { 472 struct oa_tc6 *tc6 = bus->priv; 473 474 return oa_tc6_write_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 475 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 476 val); 477 } 478 479 static int oa_tc6_get_phy_c45_mms(int devnum) 480 { 481 switch (devnum) { 482 case MDIO_MMD_PCS: 483 return OA_TC6_PHY_C45_PCS_MMS2; 484 case MDIO_MMD_PMAPMD: 485 return OA_TC6_PHY_C45_PMA_PMD_MMS3; 486 case MDIO_MMD_VEND2: 487 return OA_TC6_PHY_C45_VS_PLCA_MMS4; 488 case MDIO_MMD_AN: 489 return OA_TC6_PHY_C45_AUTO_NEG_MMS5; 490 case MDIO_MMD_POWER_UNIT: 491 return OA_TC6_PHY_C45_POWER_UNIT_MMS6; 492 default: 493 return -EOPNOTSUPP; 494 } 495 } 496 497 int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, 498 int regnum) 499 { 500 struct oa_tc6 *tc6 = bus->priv; 501 u32 regval; 502 int mms; 503 int ret; 504 505 mms = oa_tc6_get_phy_c45_mms(devnum); 506 if (mms < 0) 507 return mms; 508 509 ret = oa_tc6_read_register_mms(tc6, mms, regnum, ®val); 510 if (ret) 511 return ret; 512 513 return regval; 514 } 515 EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_read_c45); 516 517 int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, 518 int regnum, u16 val) 519 { 520 struct oa_tc6 *tc6 = bus->priv; 521 int mms; 522 523 mms = oa_tc6_get_phy_c45_mms(devnum); 524 if (mms < 0) 525 return mms; 526 527 return oa_tc6_write_register_mms(tc6, mms, regnum, val); 528 } 529 EXPORT_SYMBOL_GPL(oa_tc6_mdiobus_write_c45); 530 531 static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) 532 { 533 int ret; 534 535 tc6->mdiobus = mdiobus_alloc(); 536 if (!tc6->mdiobus) { 537 netdev_err(tc6->netdev, "MDIO bus alloc failed\n"); 538 return -ENOMEM; 539 } 540 541 tc6->mdiobus->priv = tc6; 542 tc6->mdiobus->read = oa_tc6_mdiobus_read; 543 tc6->mdiobus->write = oa_tc6_mdiobus_write; 544 /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and 545 * C45 registers space. If the PHY is discovered via C22 bus protocol it 546 * assumes it uses C22 protocol and always uses C22 registers indirect 547 * access to access C45 registers. This is because, we don't have a 548 * clean separation between C22/C45 register space and C22/C45 MDIO bus 549 * protocols. Resulting, PHY C45 registers direct access can't be used 550 * which can save multiple SPI bus access. To support this feature, PHY 551 * drivers can set .read_mmd/.write_mmd in the PHY driver to call 552 * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c 553 */ 554 tc6->mdiobus->read_c45 = oa_tc6_mdiobus_read_c45; 555 tc6->mdiobus->write_c45 = oa_tc6_mdiobus_write_c45; 556 tc6->mdiobus->name = "oa-tc6-mdiobus"; 557 tc6->mdiobus->parent = &tc6->spi->dev; 558 559 snprintf(tc6->mdiobus->id, ARRAY_SIZE(tc6->mdiobus->id), "%s", 560 dev_name(&tc6->spi->dev)); 561 562 ret = mdiobus_register(tc6->mdiobus); 563 if (ret) { 564 netdev_err(tc6->netdev, "Could not register MDIO bus\n"); 565 mdiobus_free(tc6->mdiobus); 566 return ret; 567 } 568 569 return 0; 570 } 571 572 static void oa_tc6_mdiobus_unregister(struct oa_tc6 *tc6) 573 { 574 mdiobus_unregister(tc6->mdiobus); 575 mdiobus_free(tc6->mdiobus); 576 } 577 578 static int oa_tc6_phy_init(struct oa_tc6 *tc6) 579 { 580 int ret; 581 582 if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) 583 return 0; 584 585 ret = oa_tc6_check_phy_reg_direct_access_capability(tc6); 586 if (ret) { 587 netdev_err(tc6->netdev, 588 "Direct PHY register access is not supported by the MAC-PHY\n"); 589 return ret; 590 } 591 592 ret = oa_tc6_mdiobus_register(tc6); 593 if (ret) 594 return ret; 595 596 tc6->phydev = phy_find_first(tc6->mdiobus); 597 if (!tc6->phydev) { 598 netdev_err(tc6->netdev, "No PHY found\n"); 599 oa_tc6_mdiobus_unregister(tc6); 600 return -ENODEV; 601 } 602 603 tc6->phydev->is_internal = true; 604 ret = phy_connect_direct(tc6->netdev, tc6->phydev, 605 &oa_tc6_handle_link_change, 606 PHY_INTERFACE_MODE_INTERNAL); 607 if (ret) { 608 netdev_err(tc6->netdev, "Can't attach PHY to %s\n", 609 tc6->mdiobus->id); 610 oa_tc6_mdiobus_unregister(tc6); 611 return ret; 612 } 613 614 phy_attached_info(tc6->netdev->phydev); 615 616 return 0; 617 } 618 619 static void oa_tc6_phy_exit(struct oa_tc6 *tc6) 620 { 621 if (tc6->quirk_flags & OA_TC6_BROKEN_PHY) 622 return; 623 624 phy_disconnect(tc6->phydev); 625 oa_tc6_mdiobus_unregister(tc6); 626 } 627 628 static int oa_tc6_read_status0(struct oa_tc6 *tc6) 629 { 630 u32 regval; 631 int ret; 632 633 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 634 if (ret) { 635 dev_err(&tc6->spi->dev, "STATUS0 register read failed: %d\n", 636 ret); 637 return 0; 638 } 639 640 return regval; 641 } 642 643 static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) 644 { 645 u32 regval = OA_TC6_RESET_SWRESET; 646 int ret; 647 648 ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); 649 if (ret) 650 return ret; 651 652 /* Poll for soft reset complete for every 1ms until 1s timeout */ 653 ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval, 654 regval & OA_TC6_STATUS0_RESETC, 655 STATUS0_RESETC_POLL_DELAY, 656 STATUS0_RESETC_POLL_TIMEOUT); 657 if (ret) 658 return -ENODEV; 659 660 /* Clear the reset complete status */ 661 return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 662 } 663 664 static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) 665 { 666 u32 regval; 667 int ret; 668 669 ret = oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, ®val); 670 if (ret) 671 return ret; 672 673 regval &= ~(OA_TC6_INT_MASK0_TX_PROTOCOL_ERR_MASK | 674 OA_TC6_INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | 675 OA_TC6_INT_MASK0_LOSS_OF_FRAME_ERR_MASK | 676 OA_TC6_INT_MASK0_HEADER_ERR_MASK); 677 678 return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 679 } 680 681 static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6) 682 { 683 u32 value; 684 int ret; 685 686 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, &value); 687 if (ret) 688 return ret; 689 690 /* Enable configuration synchronization for data transfer */ 691 value |= OA_TC6_CONFIG0_SYNC; 692 693 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value); 694 } 695 696 /* Called when a frame that is meant to be transmitted, is dropped. */ 697 static void oa_tc6_drop_tx_skb(struct oa_tc6 *tc6, struct sk_buff *skb) 698 { 699 if (skb) { 700 tc6->netdev->stats.tx_dropped++; 701 dev_kfree_skb_any(skb); 702 } 703 } 704 705 static struct sk_buff *oa_tc6_detach_waiting_tx_skb(struct oa_tc6 *tc6) 706 { 707 struct sk_buff *skb; 708 709 lockdep_assert_held(&tc6->tx_skb_lock); 710 skb = tc6->waiting_tx_skb; 711 tc6->waiting_tx_skb = NULL; 712 713 return skb; 714 } 715 716 static void oa_tc6_cleanup_ongoing_rx_skb(struct oa_tc6 *tc6) 717 { 718 if (tc6->rx_skb) { 719 tc6->netdev->stats.rx_dropped++; 720 kfree_skb(tc6->rx_skb); 721 tc6->rx_skb = NULL; 722 } 723 } 724 725 static void oa_tc6_cleanup_ongoing_tx_skb(struct oa_tc6 *tc6) 726 { 727 oa_tc6_drop_tx_skb(tc6, tc6->ongoing_tx_skb); 728 tc6->ongoing_tx_skb = NULL; 729 } 730 731 static void oa_tc6_cleanup_waiting_tx_skb(struct oa_tc6 *tc6) 732 { 733 struct sk_buff *skb; 734 735 spin_lock_bh(&tc6->tx_skb_lock); 736 skb = oa_tc6_detach_waiting_tx_skb(tc6); 737 spin_unlock_bh(&tc6->tx_skb_lock); 738 739 oa_tc6_drop_tx_skb(tc6, skb); 740 } 741 742 static void oa_tc6_free_ongoing_skbs(struct oa_tc6 *tc6) 743 { 744 oa_tc6_cleanup_ongoing_tx_skb(tc6); 745 oa_tc6_cleanup_ongoing_rx_skb(tc6); 746 } 747 748 static void oa_tc6_free_pending_skbs(struct oa_tc6 *tc6) 749 { 750 oa_tc6_free_ongoing_skbs(tc6); 751 oa_tc6_cleanup_waiting_tx_skb(tc6); 752 } 753 754 static void oa_tc6_look_for_new_frame(struct oa_tc6 *tc6) 755 { 756 tc6->wait_until_start_valid = true; 757 oa_tc6_cleanup_ongoing_rx_skb(tc6); 758 } 759 760 /* If the failure is at SPI interface level, masking and clearing 761 * the interrupt of the device won't work. Since SPI interrupt is 762 * disabled, it should stop the repeated interrupts. 763 */ 764 static void oa_tc6_disable_traffic(struct oa_tc6 *tc6) 765 { 766 u32 regval = OA_TC6_INT_MASK0_ALL_INTERRUPTS; 767 struct sk_buff *skb; 768 769 spin_lock_bh(&tc6->tx_skb_lock); 770 tc6->disable_traffic = true; 771 skb = oa_tc6_detach_waiting_tx_skb(tc6); 772 spin_unlock_bh(&tc6->tx_skb_lock); 773 774 /* disable_traffic, when set, is a point of no return to 775 * working state. Keeping the TX queues disabled. 776 */ 777 netif_tx_disable(tc6->netdev); 778 oa_tc6_drop_tx_skb(tc6, skb); 779 oa_tc6_free_ongoing_skbs(tc6); 780 oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 781 oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 782 oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 783 dev_err(&tc6->spi->dev, "Device interrupt disabled to avoid interrupt storm"); 784 } 785 786 static int oa_tc6_process_extended_status(struct oa_tc6 *tc6) 787 { 788 u32 value; 789 int ret; 790 791 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &value); 792 if (ret) { 793 netdev_err(tc6->netdev, "STATUS0 register read failed: %d\n", 794 ret); 795 return ret; 796 } 797 798 /* This function is called for each chunk received in a given SPI 799 * transaction. In case, extended status bit is set in more than 800 * one chunk, skip the write, if status0 is already cleared. 801 */ 802 if (!value) 803 return 0; 804 805 /* Clear the error interrupts status */ 806 ret = oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, value); 807 if (ret) { 808 netdev_err(tc6->netdev, "STATUS0 register write failed: %d\n", 809 ret); 810 return ret; 811 } 812 813 if (FIELD_GET(OA_TC6_STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { 814 oa_tc6_look_for_new_frame(tc6); 815 net_err_ratelimited("%s: Receive buffer overflow error\n", 816 tc6->netdev->name); 817 return -EAGAIN; 818 } 819 if (FIELD_GET(OA_TC6_STATUS0_TX_PROTOCOL_ERROR, value)) { 820 netdev_err(tc6->netdev, "Transmit protocol error\n"); 821 return -ENODEV; 822 } 823 /* TODO: Currently loss of frame and header errors are treated as 824 * non-recoverable errors. They will be handled in the next version. 825 */ 826 if (FIELD_GET(OA_TC6_STATUS0_LOSS_OF_FRAME_ERROR, value)) { 827 netdev_err(tc6->netdev, "Loss of frame error\n"); 828 return -ENODEV; 829 } 830 if (FIELD_GET(OA_TC6_STATUS0_HEADER_ERROR, value)) { 831 netdev_err(tc6->netdev, "Header error\n"); 832 return -ENODEV; 833 } 834 835 return 0; 836 } 837 838 static int oa_tc6_process_rx_chunk_footer(struct oa_tc6 *tc6, u32 footer) 839 { 840 int ret = 0; 841 842 /* Process rx chunk footer for the following, 843 * 1. tx credits 844 * 2. errors if any from MAC-PHY 845 * 3. receive chunks available 846 */ 847 tc6->tx_credits = FIELD_GET(OA_TC6_DATA_FOOTER_TX_CREDITS, footer); 848 tc6->rx_chunks_available = FIELD_GET(OA_TC6_DATA_FOOTER_RX_CHUNKS, 849 footer); 850 851 if (FIELD_GET(OA_TC6_DATA_FOOTER_EXTENDED_STS, footer)) { 852 ret = oa_tc6_process_extended_status(tc6); 853 /* EAGAIN error is recoverable. Move on to check 854 * HEADER and SYNC errors before returning. 855 */ 856 if (ret && ret != -EAGAIN) 857 return ret; 858 } 859 860 /* TODO: Currently received header bad and configuration unsync errors 861 * are treated as non-recoverable errors. They will be handled in the 862 * next version. 863 */ 864 if (FIELD_GET(OA_TC6_DATA_FOOTER_RXD_HEADER_BAD, footer)) { 865 netdev_err(tc6->netdev, "Rxd header bad error\n"); 866 return -ENODEV; 867 } 868 869 if (!FIELD_GET(OA_TC6_DATA_FOOTER_CONFIG_SYNC, footer)) { 870 netdev_err(tc6->netdev, "Config unsync error\n"); 871 return -ENODEV; 872 } 873 874 return ret; 875 } 876 877 static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) 878 { 879 /* MAC-PHY delivers each frame with its Ethernet FCS attached. 880 * Strip it before handing over to the stack, unless the user 881 * has asked to keep it via NETIF_F_RXFCS. Keeping the FCS 882 * in the frame is harmless for IP traffic, but is parsed as 883 * a (malformed) suffix TLV by PTP, which makes ptp4l reject 884 * every message with "bad message" error. 885 */ 886 if (!(tc6->netdev->features & NETIF_F_RXFCS) && 887 tc6->rx_skb->len > ETH_FCS_LEN) 888 skb_trim(tc6->rx_skb, tc6->rx_skb->len - ETH_FCS_LEN); 889 890 tc6->rx_skb->protocol = eth_type_trans(tc6->rx_skb, tc6->netdev); 891 tc6->netdev->stats.rx_packets++; 892 tc6->netdev->stats.rx_bytes += tc6->rx_skb->len; 893 894 netif_rx(tc6->rx_skb); 895 896 tc6->rx_skb = NULL; 897 } 898 899 /* On oversubscribed traffic condition, particularly with overwhelming rx 900 * buffer overflow errors, there could be data chunk loss. If tail + length 901 * goes beyond end pointer, that is an indication that the data chunk with 902 * end_valid bit is lost. Time to look for a data chunk with start_valid bit. 903 * 904 * If rx_skb is NULL, it is time to start looking for data chunk with 905 * start_bit. 906 */ 907 static int oa_tc6_update_rx_skb(struct oa_tc6 *tc6, u8 *payload, u8 length) 908 { 909 if (!tc6->rx_skb || 910 skb_tailroom(tc6->rx_skb) < length) { 911 oa_tc6_look_for_new_frame(tc6); 912 return -EAGAIN; 913 } 914 915 memcpy(skb_put(tc6->rx_skb, length), payload, length); 916 return 0; 917 } 918 919 /* On overwhelming rx buffer overflow errors, due to data chunk loss, it is 920 * possible that we get two data chunks with start_valid bit set, without 921 * end_valid bit set in between. In this case, rx_skb would have a valid 922 * buffer pointer. We should release, if a valid pointer is found before 923 * allocating a new one. 924 */ 925 static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6) 926 { 927 oa_tc6_cleanup_ongoing_rx_skb(tc6); 928 tc6->rx_skb = netdev_alloc_skb_ip_align(tc6->netdev, tc6->netdev->mtu + 929 ETH_HLEN + ETH_FCS_LEN); 930 if (!tc6->rx_skb) { 931 tc6->netdev->stats.rx_dropped++; 932 return -ENOMEM; 933 } 934 935 return 0; 936 } 937 938 static int oa_tc6_prcs_complete_rx_frame(struct oa_tc6 *tc6, u8 *payload, 939 u16 size) 940 { 941 int ret; 942 943 ret = oa_tc6_allocate_rx_skb(tc6); 944 if (ret) 945 return ret; 946 947 ret = oa_tc6_update_rx_skb(tc6, payload, size); 948 if (ret) 949 return ret; 950 951 oa_tc6_submit_rx_skb(tc6); 952 953 return 0; 954 } 955 956 static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16 size) 957 { 958 int ret; 959 960 ret = oa_tc6_allocate_rx_skb(tc6); 961 if (ret) 962 return ret; 963 964 return oa_tc6_update_rx_skb(tc6, payload, size); 965 } 966 967 static int oa_tc6_prcs_rx_frame_end(struct oa_tc6 *tc6, u8 *payload, u16 size) 968 { 969 int ret; 970 971 ret = oa_tc6_update_rx_skb(tc6, payload, size); 972 if (!ret) 973 oa_tc6_submit_rx_skb(tc6); 974 return ret; 975 } 976 977 static int oa_tc6_prcs_ongoing_rx_frame(struct oa_tc6 *tc6, u8 *payload, 978 u32 footer) 979 { 980 return oa_tc6_update_rx_skb(tc6, payload, 981 OA_TC6_CHUNK_PAYLOAD_SIZE); 982 } 983 984 static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *tc6, u8 *data, 985 u32 footer) 986 { 987 u8 start_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_START_WORD_OFFSET, 988 footer) * sizeof(u32); 989 u8 end_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_END_BYTE_OFFSET, 990 footer); 991 bool start_valid = FIELD_GET(OA_TC6_DATA_FOOTER_START_VALID, footer); 992 bool end_valid = FIELD_GET(OA_TC6_DATA_FOOTER_END_VALID, footer); 993 u16 size; 994 995 /* Restart the new rx frame after receiving rx buffer overflow error */ 996 if (start_valid && tc6->wait_until_start_valid) 997 tc6->wait_until_start_valid = false; 998 999 if (tc6->wait_until_start_valid) 1000 return 0; 1001 1002 /* Process the chunk with complete rx frame */ 1003 if (start_valid && end_valid && start_byte_offset < end_byte_offset) { 1004 size = end_byte_offset + 1 - start_byte_offset; 1005 return oa_tc6_prcs_complete_rx_frame(tc6, 1006 &data[start_byte_offset], 1007 size); 1008 } 1009 1010 /* Process the chunk with only rx frame start */ 1011 if (start_valid && !end_valid) { 1012 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 1013 return oa_tc6_prcs_rx_frame_start(tc6, 1014 &data[start_byte_offset], 1015 size); 1016 } 1017 1018 /* Process the chunk with only rx frame end */ 1019 if (end_valid && !start_valid) { 1020 size = end_byte_offset + 1; 1021 return oa_tc6_prcs_rx_frame_end(tc6, data, size); 1022 } 1023 1024 /* Process the chunk with previous rx frame end and next rx frame 1025 * start. 1026 */ 1027 if (start_valid && end_valid && start_byte_offset > end_byte_offset) { 1028 /* After rx buffer overflow error received, there might be a 1029 * possibility of getting an end valid of a previously 1030 * incomplete rx frame along with the new rx frame start valid. 1031 */ 1032 if (tc6->rx_skb) { 1033 size = end_byte_offset + 1; 1034 oa_tc6_prcs_rx_frame_end(tc6, data, size); 1035 1036 /* Return value from oa_tc6_prcs_rx_frame_end is not 1037 * checked. If it returned an error, it is to make 1038 * the code to look for new frame. At this stage, 1039 * code below is going to process a new frame. So, 1040 * error condition is set to false, in case it is 1041 * set before proceeding. 1042 */ 1043 tc6->wait_until_start_valid = false; 1044 } 1045 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 1046 return oa_tc6_prcs_rx_frame_start(tc6, 1047 &data[start_byte_offset], 1048 size); 1049 } 1050 1051 /* Process the chunk with ongoing rx frame data */ 1052 return oa_tc6_prcs_ongoing_rx_frame(tc6, data, footer); 1053 } 1054 1055 static u32 oa_tc6_get_rx_chunk_footer(struct oa_tc6 *tc6, u16 footer_offset) 1056 { 1057 u8 *rx_buf = tc6->spi_data_rx_buf; 1058 __be32 footer; 1059 1060 footer = *((__be32 *)&rx_buf[footer_offset]); 1061 1062 return be32_to_cpu(footer); 1063 } 1064 1065 static int oa_tc6_process_spi_data_rx_buf(struct oa_tc6 *tc6, u16 length) 1066 { 1067 u16 no_of_rx_chunks = length / OA_TC6_CHUNK_SIZE; 1068 bool retry = false; 1069 int ret = 0; 1070 u32 footer; 1071 1072 /* All the rx chunks in the receive SPI data buffer are examined here */ 1073 for (int i = 0; i < no_of_rx_chunks; i++) { 1074 /* Last 4 bytes in each received chunk consist footer info */ 1075 footer = oa_tc6_get_rx_chunk_footer(tc6, i * OA_TC6_CHUNK_SIZE + 1076 OA_TC6_CHUNK_PAYLOAD_SIZE); 1077 1078 ret = oa_tc6_process_rx_chunk_footer(tc6, footer); 1079 if (ret) { 1080 if (ret != -EAGAIN) 1081 return ret; 1082 retry = true; 1083 } 1084 1085 /* If there is a data valid chunks then process it for the 1086 * information needed to determine the validity and the location 1087 * of the receive frame data. 1088 */ 1089 if (FIELD_GET(OA_TC6_DATA_FOOTER_DATA_VALID, footer)) { 1090 u8 *payload = tc6->spi_data_rx_buf + i * 1091 OA_TC6_CHUNK_SIZE; 1092 1093 ret = oa_tc6_prcs_rx_chunk_payload(tc6, payload, 1094 footer); 1095 if (ret) { 1096 if (ret != -ENOMEM && ret != -EAGAIN) 1097 return ret; 1098 retry = true; 1099 } 1100 } 1101 } 1102 1103 /* Not bailing out on recoverable error codes, -EAGAIN and 1104 * -ENOMEM. If subsequent loop iterations, if any, succeeds, 1105 * error code would be overwritten. retry flag helps to 1106 * make the caller to continue and retry. Since recovery 1107 * action for -ENOMEM and -EAGAIN are same, we are returning 1108 * one of the error codes, that is -EAGAIN. 1109 * 1110 * Successful recovery depends on how small the frames are, 1111 * how many chunks, among the received chunks triggered the 1112 * error, whether data is intact even with error conditions. 1113 * As a result, there is no single, best method to recover 1114 * most data when error conditions hit. We do our best by 1115 * processing all the chunks with good "footer header" and 1116 * "data valid" bit set. 1117 */ 1118 if (retry) { 1119 ret = -EAGAIN; 1120 oa_tc6_look_for_new_frame(tc6); 1121 } 1122 1123 return ret; 1124 } 1125 1126 static __be32 oa_tc6_prepare_data_header(bool data_valid, bool start_valid, 1127 bool end_valid, u8 end_byte_offset) 1128 { 1129 u32 header = FIELD_PREP(OA_TC6_DATA_HEADER_DATA_NOT_CTRL, 1130 OA_TC6_DATA_HEADER) | 1131 FIELD_PREP(OA_TC6_DATA_HEADER_DATA_VALID, data_valid) | 1132 FIELD_PREP(OA_TC6_DATA_HEADER_START_VALID, start_valid) | 1133 FIELD_PREP(OA_TC6_DATA_HEADER_END_VALID, end_valid) | 1134 FIELD_PREP(OA_TC6_DATA_HEADER_END_BYTE_OFFSET, 1135 end_byte_offset); 1136 1137 header |= FIELD_PREP(OA_TC6_DATA_HEADER_PARITY, 1138 oa_tc6_get_parity(header)); 1139 1140 return cpu_to_be32(header); 1141 } 1142 1143 static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6 *tc6) 1144 { 1145 enum oa_tc6_data_end_valid_info end_valid = OA_TC6_DATA_END_INVALID; 1146 __be32 *tx_buf = tc6->spi_data_tx_buf + tc6->spi_data_tx_buf_offset; 1147 u16 remaining_len = tc6->ongoing_tx_skb->len - tc6->tx_skb_offset; 1148 u8 *tx_skb_data = tc6->ongoing_tx_skb->data + tc6->tx_skb_offset; 1149 enum oa_tc6_data_start_valid_info start_valid; 1150 u8 end_byte_offset = 0; 1151 u16 length_to_copy; 1152 1153 /* Initial value is assigned here to avoid more than 80 characters in 1154 * the declaration place. 1155 */ 1156 start_valid = OA_TC6_DATA_START_INVALID; 1157 1158 /* Set start valid if the current tx chunk contains the start of the tx 1159 * ethernet frame. 1160 */ 1161 if (!tc6->tx_skb_offset) 1162 start_valid = OA_TC6_DATA_START_VALID; 1163 1164 /* If the remaining tx skb length is more than the chunk payload size of 1165 * 64 bytes then copy only 64 bytes and leave the ongoing tx skb for 1166 * next tx chunk. 1167 */ 1168 length_to_copy = min_t(u16, remaining_len, OA_TC6_CHUNK_PAYLOAD_SIZE); 1169 1170 /* Copy the tx skb data to the tx chunk payload buffer */ 1171 memcpy(tx_buf + 1, tx_skb_data, length_to_copy); 1172 tc6->tx_skb_offset += length_to_copy; 1173 1174 /* Set end valid if the current tx chunk contains the end of the tx 1175 * ethernet frame. 1176 */ 1177 if (tc6->ongoing_tx_skb->len == tc6->tx_skb_offset) { 1178 end_valid = OA_TC6_DATA_END_VALID; 1179 end_byte_offset = length_to_copy - 1; 1180 tc6->tx_skb_offset = 0; 1181 tc6->netdev->stats.tx_bytes += tc6->ongoing_tx_skb->len; 1182 tc6->netdev->stats.tx_packets++; 1183 kfree_skb(tc6->ongoing_tx_skb); 1184 tc6->ongoing_tx_skb = NULL; 1185 } 1186 1187 *tx_buf = oa_tc6_prepare_data_header(OA_TC6_DATA_VALID, start_valid, 1188 end_valid, end_byte_offset); 1189 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1190 } 1191 1192 static u16 oa_tc6_prepare_spi_tx_buf_for_tx_skbs(struct oa_tc6 *tc6) 1193 { 1194 u16 used_tx_credits; 1195 1196 /* Get tx skbs and convert them into tx chunks based on the tx credits 1197 * available. 1198 */ 1199 for (used_tx_credits = 0; used_tx_credits < tc6->tx_credits; 1200 used_tx_credits++) { 1201 if (!tc6->ongoing_tx_skb) { 1202 spin_lock_bh(&tc6->tx_skb_lock); 1203 tc6->ongoing_tx_skb = tc6->waiting_tx_skb; 1204 tc6->waiting_tx_skb = NULL; 1205 spin_unlock_bh(&tc6->tx_skb_lock); 1206 } 1207 if (!tc6->ongoing_tx_skb) 1208 break; 1209 oa_tc6_add_tx_skb_to_spi_buf(tc6); 1210 } 1211 1212 return used_tx_credits * OA_TC6_CHUNK_SIZE; 1213 } 1214 1215 static void oa_tc6_add_empty_chunks_to_spi_buf(struct oa_tc6 *tc6, 1216 u16 needed_empty_chunks) 1217 { 1218 __be32 header; 1219 1220 header = oa_tc6_prepare_data_header(OA_TC6_DATA_INVALID, 1221 OA_TC6_DATA_START_INVALID, 1222 OA_TC6_DATA_END_INVALID, 0); 1223 1224 while (needed_empty_chunks--) { 1225 __be32 *tx_buf = tc6->spi_data_tx_buf + 1226 tc6->spi_data_tx_buf_offset; 1227 1228 *tx_buf = header; 1229 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1230 } 1231 } 1232 1233 static u16 oa_tc6_prepare_spi_tx_buf_for_rx_chunks(struct oa_tc6 *tc6, u16 len) 1234 { 1235 u16 tx_chunks = len / OA_TC6_CHUNK_SIZE; 1236 u16 needed_empty_chunks; 1237 1238 /* If there are more chunks to receive than to transmit, we need to add 1239 * enough empty tx chunks to allow the reception of the excess rx 1240 * chunks. 1241 */ 1242 if (tx_chunks >= tc6->rx_chunks_available) 1243 return len; 1244 1245 needed_empty_chunks = tc6->rx_chunks_available - tx_chunks; 1246 1247 oa_tc6_add_empty_chunks_to_spi_buf(tc6, needed_empty_chunks); 1248 1249 return needed_empty_chunks * OA_TC6_CHUNK_SIZE + len; 1250 } 1251 1252 static int oa_tc6_try_spi_transfer(struct oa_tc6 *tc6) 1253 { 1254 int ret; 1255 1256 while (true) { 1257 u16 spi_len = 0; 1258 1259 tc6->spi_data_tx_buf_offset = 0; 1260 1261 if (tc6->ongoing_tx_skb || tc6->waiting_tx_skb) 1262 spi_len = oa_tc6_prepare_spi_tx_buf_for_tx_skbs(tc6); 1263 1264 spi_len = oa_tc6_prepare_spi_tx_buf_for_rx_chunks(tc6, spi_len); 1265 1266 if (tc6->int_flag) { 1267 tc6->int_flag = false; 1268 if (spi_len == 0) { 1269 oa_tc6_add_empty_chunks_to_spi_buf(tc6, 1); 1270 spi_len = OA_TC6_CHUNK_SIZE; 1271 } 1272 } 1273 1274 if (spi_len == 0) 1275 break; 1276 1277 ret = oa_tc6_spi_transfer(tc6, OA_TC6_DATA_HEADER, spi_len); 1278 if (ret) { 1279 netdev_err(tc6->netdev, "SPI data transfer failed: %d\n", 1280 ret); 1281 return ret; 1282 } 1283 1284 ret = oa_tc6_process_spi_data_rx_buf(tc6, spi_len); 1285 1286 if (ret && ret != -EAGAIN) { 1287 oa_tc6_free_ongoing_skbs(tc6); 1288 netdev_err(tc6->netdev, "Device error: %d\n", ret); 1289 return ret; 1290 } 1291 1292 if (!tc6->waiting_tx_skb && netif_queue_stopped(tc6->netdev)) 1293 netif_wake_queue(tc6->netdev); 1294 } 1295 1296 return 0; 1297 } 1298 1299 static irqreturn_t oa_tc6_macphy_threaded_irq(int irq, void *data) 1300 { 1301 struct oa_tc6 *tc6 = data; 1302 int ret = 0; 1303 1304 /* It is possible that interrupt woke the thread before it is 1305 * disabled. Until we come up with good recovery mechanism, 1306 * no need to attempt spi transfer, once it fails. Pending skbs 1307 * are already freed. 1308 */ 1309 spin_lock_bh(&tc6->tx_skb_lock); 1310 if (tc6->disable_traffic) { 1311 spin_unlock_bh(&tc6->tx_skb_lock); 1312 return IRQ_HANDLED; 1313 } 1314 spin_unlock_bh(&tc6->tx_skb_lock); 1315 1316 while (tc6->int_flag || 1317 (tc6->waiting_tx_skb && tc6->tx_credits)) { 1318 ret = oa_tc6_try_spi_transfer(tc6); 1319 if (ret) { 1320 disable_irq_nosync(tc6->spi->irq); 1321 oa_tc6_disable_traffic(tc6); 1322 break; 1323 } 1324 } 1325 1326 return IRQ_HANDLED; 1327 } 1328 1329 static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6) 1330 { 1331 u32 value; 1332 int ret; 1333 1334 /* Initially tx credits and rx chunks available to be updated from the 1335 * register as there is no data transfer performed yet. Later they will 1336 * be updated from the rx footer. 1337 */ 1338 ret = oa_tc6_read_register(tc6, OA_TC6_REG_BUFFER_STATUS, &value); 1339 if (ret) 1340 return ret; 1341 1342 tc6->tx_credits = FIELD_GET(OA_TC6_BUFFER_STATUS_TX_CREDITS_AVAILABLE, 1343 value); 1344 tc6->rx_chunks_available = 1345 FIELD_GET(OA_TC6_BUFFER_STATUS_RX_CHUNKS_AVAILABLE, value); 1346 1347 return 0; 1348 } 1349 1350 static irqreturn_t oa_tc6_macphy_isr(int irq, void *data) 1351 { 1352 struct oa_tc6 *tc6 = data; 1353 1354 /* MAC-PHY interrupt can occur for the following reasons. 1355 * - availability of tx credits if it was 0 before and not reported in 1356 * the previous rx footer. 1357 * - availability of rx chunks if it was 0 before and not reported in 1358 * the previous rx footer. 1359 * - extended status event not reported in the previous rx footer. 1360 */ 1361 if (tc6->disable_traffic) 1362 disable_irq_nosync(tc6->spi->irq); 1363 else 1364 tc6->int_flag = true; 1365 /* Wake IRQ thread to perform spi transfer . In case 1366 * disable_traffic is set, threaded irq may run again 1367 * one more time. 1368 */ 1369 return IRQ_WAKE_THREAD; 1370 } 1371 1372 /** 1373 * oa_tc6_zero_align_receive_frame_enable - function to enable zero align 1374 * receive frame feature. 1375 * @tc6: oa_tc6 struct. 1376 * 1377 * Return: 0 on success otherwise failed. 1378 */ 1379 int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6) 1380 { 1381 u32 regval; 1382 int ret; 1383 1384 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1385 if (ret) 1386 return ret; 1387 1388 /* Set Zero-Align Receive Frame Enable */ 1389 regval |= OA_TC6_CONFIG0_ZARFE_ENABLE; 1390 1391 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval); 1392 } 1393 EXPORT_SYMBOL_GPL(oa_tc6_zero_align_receive_frame_enable); 1394 1395 /** 1396 * oa_tc6_start_xmit - function for sending the tx skb which consists ethernet 1397 * frame. 1398 * @tc6: oa_tc6 struct. 1399 * @skb: socket buffer in which the ethernet frame is stored. 1400 * 1401 * Return: NETDEV_TX_OK either on successful queueing of the packet for 1402 * transmission, or on packet getting dropped. Packet can be dropped due to 1403 * failure in linearizing the buffer or disable_traffic is set due to 1404 * earlier fatal error. Returns NETDEV_TX_BUSY when there is no room 1405 * to queue the packet. 1406 */ 1407 netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb) 1408 { 1409 if (skb_linearize(skb)) { 1410 oa_tc6_drop_tx_skb(tc6, skb); 1411 return NETDEV_TX_OK; 1412 } 1413 1414 spin_lock_bh(&tc6->tx_skb_lock); 1415 if (tc6->waiting_tx_skb) { 1416 netif_stop_queue(tc6->netdev); 1417 spin_unlock_bh(&tc6->tx_skb_lock); 1418 return NETDEV_TX_BUSY; 1419 } 1420 if (tc6->disable_traffic) { 1421 spin_unlock_bh(&tc6->tx_skb_lock); 1422 oa_tc6_drop_tx_skb(tc6, skb); 1423 return NETDEV_TX_OK; 1424 } 1425 tc6->waiting_tx_skb = skb; 1426 spin_unlock_bh(&tc6->tx_skb_lock); 1427 1428 /* Wake the threaded IRQ to perform spi transfer. */ 1429 irq_wake_thread(tc6->spi->irq, tc6); 1430 1431 return NETDEV_TX_OK; 1432 } 1433 EXPORT_SYMBOL_GPL(oa_tc6_start_xmit); 1434 1435 static int oa_tc6_check_ctrl_protection(struct oa_tc6 *tc6) 1436 { 1437 u32 regval; 1438 int ret; 1439 1440 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1441 if (ret) 1442 return ret; 1443 1444 tc6->prot_ctrl = FIELD_GET(OA_TC6_CONFIG0_PROTE, regval); 1445 1446 return 0; 1447 } 1448 1449 /** 1450 * oa_tc6_init - allocates and initializes oa_tc6 structure. 1451 * @spi: device with which data will be exchanged. 1452 * @netdev: network device interface structure. 1453 * @quirks: device specific modifiers for the OA TC6 protocol. 1454 * 1455 * Return: pointer reference to the oa_tc6 structure if the MAC-PHY 1456 * initialization is successful otherwise NULL. 1457 */ 1458 struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev, 1459 struct oa_tc6_quirks *quirks) 1460 { 1461 struct oa_tc6 *tc6; 1462 int ret; 1463 1464 tc6 = devm_kzalloc(&spi->dev, sizeof(*tc6), GFP_KERNEL); 1465 if (!tc6) 1466 return NULL; 1467 1468 tc6->spi = spi; 1469 tc6->netdev = netdev; 1470 SET_NETDEV_DEV(netdev, &spi->dev); 1471 mutex_init(&tc6->spi_ctrl_lock); 1472 spin_lock_init(&tc6->tx_skb_lock); 1473 1474 if (quirks) 1475 tc6->quirk_flags = quirks->quirk_flags; 1476 1477 /* Set the SPI controller to pump at realtime priority */ 1478 tc6->spi->rt = true; 1479 if (spi_setup(tc6->spi) < 0) 1480 return NULL; 1481 1482 tc6->spi_ctrl_tx_buf = devm_kzalloc(&tc6->spi->dev, 1483 OA_TC6_CTRL_SPI_BUF_SIZE, 1484 GFP_KERNEL); 1485 if (!tc6->spi_ctrl_tx_buf) 1486 return NULL; 1487 1488 tc6->spi_ctrl_rx_buf = devm_kzalloc(&tc6->spi->dev, 1489 OA_TC6_CTRL_SPI_BUF_SIZE, 1490 GFP_KERNEL); 1491 if (!tc6->spi_ctrl_rx_buf) 1492 return NULL; 1493 1494 tc6->spi_data_tx_buf = devm_kzalloc(&tc6->spi->dev, 1495 OA_TC6_SPI_DATA_BUF_SIZE, 1496 GFP_KERNEL); 1497 if (!tc6->spi_data_tx_buf) 1498 return NULL; 1499 1500 tc6->spi_data_rx_buf = devm_kzalloc(&tc6->spi->dev, 1501 OA_TC6_SPI_DATA_BUF_SIZE, 1502 GFP_KERNEL); 1503 if (!tc6->spi_data_rx_buf) 1504 return NULL; 1505 1506 /* Check the PROTE bit status so that we can reset the device */ 1507 ret = oa_tc6_check_ctrl_protection(tc6); 1508 if (ret) { 1509 dev_err(&tc6->spi->dev, 1510 "Failed to check the protection mode: %d\n", ret); 1511 return NULL; 1512 } 1513 1514 ret = oa_tc6_sw_reset_macphy(tc6); 1515 if (ret) { 1516 dev_err(&tc6->spi->dev, 1517 "MAC-PHY software reset failed: %d\n", ret); 1518 return NULL; 1519 } 1520 1521 ret = oa_tc6_unmask_macphy_error_interrupts(tc6); 1522 if (ret) { 1523 dev_err(&tc6->spi->dev, 1524 "MAC-PHY error interrupts unmask failed: %d\n", ret); 1525 return NULL; 1526 } 1527 1528 ret = oa_tc6_phy_init(tc6); 1529 if (ret) { 1530 dev_err(&tc6->spi->dev, 1531 "MAC internal PHY initialization failed: %d\n", ret); 1532 return NULL; 1533 } 1534 1535 ret = oa_tc6_enable_data_transfer(tc6); 1536 if (ret) { 1537 dev_err(&tc6->spi->dev, "Failed to enable data transfer: %d\n", 1538 ret); 1539 goto phy_exit; 1540 } 1541 1542 ret = oa_tc6_update_buffer_status_from_register(tc6); 1543 if (ret) { 1544 dev_err(&tc6->spi->dev, 1545 "Failed to update buffer status: %d\n", ret); 1546 goto phy_exit; 1547 } 1548 1549 ret = devm_request_threaded_irq(&tc6->spi->dev, tc6->spi->irq, 1550 oa_tc6_macphy_isr, 1551 oa_tc6_macphy_threaded_irq, 1552 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1553 dev_name(&tc6->spi->dev), tc6); 1554 if (ret) { 1555 dev_err(&tc6->spi->dev, "Failed to request macphy isr %d\n", 1556 ret); 1557 goto phy_exit; 1558 } 1559 1560 /* oa_tc6_sw_reset_macphy() function resets and clears the MAC-PHY reset 1561 * complete status. IRQ is also asserted on reset completion and it is 1562 * remain asserted until MAC-PHY receives a data chunk. So performing an 1563 * empty data chunk transmission will deassert the IRQ. Refer section 1564 * 7.7 and 9.2.8.8 in the OPEN Alliance specification for more details. 1565 */ 1566 tc6->int_flag = true; 1567 irq_wake_thread(tc6->spi->irq, tc6); 1568 1569 return tc6; 1570 1571 phy_exit: 1572 oa_tc6_phy_exit(tc6); 1573 return NULL; 1574 } 1575 EXPORT_SYMBOL_GPL(oa_tc6_init); 1576 1577 /** 1578 * oa_tc6_exit - exit function. 1579 * @tc6: oa_tc6 struct. 1580 */ 1581 void oa_tc6_exit(struct oa_tc6 *tc6) 1582 { 1583 disable_irq(tc6->spi->irq); 1584 spin_lock_bh(&tc6->tx_skb_lock); 1585 tc6->disable_traffic = true; 1586 spin_unlock_bh(&tc6->tx_skb_lock); 1587 oa_tc6_phy_exit(tc6); 1588 oa_tc6_free_pending_skbs(tc6); 1589 } 1590 EXPORT_SYMBOL_GPL(oa_tc6_exit); 1591 1592 MODULE_DESCRIPTION("OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface Lib"); 1593 MODULE_AUTHOR("Parthiban Veerasooran <parthiban.veerasooran@microchip.com>"); 1594 MODULE_LICENSE("GPL"); 1595