1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3036-cru.h> 8#include <dt-bindings/soc/rockchip,boot-mode.h> 9#include <dt-bindings/power/rk3036-power.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 compatible = "rockchip,rk3036"; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 mshc0 = &emmc; 27 mshc1 = &sdmmc; 28 mshc2 = &sdio; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 spi = &spi; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 enable-method = "rockchip,rk3036-smp"; 39 40 cpu0: cpu@f00 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a7"; 43 reg = <0xf00>; 44 resets = <&cru SRST_CORE0>; 45 operating-points = < 46 /* KHz uV */ 47 816000 1000000 48 >; 49 clock-latency = <40000>; 50 clocks = <&cru ARMCLK>; 51 }; 52 53 cpu1: cpu@f01 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf01>; 57 resets = <&cru SRST_CORE1>; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a7-pmu"; 63 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 65 interrupt-affinity = <&cpu0>, <&cpu1>; 66 }; 67 68 display-subsystem { 69 compatible = "rockchip,display-subsystem"; 70 ports = <&vop_out>; 71 }; 72 73 timer { 74 compatible = "arm,armv7-timer"; 75 arm,cpu-registers-not-fw-configured; 76 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 77 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 78 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 80 clock-frequency = <24000000>; 81 }; 82 83 xin24m: oscillator { 84 compatible = "fixed-clock"; 85 clock-frequency = <24000000>; 86 clock-output-names = "xin24m"; 87 #clock-cells = <0>; 88 }; 89 90 bus_intmem: sram@10080000 { 91 compatible = "mmio-sram"; 92 reg = <0x10080000 0x2000>; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0 0x10080000 0x2000>; 96 97 smp-sram@0 { 98 compatible = "rockchip,rk3066-smp-sram"; 99 reg = <0x00 0x10>; 100 }; 101 }; 102 103 gpu: gpu@10090000 { 104 compatible = "rockchip,rk3036-mali", "arm,mali-400"; 105 reg = <0x10090000 0x10000>; 106 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 110 interrupt-names = "gp", 111 "gpmmu", 112 "pp0", 113 "ppmmu0"; 114 assigned-clocks = <&cru SCLK_GPU>; 115 assigned-clock-rates = <100000000>; 116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 117 clock-names = "bus", "core"; 118 power-domains = <&power RK3036_PD_GPU>; 119 resets = <&cru SRST_GPU>; 120 status = "disabled"; 121 }; 122 123 vpu: video-codec@10108000 { 124 compatible = "rockchip,rk3036-vpu"; 125 reg = <0x10108000 0x800>; 126 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-names = "vdpu"; 128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 129 clock-names = "aclk", "hclk"; 130 iommus = <&vpu_mmu>; 131 power-domains = <&power RK3036_PD_VPU>; 132 }; 133 134 vpu_mmu: iommu@10108800 { 135 compatible = "rockchip,iommu"; 136 reg = <0x10108800 0x100>; 137 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 139 clock-names = "aclk", "iface"; 140 power-domains = <&power RK3036_PD_VPU>; 141 #iommu-cells = <0>; 142 }; 143 144 vop: vop@10118000 { 145 compatible = "rockchip,rk3036-vop"; 146 reg = <0x10118000 0x19c>; 147 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; 149 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 150 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; 151 reset-names = "axi", "ahb", "dclk"; 152 iommus = <&vop_mmu>; 153 power-domains = <&power RK3036_PD_VIO>; 154 status = "disabled"; 155 156 vop_out: port { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 vop_out_hdmi: endpoint@0 { 160 reg = <0>; 161 remote-endpoint = <&hdmi_in_vop>; 162 }; 163 }; 164 }; 165 166 vop_mmu: iommu@10118300 { 167 compatible = "rockchip,iommu"; 168 reg = <0x10118300 0x100>; 169 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; 171 clock-names = "aclk", "iface"; 172 power-domains = <&power RK3036_PD_VIO>; 173 #iommu-cells = <0>; 174 status = "disabled"; 175 }; 176 177 qos_gpu: qos@1012d000 { 178 compatible = "rockchip,rk3036-qos", "syscon"; 179 reg = <0x1012d000 0x20>; 180 }; 181 182 qos_vpu: qos@1012e000 { 183 compatible = "rockchip,rk3036-qos", "syscon"; 184 reg = <0x1012e000 0x20>; 185 }; 186 187 qos_vio: qos@1012f000 { 188 compatible = "rockchip,rk3036-qos", "syscon"; 189 reg = <0x1012f000 0x20>; 190 }; 191 192 gic: interrupt-controller@10139000 { 193 compatible = "arm,gic-400"; 194 interrupt-controller; 195 #interrupt-cells = <3>; 196 #address-cells = <0>; 197 198 reg = <0x10139000 0x1000>, 199 <0x1013a000 0x2000>, 200 <0x1013c000 0x2000>, 201 <0x1013e000 0x2000>; 202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 203 }; 204 205 usb_otg: usb@10180000 { 206 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 207 "snps,dwc2"; 208 reg = <0x10180000 0x40000>; 209 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&cru HCLK_OTG0>; 211 clock-names = "otg"; 212 dr_mode = "otg"; 213 g-np-tx-fifo-size = <16>; 214 g-rx-fifo-size = <275>; 215 g-tx-fifo-size = <256 128 128 64 64 32>; 216 phys = <&usb2phy_otg>; 217 phy-names = "usb2-phy"; 218 status = "disabled"; 219 }; 220 221 usb_host: usb@101c0000 { 222 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 223 "snps,dwc2"; 224 reg = <0x101c0000 0x40000>; 225 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&cru HCLK_OTG1>; 227 clock-names = "otg"; 228 dr_mode = "host"; 229 phys = <&usb2phy_host>; 230 phy-names = "usb2-phy"; 231 status = "disabled"; 232 }; 233 234 emac: ethernet@10200000 { 235 compatible = "rockchip,rk3036-emac"; 236 reg = <0x10200000 0x4000>; 237 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 238 rockchip,grf = <&grf>; 239 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; 240 clock-names = "hclk", "macref", "macclk"; 241 /* 242 * Fix the emac parent clock is DPLL instead of APLL. 243 * since that will cause some unstable things if the cpufreq 244 * is working. (e.g: the accurate 50MHz what mac_ref need) 245 */ 246 assigned-clocks = <&cru SCLK_MACPLL>; 247 assigned-clock-parents = <&cru PLL_DPLL>; 248 max-speed = <100>; 249 phy-mode = "rmii"; 250 status = "disabled"; 251 }; 252 253 sdmmc: mmc@10214000 { 254 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 255 reg = <0x10214000 0x4000>; 256 clock-frequency = <37500000>; 257 max-frequency = <37500000>; 258 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 259 clock-names = "biu", "ciu"; 260 fifo-depth = <0x100>; 261 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 262 resets = <&cru SRST_MMC0>; 263 reset-names = "reset"; 264 status = "disabled"; 265 }; 266 267 sdio: mmc@10218000 { 268 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 269 reg = <0x10218000 0x4000>; 270 max-frequency = <37500000>; 271 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 272 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 273 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 274 fifo-depth = <0x100>; 275 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 276 resets = <&cru SRST_SDIO>; 277 reset-names = "reset"; 278 status = "disabled"; 279 }; 280 281 emmc: mmc@1021c000 { 282 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 283 reg = <0x1021c000 0x4000>; 284 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 285 bus-width = <8>; 286 cap-mmc-highspeed; 287 clock-frequency = <37500000>; 288 max-frequency = <37500000>; 289 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 290 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 291 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 292 disable-wp; 293 dmas = <&pdma 12>; 294 dma-names = "rx-tx"; 295 fifo-depth = <0x100>; 296 mmc-ddr-1_8v; 297 non-removable; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 300 resets = <&cru SRST_EMMC>; 301 reset-names = "reset"; 302 status = "disabled"; 303 }; 304 305 i2s: i2s@10220000 { 306 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; 307 reg = <0x10220000 0x4000>; 308 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 309 clock-names = "i2s_clk", "i2s_hclk"; 310 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; 311 dmas = <&pdma 0>, <&pdma 1>; 312 dma-names = "tx", "rx"; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2s_bus>; 315 #sound-dai-cells = <0>; 316 status = "disabled"; 317 }; 318 319 nfc: nand-controller@10500000 { 320 compatible = "rockchip,rk3036-nfc", 321 "rockchip,rk2928-nfc"; 322 reg = <0x10500000 0x4000>; 323 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 325 clock-names = "ahb", "nfc"; 326 assigned-clocks = <&cru SCLK_NANDC>; 327 assigned-clock-rates = <150000000>; 328 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 329 &flash_rdn &flash_rdy &flash_wrn>; 330 pinctrl-names = "default"; 331 status = "disabled"; 332 }; 333 334 cru: clock-controller@20000000 { 335 compatible = "rockchip,rk3036-cru"; 336 reg = <0x20000000 0x1000>; 337 clocks = <&xin24m>; 338 clock-names = "xin24m"; 339 rockchip,grf = <&grf>; 340 #clock-cells = <1>; 341 #reset-cells = <1>; 342 assigned-clocks = <&cru PLL_GPLL>; 343 assigned-clock-rates = <594000000>; 344 }; 345 346 grf: syscon@20008000 { 347 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; 348 reg = <0x20008000 0x1000>; 349 #address-cells = <1>; 350 #size-cells = <1>; 351 352 usb2phy: usb2phy@17c { 353 compatible = "rockchip,rk3036-usb2phy"; 354 reg = <0x017c 0x20>; 355 clocks = <&cru SCLK_OTGPHY0>; 356 clock-names = "phyclk"; 357 clock-output-names = "usb480m_phy"; 358 assigned-clocks = <&cru SCLK_USB480M>; 359 assigned-clock-parents = <&usb2phy>; 360 #clock-cells = <0>; 361 status = "disabled"; 362 363 usb2phy_host: host-port { 364 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "linestate"; 366 #phy-cells = <0>; 367 status = "disabled"; 368 }; 369 370 usb2phy_otg: otg-port { 371 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-names = "otg-bvalid", "otg-id", 375 "linestate"; 376 #phy-cells = <0>; 377 status = "disabled"; 378 }; 379 }; 380 381 power: power-controller { 382 compatible = "rockchip,rk3036-power-controller"; 383 #power-domain-cells = <1>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 387 power-domain@RK3036_PD_VIO { 388 reg = <RK3036_PD_VIO>; 389 clocks = <&cru ACLK_LCDC>, 390 <&cru HCLK_LCDC>, 391 <&cru SCLK_LCDC>; 392 pm_qos = <&qos_vio>; 393 #power-domain-cells = <0>; 394 }; 395 396 power-domain@RK3036_PD_VPU { 397 reg = <RK3036_PD_VPU>; 398 clocks = <&cru ACLK_VCODEC>, 399 <&cru HCLK_VCODEC>; 400 pm_qos = <&qos_vpu>; 401 #power-domain-cells = <0>; 402 }; 403 404 power-domain@RK3036_PD_GPU { 405 reg = <RK3036_PD_GPU>; 406 clocks = <&cru SCLK_GPU>; 407 pm_qos = <&qos_gpu>; 408 #power-domain-cells = <0>; 409 }; 410 }; 411 412 reboot-mode { 413 compatible = "syscon-reboot-mode"; 414 offset = <0x1d8>; 415 mode-normal = <BOOT_NORMAL>; 416 mode-recovery = <BOOT_RECOVERY>; 417 mode-bootloader = <BOOT_FASTBOOT>; 418 mode-loader = <BOOT_BL_DOWNLOAD>; 419 }; 420 }; 421 422 acodec: audio-codec@20030000 { 423 compatible = "rockchip,rk3036-codec"; 424 reg = <0x20030000 0x4000>; 425 clock-names = "acodec_pclk"; 426 clocks = <&cru PCLK_ACODEC>; 427 rockchip,grf = <&grf>; 428 #sound-dai-cells = <0>; 429 status = "disabled"; 430 }; 431 432 hdmi: hdmi@20034000 { 433 compatible = "rockchip,rk3036-inno-hdmi"; 434 reg = <0x20034000 0x4000>; 435 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; 437 clock-names = "pclk", "ref"; 438 rockchip,grf = <&grf>; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&hdmi_ctl>; 441 #sound-dai-cells = <0>; 442 status = "disabled"; 443 444 ports { 445 #address-cells = <1>; 446 #size-cells = <0>; 447 448 hdmi_in: port@0 { 449 reg = <0>; 450 451 hdmi_in_vop: endpoint { 452 remote-endpoint = <&vop_out_hdmi>; 453 }; 454 }; 455 456 hdmi_out: port@1 { 457 reg = <1>; 458 }; 459 }; 460 }; 461 462 timer: timer@20044000 { 463 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; 464 reg = <0x20044000 0x20>; 465 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cru PCLK_TIMER>, <&xin24m>; 467 clock-names = "pclk", "timer"; 468 }; 469 470 pwm0: pwm@20050000 { 471 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 472 reg = <0x20050000 0x10>; 473 #pwm-cells = <3>; 474 clocks = <&cru PCLK_PWM>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pwm0_pin>; 477 status = "disabled"; 478 }; 479 480 pwm1: pwm@20050010 { 481 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 482 reg = <0x20050010 0x10>; 483 #pwm-cells = <3>; 484 clocks = <&cru PCLK_PWM>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pwm1_pin>; 487 status = "disabled"; 488 }; 489 490 pwm2: pwm@20050020 { 491 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 492 reg = <0x20050020 0x10>; 493 #pwm-cells = <3>; 494 clocks = <&cru PCLK_PWM>; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pwm2_pin>; 497 status = "disabled"; 498 }; 499 500 pwm3: pwm@20050030 { 501 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 502 reg = <0x20050030 0x10>; 503 #pwm-cells = <2>; 504 clocks = <&cru PCLK_PWM>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pwm3_pin>; 507 status = "disabled"; 508 }; 509 510 i2c1: i2c@20056000 { 511 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 512 reg = <0x20056000 0x1000>; 513 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 clock-names = "i2c"; 517 clocks = <&cru PCLK_I2C1>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&i2c1_xfer>; 520 status = "disabled"; 521 }; 522 523 i2c2: i2c@2005a000 { 524 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 525 reg = <0x2005a000 0x1000>; 526 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 clock-names = "i2c"; 530 clocks = <&cru PCLK_I2C2>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&i2c2_xfer>; 533 status = "disabled"; 534 }; 535 536 uart0: serial@20060000 { 537 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 538 reg = <0x20060000 0x100>; 539 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 540 reg-shift = <2>; 541 reg-io-width = <4>; 542 clock-frequency = <24000000>; 543 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 544 clock-names = "baudclk", "apb_pclk"; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 547 status = "disabled"; 548 }; 549 550 uart1: serial@20064000 { 551 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 552 reg = <0x20064000 0x100>; 553 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 554 reg-shift = <2>; 555 reg-io-width = <4>; 556 clock-frequency = <24000000>; 557 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 558 clock-names = "baudclk", "apb_pclk"; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&uart1_xfer>; 561 status = "disabled"; 562 }; 563 564 uart2: serial@20068000 { 565 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 566 reg = <0x20068000 0x100>; 567 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 568 reg-shift = <2>; 569 reg-io-width = <4>; 570 clock-frequency = <24000000>; 571 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 572 clock-names = "baudclk", "apb_pclk"; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&uart2_xfer>; 575 status = "disabled"; 576 }; 577 578 i2c0: i2c@20072000 { 579 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 580 reg = <0x20072000 0x1000>; 581 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clock-names = "i2c"; 585 clocks = <&cru PCLK_I2C0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&i2c0_xfer>; 588 status = "disabled"; 589 }; 590 591 spi: spi@20074000 { 592 compatible = "rockchip,rk3036-spi"; 593 reg = <0x20074000 0x1000>; 594 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 596 clock-names = "spiclk", "apb_pclk"; 597 dmas = <&pdma 8>, <&pdma 9>; 598 dma-names = "tx", "rx"; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 pdma: dma-controller@20078000 { 607 compatible = "arm,pl330", "arm,primecell"; 608 reg = <0x20078000 0x4000>; 609 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 611 #dma-cells = <1>; 612 arm,pl330-broken-no-flushp; 613 arm,pl330-periph-burst; 614 clocks = <&cru ACLK_DMAC2>; 615 clock-names = "apb_pclk"; 616 }; 617 618 pinctrl: pinctrl { 619 compatible = "rockchip,rk3036-pinctrl"; 620 rockchip,grf = <&grf>; 621 #address-cells = <1>; 622 #size-cells = <1>; 623 ranges; 624 625 gpio0: gpio@2007c000 { 626 compatible = "rockchip,gpio-bank"; 627 reg = <0x2007c000 0x100>; 628 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cru PCLK_GPIO0>; 630 631 gpio-controller; 632 #gpio-cells = <2>; 633 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 gpio1: gpio@20080000 { 639 compatible = "rockchip,gpio-bank"; 640 reg = <0x20080000 0x100>; 641 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cru PCLK_GPIO1>; 643 644 gpio-controller; 645 #gpio-cells = <2>; 646 647 interrupt-controller; 648 #interrupt-cells = <2>; 649 }; 650 651 gpio2: gpio@20084000 { 652 compatible = "rockchip,gpio-bank"; 653 reg = <0x20084000 0x100>; 654 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&cru PCLK_GPIO2>; 656 657 gpio-controller; 658 #gpio-cells = <2>; 659 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 }; 663 664 pcfg_pull_default: pcfg-pull-default { 665 bias-pull-pin-default; 666 }; 667 668 pcfg_pull_none: pcfg-pull-none { 669 bias-disable; 670 }; 671 672 pwm0 { 673 pwm0_pin: pwm0-pin { 674 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 675 }; 676 }; 677 678 pwm1 { 679 pwm1_pin: pwm1-pin { 680 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 681 }; 682 }; 683 684 pwm2 { 685 pwm2_pin: pwm2-pin { 686 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 687 }; 688 }; 689 690 pwm3 { 691 pwm3_pin: pwm3-pin { 692 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 693 }; 694 }; 695 696 sdmmc { 697 sdmmc_clk: sdmmc-clk { 698 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 699 }; 700 701 sdmmc_cmd: sdmmc-cmd { 702 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 703 }; 704 705 sdmmc_cd: sdmmc-cd { 706 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 707 }; 708 709 sdmmc_bus1: sdmmc-bus1 { 710 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; 711 }; 712 713 sdmmc_bus4: sdmmc-bus4 { 714 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 715 <1 RK_PC3 1 &pcfg_pull_default>, 716 <1 RK_PC4 1 &pcfg_pull_default>, 717 <1 RK_PC5 1 &pcfg_pull_default>; 718 }; 719 }; 720 721 sdio { 722 sdio_bus1: sdio-bus1 { 723 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; 724 }; 725 726 sdio_bus4: sdio-bus4 { 727 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, 728 <0 RK_PB4 1 &pcfg_pull_default>, 729 <0 RK_PB5 1 &pcfg_pull_default>, 730 <0 RK_PB6 1 &pcfg_pull_default>; 731 }; 732 733 sdio_cmd: sdio-cmd { 734 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; 735 }; 736 737 sdio_clk: sdio-clk { 738 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; 739 }; 740 }; 741 742 emmc { 743 /* 744 * We run eMMC at max speed; bump up drive strength. 745 * We also have external pulls, so disable the internal ones. 746 */ 747 emmc_clk: emmc-clk { 748 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 749 }; 750 751 emmc_cmd: emmc-cmd { 752 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; 753 }; 754 755 emmc_bus8: emmc-bus8 { 756 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 757 <1 RK_PD1 2 &pcfg_pull_default>, 758 <1 RK_PD2 2 &pcfg_pull_default>, 759 <1 RK_PD3 2 &pcfg_pull_default>, 760 <1 RK_PD4 2 &pcfg_pull_default>, 761 <1 RK_PD5 2 &pcfg_pull_default>, 762 <1 RK_PD6 2 &pcfg_pull_default>, 763 <1 RK_PD7 2 &pcfg_pull_default>; 764 }; 765 }; 766 767 nfc { 768 flash_ale: flash-ale { 769 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; 770 }; 771 772 flash_bus8: flash-bus8 { 773 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, 774 <1 RK_PD1 1 &pcfg_pull_default>, 775 <1 RK_PD2 1 &pcfg_pull_default>, 776 <1 RK_PD3 1 &pcfg_pull_default>, 777 <1 RK_PD4 1 &pcfg_pull_default>, 778 <1 RK_PD5 1 &pcfg_pull_default>, 779 <1 RK_PD6 1 &pcfg_pull_default>, 780 <1 RK_PD7 1 &pcfg_pull_default>; 781 }; 782 783 flash_cle: flash-cle { 784 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; 785 }; 786 787 flash_csn0: flash-csn0 { 788 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; 789 }; 790 791 flash_rdn: flash-rdn { 792 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; 793 }; 794 795 flash_rdy: flash-rdy { 796 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; 797 }; 798 799 flash_wrn: flash-wrn { 800 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; 801 }; 802 }; 803 804 emac { 805 emac_xfer: emac-xfer { 806 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ 807 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ 808 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ 809 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ 810 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ 811 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ 812 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ 813 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ 814 }; 815 816 emac_mdio: emac-mdio { 817 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ 818 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ 819 }; 820 }; 821 822 i2c0 { 823 i2c0_xfer: i2c0-xfer { 824 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 825 <0 RK_PA1 1 &pcfg_pull_none>; 826 }; 827 }; 828 829 i2c1 { 830 i2c1_xfer: i2c1-xfer { 831 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 832 <0 RK_PA3 1 &pcfg_pull_none>; 833 }; 834 }; 835 836 i2c2 { 837 i2c2_xfer: i2c2-xfer { 838 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 839 <2 RK_PC5 1 &pcfg_pull_none>; 840 }; 841 }; 842 843 i2s { 844 i2s_bus: i2s-bus { 845 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 846 <1 RK_PA1 1 &pcfg_pull_default>, 847 <1 RK_PA2 1 &pcfg_pull_default>, 848 <1 RK_PA3 1 &pcfg_pull_default>, 849 <1 RK_PA4 1 &pcfg_pull_default>, 850 <1 RK_PA5 1 &pcfg_pull_default>; 851 }; 852 }; 853 854 hdmi { 855 hdmi_ctl: hdmi-ctl { 856 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, 857 <1 RK_PB1 1 &pcfg_pull_none>, 858 <1 RK_PB2 1 &pcfg_pull_none>, 859 <1 RK_PB3 1 &pcfg_pull_none>; 860 }; 861 }; 862 863 uart0 { 864 uart0_xfer: uart0-xfer { 865 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 866 <0 RK_PC1 1 &pcfg_pull_none>; 867 }; 868 869 uart0_cts: uart0-cts { 870 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; 871 }; 872 873 uart0_rts: uart0-rts { 874 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; 875 }; 876 }; 877 878 uart1 { 879 uart1_xfer: uart1-xfer { 880 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, 881 <2 RK_PC7 1 &pcfg_pull_none>; 882 }; 883 /* no rts / cts for uart1 */ 884 }; 885 886 uart2 { 887 uart2_xfer: uart2-xfer { 888 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 889 <1 RK_PC3 2 &pcfg_pull_none>; 890 }; 891 /* no rts / cts for uart2 */ 892 }; 893 894 spi-pins { 895 spi_txd:spi-txd { 896 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 897 }; 898 899 spi_rxd:spi-rxd { 900 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 901 }; 902 903 spi_clk:spi-clk { 904 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 905 }; 906 907 spi_cs0:spi-cs0 { 908 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 909 910 }; 911 912 spi_cs1:spi-cs1 { 913 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 914 915 }; 916 }; 917 }; 918}; 919