1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include <linux/dmi.h> 15 #include <linux/soundwire/sdw_amd.h> 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 19 #define ACP_MAX_STREAM 8 20 21 #define ACP_DSP_BAR 0 22 23 #define ACP_HW_SEM_RETRY_COUNT 10000 24 #define ACP_REG_POLL_INTERVAL 500 25 #define ACP_REG_POLL_TIMEOUT_US 2000 26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28 #define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01 29 #define ACP3X_PGFSM_STATUS_MASK 0x03 30 #define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07 31 #define ACP6X_PGFSM_STATUS_MASK 0x0F 32 #define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F 33 #define ACP70_PGFSM_STATUS_MASK 0xFF 34 35 #define ACP_POWERED_ON 0x00 36 #define ACP_ASSERT_RESET 0x01 37 #define ACP_RELEASE_RESET 0x00 38 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 39 #define ACP_DSP_ASSERT_RESET 0x04 40 #define ACP_DSP_RELEASE_RESET 0x00 41 #define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004 42 43 #define ACP_DSP_INTR_EN_MASK 0x00000001 44 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 45 #define ACP5X_SRAM_PTE_OFFSET 0x02050000 46 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 47 #define ACP70_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET 48 #define PAGE_SIZE_4K_ENABLE 0x2 49 #define ACP_PAGE_SIZE 0x1000 50 #define ACP_DMA_CH_RUN 0x02 51 #define ACP_MAX_DESC_CNT 0x02 52 #define DSP_FW_RUN_ENABLE 0x01 53 #define ACP_SHA_RUN 0x01 54 #define ACP_SHA_RESET 0x02 55 #define ACP_SHA_HEADER 0x01 56 #define ACP_DMA_CH_RST 0x01 57 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 58 #define ACP_ATU_CACHE_INVALID 0x01 59 #define ACP_MAX_DESC 128 60 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 61 62 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 63 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 64 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 65 #define ACP_IRAM_BASE_ADDRESS 0x000000 66 #define ACP_DRAM_BASE_ADDRESS 0x01000000 67 #define ACP_DRAM_PAGE_COUNT 128 68 #define ACP_SRAM_BASE_ADDRESS 0x3806000 69 #define ACP7X_SRAM_BASE_ADDRESS 0x380C000 70 #define ACP_DSP_TO_HOST_IRQ 0x04 71 72 #define ACP_RN_PCI_ID 0x01 73 #define ACP_VANGOGH_PCI_ID 0x50 74 #define ACP_RMB_PCI_ID 0x6F 75 #define ACP63_PCI_ID 0x63 76 #define ACP70_PCI_ID 0x70 77 #define ACP71_PCI_ID 0x71 78 #define ACP72_PCI_ID 0x72 79 #define ACP7B_PCI_ID 0x7B 80 #define ACP7F_PCI_ID 0x7F 81 82 #define ACP7X_PGFSM_CNTL_POWER_ON_MASK 0x7F 83 #define ACP7X_PGFSM_STATUS_MASK 0xFFF 84 #define ACP7X_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET 85 86 #define HOST_BRIDGE_CZN 0x1630 87 #define HOST_BRIDGE_VGH 0x1645 88 #define HOST_BRIDGE_RMB 0x14B5 89 #define HOST_BRIDGE_ACP63 0x14E8 90 #define HOST_BRIDGE_ACP70 0x1507 91 #define ACP_SHA_STAT 0x8000 92 #define ACP_PSP_TIMEOUT_US 1000000 93 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 94 #define MP0_C2PMSG_114_REG 0x3810AC8 95 #define MP0_C2PMSG_73_REG 0x3810A24 96 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 97 #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000 98 #define MBOX_DELAY_US 1000 99 #define MBOX_READY_MASK 0x80000000 100 #define MBOX_STATUS_MASK 0xFFFF 101 #define MBOX_ISREADY_FLAG 0x40000000 102 #define IRAM_DRAM_FENCE_0 0X0 103 #define IRAM_DRAM_FENCE_1 0X01 104 #define IRAM_DRAM_FENCE_2 0X02 105 106 #define BOX_SIZE_512 0x200 107 #define BOX_SIZE_1024 0x400 108 109 #define EXCEPT_MAX_HDR_SIZE 0x400 110 #define AMD_STACK_DUMP_SIZE 32 111 112 #define SRAM1_SIZE 0x280000 113 #define PROBE_STATUS_BIT BIT(31) 114 115 #define ACP_FIRMWARE_SIGNATURE 0x100 116 #define ACP_IMAGE_HEADER_SIZE ACP_FIRMWARE_SIGNATURE 117 #define ACP_IMAGE_HDR_SIZE_FW_SIGNED_OFF 0x14 118 119 #define ACP_ERROR_IRQ_MASK BIT(29) 120 #define ACP_SDW0_IRQ_MASK BIT(21) 121 #define ACP_SDW1_IRQ_MASK BIT(2) 122 #define SDW_ACPI_ADDR_ACP63 5 123 #define SDW_ACPI_ADDR_ACP70 SDW_ACPI_ADDR_ACP63 124 #define ACP_DEFAULT_SRAM_LENGTH 0x00080000 125 #define ACP_SRAM_PAGE_COUNT 128 126 #define ACP6X_SDW_MAX_MANAGER_COUNT 2 127 #define ACP70_SDW_MAX_MANAGER_COUNT ACP6X_SDW_MAX_MANAGER_COUNT 128 #define ACP_DSP_MSG_SET 1 129 #define ACP_DSP_ACK_SET 1 130 131 enum clock_source { 132 ACP_CLOCK_96M = 0, 133 ACP_CLOCK_48M, 134 ACP_CLOCK_24M, 135 ACP_CLOCK_ACLK, 136 ACP_CLOCK_MCLK, 137 }; 138 139 struct acp_atu_grp_pte { 140 u32 low; 141 u32 high; 142 }; 143 144 union dma_tx_cnt { 145 struct { 146 unsigned int count : 19; 147 unsigned int reserved : 12; 148 unsigned ioc : 1; 149 } bitfields, bits; 150 unsigned int u32_all; 151 signed int i32_all; 152 }; 153 154 struct dma_descriptor { 155 unsigned int src_addr; 156 unsigned int dest_addr; 157 union dma_tx_cnt tx_cnt; 158 unsigned int reserved; 159 }; 160 161 /* Scratch memory structure for communication b/w host and dsp */ 162 struct scratch_ipc_conf { 163 /* Debug memory */ 164 u8 sof_debug_box[1024]; 165 /* Exception memory*/ 166 u8 sof_except_box[1024]; 167 /* Stream buffer */ 168 u8 sof_stream_box[1024]; 169 /* Trace buffer */ 170 u8 sof_trace_box[1024]; 171 /* Host msg flag */ 172 u32 sof_host_msg_write; 173 /* Host ack flag*/ 174 u32 sof_host_ack_write; 175 /* DSP msg flag */ 176 u32 sof_dsp_msg_write; 177 /* Dsp ack flag */ 178 u32 sof_dsp_ack_write; 179 }; 180 181 struct scratch_reg_conf { 182 struct scratch_ipc_conf info; 183 struct acp_atu_grp_pte grp1_pte[16]; 184 struct acp_atu_grp_pte grp2_pte[16]; 185 struct acp_atu_grp_pte grp3_pte[16]; 186 struct acp_atu_grp_pte grp4_pte[16]; 187 struct acp_atu_grp_pte grp5_pte[16]; 188 struct acp_atu_grp_pte grp6_pte[16]; 189 struct acp_atu_grp_pte grp7_pte[16]; 190 struct acp_atu_grp_pte grp8_pte[16]; 191 struct dma_descriptor dma_desc[64]; 192 unsigned int reg_offset[8]; 193 unsigned int buf_size[8]; 194 u8 acp_tx_fifo_buf[256]; 195 u8 acp_rx_fifo_buf[256]; 196 unsigned int reserve[]; 197 }; 198 199 struct acp_dsp_stream { 200 struct list_head list; 201 struct snd_sof_dev *sdev; 202 struct snd_pcm_substream *substream; 203 struct snd_dma_buffer *dmab; 204 int num_pages; 205 int stream_tag; 206 int active; 207 unsigned int reg_offset; 208 size_t posn_offset; 209 struct snd_compr_stream *cstream; 210 u64 cstream_posn; 211 }; 212 213 struct sof_amd_acp_desc { 214 const char *name; 215 u32 pgfsm_base; 216 u32 ext_intr_enb; 217 u32 ext_intr_cntl; 218 u32 ext_intr_stat; 219 u32 ext_intr_stat1; 220 u32 dsp_intr_base; 221 u32 sram_pte_offset; 222 u32 hw_semaphore_offset; 223 u32 acp_clkmux_sel; 224 u32 fusion_dsp_offset; 225 u32 probe_reg_offset; 226 u32 reg_start_addr; 227 u32 reg_end_addr; 228 u32 acp_error_stat; 229 u32 acp_sw0_i2s_err_reason; 230 u32 sdw_max_link_count; 231 u64 sdw_acpi_dev_addr; 232 }; 233 234 struct acp_quirk_entry { 235 bool signed_fw_image; 236 bool skip_iram_dram_size_mod; 237 bool post_fw_run_delay; 238 }; 239 240 /* Common device data struct for ACP devices */ 241 struct acp_dev_data { 242 struct snd_sof_dev *dev; 243 const struct firmware *fw_dbin; 244 /* DMIC device */ 245 struct platform_device *dmic_dev; 246 /* mutex lock to protect ACP common registers access */ 247 struct mutex acp_lock; 248 /* ACPI information stored between scan and probe steps */ 249 struct sdw_amd_acpi_info info; 250 /* sdw context allocated by SoundWire driver */ 251 struct sdw_amd_ctx *sdw; 252 unsigned int fw_bin_size; 253 unsigned int fw_data_bin_size; 254 unsigned int fw_sram_data_bin_size; 255 const char *fw_code_bin; 256 const char *fw_data_bin; 257 const char *fw_sram_data_bin; 258 u32 fw_bin_page_count; 259 u32 fw_data_bin_page_count; 260 u32 addr; 261 u32 reg_range; 262 u32 blk_type; 263 dma_addr_t sha_dma_addr; 264 u8 *bin_buf; 265 dma_addr_t dma_addr; 266 u8 *data_buf; 267 dma_addr_t sram_dma_addr; 268 u8 *sram_data_buf; 269 struct acp_quirk_entry *quirks; 270 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 271 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 272 struct acp_dsp_stream *dtrace_stream; 273 struct acp_dsp_stream *probe_stream; 274 bool enable_fw_debug; 275 bool is_dram_in_use; 276 bool is_sram_in_use; 277 bool sdw_en_stat; 278 /* acp70_sdw0_wake_event flag set to true when wake irq asserted for SW0 instance */ 279 bool acp70_sdw0_wake_event; 280 /* acp70_sdw1_wake_event flag set to true when wake irq asserted for SW1 instance */ 281 bool acp70_sdw1_wake_event; 282 unsigned int pci_rev; 283 int acp_sof_signed_firmware_image; 284 }; 285 286 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 287 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 288 289 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 290 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 291 unsigned int dest_addr, int dsp_data_size); 292 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 293 unsigned int start_addr, unsigned int dest_addr, 294 unsigned int image_length); 295 296 /* ACP device probe/remove */ 297 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 298 void amd_sof_acp_remove(struct snd_sof_dev *sdev); 299 300 /* DSP Loader callbacks */ 301 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 302 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 303 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); 304 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 305 306 /* Block IO callbacks */ 307 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 308 u32 offset, void *src, size_t size); 309 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 310 u32 offset, void *dest, size_t size); 311 312 /* IPC callbacks */ 313 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 314 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 315 void *p, size_t sz); 316 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 317 struct snd_sof_pcm_stream *sps, 318 size_t posn_offset); 319 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 320 struct snd_sof_ipc_msg *msg); 321 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 322 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 323 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 324 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 325 326 /* ACP - DSP stream callbacks */ 327 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 328 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 329 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 330 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 331 332 /* 333 * DSP PCM Operations. 334 */ 335 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 336 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 337 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 338 struct snd_pcm_hw_params *params, 339 struct snd_sof_platform_stream_params *platform_params); 340 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 341 struct snd_pcm_substream *substream); 342 343 extern const struct snd_sof_dsp_ops sof_acp_common_ops; 344 345 extern struct snd_sof_dsp_ops sof_renoir_ops; 346 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 347 extern struct snd_sof_dsp_ops sof_vangogh_ops; 348 int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 349 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 350 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 351 extern struct snd_sof_dsp_ops sof_acp63_ops; 352 int sof_acp63_ops_init(struct snd_sof_dev *sdev); 353 354 extern struct snd_sof_dsp_ops sof_acp70_ops; 355 int sof_acp70_ops_init(struct snd_sof_dev *sdev); 356 357 extern struct snd_sof_dsp_ops sof_acp7x_ops; 358 int sof_acp7x_ops_init(struct snd_sof_dev *sdev); 359 360 int amd_sof_acp7x_probe(struct snd_sof_dev *sdev); 361 void amd_sof_acp7x_remove(struct snd_sof_dev *sdev); 362 int amd_sof_acp7x_suspend(struct snd_sof_dev *sdev, u32 target_state); 363 int amd_sof_acp7x_resume(struct snd_sof_dev *sdev); 364 int amd_sof_acp7x_suspend_runtime(struct snd_sof_dev *sdev); 365 int amd_sof_acp7x_resume_runtime(struct snd_sof_dev *sdev); 366 367 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 368 /* Machine configuration */ 369 int snd_amd_acp_find_config(struct pci_dev *pci); 370 371 /* Trace */ 372 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 373 struct sof_ipc_dma_trace_params_ext *dtrace_params); 374 int acp_sof_trace_release(struct snd_sof_dev *sdev); 375 376 /* PM Callbacks */ 377 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 378 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 379 380 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 381 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 382 383 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 384 { 385 const struct sof_dev_desc *desc = pdata->desc; 386 387 return desc->chip_info; 388 } 389 390 int acp_probes_register(struct snd_sof_dev *sdev); 391 void acp_probes_unregister(struct snd_sof_dev *sdev); 392 393 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 394 extern const struct dmi_system_id acp_sof_quirk_table[]; 395 #endif 396