1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_QMI_H 8 #define ATH12K_QMI_H 9 10 #include <linux/mutex.h> 11 #include <linux/soc/qcom/qmi.h> 12 13 #define ATH12K_HOST_VERSION_STRING "WIN" 14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000 15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 16 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 17 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 18 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 19 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 20 21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 22 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332 0x2 23 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 24 #define ATH12K_QMI_RESP_LEN_MAX 8192 25 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 26 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 27 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 28 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 29 30 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 31 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 32 #define QMI_WLFW_FW_READY_IND_V01 0x0038 33 34 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 35 36 #define ATH12K_BOARD_ID_DEFAULT 0xFF 37 38 struct ath12k_base; 39 struct ath12k_hw_group; 40 41 enum ath12k_qmi_file_type { 42 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, 43 ATH12K_QMI_FILE_TYPE_CALDATA = 2, 44 ATH12K_QMI_FILE_TYPE_EEPROM = 3, 45 ATH12K_QMI_MAX_FILE_TYPE = 4, 46 }; 47 48 enum ath12k_qmi_bdf_type { 49 ATH12K_QMI_BDF_TYPE_BIN = 0, 50 ATH12K_QMI_BDF_TYPE_ELF = 1, 51 ATH12K_QMI_BDF_TYPE_REGDB = 4, 52 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, 53 }; 54 55 enum ath12k_qmi_event_type { 56 ATH12K_QMI_EVENT_SERVER_ARRIVE, 57 ATH12K_QMI_EVENT_SERVER_EXIT, 58 ATH12K_QMI_EVENT_REQUEST_MEM, 59 ATH12K_QMI_EVENT_FW_MEM_READY, 60 ATH12K_QMI_EVENT_FW_READY, 61 ATH12K_QMI_EVENT_REGISTER_DRIVER, 62 ATH12K_QMI_EVENT_UNREGISTER_DRIVER, 63 ATH12K_QMI_EVENT_RECOVERY, 64 ATH12K_QMI_EVENT_FORCE_FW_ASSERT, 65 ATH12K_QMI_EVENT_POWER_UP, 66 ATH12K_QMI_EVENT_POWER_DOWN, 67 ATH12K_QMI_EVENT_HOST_CAP, 68 ATH12K_QMI_EVENT_MAX, 69 }; 70 71 struct ath12k_qmi_driver_event { 72 struct list_head list; 73 enum ath12k_qmi_event_type type; 74 void *data; 75 }; 76 77 struct ath12k_qmi_ce_cfg { 78 const struct ce_pipe_config *tgt_ce; 79 int tgt_ce_len; 80 const struct service_to_pipe *svc_to_ce_map; 81 int svc_to_ce_map_len; 82 const u8 *shadow_reg; 83 int shadow_reg_len; 84 u32 *shadow_reg_v3; 85 int shadow_reg_v3_len; 86 }; 87 88 struct ath12k_qmi_event_msg { 89 struct list_head list; 90 enum ath12k_qmi_event_type type; 91 }; 92 93 struct target_mem_chunk { 94 u32 size; 95 u32 type; 96 u32 prev_size; 97 u32 prev_type; 98 dma_addr_t paddr; 99 union { 100 void __iomem *ioaddr; 101 void *addr; 102 } v; 103 104 dma_addr_t paddr_unaligned; 105 void *vaddr_unaligned; 106 u32 total_size; 107 }; 108 109 struct target_info { 110 u32 chip_id; 111 u32 chip_family; 112 u32 board_id; 113 u32 soc_id; 114 u32 fw_version; 115 u32 eeprom_caldata; 116 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 117 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 118 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH]; 119 }; 120 121 struct m3_mem_region { 122 /* total memory allocated */ 123 u32 total_size; 124 /* actual memory being used */ 125 u32 size; 126 dma_addr_t paddr; 127 void *vaddr; 128 }; 129 130 struct dev_mem_info { 131 u64 start; 132 u64 size; 133 }; 134 135 struct ath12k_qmi { 136 struct ath12k_base *ab; 137 struct qmi_handle handle; 138 struct sockaddr_qrtr sq; 139 struct work_struct event_work; 140 struct workqueue_struct *event_wq; 141 struct list_head event_list; 142 spinlock_t event_lock; /* spinlock for qmi event list */ 143 struct ath12k_qmi_ce_cfg ce_cfg; 144 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 145 u32 mem_seg_count; 146 u32 target_mem_mode; 147 bool target_mem_delayed; 148 u8 cal_done; 149 150 /* protected with struct ath12k_qmi::event_lock */ 151 bool block_event; 152 153 u8 num_radios; 154 struct target_info target; 155 struct m3_mem_region m3_mem; 156 struct m3_mem_region aux_uc_mem; 157 unsigned int service_ins_id; 158 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 159 u8 dynamic_ddr_support; 160 }; 161 162 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 265 163 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 164 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 165 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 166 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 167 168 struct qmi_wlanfw_host_ddr_range { 169 u64 start; 170 u64 size; 171 }; 172 173 enum ath12k_qmi_target_mem { 174 HOST_DDR_REGION_TYPE = 0x1, 175 BDF_MEM_REGION_TYPE = 0x2, 176 M3_DUMP_REGION_TYPE = 0x3, 177 CALDB_MEM_REGION_TYPE = 0x4, 178 MLO_GLOBAL_MEM_REGION_TYPE = 0x8, 179 PAGEABLE_MEM_REGION_TYPE = 0x9, 180 LPASS_SHARED_V01_REGION_TYPE = 0xb, 181 }; 182 183 enum qmi_wlanfw_host_build_type { 184 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 185 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0, 186 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1, 187 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2, 188 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 189 }; 190 191 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3 192 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2 193 194 struct wlfw_host_mlo_chip_info_s_v01 { 195 u8 chip_id; 196 u8 num_local_links; 197 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 198 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01]; 199 }; 200 201 enum ath12k_qmi_cnss_feature { 202 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, 203 CNSS_QDSS_CFG_MISS_V01 = 3, 204 CNSS_PCIE_PERST_NO_PULL_V01 = 4, 205 CNSS_AUX_UC_SUPPORT_V01 = 6, 206 CNSS_MAX_FEATURE_V01 = 64, 207 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, 208 }; 209 210 struct qmi_wlanfw_host_cap_req_msg_v01 { 211 u8 num_clients_valid; 212 u32 num_clients; 213 u8 wake_msi_valid; 214 u32 wake_msi; 215 u8 gpios_valid; 216 u32 gpios_len; 217 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 218 u8 nm_modem_valid; 219 u8 nm_modem; 220 u8 bdf_support_valid; 221 u8 bdf_support; 222 u8 bdf_cache_support_valid; 223 u8 bdf_cache_support; 224 u8 m3_support_valid; 225 u8 m3_support; 226 u8 m3_cache_support_valid; 227 u8 m3_cache_support; 228 u8 cal_filesys_support_valid; 229 u8 cal_filesys_support; 230 u8 cal_cache_support_valid; 231 u8 cal_cache_support; 232 u8 cal_done_valid; 233 u8 cal_done; 234 u8 mem_bucket_valid; 235 u32 mem_bucket; 236 u8 mem_cfg_mode_valid; 237 u8 mem_cfg_mode; 238 u8 cal_duration_valid; 239 u16 cal_duraiton; 240 u8 platform_name_valid; 241 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1]; 242 u8 ddr_range_valid; 243 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01]; 244 u8 host_build_type_valid; 245 enum qmi_wlanfw_host_build_type host_build_type; 246 u8 mlo_capable_valid; 247 u8 mlo_capable; 248 u8 mlo_chip_id_valid; 249 u16 mlo_chip_id; 250 u8 mlo_group_id_valid; 251 u8 mlo_group_id; 252 u8 max_mlo_peer_valid; 253 u16 max_mlo_peer; 254 u8 mlo_num_chips_valid; 255 u8 mlo_num_chips; 256 u8 mlo_chip_info_valid; 257 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; 258 u8 feature_list_valid; 259 u64 feature_list; 260 u8 dynamic_mem_support_valid; 261 u8 dynamic_mem_support; 262 }; 263 264 struct qmi_wlanfw_host_cap_resp_msg_v01 { 265 struct qmi_response_type_v01 resp; 266 }; 267 268 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 269 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 270 271 struct qmi_wlanfw_phy_cap_req_msg_v01 { 272 }; 273 274 struct qmi_wlanfw_phy_cap_resp_msg_v01 { 275 struct qmi_response_type_v01 resp; 276 u8 num_phy_valid; 277 u8 num_phy; 278 u8 board_id_valid; 279 u32 board_id; 280 u8 single_chip_mlo_support_valid; 281 u8 single_chip_mlo_support; 282 u8 dynamic_ddr_support_valid; 283 u8 dynamic_ddr_support; 284 }; 285 286 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 287 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 288 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 289 290 struct qmi_wlanfw_ind_register_req_msg_v01 { 291 u8 fw_ready_enable_valid; 292 u8 fw_ready_enable; 293 u8 initiate_cal_download_enable_valid; 294 u8 initiate_cal_download_enable; 295 u8 initiate_cal_update_enable_valid; 296 u8 initiate_cal_update_enable; 297 u8 msa_ready_enable_valid; 298 u8 msa_ready_enable; 299 u8 pin_connect_result_enable_valid; 300 u8 pin_connect_result_enable; 301 u8 client_id_valid; 302 u32 client_id; 303 u8 request_mem_enable_valid; 304 u8 request_mem_enable; 305 u8 fw_mem_ready_enable_valid; 306 u8 fw_mem_ready_enable; 307 u8 fw_init_done_enable_valid; 308 u8 fw_init_done_enable; 309 u8 rejuvenate_enable_valid; 310 u32 rejuvenate_enable; 311 u8 xo_cal_enable_valid; 312 u8 xo_cal_enable; 313 u8 cal_done_enable_valid; 314 u8 cal_done_enable; 315 }; 316 317 struct qmi_wlanfw_ind_register_resp_msg_v01 { 318 struct qmi_response_type_v01 resp; 319 u8 fw_status_valid; 320 u64 fw_status; 321 }; 322 323 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 324 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 325 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 326 #define QMI_WLANFW_MAX_STR_LEN_V01 16 327 328 struct qmi_wlanfw_mem_cfg_s_v01 { 329 u64 offset; 330 u32 size; 331 u8 secure_flag; 332 }; 333 334 enum qmi_wlanfw_mem_type_enum_v01 { 335 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 336 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 337 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 338 QMI_WLANFW_MEM_BDF_V01 = 2, 339 QMI_WLANFW_MEM_M3_V01 = 3, 340 QMI_WLANFW_MEM_CAL_V01 = 4, 341 QMI_WLANFW_MEM_DPD_V01 = 5, 342 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 343 }; 344 345 struct qmi_wlanfw_mem_seg_s_v01 { 346 u32 size; 347 enum qmi_wlanfw_mem_type_enum_v01 type; 348 u32 mem_cfg_len; 349 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 350 }; 351 352 struct qmi_wlanfw_request_mem_ind_msg_v01 { 353 u32 mem_seg_len; 354 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 355 }; 356 357 struct qmi_wlanfw_mem_seg_resp_s_v01 { 358 u64 addr; 359 u32 size; 360 enum qmi_wlanfw_mem_type_enum_v01 type; 361 u8 restore; 362 }; 363 364 struct qmi_wlanfw_respond_mem_req_msg_v01 { 365 u32 mem_seg_len; 366 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 367 }; 368 369 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 370 struct qmi_response_type_v01 resp; 371 }; 372 373 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 374 char placeholder; 375 }; 376 377 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 378 char placeholder; 379 }; 380 381 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 382 #define QMI_WLANFW_CAP_REQ_V01 0x0024 383 384 enum qmi_wlanfw_pipedir_enum_v01 { 385 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 386 QMI_WLFW_PIPEDIR_IN_V01 = 1, 387 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 388 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 389 }; 390 391 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 392 u32 pipe_num; 393 u32 pipe_dir; 394 u32 nentries; 395 u32 nbytes_max; 396 u32 flags; 397 }; 398 399 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 400 u32 service_id; 401 u32 pipe_dir; 402 u32 pipe_num; 403 }; 404 405 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 406 u16 id; 407 u16 offset; 408 }; 409 410 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 { 411 u32 addr; 412 }; 413 414 struct qmi_wlanfw_memory_region_info_s_v01 { 415 u64 region_addr; 416 u32 size; 417 u8 secure_flag; 418 }; 419 420 struct qmi_wlanfw_rf_chip_info_s_v01 { 421 u32 chip_id; 422 u32 chip_family; 423 }; 424 425 struct qmi_wlanfw_rf_board_info_s_v01 { 426 u32 board_id; 427 }; 428 429 struct qmi_wlanfw_soc_info_s_v01 { 430 u32 soc_id; 431 }; 432 433 struct qmi_wlanfw_fw_version_info_s_v01 { 434 u32 fw_version; 435 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 436 }; 437 438 struct qmi_wlanfw_dev_mem_info_s_v01 { 439 u64 start; 440 u64 size; 441 }; 442 443 enum qmi_wlanfw_cal_temp_id_enum_v01 { 444 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 445 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 446 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 447 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 448 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 449 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 450 }; 451 452 enum qmi_wlanfw_rd_card_chain_cap_v01 { 453 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN, 454 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0, 455 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1, 456 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2, 457 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX, 458 }; 459 460 struct qmi_wlanfw_cap_resp_msg_v01 { 461 struct qmi_response_type_v01 resp; 462 u8 chip_info_valid; 463 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 464 u8 board_info_valid; 465 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 466 u8 soc_info_valid; 467 struct qmi_wlanfw_soc_info_s_v01 soc_info; 468 u8 fw_version_info_valid; 469 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 470 u8 fw_build_id_valid; 471 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 472 u8 num_macs_valid; 473 u8 num_macs; 474 u8 voltage_mv_valid; 475 u32 voltage_mv; 476 u8 time_freq_hz_valid; 477 u32 time_freq_hz; 478 u8 otp_version_valid; 479 u32 otp_version; 480 u8 eeprom_caldata_read_timeout_valid; 481 u32 eeprom_caldata_read_timeout; 482 u8 fw_caps_valid; 483 u64 fw_caps; 484 u8 rd_card_chain_cap_valid; 485 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; 486 u8 dev_mem_info_valid; 487 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; 488 }; 489 490 struct qmi_wlanfw_cap_req_msg_v01 { 491 char placeholder; 492 }; 493 494 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 495 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 496 /* TODO: Need to check with MCL and FW team that data can be pointer and 497 * can be last element in structure 498 */ 499 struct qmi_wlanfw_bdf_download_req_msg_v01 { 500 u8 valid; 501 u8 file_id_valid; 502 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 503 u8 total_size_valid; 504 u32 total_size; 505 u8 seg_id_valid; 506 u32 seg_id; 507 u8 data_valid; 508 u32 data_len; 509 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 510 u8 end_valid; 511 u8 end; 512 u8 bdf_type_valid; 513 u8 bdf_type; 514 515 }; 516 517 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 518 struct qmi_response_type_v01 resp; 519 }; 520 521 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 522 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 523 524 struct qmi_wlanfw_m3_info_req_msg_v01 { 525 u64 addr; 526 u32 size; 527 }; 528 529 struct qmi_wlanfw_m3_info_resp_msg_v01 { 530 struct qmi_response_type_v01 resp; 531 }; 532 533 #define QMI_WLANFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 534 #define QMI_WLANFW_AUX_UC_INFO_REQ_V01 0x005A 535 536 struct qmi_wlanfw_aux_uc_info_req_msg_v01 { 537 u64 addr; 538 u32 size; 539 }; 540 541 struct qmi_wlanfw_aux_uc_info_resp_msg_v01 { 542 struct qmi_response_type_v01 resp; 543 }; 544 545 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 546 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 547 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 548 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 549 #define QMI_WLANFW_MAX_STR_LEN_V01 16 550 #define QMI_WLANFW_MAX_NUM_CE_V01 12 551 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 552 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 553 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60 554 555 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 556 u32 mode; 557 u8 hw_debug_valid; 558 u8 hw_debug; 559 }; 560 561 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 562 struct qmi_response_type_v01 resp; 563 }; 564 565 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 566 u8 host_version_valid; 567 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 568 u8 tgt_cfg_valid; 569 u32 tgt_cfg_len; 570 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 571 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 572 u8 svc_cfg_valid; 573 u32 svc_cfg_len; 574 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 575 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 576 u8 shadow_reg_valid; 577 u32 shadow_reg_len; 578 struct qmi_wlanfw_shadow_reg_cfg_s_v01 579 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 580 u8 shadow_reg_v3_valid; 581 u32 shadow_reg_v3_len; 582 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 583 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01]; 584 }; 585 586 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 587 struct qmi_response_type_v01 resp; 588 }; 589 590 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 591 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7 592 593 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 594 /* Must be set to true if enable_fwlog is being passed */ 595 u8 enable_fwlog_valid; 596 u8 enable_fwlog; 597 }; 598 599 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 600 struct qmi_response_type_v01 resp; 601 }; 602 603 enum ath12k_qmi_mem_mode { 604 ATH12K_QMI_MEMORY_MODE_DEFAULT = 0, 605 ATH12K_QMI_MEMORY_MODE_LOW_512_M, 606 }; 607 608 enum ath12k_qmi_firmware_mode { 609 /* the default mode, standard 802.11 functionality */ 610 ATH12K_QMI_FIRMWARE_MODE_NORMAL, 611 612 /* factory tests etc */ 613 ATH12K_QMI_FIRMWARE_MODE_FTM, 614 615 /* firmware offline; values 2-3 reserved by firmware ABI */ 616 ATH12K_QMI_FIRMWARE_MODE_OFF = 4, 617 }; 618 619 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block) 620 { 621 lockdep_assert_held(&qmi->event_lock); 622 623 qmi->block_event = block; 624 } 625 626 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi) 627 { 628 lockdep_assert_held(&qmi->event_lock); 629 630 return qmi->block_event; 631 } 632 633 int ath12k_qmi_firmware_start(struct ath12k_base *ab, 634 enum ath12k_qmi_firmware_mode mode); 635 void ath12k_qmi_firmware_stop(struct ath12k_base *ab); 636 void ath12k_qmi_deinit_service(struct ath12k_base *ab); 637 int ath12k_qmi_init_service(struct ath12k_base *ab); 638 void ath12k_qmi_free_resource(struct ath12k_base *ab); 639 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab); 640 void ath12k_qmi_reset_mlo_mem(struct ath12k_hw_group *ag); 641 642 #endif 643