1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // tegra210_ahub.c - Tegra210 AHUB driver 4 // 5 // Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved. 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 #include "tegra210_ahub.h" 16 17 static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl, 18 struct snd_ctl_elem_value *uctl) 19 { 20 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_to_component(kctl); 21 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 23 int val_bytes = snd_soc_component_regmap_val_bytes(cmpnt); 24 unsigned int reg, i, bit_pos = 0; 25 26 /* 27 * Find the bit position of current MUX input. 28 * If nothing is set, position would be 0 and it corresponds to 'None'. 29 */ 30 for (i = 0; i < ahub->soc_data->reg_count; i++) { 31 unsigned int reg_val; 32 33 reg = e->reg + (ahub->soc_data->xbar_part_size * i); 34 reg_val = snd_soc_component_read(cmpnt, reg); 35 reg_val &= ahub->soc_data->mask[i]; 36 37 if (reg_val) { 38 bit_pos = ffs(reg_val) + 39 (8 * val_bytes * i); 40 break; 41 } 42 } 43 44 /* Find index related to the item in array *_ahub_mux_texts[] */ 45 for (i = 0; i < e->items; i++) { 46 if (bit_pos == e->values[i]) { 47 uctl->value.enumerated.item[0] = i; 48 break; 49 } 50 } 51 52 return 0; 53 } 54 55 static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl, 56 struct snd_ctl_elem_value *uctl) 57 { 58 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_to_component(kctl); 59 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 60 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kctl); 61 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 62 struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { }; 63 int val_bytes = snd_soc_component_regmap_val_bytes(cmpnt); 64 unsigned int *item = uctl->value.enumerated.item; 65 unsigned int value; 66 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; 67 int change = 0; 68 69 if (item[0] >= e->items) 70 return -EINVAL; 71 72 value = e->values[item[0]]; 73 74 if (value) { 75 /* Get the register index and value to set */ 76 reg_idx = (value - 1) / (8 * val_bytes); 77 bit_pos = (value - 1) % (8 * val_bytes); 78 reg_val = BIT(bit_pos); 79 } 80 81 /* 82 * Run through all parts of a MUX register to find the state changes. 83 * There will be an additional update if new MUX input value is from 84 * different part of the MUX register. 85 */ 86 for (i = 0; i < ahub->soc_data->reg_count; i++) { 87 update[i].reg = e->reg + (ahub->soc_data->xbar_part_size * i); 88 update[i].val = (i == reg_idx) ? reg_val : 0; 89 update[i].mask = ahub->soc_data->mask[i]; 90 update[i].kcontrol = kctl; 91 92 /* Update widget power if state has changed */ 93 if (snd_soc_component_test_bits(cmpnt, update[i].reg, 94 update[i].mask, 95 update[i].val)) 96 change |= snd_soc_dapm_mux_update_power(dapm, kctl, 97 item[0], e, 98 &update[i]); 99 } 100 101 return change; 102 } 103 104 static struct snd_soc_dai_driver tegra210_ahub_dais[] = { 105 DAI(ADMAIF1), 106 DAI(ADMAIF2), 107 DAI(ADMAIF3), 108 DAI(ADMAIF4), 109 DAI(ADMAIF5), 110 DAI(ADMAIF6), 111 DAI(ADMAIF7), 112 DAI(ADMAIF8), 113 DAI(ADMAIF9), 114 DAI(ADMAIF10), 115 /* XBAR <-> I2S <-> Codec */ 116 DAI(I2S1), 117 DAI(I2S2), 118 DAI(I2S3), 119 DAI(I2S4), 120 DAI(I2S5), 121 /* XBAR <- DMIC <- Codec */ 122 DAI(DMIC1), 123 DAI(DMIC2), 124 DAI(DMIC3), 125 /* XBAR -> SFC -> XBAR */ 126 DAI(SFC1 RX), 127 DAI(SFC1 TX), 128 DAI(SFC2 RX), 129 DAI(SFC2 TX), 130 DAI(SFC3 RX), 131 DAI(SFC3 TX), 132 DAI(SFC4 RX), 133 DAI(SFC4 TX), 134 /* XBAR -> MVC -> XBAR */ 135 DAI(MVC1 RX), 136 DAI(MVC1 TX), 137 DAI(MVC2 RX), 138 DAI(MVC2 TX), 139 /* XBAR -> AMX(4:1) -> XBAR */ 140 DAI(AMX1 RX1), 141 DAI(AMX1 RX2), 142 DAI(AMX1 RX3), 143 DAI(AMX1 RX4), 144 DAI(AMX1), 145 DAI(AMX2 RX1), 146 DAI(AMX2 RX2), 147 DAI(AMX2 RX3), 148 DAI(AMX2 RX4), 149 DAI(AMX2), 150 /* XBAR -> ADX(1:4) -> XBAR */ 151 DAI(ADX1), 152 DAI(ADX1 TX1), 153 DAI(ADX1 TX2), 154 DAI(ADX1 TX3), 155 DAI(ADX1 TX4), 156 DAI(ADX2), 157 DAI(ADX2 TX1), 158 DAI(ADX2 TX2), 159 DAI(ADX2 TX3), 160 DAI(ADX2 TX4), 161 /* XBAR -> MIXER(10:5) -> XBAR */ 162 DAI(MIXER1 RX1), 163 DAI(MIXER1 RX2), 164 DAI(MIXER1 RX3), 165 DAI(MIXER1 RX4), 166 DAI(MIXER1 RX5), 167 DAI(MIXER1 RX6), 168 DAI(MIXER1 RX7), 169 DAI(MIXER1 RX8), 170 DAI(MIXER1 RX9), 171 DAI(MIXER1 RX10), 172 DAI(MIXER1 TX1), 173 DAI(MIXER1 TX2), 174 DAI(MIXER1 TX3), 175 DAI(MIXER1 TX4), 176 DAI(MIXER1 TX5), 177 /* XBAR -> OPE -> XBAR */ 178 DAI(OPE1 RX), 179 DAI(OPE1 TX), 180 DAI(OPE2 RX), 181 DAI(OPE2 TX), 182 }; 183 184 static struct snd_soc_dai_driver tegra186_ahub_dais[] = { 185 DAI(ADMAIF1), 186 DAI(ADMAIF2), 187 DAI(ADMAIF3), 188 DAI(ADMAIF4), 189 DAI(ADMAIF5), 190 DAI(ADMAIF6), 191 DAI(ADMAIF7), 192 DAI(ADMAIF8), 193 DAI(ADMAIF9), 194 DAI(ADMAIF10), 195 DAI(ADMAIF11), 196 DAI(ADMAIF12), 197 DAI(ADMAIF13), 198 DAI(ADMAIF14), 199 DAI(ADMAIF15), 200 DAI(ADMAIF16), 201 DAI(ADMAIF17), 202 DAI(ADMAIF18), 203 DAI(ADMAIF19), 204 DAI(ADMAIF20), 205 /* XBAR <-> I2S <-> Codec */ 206 DAI(I2S1), 207 DAI(I2S2), 208 DAI(I2S3), 209 DAI(I2S4), 210 DAI(I2S5), 211 DAI(I2S6), 212 /* XBAR <- DMIC <- Codec */ 213 DAI(DMIC1), 214 DAI(DMIC2), 215 DAI(DMIC3), 216 DAI(DMIC4), 217 /* XBAR -> DSPK -> Codec */ 218 DAI(DSPK1), 219 DAI(DSPK2), 220 /* XBAR -> SFC -> XBAR */ 221 DAI(SFC1 RX), 222 DAI(SFC1 TX), 223 DAI(SFC2 RX), 224 DAI(SFC2 TX), 225 DAI(SFC3 RX), 226 DAI(SFC3 TX), 227 DAI(SFC4 RX), 228 DAI(SFC4 TX), 229 /* XBAR -> MVC -> XBAR */ 230 DAI(MVC1 RX), 231 DAI(MVC1 TX), 232 DAI(MVC2 RX), 233 DAI(MVC2 TX), 234 /* XBAR -> AMX(4:1) -> XBAR */ 235 DAI(AMX1 RX1), 236 DAI(AMX1 RX2), 237 DAI(AMX1 RX3), 238 DAI(AMX1 RX4), 239 DAI(AMX1), 240 DAI(AMX2 RX1), 241 DAI(AMX2 RX2), 242 DAI(AMX2 RX3), 243 DAI(AMX2 RX4), 244 DAI(AMX2), 245 DAI(AMX3 RX1), 246 DAI(AMX3 RX2), 247 DAI(AMX3 RX3), 248 DAI(AMX3 RX4), 249 DAI(AMX3), 250 DAI(AMX4 RX1), 251 DAI(AMX4 RX2), 252 DAI(AMX4 RX3), 253 DAI(AMX4 RX4), 254 DAI(AMX4), 255 /* XBAR -> ADX(1:4) -> XBAR */ 256 DAI(ADX1), 257 DAI(ADX1 TX1), 258 DAI(ADX1 TX2), 259 DAI(ADX1 TX3), 260 DAI(ADX1 TX4), 261 DAI(ADX2), 262 DAI(ADX2 TX1), 263 DAI(ADX2 TX2), 264 DAI(ADX2 TX3), 265 DAI(ADX2 TX4), 266 DAI(ADX3), 267 DAI(ADX3 TX1), 268 DAI(ADX3 TX2), 269 DAI(ADX3 TX3), 270 DAI(ADX3 TX4), 271 DAI(ADX4), 272 DAI(ADX4 TX1), 273 DAI(ADX4 TX2), 274 DAI(ADX4 TX3), 275 DAI(ADX4 TX4), 276 /* XBAR -> MIXER1(10:5) -> XBAR */ 277 DAI(MIXER1 RX1), 278 DAI(MIXER1 RX2), 279 DAI(MIXER1 RX3), 280 DAI(MIXER1 RX4), 281 DAI(MIXER1 RX5), 282 DAI(MIXER1 RX6), 283 DAI(MIXER1 RX7), 284 DAI(MIXER1 RX8), 285 DAI(MIXER1 RX9), 286 DAI(MIXER1 RX10), 287 DAI(MIXER1 TX1), 288 DAI(MIXER1 TX2), 289 DAI(MIXER1 TX3), 290 DAI(MIXER1 TX4), 291 DAI(MIXER1 TX5), 292 /* XBAR -> ASRC -> XBAR */ 293 DAI(ASRC1 RX1), 294 DAI(ASRC1 TX1), 295 DAI(ASRC1 RX2), 296 DAI(ASRC1 TX2), 297 DAI(ASRC1 RX3), 298 DAI(ASRC1 TX3), 299 DAI(ASRC1 RX4), 300 DAI(ASRC1 TX4), 301 DAI(ASRC1 RX5), 302 DAI(ASRC1 TX5), 303 DAI(ASRC1 RX6), 304 DAI(ASRC1 TX6), 305 DAI(ASRC1 RX7), 306 /* XBAR -> OPE -> XBAR */ 307 DAI(OPE1 RX), 308 DAI(OPE1 TX), 309 }; 310 311 static struct snd_soc_dai_driver tegra264_ahub_dais[] = { 312 DAI(ADMAIF1), 313 DAI(ADMAIF2), 314 DAI(ADMAIF3), 315 DAI(ADMAIF4), 316 DAI(ADMAIF5), 317 DAI(ADMAIF6), 318 DAI(ADMAIF7), 319 DAI(ADMAIF8), 320 DAI(ADMAIF9), 321 DAI(ADMAIF10), 322 DAI(ADMAIF11), 323 DAI(ADMAIF12), 324 DAI(ADMAIF13), 325 DAI(ADMAIF14), 326 DAI(ADMAIF15), 327 DAI(ADMAIF16), 328 DAI(ADMAIF17), 329 DAI(ADMAIF18), 330 DAI(ADMAIF19), 331 DAI(ADMAIF20), 332 DAI(ADMAIF21), 333 DAI(ADMAIF22), 334 DAI(ADMAIF23), 335 DAI(ADMAIF24), 336 DAI(ADMAIF25), 337 DAI(ADMAIF26), 338 DAI(ADMAIF27), 339 DAI(ADMAIF28), 340 DAI(ADMAIF29), 341 DAI(ADMAIF30), 342 DAI(ADMAIF31), 343 DAI(ADMAIF32), 344 /* XBAR <-> I2S <-> Codec */ 345 DAI(I2S1), 346 DAI(I2S2), 347 DAI(I2S3), 348 DAI(I2S4), 349 DAI(I2S5), 350 DAI(I2S6), 351 DAI(I2S7), 352 DAI(I2S8), 353 /* XBAR <-> DMIC <-> Codec */ 354 DAI(DMIC1), 355 DAI(DMIC2), 356 /* XBAR <-> DSPK <-> Codec */ 357 DAI(DSPK1), 358 /* XBAR -> SFC -> XBAR */ 359 DAI(SFC1 RX), 360 DAI(SFC1 TX), 361 DAI(SFC2 RX), 362 DAI(SFC2 TX), 363 DAI(SFC3 RX), 364 DAI(SFC3 TX), 365 DAI(SFC4 RX), 366 DAI(SFC4 TX), 367 /* XBAR -> MVC -> XBAR */ 368 DAI(MVC1 RX), 369 DAI(MVC1 TX), 370 DAI(MVC2 RX), 371 DAI(MVC2 TX), 372 /* XBAR -> AMX(4:1) -> XBAR */ 373 DAI(AMX1 RX1), 374 DAI(AMX1 RX2), 375 DAI(AMX1 RX3), 376 DAI(AMX1 RX4), 377 DAI(AMX1), 378 DAI(AMX2 RX1), 379 DAI(AMX2 RX2), 380 DAI(AMX2 RX3), 381 DAI(AMX2 RX4), 382 DAI(AMX2), 383 DAI(AMX3 RX1), 384 DAI(AMX3 RX2), 385 DAI(AMX3 RX3), 386 DAI(AMX3 RX4), 387 DAI(AMX3), 388 DAI(AMX4 RX1), 389 DAI(AMX4 RX2), 390 DAI(AMX4 RX3), 391 DAI(AMX4 RX4), 392 DAI(AMX4), 393 DAI(AMX5 RX1), 394 DAI(AMX5 RX2), 395 DAI(AMX5 RX3), 396 DAI(AMX5 RX4), 397 DAI(AMX5), 398 DAI(AMX6 RX1), 399 DAI(AMX6 RX2), 400 DAI(AMX6 RX3), 401 DAI(AMX6 RX4), 402 DAI(AMX6), 403 /* XBAR -> ADX(1:4) -> XBAR */ 404 DAI(ADX1), 405 DAI(ADX1 TX1), 406 DAI(ADX1 TX2), 407 DAI(ADX1 TX3), 408 DAI(ADX1 TX4), 409 DAI(ADX2), 410 DAI(ADX2 TX1), 411 DAI(ADX2 TX2), 412 DAI(ADX2 TX3), 413 DAI(ADX2 TX4), 414 DAI(ADX3), 415 DAI(ADX3 TX1), 416 DAI(ADX3 TX2), 417 DAI(ADX3 TX3), 418 DAI(ADX3 TX4), 419 DAI(ADX4), 420 DAI(ADX4 TX1), 421 DAI(ADX4 TX2), 422 DAI(ADX4 TX3), 423 DAI(ADX4 TX4), 424 DAI(ADX5), 425 DAI(ADX5 TX1), 426 DAI(ADX5 TX2), 427 DAI(ADX5 TX3), 428 DAI(ADX5 TX4), 429 DAI(ADX6), 430 DAI(ADX6 TX1), 431 DAI(ADX6 TX2), 432 DAI(ADX6 TX3), 433 DAI(ADX6 TX4), 434 /* XBAR -> MIXER1(10:5) -> XBAR */ 435 DAI(MIXER1 RX1), 436 DAI(MIXER1 RX2), 437 DAI(MIXER1 RX3), 438 DAI(MIXER1 RX4), 439 DAI(MIXER1 RX5), 440 DAI(MIXER1 RX6), 441 DAI(MIXER1 RX7), 442 DAI(MIXER1 RX8), 443 DAI(MIXER1 RX9), 444 DAI(MIXER1 RX10), 445 DAI(MIXER1 TX1), 446 DAI(MIXER1 TX2), 447 DAI(MIXER1 TX3), 448 DAI(MIXER1 TX4), 449 DAI(MIXER1 TX5), 450 /* XBAR -> ASRC -> XBAR */ 451 DAI(ASRC1 RX1), 452 DAI(ASRC1 TX1), 453 DAI(ASRC1 RX2), 454 DAI(ASRC1 TX2), 455 DAI(ASRC1 RX3), 456 DAI(ASRC1 TX3), 457 DAI(ASRC1 RX4), 458 DAI(ASRC1 TX4), 459 DAI(ASRC1 RX5), 460 DAI(ASRC1 TX5), 461 DAI(ASRC1 RX6), 462 DAI(ASRC1 TX6), 463 DAI(ASRC1 RX7), 464 /* XBAR -> OPE -> XBAR */ 465 DAI(OPE1 RX), 466 DAI(OPE1 TX), 467 }; 468 469 static const char * const tegra210_ahub_mux_texts[] = { 470 "None", 471 "ADMAIF1", 472 "ADMAIF2", 473 "ADMAIF3", 474 "ADMAIF4", 475 "ADMAIF5", 476 "ADMAIF6", 477 "ADMAIF7", 478 "ADMAIF8", 479 "ADMAIF9", 480 "ADMAIF10", 481 "I2S1", 482 "I2S2", 483 "I2S3", 484 "I2S4", 485 "I2S5", 486 "DMIC1", 487 "DMIC2", 488 "DMIC3", 489 "SFC1", 490 "SFC2", 491 "SFC3", 492 "SFC4", 493 "MVC1", 494 "MVC2", 495 "AMX1", 496 "AMX2", 497 "ADX1 TX1", 498 "ADX1 TX2", 499 "ADX1 TX3", 500 "ADX1 TX4", 501 "ADX2 TX1", 502 "ADX2 TX2", 503 "ADX2 TX3", 504 "ADX2 TX4", 505 "MIXER1 TX1", 506 "MIXER1 TX2", 507 "MIXER1 TX3", 508 "MIXER1 TX4", 509 "MIXER1 TX5", 510 "OPE1", 511 "OPE2", 512 }; 513 514 static const char * const tegra186_ahub_mux_texts[] = { 515 "None", 516 "ADMAIF1", 517 "ADMAIF2", 518 "ADMAIF3", 519 "ADMAIF4", 520 "ADMAIF5", 521 "ADMAIF6", 522 "ADMAIF7", 523 "ADMAIF8", 524 "ADMAIF9", 525 "ADMAIF10", 526 "ADMAIF11", 527 "ADMAIF12", 528 "ADMAIF13", 529 "ADMAIF14", 530 "ADMAIF15", 531 "ADMAIF16", 532 "I2S1", 533 "I2S2", 534 "I2S3", 535 "I2S4", 536 "I2S5", 537 "I2S6", 538 "ADMAIF17", 539 "ADMAIF18", 540 "ADMAIF19", 541 "ADMAIF20", 542 "DMIC1", 543 "DMIC2", 544 "DMIC3", 545 "DMIC4", 546 "SFC1", 547 "SFC2", 548 "SFC3", 549 "SFC4", 550 "MVC1", 551 "MVC2", 552 "AMX1", 553 "AMX2", 554 "AMX3", 555 "AMX4", 556 "ADX1 TX1", 557 "ADX1 TX2", 558 "ADX1 TX3", 559 "ADX1 TX4", 560 "ADX2 TX1", 561 "ADX2 TX2", 562 "ADX2 TX3", 563 "ADX2 TX4", 564 "ADX3 TX1", 565 "ADX3 TX2", 566 "ADX3 TX3", 567 "ADX3 TX4", 568 "ADX4 TX1", 569 "ADX4 TX2", 570 "ADX4 TX3", 571 "ADX4 TX4", 572 "MIXER1 TX1", 573 "MIXER1 TX2", 574 "MIXER1 TX3", 575 "MIXER1 TX4", 576 "MIXER1 TX5", 577 "ASRC1 TX1", 578 "ASRC1 TX2", 579 "ASRC1 TX3", 580 "ASRC1 TX4", 581 "ASRC1 TX5", 582 "ASRC1 TX6", 583 "OPE1", 584 }; 585 586 static const char * const tegra264_ahub_mux_texts[] = { 587 "None", 588 "ADMAIF1", 589 "ADMAIF2", 590 "ADMAIF3", 591 "ADMAIF4", 592 "ADMAIF5", 593 "ADMAIF6", 594 "ADMAIF7", 595 "ADMAIF8", 596 "ADMAIF9", 597 "ADMAIF10", 598 "ADMAIF11", 599 "ADMAIF12", 600 "ADMAIF13", 601 "ADMAIF14", 602 "ADMAIF15", 603 "ADMAIF16", 604 "I2S1", 605 "I2S2", 606 "I2S3", 607 "I2S4", 608 "I2S5", 609 "I2S6", 610 "I2S7", 611 "I2S8", 612 "SFC1", 613 "SFC2", 614 "SFC3", 615 "SFC4", 616 "MIXER1 TX1", 617 "MIXER1 TX2", 618 "MIXER1 TX3", 619 "MIXER1 TX4", 620 "MIXER1 TX5", 621 "AMX1", 622 "AMX2", 623 "AMX3", 624 "AMX4", 625 "AMX5", 626 "AMX6", 627 "OPE1", 628 "MVC1", 629 "MVC2", 630 "DMIC1", 631 "DMIC2", 632 "ADX1 TX1", 633 "ADX1 TX2", 634 "ADX1 TX3", 635 "ADX1 TX4", 636 "ADX2 TX1", 637 "ADX2 TX2", 638 "ADX2 TX3", 639 "ADX2 TX4", 640 "ADX3 TX1", 641 "ADX3 TX2", 642 "ADX3 TX3", 643 "ADX3 TX4", 644 "ADX4 TX1", 645 "ADX4 TX2", 646 "ADX4 TX3", 647 "ADX4 TX4", 648 "ADX5 TX1", 649 "ADX5 TX2", 650 "ADX5 TX3", 651 "ADX5 TX4", 652 "ADX6 TX1", 653 "ADX6 TX2", 654 "ADX6 TX3", 655 "ADX6 TX4", 656 "ASRC1 TX1", 657 "ASRC1 TX2", 658 "ASRC1 TX3", 659 "ASRC1 TX4", 660 "ASRC1 TX5", 661 "ASRC1 TX6", 662 "ADMAIF17", 663 "ADMAIF18", 664 "ADMAIF19", 665 "ADMAIF20", 666 "ADMAIF21", 667 "ADMAIF22", 668 "ADMAIF23", 669 "ADMAIF24", 670 "ADMAIF25", 671 "ADMAIF26", 672 "ADMAIF27", 673 "ADMAIF28", 674 "ADMAIF29", 675 "ADMAIF30", 676 "ADMAIF31", 677 "ADMAIF32", 678 }; 679 680 static const unsigned int tegra210_ahub_mux_values[] = { 681 0, 682 /* ADMAIF */ 683 MUX_VALUE(0, 0), 684 MUX_VALUE(0, 1), 685 MUX_VALUE(0, 2), 686 MUX_VALUE(0, 3), 687 MUX_VALUE(0, 4), 688 MUX_VALUE(0, 5), 689 MUX_VALUE(0, 6), 690 MUX_VALUE(0, 7), 691 MUX_VALUE(0, 8), 692 MUX_VALUE(0, 9), 693 /* I2S */ 694 MUX_VALUE(0, 16), 695 MUX_VALUE(0, 17), 696 MUX_VALUE(0, 18), 697 MUX_VALUE(0, 19), 698 MUX_VALUE(0, 20), 699 /* DMIC */ 700 MUX_VALUE(2, 18), 701 MUX_VALUE(2, 19), 702 MUX_VALUE(2, 20), 703 /* SFC */ 704 MUX_VALUE(0, 24), 705 MUX_VALUE(0, 25), 706 MUX_VALUE(0, 26), 707 MUX_VALUE(0, 27), 708 /* MVC */ 709 MUX_VALUE(2, 8), 710 MUX_VALUE(2, 9), 711 /* AMX */ 712 MUX_VALUE(1, 8), 713 MUX_VALUE(1, 9), 714 /* ADX */ 715 MUX_VALUE(2, 24), 716 MUX_VALUE(2, 25), 717 MUX_VALUE(2, 26), 718 MUX_VALUE(2, 27), 719 MUX_VALUE(2, 28), 720 MUX_VALUE(2, 29), 721 MUX_VALUE(2, 30), 722 MUX_VALUE(2, 31), 723 /* MIXER */ 724 MUX_VALUE(1, 0), 725 MUX_VALUE(1, 1), 726 MUX_VALUE(1, 2), 727 MUX_VALUE(1, 3), 728 MUX_VALUE(1, 4), 729 /* OPE */ 730 MUX_VALUE(2, 0), 731 MUX_VALUE(2, 1), 732 }; 733 734 static const unsigned int tegra186_ahub_mux_values[] = { 735 0, 736 /* ADMAIF */ 737 MUX_VALUE(0, 0), 738 MUX_VALUE(0, 1), 739 MUX_VALUE(0, 2), 740 MUX_VALUE(0, 3), 741 MUX_VALUE(0, 4), 742 MUX_VALUE(0, 5), 743 MUX_VALUE(0, 6), 744 MUX_VALUE(0, 7), 745 MUX_VALUE(0, 8), 746 MUX_VALUE(0, 9), 747 MUX_VALUE(0, 10), 748 MUX_VALUE(0, 11), 749 MUX_VALUE(0, 12), 750 MUX_VALUE(0, 13), 751 MUX_VALUE(0, 14), 752 MUX_VALUE(0, 15), 753 /* I2S */ 754 MUX_VALUE(0, 16), 755 MUX_VALUE(0, 17), 756 MUX_VALUE(0, 18), 757 MUX_VALUE(0, 19), 758 MUX_VALUE(0, 20), 759 MUX_VALUE(0, 21), 760 /* ADMAIF */ 761 MUX_VALUE(3, 16), 762 MUX_VALUE(3, 17), 763 MUX_VALUE(3, 18), 764 MUX_VALUE(3, 19), 765 /* DMIC */ 766 MUX_VALUE(2, 18), 767 MUX_VALUE(2, 19), 768 MUX_VALUE(2, 20), 769 MUX_VALUE(2, 21), 770 /* SFC */ 771 MUX_VALUE(0, 24), 772 MUX_VALUE(0, 25), 773 MUX_VALUE(0, 26), 774 MUX_VALUE(0, 27), 775 /* MVC */ 776 MUX_VALUE(2, 8), 777 MUX_VALUE(2, 9), 778 /* AMX */ 779 MUX_VALUE(1, 8), 780 MUX_VALUE(1, 9), 781 MUX_VALUE(1, 10), 782 MUX_VALUE(1, 11), 783 /* ADX */ 784 MUX_VALUE(2, 24), 785 MUX_VALUE(2, 25), 786 MUX_VALUE(2, 26), 787 MUX_VALUE(2, 27), 788 MUX_VALUE(2, 28), 789 MUX_VALUE(2, 29), 790 MUX_VALUE(2, 30), 791 MUX_VALUE(2, 31), 792 MUX_VALUE(3, 0), 793 MUX_VALUE(3, 1), 794 MUX_VALUE(3, 2), 795 MUX_VALUE(3, 3), 796 MUX_VALUE(3, 4), 797 MUX_VALUE(3, 5), 798 MUX_VALUE(3, 6), 799 MUX_VALUE(3, 7), 800 /* MIXER */ 801 MUX_VALUE(1, 0), 802 MUX_VALUE(1, 1), 803 MUX_VALUE(1, 2), 804 MUX_VALUE(1, 3), 805 MUX_VALUE(1, 4), 806 /* ASRC */ 807 MUX_VALUE(3, 24), 808 MUX_VALUE(3, 25), 809 MUX_VALUE(3, 26), 810 MUX_VALUE(3, 27), 811 MUX_VALUE(3, 28), 812 MUX_VALUE(3, 29), 813 /* OPE */ 814 MUX_VALUE(2, 0), 815 }; 816 817 static const unsigned int tegra264_ahub_mux_values[] = { 818 0, 819 /* ADMAIF */ 820 MUX_VALUE(0, 0), 821 MUX_VALUE(0, 1), 822 MUX_VALUE(0, 2), 823 MUX_VALUE(0, 3), 824 MUX_VALUE(0, 4), 825 MUX_VALUE(0, 5), 826 MUX_VALUE(0, 6), 827 MUX_VALUE(0, 7), 828 MUX_VALUE(0, 8), 829 MUX_VALUE(0, 9), 830 MUX_VALUE(0, 10), 831 MUX_VALUE(0, 11), 832 MUX_VALUE(0, 12), 833 MUX_VALUE(0, 13), 834 MUX_VALUE(0, 14), 835 MUX_VALUE(0, 15), 836 /* I2S */ 837 MUX_VALUE(0, 16), 838 MUX_VALUE(0, 17), 839 MUX_VALUE(0, 18), 840 MUX_VALUE(0, 19), 841 MUX_VALUE(0, 20), 842 MUX_VALUE(0, 21), 843 MUX_VALUE(0, 22), 844 MUX_VALUE(0, 23), 845 /* SFC */ 846 MUX_VALUE(0, 24), 847 MUX_VALUE(0, 25), 848 MUX_VALUE(0, 26), 849 MUX_VALUE(0, 27), 850 /* MIXER */ 851 MUX_VALUE(1, 0), 852 MUX_VALUE(1, 1), 853 MUX_VALUE(1, 2), 854 MUX_VALUE(1, 3), 855 MUX_VALUE(1, 4), 856 /* AMX */ 857 MUX_VALUE(1, 8), 858 MUX_VALUE(1, 9), 859 MUX_VALUE(1, 10), 860 MUX_VALUE(1, 11), 861 MUX_VALUE(1, 12), 862 MUX_VALUE(1, 13), 863 /* OPE */ 864 MUX_VALUE(2, 0), 865 /* MVC */ 866 MUX_VALUE(2, 8), 867 MUX_VALUE(2, 9), 868 /* DMIC */ 869 MUX_VALUE(2, 18), 870 MUX_VALUE(2, 19), 871 /* ADX */ 872 MUX_VALUE(2, 24), 873 MUX_VALUE(2, 25), 874 MUX_VALUE(2, 26), 875 MUX_VALUE(2, 27), 876 MUX_VALUE(2, 28), 877 MUX_VALUE(2, 29), 878 MUX_VALUE(2, 30), 879 MUX_VALUE(2, 31), 880 MUX_VALUE(3, 0), 881 MUX_VALUE(3, 1), 882 MUX_VALUE(3, 2), 883 MUX_VALUE(3, 3), 884 MUX_VALUE(3, 4), 885 MUX_VALUE(3, 5), 886 MUX_VALUE(3, 6), 887 MUX_VALUE(3, 7), 888 MUX_VALUE(3, 8), 889 MUX_VALUE(3, 9), 890 MUX_VALUE(3, 10), 891 MUX_VALUE(3, 11), 892 MUX_VALUE(3, 12), 893 MUX_VALUE(3, 13), 894 MUX_VALUE(3, 14), 895 MUX_VALUE(3, 15), 896 /* ASRC */ 897 MUX_VALUE(3, 24), 898 MUX_VALUE(3, 25), 899 MUX_VALUE(3, 26), 900 MUX_VALUE(3, 27), 901 MUX_VALUE(3, 28), 902 MUX_VALUE(3, 29), 903 /* ADMAIF */ 904 MUX_VALUE(4, 7), 905 MUX_VALUE(4, 8), 906 MUX_VALUE(4, 9), 907 MUX_VALUE(4, 10), 908 MUX_VALUE(4, 11), 909 MUX_VALUE(4, 12), 910 MUX_VALUE(4, 13), 911 MUX_VALUE(4, 14), 912 MUX_VALUE(4, 15), 913 MUX_VALUE(4, 16), 914 MUX_VALUE(4, 17), 915 MUX_VALUE(4, 18), 916 MUX_VALUE(4, 19), 917 MUX_VALUE(4, 20), 918 MUX_VALUE(4, 21), 919 MUX_VALUE(4, 22), 920 }; 921 922 /* Controls for t210 */ 923 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00); 924 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01); 925 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02); 926 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03); 927 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04); 928 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05); 929 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06); 930 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07); 931 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08); 932 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09); 933 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10); 934 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11); 935 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12); 936 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13); 937 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14); 938 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18); 939 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19); 940 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a); 941 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b); 942 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48); 943 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49); 944 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50); 945 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51); 946 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52); 947 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53); 948 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54); 949 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55); 950 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56); 951 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57); 952 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58); 953 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59); 954 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20); 955 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21); 956 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22); 957 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23); 958 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24); 959 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25); 960 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26); 961 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27); 962 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28); 963 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29); 964 MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40); 965 MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41); 966 967 /* Controls for t186 */ 968 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00); 969 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01); 970 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02); 971 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03); 972 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04); 973 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05); 974 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06); 975 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07); 976 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08); 977 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09); 978 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10); 979 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11); 980 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12); 981 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13); 982 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14); 983 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a); 984 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b); 985 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c); 986 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d); 987 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e); 988 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f); 989 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15); 990 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); 991 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); 992 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68); 993 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69); 994 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a); 995 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b); 996 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18); 997 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19); 998 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a); 999 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b); 1000 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48); 1001 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49); 1002 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50); 1003 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51); 1004 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52); 1005 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53); 1006 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54); 1007 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55); 1008 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56); 1009 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57); 1010 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58); 1011 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59); 1012 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a); 1013 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b); 1014 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64); 1015 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65); 1016 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66); 1017 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67); 1018 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60); 1019 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61); 1020 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62); 1021 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63); 1022 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20); 1023 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21); 1024 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22); 1025 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23); 1026 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24); 1027 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25); 1028 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26); 1029 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); 1030 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); 1031 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); 1032 MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c); 1033 MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d); 1034 MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e); 1035 MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f); 1036 MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70); 1037 MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71); 1038 MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72); 1039 MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40); 1040 1041 /* Controls for t234 */ 1042 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44); 1043 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45); 1044 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48); 1045 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49); 1046 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a); 1047 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b); 1048 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c); 1049 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d); 1050 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e); 1051 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f); 1052 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50); 1053 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51); 1054 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52); 1055 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53); 1056 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58); 1057 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59); 1058 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a); 1059 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b); 1060 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c); 1061 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d); 1062 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e); 1063 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f); 1064 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60); 1065 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61); 1066 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62); 1067 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63); 1068 MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64); 1069 MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65); 1070 MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66); 1071 MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67); 1072 MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68); 1073 MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69); 1074 MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a); 1075 1076 /* Controls for t264 */ 1077 MUX_ENUM_CTRL_DECL_264(t264_admaif1_tx, 0x00); 1078 MUX_ENUM_CTRL_DECL_264(t264_admaif2_tx, 0x01); 1079 MUX_ENUM_CTRL_DECL_264(t264_admaif3_tx, 0x02); 1080 MUX_ENUM_CTRL_DECL_264(t264_admaif4_tx, 0x03); 1081 MUX_ENUM_CTRL_DECL_264(t264_admaif5_tx, 0x04); 1082 MUX_ENUM_CTRL_DECL_264(t264_admaif6_tx, 0x05); 1083 MUX_ENUM_CTRL_DECL_264(t264_admaif7_tx, 0x06); 1084 MUX_ENUM_CTRL_DECL_264(t264_admaif8_tx, 0x07); 1085 MUX_ENUM_CTRL_DECL_264(t264_admaif9_tx, 0x08); 1086 MUX_ENUM_CTRL_DECL_264(t264_admaif10_tx, 0x09); 1087 MUX_ENUM_CTRL_DECL_264(t264_admaif11_tx, 0x0a); 1088 MUX_ENUM_CTRL_DECL_264(t264_admaif12_tx, 0x0b); 1089 MUX_ENUM_CTRL_DECL_264(t264_admaif13_tx, 0x0c); 1090 MUX_ENUM_CTRL_DECL_264(t264_admaif14_tx, 0x0d); 1091 MUX_ENUM_CTRL_DECL_264(t264_admaif15_tx, 0x0e); 1092 MUX_ENUM_CTRL_DECL_264(t264_admaif16_tx, 0x0f); 1093 MUX_ENUM_CTRL_DECL_264(t264_i2s1_tx, 0x10); 1094 MUX_ENUM_CTRL_DECL_264(t264_i2s2_tx, 0x11); 1095 MUX_ENUM_CTRL_DECL_264(t264_i2s3_tx, 0x12); 1096 MUX_ENUM_CTRL_DECL_264(t264_i2s4_tx, 0x13); 1097 MUX_ENUM_CTRL_DECL_264(t264_i2s5_tx, 0x14); 1098 MUX_ENUM_CTRL_DECL_264(t264_i2s6_tx, 0x15); 1099 MUX_ENUM_CTRL_DECL_264(t264_i2s7_tx, 0x16); 1100 MUX_ENUM_CTRL_DECL_264(t264_i2s8_tx, 0x17); 1101 MUX_ENUM_CTRL_DECL_264(t264_sfc1_tx, 0x18); 1102 MUX_ENUM_CTRL_DECL_264(t264_sfc2_tx, 0x19); 1103 MUX_ENUM_CTRL_DECL_264(t264_sfc3_tx, 0x1a); 1104 MUX_ENUM_CTRL_DECL_264(t264_sfc4_tx, 0x1b); 1105 MUX_ENUM_CTRL_DECL_264(t264_mixer11_tx, 0x20); 1106 MUX_ENUM_CTRL_DECL_264(t264_mixer12_tx, 0x21); 1107 MUX_ENUM_CTRL_DECL_264(t264_mixer13_tx, 0x22); 1108 MUX_ENUM_CTRL_DECL_264(t264_mixer14_tx, 0x23); 1109 MUX_ENUM_CTRL_DECL_264(t264_mixer15_tx, 0x24); 1110 MUX_ENUM_CTRL_DECL_264(t264_mixer16_tx, 0x25); 1111 MUX_ENUM_CTRL_DECL_264(t264_mixer17_tx, 0x26); 1112 MUX_ENUM_CTRL_DECL_264(t264_mixer18_tx, 0x27); 1113 MUX_ENUM_CTRL_DECL_264(t264_mixer19_tx, 0x28); 1114 MUX_ENUM_CTRL_DECL_264(t264_mixer110_tx, 0x29); 1115 MUX_ENUM_CTRL_DECL_264(t264_dspk1_tx, 0x30); 1116 MUX_ENUM_CTRL_DECL_264(t264_ope1_tx, 0x40); 1117 MUX_ENUM_CTRL_DECL_264(t264_mvc1_tx, 0x44); 1118 MUX_ENUM_CTRL_DECL_264(t264_mvc2_tx, 0x45); 1119 MUX_ENUM_CTRL_DECL_264(t264_amx11_tx, 0x48); 1120 MUX_ENUM_CTRL_DECL_264(t264_amx12_tx, 0x49); 1121 MUX_ENUM_CTRL_DECL_264(t264_amx13_tx, 0x4a); 1122 MUX_ENUM_CTRL_DECL_264(t264_amx14_tx, 0x4b); 1123 MUX_ENUM_CTRL_DECL_264(t264_amx21_tx, 0x4c); 1124 MUX_ENUM_CTRL_DECL_264(t264_amx22_tx, 0x4d); 1125 MUX_ENUM_CTRL_DECL_264(t264_amx23_tx, 0x4e); 1126 MUX_ENUM_CTRL_DECL_264(t264_amx24_tx, 0x4f); 1127 MUX_ENUM_CTRL_DECL_264(t264_amx31_tx, 0x50); 1128 MUX_ENUM_CTRL_DECL_264(t264_amx32_tx, 0x51); 1129 MUX_ENUM_CTRL_DECL_264(t264_amx33_tx, 0x52); 1130 MUX_ENUM_CTRL_DECL_264(t264_amx34_tx, 0x53); 1131 MUX_ENUM_CTRL_DECL_264(t264_adx1_tx, 0x58); 1132 MUX_ENUM_CTRL_DECL_264(t264_adx2_tx, 0x59); 1133 MUX_ENUM_CTRL_DECL_264(t264_adx3_tx, 0x5a); 1134 MUX_ENUM_CTRL_DECL_264(t264_adx4_tx, 0x5b); 1135 MUX_ENUM_CTRL_DECL_264(t264_amx41_tx, 0x5c); 1136 MUX_ENUM_CTRL_DECL_264(t264_amx42_tx, 0x5d); 1137 MUX_ENUM_CTRL_DECL_264(t264_amx43_tx, 0x5e); 1138 MUX_ENUM_CTRL_DECL_264(t264_amx44_tx, 0x5f); 1139 MUX_ENUM_CTRL_DECL_264(t264_admaif17_tx, 0x60); 1140 MUX_ENUM_CTRL_DECL_264(t264_admaif18_tx, 0x61); 1141 MUX_ENUM_CTRL_DECL_264(t264_admaif19_tx, 0x62); 1142 MUX_ENUM_CTRL_DECL_264(t264_admaif20_tx, 0x63); 1143 MUX_ENUM_CTRL_DECL_264(t264_asrc11_tx, 0x64); 1144 MUX_ENUM_CTRL_DECL_264(t264_asrc12_tx, 0x65); 1145 MUX_ENUM_CTRL_DECL_264(t264_asrc13_tx, 0x66); 1146 MUX_ENUM_CTRL_DECL_264(t264_asrc14_tx, 0x67); 1147 MUX_ENUM_CTRL_DECL_264(t264_asrc15_tx, 0x68); 1148 MUX_ENUM_CTRL_DECL_264(t264_asrc16_tx, 0x69); 1149 MUX_ENUM_CTRL_DECL_264(t264_asrc17_tx, 0x6a); 1150 MUX_ENUM_CTRL_DECL_264(t264_admaif21_tx, 0x74); 1151 MUX_ENUM_CTRL_DECL_264(t264_admaif22_tx, 0x75); 1152 MUX_ENUM_CTRL_DECL_264(t264_admaif23_tx, 0x76); 1153 MUX_ENUM_CTRL_DECL_264(t264_admaif24_tx, 0x77); 1154 MUX_ENUM_CTRL_DECL_264(t264_admaif25_tx, 0x78); 1155 MUX_ENUM_CTRL_DECL_264(t264_admaif26_tx, 0x79); 1156 MUX_ENUM_CTRL_DECL_264(t264_admaif27_tx, 0x7a); 1157 MUX_ENUM_CTRL_DECL_264(t264_admaif28_tx, 0x7b); 1158 MUX_ENUM_CTRL_DECL_264(t264_admaif29_tx, 0x7c); 1159 MUX_ENUM_CTRL_DECL_264(t264_admaif30_tx, 0x7d); 1160 MUX_ENUM_CTRL_DECL_264(t264_admaif31_tx, 0x7e); 1161 MUX_ENUM_CTRL_DECL_264(t264_admaif32_tx, 0x7f); 1162 MUX_ENUM_CTRL_DECL_264(t264_amx51_tx, 0x80); 1163 MUX_ENUM_CTRL_DECL_264(t264_amx52_tx, 0x81); 1164 MUX_ENUM_CTRL_DECL_264(t264_amx53_tx, 0x82); 1165 MUX_ENUM_CTRL_DECL_264(t264_amx54_tx, 0x83); 1166 MUX_ENUM_CTRL_DECL_264(t264_amx61_tx, 0x84); 1167 MUX_ENUM_CTRL_DECL_264(t264_amx62_tx, 0x85); 1168 MUX_ENUM_CTRL_DECL_264(t264_amx63_tx, 0x86); 1169 MUX_ENUM_CTRL_DECL_264(t264_amx64_tx, 0x87); 1170 MUX_ENUM_CTRL_DECL_264(t264_adx5_tx, 0x88); 1171 MUX_ENUM_CTRL_DECL_264(t264_adx6_tx, 0x89); 1172 1173 static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { 1174 WIDGETS("ADMAIF1", t210_admaif1_tx), 1175 WIDGETS("ADMAIF2", t210_admaif2_tx), 1176 WIDGETS("ADMAIF3", t210_admaif3_tx), 1177 WIDGETS("ADMAIF4", t210_admaif4_tx), 1178 WIDGETS("ADMAIF5", t210_admaif5_tx), 1179 WIDGETS("ADMAIF6", t210_admaif6_tx), 1180 WIDGETS("ADMAIF7", t210_admaif7_tx), 1181 WIDGETS("ADMAIF8", t210_admaif8_tx), 1182 WIDGETS("ADMAIF9", t210_admaif9_tx), 1183 WIDGETS("ADMAIF10", t210_admaif10_tx), 1184 WIDGETS("I2S1", t210_i2s1_tx), 1185 WIDGETS("I2S2", t210_i2s2_tx), 1186 WIDGETS("I2S3", t210_i2s3_tx), 1187 WIDGETS("I2S4", t210_i2s4_tx), 1188 WIDGETS("I2S5", t210_i2s5_tx), 1189 TX_WIDGETS("DMIC1"), 1190 TX_WIDGETS("DMIC2"), 1191 TX_WIDGETS("DMIC3"), 1192 WIDGETS("SFC1", t210_sfc1_tx), 1193 WIDGETS("SFC2", t210_sfc2_tx), 1194 WIDGETS("SFC3", t210_sfc3_tx), 1195 WIDGETS("SFC4", t210_sfc4_tx), 1196 WIDGETS("MVC1", t210_mvc1_tx), 1197 WIDGETS("MVC2", t210_mvc2_tx), 1198 WIDGETS("AMX1 RX1", t210_amx11_tx), 1199 WIDGETS("AMX1 RX2", t210_amx12_tx), 1200 WIDGETS("AMX1 RX3", t210_amx13_tx), 1201 WIDGETS("AMX1 RX4", t210_amx14_tx), 1202 WIDGETS("AMX2 RX1", t210_amx21_tx), 1203 WIDGETS("AMX2 RX2", t210_amx22_tx), 1204 WIDGETS("AMX2 RX3", t210_amx23_tx), 1205 WIDGETS("AMX2 RX4", t210_amx24_tx), 1206 TX_WIDGETS("AMX1"), 1207 TX_WIDGETS("AMX2"), 1208 WIDGETS("ADX1", t210_adx1_tx), 1209 WIDGETS("ADX2", t210_adx2_tx), 1210 TX_WIDGETS("ADX1 TX1"), 1211 TX_WIDGETS("ADX1 TX2"), 1212 TX_WIDGETS("ADX1 TX3"), 1213 TX_WIDGETS("ADX1 TX4"), 1214 TX_WIDGETS("ADX2 TX1"), 1215 TX_WIDGETS("ADX2 TX2"), 1216 TX_WIDGETS("ADX2 TX3"), 1217 TX_WIDGETS("ADX2 TX4"), 1218 WIDGETS("MIXER1 RX1", t210_mixer11_tx), 1219 WIDGETS("MIXER1 RX2", t210_mixer12_tx), 1220 WIDGETS("MIXER1 RX3", t210_mixer13_tx), 1221 WIDGETS("MIXER1 RX4", t210_mixer14_tx), 1222 WIDGETS("MIXER1 RX5", t210_mixer15_tx), 1223 WIDGETS("MIXER1 RX6", t210_mixer16_tx), 1224 WIDGETS("MIXER1 RX7", t210_mixer17_tx), 1225 WIDGETS("MIXER1 RX8", t210_mixer18_tx), 1226 WIDGETS("MIXER1 RX9", t210_mixer19_tx), 1227 WIDGETS("MIXER1 RX10", t210_mixer110_tx), 1228 TX_WIDGETS("MIXER1 TX1"), 1229 TX_WIDGETS("MIXER1 TX2"), 1230 TX_WIDGETS("MIXER1 TX3"), 1231 TX_WIDGETS("MIXER1 TX4"), 1232 TX_WIDGETS("MIXER1 TX5"), 1233 WIDGETS("OPE1", t210_ope1_tx), 1234 WIDGETS("OPE2", t210_ope2_tx), 1235 }; 1236 1237 static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { 1238 WIDGETS("ADMAIF1", t186_admaif1_tx), 1239 WIDGETS("ADMAIF2", t186_admaif2_tx), 1240 WIDGETS("ADMAIF3", t186_admaif3_tx), 1241 WIDGETS("ADMAIF4", t186_admaif4_tx), 1242 WIDGETS("ADMAIF5", t186_admaif5_tx), 1243 WIDGETS("ADMAIF6", t186_admaif6_tx), 1244 WIDGETS("ADMAIF7", t186_admaif7_tx), 1245 WIDGETS("ADMAIF8", t186_admaif8_tx), 1246 WIDGETS("ADMAIF9", t186_admaif9_tx), 1247 WIDGETS("ADMAIF10", t186_admaif10_tx), 1248 WIDGETS("ADMAIF11", t186_admaif11_tx), 1249 WIDGETS("ADMAIF12", t186_admaif12_tx), 1250 WIDGETS("ADMAIF13", t186_admaif13_tx), 1251 WIDGETS("ADMAIF14", t186_admaif14_tx), 1252 WIDGETS("ADMAIF15", t186_admaif15_tx), 1253 WIDGETS("ADMAIF16", t186_admaif16_tx), 1254 WIDGETS("ADMAIF17", t186_admaif17_tx), 1255 WIDGETS("ADMAIF18", t186_admaif18_tx), 1256 WIDGETS("ADMAIF19", t186_admaif19_tx), 1257 WIDGETS("ADMAIF20", t186_admaif20_tx), 1258 WIDGETS("I2S1", t186_i2s1_tx), 1259 WIDGETS("I2S2", t186_i2s2_tx), 1260 WIDGETS("I2S3", t186_i2s3_tx), 1261 WIDGETS("I2S4", t186_i2s4_tx), 1262 WIDGETS("I2S5", t186_i2s5_tx), 1263 WIDGETS("I2S6", t186_i2s6_tx), 1264 TX_WIDGETS("DMIC1"), 1265 TX_WIDGETS("DMIC2"), 1266 TX_WIDGETS("DMIC3"), 1267 TX_WIDGETS("DMIC4"), 1268 WIDGETS("DSPK1", t186_dspk1_tx), 1269 WIDGETS("DSPK2", t186_dspk2_tx), 1270 WIDGETS("SFC1", t186_sfc1_tx), 1271 WIDGETS("SFC2", t186_sfc2_tx), 1272 WIDGETS("SFC3", t186_sfc3_tx), 1273 WIDGETS("SFC4", t186_sfc4_tx), 1274 WIDGETS("MVC1", t186_mvc1_tx), 1275 WIDGETS("MVC2", t186_mvc2_tx), 1276 WIDGETS("AMX1 RX1", t186_amx11_tx), 1277 WIDGETS("AMX1 RX2", t186_amx12_tx), 1278 WIDGETS("AMX1 RX3", t186_amx13_tx), 1279 WIDGETS("AMX1 RX4", t186_amx14_tx), 1280 WIDGETS("AMX2 RX1", t186_amx21_tx), 1281 WIDGETS("AMX2 RX2", t186_amx22_tx), 1282 WIDGETS("AMX2 RX3", t186_amx23_tx), 1283 WIDGETS("AMX2 RX4", t186_amx24_tx), 1284 WIDGETS("AMX3 RX1", t186_amx31_tx), 1285 WIDGETS("AMX3 RX2", t186_amx32_tx), 1286 WIDGETS("AMX3 RX3", t186_amx33_tx), 1287 WIDGETS("AMX3 RX4", t186_amx34_tx), 1288 WIDGETS("AMX4 RX1", t186_amx41_tx), 1289 WIDGETS("AMX4 RX2", t186_amx42_tx), 1290 WIDGETS("AMX4 RX3", t186_amx43_tx), 1291 WIDGETS("AMX4 RX4", t186_amx44_tx), 1292 TX_WIDGETS("AMX1"), 1293 TX_WIDGETS("AMX2"), 1294 TX_WIDGETS("AMX3"), 1295 TX_WIDGETS("AMX4"), 1296 WIDGETS("ADX1", t186_adx1_tx), 1297 WIDGETS("ADX2", t186_adx2_tx), 1298 WIDGETS("ADX3", t186_adx3_tx), 1299 WIDGETS("ADX4", t186_adx4_tx), 1300 TX_WIDGETS("ADX1 TX1"), 1301 TX_WIDGETS("ADX1 TX2"), 1302 TX_WIDGETS("ADX1 TX3"), 1303 TX_WIDGETS("ADX1 TX4"), 1304 TX_WIDGETS("ADX2 TX1"), 1305 TX_WIDGETS("ADX2 TX2"), 1306 TX_WIDGETS("ADX2 TX3"), 1307 TX_WIDGETS("ADX2 TX4"), 1308 TX_WIDGETS("ADX3 TX1"), 1309 TX_WIDGETS("ADX3 TX2"), 1310 TX_WIDGETS("ADX3 TX3"), 1311 TX_WIDGETS("ADX3 TX4"), 1312 TX_WIDGETS("ADX4 TX1"), 1313 TX_WIDGETS("ADX4 TX2"), 1314 TX_WIDGETS("ADX4 TX3"), 1315 TX_WIDGETS("ADX4 TX4"), 1316 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 1317 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 1318 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 1319 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 1320 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 1321 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 1322 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 1323 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 1324 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 1325 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 1326 TX_WIDGETS("MIXER1 TX1"), 1327 TX_WIDGETS("MIXER1 TX2"), 1328 TX_WIDGETS("MIXER1 TX3"), 1329 TX_WIDGETS("MIXER1 TX4"), 1330 TX_WIDGETS("MIXER1 TX5"), 1331 WIDGETS("ASRC1 RX1", t186_asrc11_tx), 1332 WIDGETS("ASRC1 RX2", t186_asrc12_tx), 1333 WIDGETS("ASRC1 RX3", t186_asrc13_tx), 1334 WIDGETS("ASRC1 RX4", t186_asrc14_tx), 1335 WIDGETS("ASRC1 RX5", t186_asrc15_tx), 1336 WIDGETS("ASRC1 RX6", t186_asrc16_tx), 1337 WIDGETS("ASRC1 RX7", t186_asrc17_tx), 1338 TX_WIDGETS("ASRC1 TX1"), 1339 TX_WIDGETS("ASRC1 TX2"), 1340 TX_WIDGETS("ASRC1 TX3"), 1341 TX_WIDGETS("ASRC1 TX4"), 1342 TX_WIDGETS("ASRC1 TX5"), 1343 TX_WIDGETS("ASRC1 TX6"), 1344 WIDGETS("OPE1", t186_ope1_tx), 1345 }; 1346 1347 static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = { 1348 WIDGETS("ADMAIF1", t186_admaif1_tx), 1349 WIDGETS("ADMAIF2", t186_admaif2_tx), 1350 WIDGETS("ADMAIF3", t186_admaif3_tx), 1351 WIDGETS("ADMAIF4", t186_admaif4_tx), 1352 WIDGETS("ADMAIF5", t186_admaif5_tx), 1353 WIDGETS("ADMAIF6", t186_admaif6_tx), 1354 WIDGETS("ADMAIF7", t186_admaif7_tx), 1355 WIDGETS("ADMAIF8", t186_admaif8_tx), 1356 WIDGETS("ADMAIF9", t186_admaif9_tx), 1357 WIDGETS("ADMAIF10", t186_admaif10_tx), 1358 WIDGETS("ADMAIF11", t186_admaif11_tx), 1359 WIDGETS("ADMAIF12", t186_admaif12_tx), 1360 WIDGETS("ADMAIF13", t186_admaif13_tx), 1361 WIDGETS("ADMAIF14", t186_admaif14_tx), 1362 WIDGETS("ADMAIF15", t186_admaif15_tx), 1363 WIDGETS("ADMAIF16", t186_admaif16_tx), 1364 WIDGETS("ADMAIF17", t234_admaif17_tx), 1365 WIDGETS("ADMAIF18", t234_admaif18_tx), 1366 WIDGETS("ADMAIF19", t234_admaif19_tx), 1367 WIDGETS("ADMAIF20", t234_admaif20_tx), 1368 WIDGETS("I2S1", t186_i2s1_tx), 1369 WIDGETS("I2S2", t186_i2s2_tx), 1370 WIDGETS("I2S3", t186_i2s3_tx), 1371 WIDGETS("I2S4", t186_i2s4_tx), 1372 WIDGETS("I2S5", t186_i2s5_tx), 1373 WIDGETS("I2S6", t186_i2s6_tx), 1374 TX_WIDGETS("DMIC1"), 1375 TX_WIDGETS("DMIC2"), 1376 TX_WIDGETS("DMIC3"), 1377 TX_WIDGETS("DMIC4"), 1378 WIDGETS("DSPK1", t186_dspk1_tx), 1379 WIDGETS("DSPK2", t186_dspk2_tx), 1380 WIDGETS("SFC1", t186_sfc1_tx), 1381 WIDGETS("SFC2", t186_sfc2_tx), 1382 WIDGETS("SFC3", t186_sfc3_tx), 1383 WIDGETS("SFC4", t186_sfc4_tx), 1384 WIDGETS("MVC1", t234_mvc1_tx), 1385 WIDGETS("MVC2", t234_mvc2_tx), 1386 WIDGETS("AMX1 RX1", t234_amx11_tx), 1387 WIDGETS("AMX1 RX2", t234_amx12_tx), 1388 WIDGETS("AMX1 RX3", t234_amx13_tx), 1389 WIDGETS("AMX1 RX4", t234_amx14_tx), 1390 WIDGETS("AMX2 RX1", t234_amx21_tx), 1391 WIDGETS("AMX2 RX2", t234_amx22_tx), 1392 WIDGETS("AMX2 RX3", t234_amx23_tx), 1393 WIDGETS("AMX2 RX4", t234_amx24_tx), 1394 WIDGETS("AMX3 RX1", t234_amx31_tx), 1395 WIDGETS("AMX3 RX2", t234_amx32_tx), 1396 WIDGETS("AMX3 RX3", t234_amx33_tx), 1397 WIDGETS("AMX3 RX4", t234_amx34_tx), 1398 WIDGETS("AMX4 RX1", t234_amx41_tx), 1399 WIDGETS("AMX4 RX2", t234_amx42_tx), 1400 WIDGETS("AMX4 RX3", t234_amx43_tx), 1401 WIDGETS("AMX4 RX4", t234_amx44_tx), 1402 TX_WIDGETS("AMX1"), 1403 TX_WIDGETS("AMX2"), 1404 TX_WIDGETS("AMX3"), 1405 TX_WIDGETS("AMX4"), 1406 WIDGETS("ADX1", t234_adx1_tx), 1407 WIDGETS("ADX2", t234_adx2_tx), 1408 WIDGETS("ADX3", t234_adx3_tx), 1409 WIDGETS("ADX4", t234_adx4_tx), 1410 TX_WIDGETS("ADX1 TX1"), 1411 TX_WIDGETS("ADX1 TX2"), 1412 TX_WIDGETS("ADX1 TX3"), 1413 TX_WIDGETS("ADX1 TX4"), 1414 TX_WIDGETS("ADX2 TX1"), 1415 TX_WIDGETS("ADX2 TX2"), 1416 TX_WIDGETS("ADX2 TX3"), 1417 TX_WIDGETS("ADX2 TX4"), 1418 TX_WIDGETS("ADX3 TX1"), 1419 TX_WIDGETS("ADX3 TX2"), 1420 TX_WIDGETS("ADX3 TX3"), 1421 TX_WIDGETS("ADX3 TX4"), 1422 TX_WIDGETS("ADX4 TX1"), 1423 TX_WIDGETS("ADX4 TX2"), 1424 TX_WIDGETS("ADX4 TX3"), 1425 TX_WIDGETS("ADX4 TX4"), 1426 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 1427 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 1428 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 1429 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 1430 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 1431 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 1432 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 1433 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 1434 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 1435 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 1436 TX_WIDGETS("MIXER1 TX1"), 1437 TX_WIDGETS("MIXER1 TX2"), 1438 TX_WIDGETS("MIXER1 TX3"), 1439 TX_WIDGETS("MIXER1 TX4"), 1440 TX_WIDGETS("MIXER1 TX5"), 1441 WIDGETS("ASRC1 RX1", t234_asrc11_tx), 1442 WIDGETS("ASRC1 RX2", t234_asrc12_tx), 1443 WIDGETS("ASRC1 RX3", t234_asrc13_tx), 1444 WIDGETS("ASRC1 RX4", t234_asrc14_tx), 1445 WIDGETS("ASRC1 RX5", t234_asrc15_tx), 1446 WIDGETS("ASRC1 RX6", t234_asrc16_tx), 1447 WIDGETS("ASRC1 RX7", t234_asrc17_tx), 1448 TX_WIDGETS("ASRC1 TX1"), 1449 TX_WIDGETS("ASRC1 TX2"), 1450 TX_WIDGETS("ASRC1 TX3"), 1451 TX_WIDGETS("ASRC1 TX4"), 1452 TX_WIDGETS("ASRC1 TX5"), 1453 TX_WIDGETS("ASRC1 TX6"), 1454 WIDGETS("OPE1", t186_ope1_tx), 1455 }; 1456 1457 static const struct snd_soc_dapm_widget tegra264_ahub_widgets[] = { 1458 WIDGETS("ADMAIF1", t264_admaif1_tx), 1459 WIDGETS("ADMAIF2", t264_admaif2_tx), 1460 WIDGETS("ADMAIF3", t264_admaif3_tx), 1461 WIDGETS("ADMAIF4", t264_admaif4_tx), 1462 WIDGETS("ADMAIF5", t264_admaif5_tx), 1463 WIDGETS("ADMAIF6", t264_admaif6_tx), 1464 WIDGETS("ADMAIF7", t264_admaif7_tx), 1465 WIDGETS("ADMAIF8", t264_admaif8_tx), 1466 WIDGETS("ADMAIF9", t264_admaif9_tx), 1467 WIDGETS("ADMAIF10", t264_admaif10_tx), 1468 WIDGETS("ADMAIF11", t264_admaif11_tx), 1469 WIDGETS("ADMAIF12", t264_admaif12_tx), 1470 WIDGETS("ADMAIF13", t264_admaif13_tx), 1471 WIDGETS("ADMAIF14", t264_admaif14_tx), 1472 WIDGETS("ADMAIF15", t264_admaif15_tx), 1473 WIDGETS("ADMAIF16", t264_admaif16_tx), 1474 WIDGETS("ADMAIF17", t264_admaif17_tx), 1475 WIDGETS("ADMAIF18", t264_admaif18_tx), 1476 WIDGETS("ADMAIF19", t264_admaif19_tx), 1477 WIDGETS("ADMAIF20", t264_admaif20_tx), 1478 WIDGETS("ADMAIF21", t264_admaif21_tx), 1479 WIDGETS("ADMAIF22", t264_admaif22_tx), 1480 WIDGETS("ADMAIF23", t264_admaif23_tx), 1481 WIDGETS("ADMAIF24", t264_admaif24_tx), 1482 WIDGETS("ADMAIF25", t264_admaif25_tx), 1483 WIDGETS("ADMAIF26", t264_admaif26_tx), 1484 WIDGETS("ADMAIF27", t264_admaif27_tx), 1485 WIDGETS("ADMAIF28", t264_admaif28_tx), 1486 WIDGETS("ADMAIF29", t264_admaif29_tx), 1487 WIDGETS("ADMAIF30", t264_admaif30_tx), 1488 WIDGETS("ADMAIF31", t264_admaif31_tx), 1489 WIDGETS("ADMAIF32", t264_admaif32_tx), 1490 WIDGETS("I2S1", t264_i2s1_tx), 1491 WIDGETS("I2S2", t264_i2s2_tx), 1492 WIDGETS("I2S3", t264_i2s3_tx), 1493 WIDGETS("I2S4", t264_i2s4_tx), 1494 WIDGETS("I2S5", t264_i2s5_tx), 1495 WIDGETS("I2S6", t264_i2s6_tx), 1496 WIDGETS("I2S7", t264_i2s7_tx), 1497 WIDGETS("I2S8", t264_i2s8_tx), 1498 TX_WIDGETS("DMIC1"), 1499 TX_WIDGETS("DMIC2"), 1500 WIDGETS("DSPK1", t264_dspk1_tx), 1501 WIDGETS("SFC1", t264_sfc1_tx), 1502 WIDGETS("SFC2", t264_sfc2_tx), 1503 WIDGETS("SFC3", t264_sfc3_tx), 1504 WIDGETS("SFC4", t264_sfc4_tx), 1505 WIDGETS("MVC1", t264_mvc1_tx), 1506 WIDGETS("MVC2", t264_mvc2_tx), 1507 WIDGETS("AMX1 RX1", t264_amx11_tx), 1508 WIDGETS("AMX1 RX2", t264_amx12_tx), 1509 WIDGETS("AMX1 RX3", t264_amx13_tx), 1510 WIDGETS("AMX1 RX4", t264_amx14_tx), 1511 WIDGETS("AMX2 RX1", t264_amx21_tx), 1512 WIDGETS("AMX2 RX2", t264_amx22_tx), 1513 WIDGETS("AMX2 RX3", t264_amx23_tx), 1514 WIDGETS("AMX2 RX4", t264_amx24_tx), 1515 WIDGETS("AMX3 RX1", t264_amx31_tx), 1516 WIDGETS("AMX3 RX2", t264_amx32_tx), 1517 WIDGETS("AMX3 RX3", t264_amx33_tx), 1518 WIDGETS("AMX3 RX4", t264_amx34_tx), 1519 WIDGETS("AMX4 RX1", t264_amx41_tx), 1520 WIDGETS("AMX4 RX2", t264_amx42_tx), 1521 WIDGETS("AMX4 RX3", t264_amx43_tx), 1522 WIDGETS("AMX4 RX4", t264_amx44_tx), 1523 WIDGETS("AMX5 RX1", t264_amx51_tx), 1524 WIDGETS("AMX5 RX2", t264_amx52_tx), 1525 WIDGETS("AMX5 RX3", t264_amx53_tx), 1526 WIDGETS("AMX5 RX4", t264_amx54_tx), 1527 WIDGETS("AMX6 RX1", t264_amx61_tx), 1528 WIDGETS("AMX6 RX2", t264_amx62_tx), 1529 WIDGETS("AMX6 RX3", t264_amx63_tx), 1530 WIDGETS("AMX6 RX4", t264_amx64_tx), 1531 TX_WIDGETS("AMX1"), 1532 TX_WIDGETS("AMX2"), 1533 TX_WIDGETS("AMX3"), 1534 TX_WIDGETS("AMX4"), 1535 TX_WIDGETS("AMX5"), 1536 TX_WIDGETS("AMX6"), 1537 WIDGETS("ADX1", t264_adx1_tx), 1538 WIDGETS("ADX2", t264_adx2_tx), 1539 WIDGETS("ADX3", t264_adx3_tx), 1540 WIDGETS("ADX4", t264_adx4_tx), 1541 WIDGETS("ADX5", t264_adx5_tx), 1542 WIDGETS("ADX6", t264_adx6_tx), 1543 TX_WIDGETS("ADX1 TX1"), 1544 TX_WIDGETS("ADX1 TX2"), 1545 TX_WIDGETS("ADX1 TX3"), 1546 TX_WIDGETS("ADX1 TX4"), 1547 TX_WIDGETS("ADX2 TX1"), 1548 TX_WIDGETS("ADX2 TX2"), 1549 TX_WIDGETS("ADX2 TX3"), 1550 TX_WIDGETS("ADX2 TX4"), 1551 TX_WIDGETS("ADX3 TX1"), 1552 TX_WIDGETS("ADX3 TX2"), 1553 TX_WIDGETS("ADX3 TX3"), 1554 TX_WIDGETS("ADX3 TX4"), 1555 TX_WIDGETS("ADX4 TX1"), 1556 TX_WIDGETS("ADX4 TX2"), 1557 TX_WIDGETS("ADX4 TX3"), 1558 TX_WIDGETS("ADX4 TX4"), 1559 TX_WIDGETS("ADX5 TX1"), 1560 TX_WIDGETS("ADX5 TX2"), 1561 TX_WIDGETS("ADX5 TX3"), 1562 TX_WIDGETS("ADX5 TX4"), 1563 TX_WIDGETS("ADX6 TX1"), 1564 TX_WIDGETS("ADX6 TX2"), 1565 TX_WIDGETS("ADX6 TX3"), 1566 TX_WIDGETS("ADX6 TX4"), 1567 WIDGETS("MIXER1 RX1", t264_mixer11_tx), 1568 WIDGETS("MIXER1 RX2", t264_mixer12_tx), 1569 WIDGETS("MIXER1 RX3", t264_mixer13_tx), 1570 WIDGETS("MIXER1 RX4", t264_mixer14_tx), 1571 WIDGETS("MIXER1 RX5", t264_mixer15_tx), 1572 WIDGETS("MIXER1 RX6", t264_mixer16_tx), 1573 WIDGETS("MIXER1 RX7", t264_mixer17_tx), 1574 WIDGETS("MIXER1 RX8", t264_mixer18_tx), 1575 WIDGETS("MIXER1 RX9", t264_mixer19_tx), 1576 WIDGETS("MIXER1 RX10", t264_mixer110_tx), 1577 TX_WIDGETS("MIXER1 TX1"), 1578 TX_WIDGETS("MIXER1 TX2"), 1579 TX_WIDGETS("MIXER1 TX3"), 1580 TX_WIDGETS("MIXER1 TX4"), 1581 TX_WIDGETS("MIXER1 TX5"), 1582 WIDGETS("ASRC1 RX1", t264_asrc11_tx), 1583 WIDGETS("ASRC1 RX2", t264_asrc12_tx), 1584 WIDGETS("ASRC1 RX3", t264_asrc13_tx), 1585 WIDGETS("ASRC1 RX4", t264_asrc14_tx), 1586 WIDGETS("ASRC1 RX5", t264_asrc15_tx), 1587 WIDGETS("ASRC1 RX6", t264_asrc16_tx), 1588 WIDGETS("ASRC1 RX7", t264_asrc17_tx), 1589 TX_WIDGETS("ASRC1 TX1"), 1590 TX_WIDGETS("ASRC1 TX2"), 1591 TX_WIDGETS("ASRC1 TX3"), 1592 TX_WIDGETS("ASRC1 TX4"), 1593 TX_WIDGETS("ASRC1 TX5"), 1594 TX_WIDGETS("ASRC1 TX6"), 1595 WIDGETS("OPE1", t264_ope1_tx), 1596 }; 1597 1598 #define TEGRA_COMMON_MUX_ROUTES(name) \ 1599 { name " XBAR-TX", NULL, name " Mux" }, \ 1600 { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \ 1601 { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \ 1602 { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \ 1603 { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \ 1604 { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \ 1605 { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \ 1606 { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \ 1607 { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \ 1608 { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \ 1609 { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \ 1610 { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \ 1611 { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \ 1612 { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \ 1613 { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \ 1614 { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \ 1615 { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \ 1616 { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \ 1617 { name " Mux", "SFC1", "SFC1 XBAR-RX" }, \ 1618 { name " Mux", "SFC2", "SFC2 XBAR-RX" }, \ 1619 { name " Mux", "SFC3", "SFC3 XBAR-RX" }, \ 1620 { name " Mux", "SFC4", "SFC4 XBAR-RX" }, \ 1621 { name " Mux", "MVC1", "MVC1 XBAR-RX" }, \ 1622 { name " Mux", "MVC2", "MVC2 XBAR-RX" }, \ 1623 { name " Mux", "AMX1", "AMX1 XBAR-RX" }, \ 1624 { name " Mux", "AMX2", "AMX2 XBAR-RX" }, \ 1625 { name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \ 1626 { name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \ 1627 { name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \ 1628 { name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \ 1629 { name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \ 1630 { name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \ 1631 { name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \ 1632 { name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \ 1633 { name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \ 1634 { name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \ 1635 { name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \ 1636 { name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \ 1637 { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, \ 1638 { name " Mux", "OPE1", "OPE1 XBAR-RX" }, 1639 1640 #define TEGRA210_ONLY_MUX_ROUTES(name) \ 1641 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1642 { name " Mux", "OPE2", "OPE2 XBAR-RX" }, 1643 1644 #define TEGRA186_ONLY_MUX_ROUTES(name) \ 1645 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1646 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1647 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1648 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1649 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1650 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1651 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1652 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1653 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1654 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1655 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1656 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1657 { name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \ 1658 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1659 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1660 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1661 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1662 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1663 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1664 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1665 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1666 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1667 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1668 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1669 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1670 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1671 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1672 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1673 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1674 1675 #define TEGRA264_ONLY_MUX_ROUTES(name) \ 1676 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1677 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1678 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1679 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1680 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1681 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1682 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1683 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1684 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1685 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1686 { name " Mux", "ADMAIF21", "ADMAIF21 XBAR-RX" }, \ 1687 { name " Mux", "ADMAIF22", "ADMAIF22 XBAR-RX" }, \ 1688 { name " Mux", "ADMAIF23", "ADMAIF23 XBAR-RX" }, \ 1689 { name " Mux", "ADMAIF24", "ADMAIF24 XBAR-RX" }, \ 1690 { name " Mux", "ADMAIF25", "ADMAIF25 XBAR-RX" }, \ 1691 { name " Mux", "ADMAIF26", "ADMAIF26 XBAR-RX" }, \ 1692 { name " Mux", "ADMAIF27", "ADMAIF27 XBAR-RX" }, \ 1693 { name " Mux", "ADMAIF28", "ADMAIF28 XBAR-RX" }, \ 1694 { name " Mux", "ADMAIF29", "ADMAIF29 XBAR-RX" }, \ 1695 { name " Mux", "ADMAIF30", "ADMAIF30 XBAR-RX" }, \ 1696 { name " Mux", "ADMAIF31", "ADMAIF31 XBAR-RX" }, \ 1697 { name " Mux", "ADMAIF32", "ADMAIF32 XBAR-RX" }, \ 1698 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1699 { name " Mux", "I2S7", "I2S7 XBAR-RX" }, \ 1700 { name " Mux", "I2S8", "I2S8 XBAR-RX" }, \ 1701 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1702 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1703 { name " Mux", "AMX5", "AMX5 XBAR-RX" }, \ 1704 { name " Mux", "AMX6", "AMX6 XBAR-RX" }, \ 1705 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1706 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1707 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1708 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1709 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1710 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1711 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1712 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1713 { name " Mux", "ADX5 TX1", "ADX5 TX1 XBAR-RX" }, \ 1714 { name " Mux", "ADX5 TX2", "ADX5 TX2 XBAR-RX" }, \ 1715 { name " Mux", "ADX5 TX3", "ADX5 TX3 XBAR-RX" }, \ 1716 { name " Mux", "ADX5 TX4", "ADX5 TX4 XBAR-RX" }, \ 1717 { name " Mux", "ADX6 TX1", "ADX6 TX1 XBAR-RX" }, \ 1718 { name " Mux", "ADX6 TX2", "ADX6 TX2 XBAR-RX" }, \ 1719 { name " Mux", "ADX6 TX3", "ADX6 TX3 XBAR-RX" }, \ 1720 { name " Mux", "ADX6 TX4", "ADX6 TX4 XBAR-RX" }, \ 1721 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1722 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1723 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1724 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1725 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1726 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1727 1728 #define TEGRA210_MUX_ROUTES(name) \ 1729 TEGRA_COMMON_MUX_ROUTES(name) \ 1730 TEGRA210_ONLY_MUX_ROUTES(name) 1731 1732 #define TEGRA186_MUX_ROUTES(name) \ 1733 TEGRA_COMMON_MUX_ROUTES(name) \ 1734 TEGRA186_ONLY_MUX_ROUTES(name) 1735 1736 #define TEGRA264_MUX_ROUTES(name) \ 1737 TEGRA_COMMON_MUX_ROUTES(name) \ 1738 TEGRA264_ONLY_MUX_ROUTES(name) 1739 1740 /* Connect FEs with XBAR */ 1741 #define TEGRA_FE_ROUTES(name) \ 1742 { name " XBAR-Playback", NULL, name " Playback" }, \ 1743 { name " XBAR-RX", NULL, name " XBAR-Playback"}, \ 1744 { name " XBAR-Capture", NULL, name " XBAR-TX" }, \ 1745 { name " Capture", NULL, name " XBAR-Capture" }, 1746 1747 static const struct snd_soc_dapm_route tegra210_ahub_routes[] = { 1748 TEGRA_FE_ROUTES("ADMAIF1") 1749 TEGRA_FE_ROUTES("ADMAIF2") 1750 TEGRA_FE_ROUTES("ADMAIF3") 1751 TEGRA_FE_ROUTES("ADMAIF4") 1752 TEGRA_FE_ROUTES("ADMAIF5") 1753 TEGRA_FE_ROUTES("ADMAIF6") 1754 TEGRA_FE_ROUTES("ADMAIF7") 1755 TEGRA_FE_ROUTES("ADMAIF8") 1756 TEGRA_FE_ROUTES("ADMAIF9") 1757 TEGRA_FE_ROUTES("ADMAIF10") 1758 TEGRA210_MUX_ROUTES("ADMAIF1") 1759 TEGRA210_MUX_ROUTES("ADMAIF2") 1760 TEGRA210_MUX_ROUTES("ADMAIF3") 1761 TEGRA210_MUX_ROUTES("ADMAIF4") 1762 TEGRA210_MUX_ROUTES("ADMAIF5") 1763 TEGRA210_MUX_ROUTES("ADMAIF6") 1764 TEGRA210_MUX_ROUTES("ADMAIF7") 1765 TEGRA210_MUX_ROUTES("ADMAIF8") 1766 TEGRA210_MUX_ROUTES("ADMAIF9") 1767 TEGRA210_MUX_ROUTES("ADMAIF10") 1768 TEGRA210_MUX_ROUTES("I2S1") 1769 TEGRA210_MUX_ROUTES("I2S2") 1770 TEGRA210_MUX_ROUTES("I2S3") 1771 TEGRA210_MUX_ROUTES("I2S4") 1772 TEGRA210_MUX_ROUTES("I2S5") 1773 TEGRA210_MUX_ROUTES("SFC1") 1774 TEGRA210_MUX_ROUTES("SFC2") 1775 TEGRA210_MUX_ROUTES("SFC3") 1776 TEGRA210_MUX_ROUTES("SFC4") 1777 TEGRA210_MUX_ROUTES("MVC1") 1778 TEGRA210_MUX_ROUTES("MVC2") 1779 TEGRA210_MUX_ROUTES("AMX1 RX1") 1780 TEGRA210_MUX_ROUTES("AMX1 RX2") 1781 TEGRA210_MUX_ROUTES("AMX1 RX3") 1782 TEGRA210_MUX_ROUTES("AMX1 RX4") 1783 TEGRA210_MUX_ROUTES("AMX2 RX1") 1784 TEGRA210_MUX_ROUTES("AMX2 RX2") 1785 TEGRA210_MUX_ROUTES("AMX2 RX3") 1786 TEGRA210_MUX_ROUTES("AMX2 RX4") 1787 TEGRA210_MUX_ROUTES("ADX1") 1788 TEGRA210_MUX_ROUTES("ADX2") 1789 TEGRA210_MUX_ROUTES("MIXER1 RX1") 1790 TEGRA210_MUX_ROUTES("MIXER1 RX2") 1791 TEGRA210_MUX_ROUTES("MIXER1 RX3") 1792 TEGRA210_MUX_ROUTES("MIXER1 RX4") 1793 TEGRA210_MUX_ROUTES("MIXER1 RX5") 1794 TEGRA210_MUX_ROUTES("MIXER1 RX6") 1795 TEGRA210_MUX_ROUTES("MIXER1 RX7") 1796 TEGRA210_MUX_ROUTES("MIXER1 RX8") 1797 TEGRA210_MUX_ROUTES("MIXER1 RX9") 1798 TEGRA210_MUX_ROUTES("MIXER1 RX10") 1799 TEGRA210_MUX_ROUTES("OPE1") 1800 TEGRA210_MUX_ROUTES("OPE2") 1801 }; 1802 1803 static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { 1804 TEGRA_FE_ROUTES("ADMAIF1") 1805 TEGRA_FE_ROUTES("ADMAIF2") 1806 TEGRA_FE_ROUTES("ADMAIF3") 1807 TEGRA_FE_ROUTES("ADMAIF4") 1808 TEGRA_FE_ROUTES("ADMAIF5") 1809 TEGRA_FE_ROUTES("ADMAIF6") 1810 TEGRA_FE_ROUTES("ADMAIF7") 1811 TEGRA_FE_ROUTES("ADMAIF8") 1812 TEGRA_FE_ROUTES("ADMAIF9") 1813 TEGRA_FE_ROUTES("ADMAIF10") 1814 TEGRA_FE_ROUTES("ADMAIF11") 1815 TEGRA_FE_ROUTES("ADMAIF12") 1816 TEGRA_FE_ROUTES("ADMAIF13") 1817 TEGRA_FE_ROUTES("ADMAIF14") 1818 TEGRA_FE_ROUTES("ADMAIF15") 1819 TEGRA_FE_ROUTES("ADMAIF16") 1820 TEGRA_FE_ROUTES("ADMAIF17") 1821 TEGRA_FE_ROUTES("ADMAIF18") 1822 TEGRA_FE_ROUTES("ADMAIF19") 1823 TEGRA_FE_ROUTES("ADMAIF20") 1824 TEGRA186_MUX_ROUTES("ADMAIF1") 1825 TEGRA186_MUX_ROUTES("ADMAIF2") 1826 TEGRA186_MUX_ROUTES("ADMAIF3") 1827 TEGRA186_MUX_ROUTES("ADMAIF4") 1828 TEGRA186_MUX_ROUTES("ADMAIF5") 1829 TEGRA186_MUX_ROUTES("ADMAIF6") 1830 TEGRA186_MUX_ROUTES("ADMAIF7") 1831 TEGRA186_MUX_ROUTES("ADMAIF8") 1832 TEGRA186_MUX_ROUTES("ADMAIF9") 1833 TEGRA186_MUX_ROUTES("ADMAIF10") 1834 TEGRA186_MUX_ROUTES("ADMAIF11") 1835 TEGRA186_MUX_ROUTES("ADMAIF12") 1836 TEGRA186_MUX_ROUTES("ADMAIF13") 1837 TEGRA186_MUX_ROUTES("ADMAIF14") 1838 TEGRA186_MUX_ROUTES("ADMAIF15") 1839 TEGRA186_MUX_ROUTES("ADMAIF16") 1840 TEGRA186_MUX_ROUTES("ADMAIF17") 1841 TEGRA186_MUX_ROUTES("ADMAIF18") 1842 TEGRA186_MUX_ROUTES("ADMAIF19") 1843 TEGRA186_MUX_ROUTES("ADMAIF20") 1844 TEGRA186_MUX_ROUTES("I2S1") 1845 TEGRA186_MUX_ROUTES("I2S2") 1846 TEGRA186_MUX_ROUTES("I2S3") 1847 TEGRA186_MUX_ROUTES("I2S4") 1848 TEGRA186_MUX_ROUTES("I2S5") 1849 TEGRA186_MUX_ROUTES("I2S6") 1850 TEGRA186_MUX_ROUTES("DSPK1") 1851 TEGRA186_MUX_ROUTES("DSPK2") 1852 TEGRA186_MUX_ROUTES("SFC1") 1853 TEGRA186_MUX_ROUTES("SFC2") 1854 TEGRA186_MUX_ROUTES("SFC3") 1855 TEGRA186_MUX_ROUTES("SFC4") 1856 TEGRA186_MUX_ROUTES("MVC1") 1857 TEGRA186_MUX_ROUTES("MVC2") 1858 TEGRA186_MUX_ROUTES("AMX1 RX1") 1859 TEGRA186_MUX_ROUTES("AMX1 RX2") 1860 TEGRA186_MUX_ROUTES("AMX1 RX3") 1861 TEGRA186_MUX_ROUTES("AMX1 RX4") 1862 TEGRA186_MUX_ROUTES("AMX2 RX1") 1863 TEGRA186_MUX_ROUTES("AMX2 RX2") 1864 TEGRA186_MUX_ROUTES("AMX2 RX3") 1865 TEGRA186_MUX_ROUTES("AMX2 RX4") 1866 TEGRA186_MUX_ROUTES("AMX3 RX1") 1867 TEGRA186_MUX_ROUTES("AMX3 RX2") 1868 TEGRA186_MUX_ROUTES("AMX3 RX3") 1869 TEGRA186_MUX_ROUTES("AMX3 RX4") 1870 TEGRA186_MUX_ROUTES("AMX4 RX1") 1871 TEGRA186_MUX_ROUTES("AMX4 RX2") 1872 TEGRA186_MUX_ROUTES("AMX4 RX3") 1873 TEGRA186_MUX_ROUTES("AMX4 RX4") 1874 TEGRA186_MUX_ROUTES("ADX1") 1875 TEGRA186_MUX_ROUTES("ADX2") 1876 TEGRA186_MUX_ROUTES("ADX3") 1877 TEGRA186_MUX_ROUTES("ADX4") 1878 TEGRA186_MUX_ROUTES("MIXER1 RX1") 1879 TEGRA186_MUX_ROUTES("MIXER1 RX2") 1880 TEGRA186_MUX_ROUTES("MIXER1 RX3") 1881 TEGRA186_MUX_ROUTES("MIXER1 RX4") 1882 TEGRA186_MUX_ROUTES("MIXER1 RX5") 1883 TEGRA186_MUX_ROUTES("MIXER1 RX6") 1884 TEGRA186_MUX_ROUTES("MIXER1 RX7") 1885 TEGRA186_MUX_ROUTES("MIXER1 RX8") 1886 TEGRA186_MUX_ROUTES("MIXER1 RX9") 1887 TEGRA186_MUX_ROUTES("MIXER1 RX10") 1888 TEGRA186_MUX_ROUTES("ASRC1 RX1") 1889 TEGRA186_MUX_ROUTES("ASRC1 RX2") 1890 TEGRA186_MUX_ROUTES("ASRC1 RX3") 1891 TEGRA186_MUX_ROUTES("ASRC1 RX4") 1892 TEGRA186_MUX_ROUTES("ASRC1 RX5") 1893 TEGRA186_MUX_ROUTES("ASRC1 RX6") 1894 TEGRA186_MUX_ROUTES("ASRC1 RX7") 1895 TEGRA186_MUX_ROUTES("OPE1") 1896 }; 1897 1898 static const struct snd_soc_dapm_route tegra264_ahub_routes[] = { 1899 TEGRA_FE_ROUTES("ADMAIF1") 1900 TEGRA_FE_ROUTES("ADMAIF2") 1901 TEGRA_FE_ROUTES("ADMAIF3") 1902 TEGRA_FE_ROUTES("ADMAIF4") 1903 TEGRA_FE_ROUTES("ADMAIF5") 1904 TEGRA_FE_ROUTES("ADMAIF6") 1905 TEGRA_FE_ROUTES("ADMAIF7") 1906 TEGRA_FE_ROUTES("ADMAIF8") 1907 TEGRA_FE_ROUTES("ADMAIF9") 1908 TEGRA_FE_ROUTES("ADMAIF10") 1909 TEGRA_FE_ROUTES("ADMAIF11") 1910 TEGRA_FE_ROUTES("ADMAIF12") 1911 TEGRA_FE_ROUTES("ADMAIF13") 1912 TEGRA_FE_ROUTES("ADMAIF14") 1913 TEGRA_FE_ROUTES("ADMAIF15") 1914 TEGRA_FE_ROUTES("ADMAIF16") 1915 TEGRA_FE_ROUTES("ADMAIF17") 1916 TEGRA_FE_ROUTES("ADMAIF18") 1917 TEGRA_FE_ROUTES("ADMAIF19") 1918 TEGRA_FE_ROUTES("ADMAIF20") 1919 TEGRA_FE_ROUTES("ADMAIF21") 1920 TEGRA_FE_ROUTES("ADMAIF22") 1921 TEGRA_FE_ROUTES("ADMAIF23") 1922 TEGRA_FE_ROUTES("ADMAIF24") 1923 TEGRA_FE_ROUTES("ADMAIF25") 1924 TEGRA_FE_ROUTES("ADMAIF26") 1925 TEGRA_FE_ROUTES("ADMAIF27") 1926 TEGRA_FE_ROUTES("ADMAIF28") 1927 TEGRA_FE_ROUTES("ADMAIF29") 1928 TEGRA_FE_ROUTES("ADMAIF30") 1929 TEGRA_FE_ROUTES("ADMAIF31") 1930 TEGRA_FE_ROUTES("ADMAIF32") 1931 TEGRA264_MUX_ROUTES("ADMAIF1") 1932 TEGRA264_MUX_ROUTES("ADMAIF2") 1933 TEGRA264_MUX_ROUTES("ADMAIF3") 1934 TEGRA264_MUX_ROUTES("ADMAIF4") 1935 TEGRA264_MUX_ROUTES("ADMAIF5") 1936 TEGRA264_MUX_ROUTES("ADMAIF6") 1937 TEGRA264_MUX_ROUTES("ADMAIF7") 1938 TEGRA264_MUX_ROUTES("ADMAIF8") 1939 TEGRA264_MUX_ROUTES("ADMAIF9") 1940 TEGRA264_MUX_ROUTES("ADMAIF10") 1941 TEGRA264_MUX_ROUTES("ADMAIF11") 1942 TEGRA264_MUX_ROUTES("ADMAIF12") 1943 TEGRA264_MUX_ROUTES("ADMAIF13") 1944 TEGRA264_MUX_ROUTES("ADMAIF14") 1945 TEGRA264_MUX_ROUTES("ADMAIF15") 1946 TEGRA264_MUX_ROUTES("ADMAIF16") 1947 TEGRA264_MUX_ROUTES("ADMAIF17") 1948 TEGRA264_MUX_ROUTES("ADMAIF18") 1949 TEGRA264_MUX_ROUTES("ADMAIF19") 1950 TEGRA264_MUX_ROUTES("ADMAIF20") 1951 TEGRA264_MUX_ROUTES("ADMAIF21") 1952 TEGRA264_MUX_ROUTES("ADMAIF22") 1953 TEGRA264_MUX_ROUTES("ADMAIF23") 1954 TEGRA264_MUX_ROUTES("ADMAIF24") 1955 TEGRA264_MUX_ROUTES("ADMAIF25") 1956 TEGRA264_MUX_ROUTES("ADMAIF26") 1957 TEGRA264_MUX_ROUTES("ADMAIF27") 1958 TEGRA264_MUX_ROUTES("ADMAIF28") 1959 TEGRA264_MUX_ROUTES("ADMAIF29") 1960 TEGRA264_MUX_ROUTES("ADMAIF30") 1961 TEGRA264_MUX_ROUTES("ADMAIF31") 1962 TEGRA264_MUX_ROUTES("ADMAIF32") 1963 TEGRA264_MUX_ROUTES("I2S1") 1964 TEGRA264_MUX_ROUTES("I2S2") 1965 TEGRA264_MUX_ROUTES("I2S3") 1966 TEGRA264_MUX_ROUTES("I2S4") 1967 TEGRA264_MUX_ROUTES("I2S5") 1968 TEGRA264_MUX_ROUTES("I2S6") 1969 TEGRA264_MUX_ROUTES("I2S7") 1970 TEGRA264_MUX_ROUTES("I2S8") 1971 TEGRA264_MUX_ROUTES("DSPK1") 1972 TEGRA264_MUX_ROUTES("SFC1") 1973 TEGRA264_MUX_ROUTES("SFC2") 1974 TEGRA264_MUX_ROUTES("SFC3") 1975 TEGRA264_MUX_ROUTES("SFC4") 1976 TEGRA264_MUX_ROUTES("MVC1") 1977 TEGRA264_MUX_ROUTES("MVC2") 1978 TEGRA264_MUX_ROUTES("AMX1 RX1") 1979 TEGRA264_MUX_ROUTES("AMX1 RX2") 1980 TEGRA264_MUX_ROUTES("AMX1 RX3") 1981 TEGRA264_MUX_ROUTES("AMX1 RX4") 1982 TEGRA264_MUX_ROUTES("AMX2 RX1") 1983 TEGRA264_MUX_ROUTES("AMX2 RX2") 1984 TEGRA264_MUX_ROUTES("AMX2 RX3") 1985 TEGRA264_MUX_ROUTES("AMX2 RX4") 1986 TEGRA264_MUX_ROUTES("AMX3 RX1") 1987 TEGRA264_MUX_ROUTES("AMX3 RX2") 1988 TEGRA264_MUX_ROUTES("AMX3 RX3") 1989 TEGRA264_MUX_ROUTES("AMX3 RX4") 1990 TEGRA264_MUX_ROUTES("AMX4 RX1") 1991 TEGRA264_MUX_ROUTES("AMX4 RX2") 1992 TEGRA264_MUX_ROUTES("AMX4 RX3") 1993 TEGRA264_MUX_ROUTES("AMX4 RX4") 1994 TEGRA264_MUX_ROUTES("AMX5 RX1") 1995 TEGRA264_MUX_ROUTES("AMX5 RX2") 1996 TEGRA264_MUX_ROUTES("AMX5 RX3") 1997 TEGRA264_MUX_ROUTES("AMX5 RX4") 1998 TEGRA264_MUX_ROUTES("AMX6 RX1") 1999 TEGRA264_MUX_ROUTES("AMX6 RX2") 2000 TEGRA264_MUX_ROUTES("AMX6 RX3") 2001 TEGRA264_MUX_ROUTES("AMX6 RX4") 2002 TEGRA264_MUX_ROUTES("ADX1") 2003 TEGRA264_MUX_ROUTES("ADX2") 2004 TEGRA264_MUX_ROUTES("ADX3") 2005 TEGRA264_MUX_ROUTES("ADX4") 2006 TEGRA264_MUX_ROUTES("ADX5") 2007 TEGRA264_MUX_ROUTES("ADX6") 2008 TEGRA264_MUX_ROUTES("MIXER1 RX1") 2009 TEGRA264_MUX_ROUTES("MIXER1 RX2") 2010 TEGRA264_MUX_ROUTES("MIXER1 RX3") 2011 TEGRA264_MUX_ROUTES("MIXER1 RX4") 2012 TEGRA264_MUX_ROUTES("MIXER1 RX5") 2013 TEGRA264_MUX_ROUTES("MIXER1 RX6") 2014 TEGRA264_MUX_ROUTES("MIXER1 RX7") 2015 TEGRA264_MUX_ROUTES("MIXER1 RX8") 2016 TEGRA264_MUX_ROUTES("MIXER1 RX9") 2017 TEGRA264_MUX_ROUTES("MIXER1 RX10") 2018 TEGRA264_MUX_ROUTES("ASRC1 RX1") 2019 TEGRA264_MUX_ROUTES("ASRC1 RX2") 2020 TEGRA264_MUX_ROUTES("ASRC1 RX3") 2021 TEGRA264_MUX_ROUTES("ASRC1 RX4") 2022 TEGRA264_MUX_ROUTES("ASRC1 RX5") 2023 TEGRA264_MUX_ROUTES("ASRC1 RX6") 2024 TEGRA264_MUX_ROUTES("ASRC1 RX7") 2025 TEGRA264_MUX_ROUTES("OPE1") 2026 }; 2027 2028 static const struct snd_soc_component_driver tegra210_ahub_component = { 2029 .dapm_widgets = tegra210_ahub_widgets, 2030 .num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets), 2031 .dapm_routes = tegra210_ahub_routes, 2032 .num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes), 2033 }; 2034 2035 static const struct snd_soc_component_driver tegra186_ahub_component = { 2036 .dapm_widgets = tegra186_ahub_widgets, 2037 .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets), 2038 .dapm_routes = tegra186_ahub_routes, 2039 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 2040 }; 2041 2042 static const struct snd_soc_component_driver tegra234_ahub_component = { 2043 .dapm_widgets = tegra234_ahub_widgets, 2044 .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets), 2045 .dapm_routes = tegra186_ahub_routes, 2046 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 2047 }; 2048 2049 static const struct snd_soc_component_driver tegra264_ahub_component = { 2050 .dapm_widgets = tegra264_ahub_widgets, 2051 .num_dapm_widgets = ARRAY_SIZE(tegra264_ahub_widgets), 2052 .dapm_routes = tegra264_ahub_routes, 2053 .num_dapm_routes = ARRAY_SIZE(tegra264_ahub_routes), 2054 }; 2055 2056 static bool tegra210_ahub_wr_reg(struct device *dev, unsigned int reg) 2057 { 2058 int part; 2059 2060 if (reg % TEGRA210_XBAR_RX_STRIDE) 2061 return false; 2062 2063 for (part = 0; part < TEGRA210_XBAR_UPDATE_MAX_REG; part++) { 2064 switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { 2065 case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0: 2066 case TEGRA210_AXBAR_PART_0_I2S1_RX1_0 ... TEGRA210_AXBAR_PART_0_I2S5_RX1_0: 2067 case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0: 2068 case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0: 2069 case TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 ... TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0: 2070 case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0: 2071 case TEGRA210_AXBAR_PART_0_OPE1_RX1_0 ... TEGRA210_AXBAR_PART_0_OPE2_RX1_0: 2072 case TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0: 2073 case TEGRA210_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA210_AXBAR_PART_0_MVC2_RX1_0: 2074 case TEGRA210_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA210_AXBAR_PART_0_ADX2_RX1_0: 2075 return true; 2076 default: 2077 break; 2078 } 2079 } 2080 2081 return false; 2082 } 2083 2084 static bool tegra186_ahub_wr_reg(struct device *dev, unsigned int reg) 2085 { 2086 int part; 2087 2088 if (reg % TEGRA210_XBAR_RX_STRIDE) 2089 return false; 2090 2091 for (part = 0; part < TEGRA186_XBAR_UPDATE_MAX_REG; part++) { 2092 switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { 2093 case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA186_AXBAR_PART_0_I2S6_RX1_0: 2094 case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0: 2095 case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0: 2096 case TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 ... TEGRA186_AXBAR_PART_0_DSPK2_RX1_0: 2097 case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0: 2098 case TEGRA210_AXBAR_PART_0_OPE1_RX1_0: 2099 case TEGRA186_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA186_AXBAR_PART_0_MVC2_RX1_0: 2100 case TEGRA186_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA186_AXBAR_PART_0_AMX3_RX4_0: 2101 case TEGRA210_AXBAR_PART_0_ADX1_RX1_0 ... TEGRA186_AXBAR_PART_0_ASRC1_RX7_0: 2102 return true; 2103 default: 2104 break; 2105 } 2106 } 2107 2108 return false; 2109 } 2110 2111 static bool tegra264_ahub_wr_reg(struct device *dev, unsigned int reg) 2112 { 2113 int part; 2114 2115 for (part = 0; part < TEGRA264_XBAR_UPDATE_MAX_REG; part++) { 2116 switch (reg & ~(part << 12)) { 2117 case TEGRA264_AXBAR_ADMAIF_RX1 ... TEGRA264_AXBAR_SFC4_RX1: 2118 case TEGRA264_AXBAR_MIXER1_RX1 ... TEGRA264_AXBAR_MIXER1_RX10: 2119 case TEGRA264_AXBAR_DSPK1_RX1: 2120 case TEGRA264_AXBAR_OPE1_RX1: 2121 case TEGRA264_AXBAR_MVC1_RX1 ... TEGRA264_AXBAR_MVC2_RX1: 2122 case TEGRA264_AXBAR_AMX1_RX1 ... TEGRA264_AXBAR_AMX3_RX4: 2123 case TEGRA264_AXBAR_ADX1_RX1 ... TEGRA264_AXBAR_ASRC1_RX7: 2124 case TEGRA264_AXBAR_ADMAIF_RX21 ... TEGRA264_AXBAR_ADX6_RX1: 2125 return true; 2126 default: 2127 break; 2128 } 2129 } 2130 2131 return false; 2132 } 2133 2134 static const struct regmap_config tegra210_ahub_regmap_config = { 2135 .reg_bits = 32, 2136 .val_bits = 32, 2137 .reg_stride = 4, 2138 .writeable_reg = tegra210_ahub_wr_reg, 2139 .max_register = TEGRA210_MAX_REGISTER_ADDR, 2140 .reg_default_cb = regmap_default_zero_cb, 2141 .cache_type = REGCACHE_FLAT, 2142 }; 2143 2144 static const struct regmap_config tegra186_ahub_regmap_config = { 2145 .reg_bits = 32, 2146 .val_bits = 32, 2147 .reg_stride = 4, 2148 .writeable_reg = tegra186_ahub_wr_reg, 2149 .max_register = TEGRA186_MAX_REGISTER_ADDR, 2150 .reg_default_cb = regmap_default_zero_cb, 2151 .cache_type = REGCACHE_FLAT, 2152 }; 2153 2154 static const struct regmap_config tegra264_ahub_regmap_config = { 2155 .reg_bits = 32, 2156 .val_bits = 32, 2157 .reg_stride = 4, 2158 .writeable_reg = tegra264_ahub_wr_reg, 2159 .max_register = TEGRA264_MAX_REGISTER_ADDR, 2160 .reg_default_cb = regmap_default_zero_cb, 2161 .cache_type = REGCACHE_FLAT, 2162 }; 2163 2164 static const struct tegra_ahub_soc_data soc_data_tegra210 = { 2165 .cmpnt_drv = &tegra210_ahub_component, 2166 .dai_drv = tegra210_ahub_dais, 2167 .num_dais = ARRAY_SIZE(tegra210_ahub_dais), 2168 .regmap_config = &tegra210_ahub_regmap_config, 2169 .mask[0] = TEGRA210_XBAR_REG_MASK_0, 2170 .mask[1] = TEGRA210_XBAR_REG_MASK_1, 2171 .mask[2] = TEGRA210_XBAR_REG_MASK_2, 2172 .mask[3] = TEGRA210_XBAR_REG_MASK_3, 2173 .reg_count = TEGRA210_XBAR_UPDATE_MAX_REG, 2174 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2175 }; 2176 2177 static const struct tegra_ahub_soc_data soc_data_tegra186 = { 2178 .cmpnt_drv = &tegra186_ahub_component, 2179 .dai_drv = tegra186_ahub_dais, 2180 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 2181 .regmap_config = &tegra186_ahub_regmap_config, 2182 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 2183 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 2184 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 2185 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 2186 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 2187 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2188 }; 2189 2190 static const struct tegra_ahub_soc_data soc_data_tegra234 = { 2191 .cmpnt_drv = &tegra234_ahub_component, 2192 .dai_drv = tegra186_ahub_dais, 2193 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 2194 .regmap_config = &tegra186_ahub_regmap_config, 2195 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 2196 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 2197 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 2198 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 2199 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 2200 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2201 }; 2202 2203 static const struct tegra_ahub_soc_data soc_data_tegra264 = { 2204 .cmpnt_drv = &tegra264_ahub_component, 2205 .dai_drv = tegra264_ahub_dais, 2206 .num_dais = ARRAY_SIZE(tegra264_ahub_dais), 2207 .regmap_config = &tegra264_ahub_regmap_config, 2208 .mask[0] = TEGRA264_XBAR_REG_MASK_0, 2209 .mask[1] = TEGRA264_XBAR_REG_MASK_1, 2210 .mask[2] = TEGRA264_XBAR_REG_MASK_2, 2211 .mask[3] = TEGRA264_XBAR_REG_MASK_3, 2212 .mask[4] = TEGRA264_XBAR_REG_MASK_4, 2213 .reg_count = TEGRA264_XBAR_UPDATE_MAX_REG, 2214 .xbar_part_size = TEGRA264_XBAR_PART1_RX, 2215 }; 2216 2217 static const struct of_device_id tegra_ahub_of_match[] = { 2218 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 }, 2219 { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 }, 2220 { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 }, 2221 { .compatible = "nvidia,tegra264-ahub", .data = &soc_data_tegra264 }, 2222 {}, 2223 }; 2224 MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); 2225 2226 static int tegra_ahub_runtime_suspend(struct device *dev) 2227 { 2228 struct tegra_ahub *ahub = dev_get_drvdata(dev); 2229 2230 regcache_cache_only(ahub->regmap, true); 2231 regcache_mark_dirty(ahub->regmap); 2232 2233 clk_disable_unprepare(ahub->clk); 2234 2235 return 0; 2236 } 2237 2238 static int tegra_ahub_runtime_resume(struct device *dev) 2239 { 2240 struct tegra_ahub *ahub = dev_get_drvdata(dev); 2241 int err; 2242 2243 err = clk_prepare_enable(ahub->clk); 2244 if (err) { 2245 dev_err(dev, "failed to enable AHUB clock, err: %d\n", err); 2246 return err; 2247 } 2248 2249 regcache_cache_only(ahub->regmap, false); 2250 regcache_sync(ahub->regmap); 2251 2252 return 0; 2253 } 2254 2255 static int tegra_ahub_probe(struct platform_device *pdev) 2256 { 2257 struct tegra_ahub *ahub; 2258 void __iomem *regs; 2259 int err; 2260 2261 ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL); 2262 if (!ahub) 2263 return -ENOMEM; 2264 2265 ahub->soc_data = of_device_get_match_data(&pdev->dev); 2266 if (!ahub->soc_data) 2267 return -ENODEV; 2268 2269 platform_set_drvdata(pdev, ahub); 2270 2271 ahub->clk = devm_clk_get(&pdev->dev, "ahub"); 2272 if (IS_ERR(ahub->clk)) 2273 return dev_err_probe(&pdev->dev, PTR_ERR(ahub->clk), 2274 "can't retrieve AHUB clock\n"); 2275 2276 regs = devm_platform_ioremap_resource(pdev, 0); 2277 if (IS_ERR(regs)) 2278 return PTR_ERR(regs); 2279 2280 ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 2281 ahub->soc_data->regmap_config); 2282 if (IS_ERR(ahub->regmap)) 2283 return dev_err_probe(&pdev->dev, PTR_ERR(ahub->regmap), 2284 "regmap init failed\n"); 2285 2286 regcache_cache_only(ahub->regmap, true); 2287 2288 err = devm_snd_soc_register_component(&pdev->dev, 2289 ahub->soc_data->cmpnt_drv, 2290 ahub->soc_data->dai_drv, 2291 ahub->soc_data->num_dais); 2292 if (err) 2293 return dev_err_probe(&pdev->dev, err, 2294 "can't register AHUB component\n"); 2295 2296 pm_runtime_enable(&pdev->dev); 2297 2298 err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 2299 if (err) { 2300 pm_runtime_disable(&pdev->dev); 2301 return dev_err_probe(&pdev->dev, err, 2302 "failed to populate child nodes\n"); 2303 } 2304 2305 return 0; 2306 } 2307 2308 static void tegra_ahub_remove(struct platform_device *pdev) 2309 { 2310 pm_runtime_disable(&pdev->dev); 2311 } 2312 2313 static const struct dev_pm_ops tegra_ahub_pm_ops = { 2314 RUNTIME_PM_OPS(tegra_ahub_runtime_suspend, 2315 tegra_ahub_runtime_resume, NULL) 2316 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 2317 }; 2318 2319 static struct platform_driver tegra_ahub_driver = { 2320 .probe = tegra_ahub_probe, 2321 .remove = tegra_ahub_remove, 2322 .driver = { 2323 .name = "tegra210-ahub", 2324 .of_match_table = tegra_ahub_of_match, 2325 .pm = pm_ptr(&tegra_ahub_pm_ops), 2326 }, 2327 }; 2328 module_platform_driver(tegra_ahub_driver); 2329 2330 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 2331 MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>"); 2332 MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver"); 2333 MODULE_LICENSE("GPL v2"); 2334