1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_INTERNAL_SHARED_TYPES_H__ 6 #define __DML2_INTERNAL_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_types.h" 10 #include "dml2_core_shared_types.h" 11 /* 12 * DML2 MCG Types and Interfaces 13 */ 14 15 #define DML_MCG_MAX_CLK_TABLE_SIZE 20 16 17 struct dram_bw_to_min_clk_table_entry { 18 unsigned long long pre_derate_dram_bw_kbps; 19 unsigned long min_fclk_khz; 20 unsigned long min_dcfclk_khz; 21 }; 22 23 struct dml2_mcg_dram_bw_to_min_clk_table { 24 struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE]; 25 26 unsigned int num_entries; 27 }; 28 29 struct dml2_mcg_min_clock_table { 30 struct { 31 unsigned int dispclk; 32 unsigned int dppclk; 33 unsigned int dscclk; 34 unsigned int dtbclk; 35 unsigned int phyclk; 36 unsigned int fclk; 37 unsigned int dcfclk; 38 } max_clocks_khz; 39 40 struct { 41 unsigned int dprefclk; 42 unsigned int xtalclk; 43 unsigned int pcierefclk; 44 unsigned int dchubrefclk; 45 unsigned int amclk; 46 } fixed_clocks_khz; 47 48 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; 49 }; 50 51 struct dml2_mcg_build_min_clock_table_params_in_out { 52 /* 53 * Input 54 */ 55 struct dml2_soc_bb *soc_bb; 56 struct { 57 bool perform_pseudo_build; 58 } clean_me_up; 59 60 /* 61 * Output 62 */ 63 struct dml2_mcg_min_clock_table *min_clk_table; 64 }; 65 struct dml2_mcg_instance { 66 bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); 67 bool (*unit_test)(void); 68 }; 69 70 /* 71 * DML2 DPMM Types and Interfaces 72 */ 73 74 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out { 75 /* 76 * Input 77 */ 78 struct dml2_core_ip_params *ip; 79 struct dml2_soc_bb *soc_bb; 80 struct dml2_mcg_min_clock_table *min_clk_table; 81 const struct display_configuation_with_meta *display_cfg; 82 struct { 83 bool perform_pseudo_map; 84 struct dml2_core_internal_soc_bb *soc_bb; 85 } clean_me_up; 86 87 /* 88 * Output 89 */ 90 struct dml2_display_cfg_programming *programming; 91 }; 92 93 struct dml2_dpmm_map_watermarks_params_in_out { 94 /* 95 * Input 96 */ 97 const struct display_configuation_with_meta *display_cfg; 98 const struct dml2_core_instance *core; 99 100 /* 101 * Output 102 */ 103 struct dml2_display_cfg_programming *programming; 104 }; 105 106 struct dml2_dpmm_scratch { 107 struct dml2_display_cfg_programming programming; 108 }; 109 110 struct dml2_dpmm_instance { 111 bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); 112 bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out); 113 bool (*unit_test)(void); 114 115 struct dml2_dpmm_scratch dpmm_scratch; 116 }; 117 118 /* 119 * DML2 Core Types and Interfaces 120 */ 121 122 struct dml2_core_initialize_in_out { 123 enum dml2_project_id project_id; 124 struct dml2_core_instance *instance; 125 struct dml2_soc_bb *soc_bb; 126 struct dml2_ip_capabilities *ip_caps; 127 128 struct dml2_mcg_min_clock_table *minimum_clock_table; 129 130 void *explicit_ip_bb; 131 unsigned int explicit_ip_bb_size; 132 133 // FIXME_STAGE2 can remove but dcn3 version still need this 134 struct { 135 struct soc_bounding_box_st *soc_bb; 136 struct soc_states_st *soc_states; 137 } legacy; 138 }; 139 140 struct core_bandwidth_requirements { 141 int urgent_bandwidth_kbytes_per_sec; 142 int average_bandwidth_kbytes_per_sec; 143 }; 144 145 struct core_plane_support_info { 146 int dpps_used; 147 int dram_change_latency_hiding_margin_in_active; 148 int active_latency_hiding_us; 149 int mall_svp_size_requirement_ways; 150 int nominal_vblank_pstate_latency_hiding_us; 151 unsigned int dram_change_vactive_det_fill_delay_us; 152 }; 153 154 struct core_stream_support_info { 155 unsigned int odms_used; 156 unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2) 157 158 /* FAMS2 SubVP support info */ 159 unsigned int phantom_min_v_active; 160 unsigned int phantom_v_startup; 161 162 unsigned int phantom_v_active; 163 unsigned int phantom_v_total; 164 int vblank_reserved_time_us; 165 int num_dsc_slices; 166 bool dsc_enable; 167 }; 168 169 struct core_display_cfg_support_info { 170 bool is_supported; 171 172 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES]; 173 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES]; 174 175 struct { 176 struct dml2_core_internal_mode_support_info support_info; 177 } clean_me_up; 178 }; 179 180 struct dml2_core_mode_support_result { 181 struct { 182 struct { 183 unsigned long urgent_bw_sdp_kbps; 184 unsigned long average_bw_sdp_kbps; 185 unsigned long urgent_bw_dram_kbps; 186 unsigned long average_bw_dram_kbps; 187 unsigned long dcfclk_khz; 188 unsigned long fclk_khz; 189 } svp_prefetch; 190 191 struct { 192 unsigned long urgent_bw_sdp_kbps; 193 unsigned long average_bw_sdp_kbps; 194 unsigned long urgent_bw_dram_kbps; 195 unsigned long average_bw_dram_kbps; 196 unsigned long dcfclk_khz; 197 unsigned long fclk_khz; 198 } active; 199 200 unsigned int dispclk_khz; 201 unsigned int dcfclk_deepsleep_khz; 202 unsigned int socclk_khz; 203 204 unsigned int uclk_pstate_supported; 205 unsigned int fclk_pstate_supported; 206 } global; 207 208 struct { 209 unsigned int dscclk_khz; 210 unsigned int dtbclk_khz; 211 unsigned int phyclk_khz; 212 } per_stream[DML2_MAX_PLANES]; 213 214 struct { 215 unsigned int dppclk_khz; 216 unsigned int mall_svp_allocation_mblks; 217 unsigned int mall_full_frame_allocation_mblks; 218 } per_plane[DML2_MAX_PLANES]; 219 220 struct core_display_cfg_support_info cfg_support_info; 221 }; 222 223 struct dml2_optimization_stage1_state { 224 bool performed; 225 bool success; 226 227 int min_clk_index_for_latency; 228 }; 229 230 struct dml2_optimization_stage2_state { 231 bool performed; 232 bool success; 233 234 // Whether or not each plane supports mcache 235 // The number of valid elements == display_cfg.num_planes 236 // The indexing of pstate_switch_modes matches plane_descriptors[] 237 bool per_plane_mcache_support[DML2_MAX_PLANES]; 238 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 239 }; 240 241 #define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8 242 #define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10 243 #define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3 244 245 struct dml2_implicit_svp_meta { 246 bool valid; 247 unsigned long v_active; 248 unsigned long v_total; 249 unsigned long v_front_porch; 250 }; 251 252 struct dml2_fams2_per_method_common_meta { 253 /* generic params */ 254 unsigned int allow_start_otg_vline; 255 unsigned int allow_end_otg_vline; 256 /* scheduling params */ 257 double allow_time_us; 258 double disallow_time_us; 259 double period_us; 260 }; 261 262 struct dml2_fams2_meta { 263 bool valid; 264 double otg_vline_time_us; 265 unsigned int scheduling_delay_otg_vlines; 266 unsigned int vertical_interrupt_ack_delay_otg_vlines; 267 unsigned int allow_to_target_delay_otg_vlines; 268 unsigned int contention_delay_otg_vlines; 269 unsigned int min_allow_width_otg_vlines; 270 unsigned int nom_vtotal; 271 unsigned int vblank_start; 272 double nom_refresh_rate_hz; 273 double nom_frame_time_us; 274 unsigned int max_vtotal; 275 double min_refresh_rate_hz; 276 double max_frame_time_us; 277 unsigned int dram_clk_change_blackout_otg_vlines; 278 struct { 279 double max_vactive_det_fill_delay_us; 280 unsigned int max_vactive_det_fill_delay_otg_vlines; 281 struct dml2_fams2_per_method_common_meta common; 282 } method_vactive; 283 struct { 284 struct dml2_fams2_per_method_common_meta common; 285 } method_vblank; 286 struct { 287 unsigned int programming_delay_otg_vlines; 288 unsigned int df_throttle_delay_otg_vlines; 289 unsigned int prefetch_to_mall_delay_otg_vlines; 290 unsigned long phantom_vactive; 291 unsigned long phantom_vfp; 292 unsigned long phantom_vtotal; 293 struct dml2_fams2_per_method_common_meta common; 294 } method_subvp; 295 struct { 296 unsigned int programming_delay_otg_vlines; 297 unsigned int stretched_vtotal; 298 struct dml2_fams2_per_method_common_meta common; 299 } method_drr; 300 }; 301 302 struct dml2_optimization_stage3_state { 303 bool performed; 304 bool success; 305 306 // The pstate support mode for each plane 307 // The number of valid elements == display_cfg.num_planes 308 // The indexing of pstate_switch_modes matches plane_descriptors[] 309 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 310 311 // Meta-data for implicit SVP generation, indexed by stream index 312 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 313 314 // Meta-data for FAMS2 315 bool fams2_required; 316 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 317 318 int min_clk_index_for_latency; 319 }; 320 321 struct dml2_optimization_stage4_state { 322 bool performed; 323 bool success; 324 bool unoptimizable_streams[DML2_MAX_DCN_PIPES]; 325 }; 326 327 struct dml2_optimization_stage5_state { 328 bool performed; 329 bool success; 330 331 bool optimal_reserved_time_in_vblank_us; 332 bool vblank_includes_z8_optimization; 333 }; 334 335 struct display_configuation_with_meta { 336 struct dml2_display_cfg display_config; 337 338 struct dml2_core_mode_support_result mode_support_result; 339 340 // Stage 1 = Min Clocks for Latency 341 struct dml2_optimization_stage1_state stage1; 342 343 // Stage 2 = MCache 344 struct dml2_optimization_stage2_state stage2; 345 346 // Stage 3 = UCLK PState 347 struct dml2_optimization_stage3_state stage3; 348 349 // Stage 4 = Vmin 350 struct dml2_optimization_stage4_state stage4; 351 352 // Stage 5 = Stutter 353 struct dml2_optimization_stage5_state stage5; 354 }; 355 356 struct dml2_pmo_pstate_strategy { 357 enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES]; 358 bool allow_state_increase; 359 }; 360 struct dml2_core_mode_support_in_out { 361 /* 362 * Inputs 363 */ 364 struct dml2_core_instance *instance; 365 const struct display_configuation_with_meta *display_cfg; 366 367 struct dml2_mcg_min_clock_table *min_clk_table; 368 int min_clk_index; 369 /* 370 * Outputs 371 */ 372 struct dml2_core_mode_support_result mode_support_result; 373 374 struct { 375 // Inputs 376 struct dml_display_cfg_st *display_cfg; 377 378 // Outputs 379 struct dml_mode_support_info_st *support_info; 380 unsigned int out_lowest_state_idx; 381 unsigned int min_fclk_khz; 382 unsigned int min_dcfclk_khz; 383 unsigned int min_dram_speed_mts; 384 unsigned int min_socclk_khz; 385 unsigned int min_dscclk_khz; 386 unsigned int min_dtbclk_khz; 387 unsigned int min_phyclk_khz; 388 } legacy; 389 }; 390 391 struct dml2_core_mode_programming_in_out { 392 /* 393 * Inputs 394 */ 395 struct dml2_core_instance *instance; 396 const struct display_configuation_with_meta *display_cfg; 397 const struct core_display_cfg_support_info *cfg_support_info; 398 /* 399 * Outputs (also Input the clk freq are also from programming struct) 400 */ 401 struct dml2_display_cfg_programming *programming; 402 403 }; 404 405 struct dml2_core_populate_informative_in_out { 406 /* 407 * Inputs 408 */ 409 struct dml2_core_instance *instance; 410 411 // If this is set, then the mode was supported, and mode programming 412 // was successfully run. 413 // Otherwise, mode programming was not run, because mode support failed. 414 bool mode_is_supported; 415 416 /* 417 * Outputs 418 */ 419 struct dml2_display_cfg_programming *programming; 420 }; 421 422 struct dml2_calculate_mcache_allocation_in_out { 423 /* 424 * Inputs 425 */ 426 struct dml2_core_instance *instance; 427 const struct dml2_plane_parameters *plane_descriptor; 428 unsigned int plane_index; 429 430 /* 431 * Outputs 432 */ 433 struct dml2_mcache_surface_allocation *mcache_allocation; 434 }; 435 436 struct dml2_core_internal_state_inputs { 437 unsigned int dummy; 438 }; 439 440 struct dml2_core_internal_state_intermediates { 441 unsigned int dummy; 442 }; 443 444 struct dml2_core_mode_support_locals { 445 struct dml2_core_calcs_mode_support_ex mode_support_ex_params; 446 struct dml2_display_cfg svp_expanded_display_cfg; 447 struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params; 448 }; 449 450 struct dml2_core_mode_programming_locals { 451 struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; 452 struct dml2_display_cfg svp_expanded_display_cfg; 453 }; 454 455 struct dml2_core_scratch { 456 struct dml2_core_mode_support_locals mode_support_locals; 457 struct dml2_core_mode_programming_locals mode_programming_locals; 458 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES]; 459 int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES]; 460 int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES]; 461 int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES]; 462 }; 463 464 struct dml2_core_instance { 465 struct dml2_mcg_min_clock_table *minimum_clock_table; 466 struct dml2_core_internal_state_inputs inputs; 467 struct dml2_core_internal_state_intermediates intermediates; 468 469 struct dml2_core_scratch scratch; 470 471 bool (*initialize)(struct dml2_core_initialize_in_out *in_out); 472 bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out); 473 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); 474 bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); 475 bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); 476 bool (*unit_test)(void); 477 478 struct { 479 struct dml2_core_internal_display_mode_lib mode_lib; 480 } clean_me_up; 481 }; 482 483 /* 484 * DML2 PMO Types and Interfaces 485 */ 486 487 struct dml2_pmo_initialize_in_out { 488 /* 489 * Input 490 */ 491 struct dml2_pmo_instance *instance; 492 struct dml2_soc_bb *soc_bb; 493 struct dml2_ip_capabilities *ip_caps; 494 struct dml2_pmo_options *options; 495 int mcg_clock_table_size; 496 }; 497 498 struct dml2_pmo_optimize_dcc_mcache_in_out { 499 /* 500 * Input 501 */ 502 struct dml2_pmo_instance *instance; 503 const struct dml2_display_cfg *display_config; 504 bool *dcc_mcache_supported; 505 struct core_display_cfg_support_info *cfg_support_info; 506 507 /* 508 * Output 509 */ 510 struct dml2_display_cfg *optimized_display_cfg; 511 }; 512 513 struct dml2_pmo_init_for_vmin_in_out { 514 /* 515 * Input 516 */ 517 struct dml2_pmo_instance *instance; 518 struct display_configuation_with_meta *base_display_config; 519 }; 520 521 struct dml2_pmo_test_for_vmin_in_out { 522 /* 523 * Input 524 */ 525 struct dml2_pmo_instance *instance; 526 const struct display_configuation_with_meta *display_config; 527 const struct dml2_soc_vmin_clock_limits *vmin_limits; 528 }; 529 530 struct dml2_pmo_optimize_for_vmin_in_out { 531 /* 532 * Input 533 */ 534 struct dml2_pmo_instance *instance; 535 struct display_configuation_with_meta *base_display_config; 536 537 /* 538 * Output 539 */ 540 struct display_configuation_with_meta *optimized_display_config; 541 }; 542 543 struct dml2_pmo_init_for_pstate_support_in_out { 544 /* 545 * Input 546 */ 547 struct dml2_pmo_instance *instance; 548 struct display_configuation_with_meta *base_display_config; 549 }; 550 551 struct dml2_pmo_test_for_pstate_support_in_out { 552 /* 553 * Input 554 */ 555 struct dml2_pmo_instance *instance; 556 struct display_configuation_with_meta *base_display_config; 557 }; 558 559 struct dml2_pmo_optimize_for_pstate_support_in_out { 560 /* 561 * Input 562 */ 563 struct dml2_pmo_instance *instance; 564 struct display_configuation_with_meta *base_display_config; 565 bool last_candidate_failed; 566 567 /* 568 * Output 569 */ 570 struct display_configuation_with_meta *optimized_display_config; 571 }; 572 573 struct dml2_pmo_init_for_stutter_in_out { 574 /* 575 * Input 576 */ 577 struct dml2_pmo_instance *instance; 578 struct display_configuation_with_meta *base_display_config; 579 }; 580 581 struct dml2_pmo_test_for_stutter_in_out { 582 /* 583 * Input 584 */ 585 struct dml2_pmo_instance *instance; 586 struct display_configuation_with_meta *base_display_config; 587 }; 588 589 struct dml2_pmo_optimize_for_stutter_in_out { 590 /* 591 * Input 592 */ 593 struct dml2_pmo_instance *instance; 594 struct display_configuation_with_meta *base_display_config; 595 bool last_candidate_failed; 596 597 /* 598 * Output 599 */ 600 struct display_configuation_with_meta *optimized_display_config; 601 }; 602 603 #define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) << dml2_pstate_method_na) 604 #define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 605 #define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 606 #define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) << dml2_pstate_method_fw_drr) 607 #define PMO_FW_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) << dml2_pstate_method_fw_svp) 608 609 #define PMO_DCN4_MAX_DISPLAYS 4 610 #define PMO_DCN4_MAX_NUM_VARIANTS 2 611 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 612 613 struct dml2_pmo_scratch { 614 union { 615 struct { 616 double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS]; 617 int reserved_time_candidates_count[DML2_MAX_PLANES]; 618 int current_candidate[DML2_MAX_PLANES]; 619 int min_latency_index; 620 int max_latency_index; 621 int cur_latency_index; 622 int stream_mask; 623 } pmo_dcn3; 624 struct { 625 struct dml2_pmo_pstate_strategy expanded_override_strategy_list[2 * 2 * 2 * 2]; 626 unsigned int num_expanded_override_strategies; 627 struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE]; 628 int num_pstate_candidates; 629 int cur_pstate_candidate; 630 631 unsigned int stream_plane_mask[DML2_MAX_PLANES]; 632 633 unsigned int stream_vactive_capability_mask; 634 635 int min_latency_index; 636 int max_latency_index; 637 int cur_latency_index; 638 639 // Stores all the implicit SVP meta information indexed by stream index of the display 640 // configuration under inspection, built at optimization stage init 641 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 642 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 643 644 unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; 645 unsigned int num_stutter_candidates; 646 unsigned int cur_stutter_candidate; 647 bool z8_vblank_optimizable; 648 649 /* mask of synchronized timings by stream index */ 650 unsigned int num_timing_groups; 651 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 652 bool group_is_drr_enabled[DML2_MAX_PLANES]; 653 bool group_is_drr_active[DML2_MAX_PLANES]; 654 double group_line_time_us[DML2_MAX_PLANES]; 655 656 /* scheduling check locals */ 657 struct dml2_fams2_per_method_common_meta group_common_fams2_meta[DML2_MAX_PLANES]; 658 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 659 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 660 double group_phase_offset[DML2_MAX_PLANES]; 661 } pmo_dcn4; 662 }; 663 }; 664 665 struct dml2_pmo_init_data { 666 union { 667 struct { 668 /* populated once during initialization */ 669 struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2]; 670 struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4]; 671 struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6]; 672 struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8]; 673 unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS]; 674 } pmo_dcn4; 675 }; 676 }; 677 678 struct dml2_pmo_instance { 679 struct dml2_soc_bb *soc_bb; 680 struct dml2_ip_capabilities *ip_caps; 681 682 struct dml2_pmo_options *options; 683 684 int disp_clk_vmin_threshold; 685 int mpc_combine_limit; 686 int odm_combine_limit; 687 int mcg_clock_table_size; 688 union { 689 struct { 690 struct { 691 int prefetch_end_to_mall_start_us; 692 int fw_processing_delay_us; 693 int refresh_rate_limit_min; 694 int refresh_rate_limit_max; 695 } subvp; 696 } v1; 697 struct { 698 struct { 699 int refresh_rate_limit_min; 700 int refresh_rate_limit_max; 701 } subvp; 702 struct { 703 int refresh_rate_limit_min; 704 int refresh_rate_limit_max; 705 } drr; 706 } v2; 707 } fams_params; 708 709 bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out); 710 bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out); 711 712 bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out); 713 bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out); 714 bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out); 715 716 bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out); 717 bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out); 718 bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out); 719 720 bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out); 721 bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); 722 bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); 723 724 bool (*unit_test)(void); 725 726 struct dml2_pmo_init_data init_data; 727 struct dml2_pmo_scratch scratch; 728 }; 729 730 /* 731 * DML2 MCache Types 732 */ 733 734 struct top_mcache_validate_admissability_in_out { 735 struct dml2_instance *dml2_instance; 736 737 const struct dml2_display_cfg *display_cfg; 738 const struct core_display_cfg_support_info *cfg_support_info; 739 struct dml2_mcache_surface_allocation *mcache_allocations; 740 741 bool per_plane_status[DML2_MAX_PLANES]; 742 743 struct { 744 const struct dml_mode_support_info_st *mode_support_info; 745 } legacy; 746 }; 747 748 struct top_mcache_assign_ids_in_out { 749 /* 750 * Input 751 */ 752 const struct dml2_mcache_surface_allocation *mcache_allocations; 753 int plane_count; 754 755 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 756 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 757 int pipe_count_per_plane[DML2_MAX_PLANES]; 758 759 struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 760 761 /* 762 * Output 763 */ 764 struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 765 struct dml2_build_mcache_programming_in_out *mcache_programming; 766 }; 767 768 struct top_mcache_calc_mcache_count_and_offsets_in_out { 769 /* 770 * Inputs 771 */ 772 struct dml2_instance *dml2_instance; 773 const struct dml2_display_cfg *display_config; 774 775 /* 776 * Outputs 777 */ 778 struct dml2_mcache_surface_allocation *mcache_allocations; 779 }; 780 781 struct top_mcache_assign_global_mcache_ids_in_out { 782 /* 783 * Inputs/Outputs 784 */ 785 struct dml2_mcache_surface_allocation *allocations; 786 int num_allocations; 787 }; 788 789 /* 790 * DML2 Top Types 791 */ 792 793 struct dml2_initialize_instance_locals { 794 int dummy; 795 }; 796 797 struct dml2_optimization_init_function_locals { 798 union { 799 struct { 800 struct dml2_pmo_init_for_pstate_support_in_out init_params; 801 } uclk_pstate; 802 struct { 803 struct dml2_pmo_init_for_stutter_in_out stutter_params; 804 } stutter; 805 struct { 806 struct dml2_pmo_init_for_vmin_in_out init_params; 807 } vmin; 808 }; 809 }; 810 811 struct dml2_optimization_test_function_locals { 812 union { 813 struct { 814 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 815 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 816 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 817 } test_mcache; 818 struct { 819 struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params; 820 } test_vmin; 821 struct { 822 struct dml2_pmo_test_for_pstate_support_in_out test_params; 823 } uclk_pstate; 824 struct { 825 struct dml2_pmo_test_for_stutter_in_out stutter_params; 826 } stutter; 827 }; 828 }; 829 830 struct dml2_optimization_optimize_function_locals { 831 union { 832 struct { 833 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 834 } optimize_mcache; 835 struct { 836 struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params; 837 } optimize_vmin; 838 struct { 839 struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params; 840 } uclk_pstate; 841 struct { 842 struct dml2_pmo_optimize_for_stutter_in_out stutter_params; 843 } stutter; 844 }; 845 }; 846 847 struct dml2_optimization_phase_locals { 848 struct display_configuation_with_meta cur_candidate_display_cfg; 849 struct display_configuation_with_meta next_candidate_display_cfg; 850 struct dml2_core_mode_support_in_out mode_support_params; 851 struct dml2_optimization_init_function_locals init_function_locals; 852 struct dml2_optimization_test_function_locals test_function_locals; 853 struct dml2_optimization_optimize_function_locals optimize_function_locals; 854 }; 855 856 struct dml2_check_mode_supported_locals { 857 struct dml2_display_cfg display_cfg_working_copy; 858 struct dml2_core_mode_support_in_out mode_support_params; 859 struct dml2_optimization_phase_locals optimization_phase_locals; 860 struct display_configuation_with_meta base_display_config_with_meta; 861 struct display_configuation_with_meta optimized_display_config_with_meta; 862 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 863 }; 864 865 struct optimization_init_function_params { 866 struct dml2_optimization_init_function_locals *locals; 867 struct dml2_instance *dml; 868 struct display_configuation_with_meta *display_config; 869 }; 870 871 struct optimization_test_function_params { 872 struct dml2_optimization_test_function_locals *locals; 873 struct dml2_instance *dml; 874 struct display_configuation_with_meta *display_config; 875 }; 876 877 struct optimization_optimize_function_params { 878 bool last_candidate_supported; 879 struct dml2_optimization_optimize_function_locals *locals; 880 struct dml2_instance *dml; 881 struct display_configuation_with_meta *display_config; 882 struct display_configuation_with_meta *optimized_display_config; 883 }; 884 885 struct optimization_phase_params { 886 struct dml2_instance *dml; 887 const struct display_configuation_with_meta *display_config; // Initial Display Configuration 888 bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete 889 bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete 890 bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration 891 struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration 892 893 bool all_or_nothing; 894 }; 895 896 struct dml2_build_mode_programming_locals { 897 struct dml2_core_mode_support_in_out mode_support_params; 898 struct dml2_core_mode_programming_in_out mode_programming_params; 899 struct dml2_core_populate_informative_in_out informative_params; 900 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 901 struct display_configuation_with_meta base_display_config_with_meta; 902 struct display_configuation_with_meta optimized_display_config_with_meta; 903 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 904 struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params; 905 struct dml2_optimization_phase_locals optimization_phase_locals; 906 struct optimization_phase_params min_clock_for_latency_phase; 907 struct optimization_phase_params mcache_phase; 908 struct optimization_phase_params uclk_pstate_phase; 909 struct optimization_phase_params vmin_phase; 910 struct optimization_phase_params stutter_phase; 911 }; 912 913 struct dml2_legacy_core_build_mode_programming_wrapper_locals { 914 struct dml2_core_mode_support_in_out mode_support_params; 915 struct dml2_core_mode_programming_in_out mode_programming_params; 916 struct dml2_core_populate_informative_in_out informative_params; 917 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 918 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 919 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 920 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 921 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 922 struct dml2_display_cfg optimized_display_cfg; 923 struct core_display_cfg_support_info core_support_info; 924 }; 925 926 struct dml2_top_mcache_verify_mcache_size_locals { 927 struct dml2_calculate_mcache_allocation_in_out calc_mcache_params; 928 }; 929 930 struct dml2_top_mcache_validate_admissability_locals { 931 struct { 932 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 933 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 934 } plane0; 935 struct { 936 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 937 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 938 } plane1; 939 }; 940 941 struct dml2_top_display_cfg_support_info { 942 const struct dml2_display_cfg *display_config; 943 struct core_display_cfg_support_info core_info; 944 }; 945 946 struct dml2_top_funcs { 947 bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out); 948 bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out); 949 bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out); 950 bool (*unit_test)(void); 951 }; 952 953 struct dml2_instance { 954 enum dml2_project_id project_id; 955 956 struct dml2_core_instance core_instance; 957 struct dml2_mcg_instance mcg_instance; 958 struct dml2_dpmm_instance dpmm_instance; 959 struct dml2_pmo_instance pmo_instance; 960 961 struct dml2_soc_bb soc_bbox; 962 struct dml2_ip_capabilities ip_caps; 963 964 struct dml2_mcg_min_clock_table min_clk_table; 965 struct dml2_pmo_options pmo_options; 966 struct dml2_top_funcs funcs; 967 968 struct { 969 struct dml2_initialize_instance_locals initialize_instance_locals; 970 struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals; 971 struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals; 972 struct dml2_check_mode_supported_locals check_mode_supported_locals; 973 struct dml2_build_mode_programming_locals build_mode_programming_locals; 974 } scratch; 975 976 struct { 977 struct { 978 struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals; 979 } scratch; 980 } legacy; 981 }; 982 #endif 983