1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_smu.h"
36 #include "atom.h"
37 #include "amd_pcie.h"
38
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41 #include "mp/mp_13_0_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15_common.h"
45 #include "soc21.h"
46 #include "mxgpu_nv.h"
47
48 static const struct amd_ip_funcs soc21_common_ip_funcs;
49
50 /* SOC21 */
51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
55 };
56
57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
60 };
61
62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
65 };
66
67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
70 };
71
72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
78 };
79
80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
85 };
86
87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
90 };
91
92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
95 };
96
97 /* SRIOV SOC21, not const since data is controlled by host */
98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102 };
103
104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
107 };
108
109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
112 };
113
114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
117 };
118
119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
125 };
126
127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
132 };
133
134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
137 };
138
139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
142 };
143
144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = {
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
148 };
149
150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = {
151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0),
152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0,
153 };
154
155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = {
156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
161 };
162
163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = {
164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0),
165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0,
166 };
167
168
soc21_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
170 const struct amdgpu_video_codecs **codecs)
171 {
172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
173 return -EINVAL;
174
175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
176 case IP_VERSION(4, 0, 0):
177 case IP_VERSION(4, 0, 2):
178 case IP_VERSION(4, 0, 4):
179 case IP_VERSION(4, 0, 5):
180 if (amdgpu_sriov_vf(adev)) {
181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
182 !amdgpu_sriov_is_av1_support(adev)) {
183 if (encode)
184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
185 else
186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
187 } else {
188 if (encode)
189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
190 else
191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
192 }
193 } else {
194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
195 if (encode)
196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
197 else
198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
199 } else {
200 if (encode)
201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
202 else
203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
204 }
205 }
206 return 0;
207 case IP_VERSION(4, 0, 6):
208 if (encode)
209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
210 else
211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
212 return 0;
213 case IP_VERSION(5, 3, 0):
214 if (encode)
215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0;
216 else
217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0;
218 return 0;
219 default:
220 return -EINVAL;
221 }
222 }
223
soc21_didt_rreg(struct amdgpu_device * adev,u32 reg)224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
225 {
226 unsigned long flags, address, data;
227 u32 r;
228
229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
231
232 spin_lock_irqsave(&adev->reg.didt.lock, flags);
233 WREG32(address, (reg));
234 r = RREG32(data);
235 spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
236 return r;
237 }
238
soc21_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
240 {
241 unsigned long flags, address, data;
242
243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
245
246 spin_lock_irqsave(&adev->reg.didt.lock, flags);
247 WREG32(address, (reg));
248 WREG32(data, (v));
249 spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
250 }
251
soc21_get_config_memsize(struct amdgpu_device * adev)252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
253 {
254 return adev->nbio.funcs->get_memsize(adev);
255 }
256
soc21_get_xclk(struct amdgpu_device * adev)257 static u32 soc21_get_xclk(struct amdgpu_device *adev)
258 {
259 u32 reference_clock = adev->clock.spll.reference_freq;
260
261 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */
262 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000)
263 return 9981;
264
265 return reference_clock;
266 }
267
268
soc21_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)269 void soc21_grbm_select(struct amdgpu_device *adev,
270 u32 me, u32 pipe, u32 queue, u32 vmid)
271 {
272 u32 grbm_gfx_cntl = 0;
273 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
277
278 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
279 }
280
soc21_read_disabled_bios(struct amdgpu_device * adev)281 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
282 {
283 /* todo */
284 return false;
285 }
286
287 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
288 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
295 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
296 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
297 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
300 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
303 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
306 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
307 };
308
soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)309 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
310 u32 sh_num, u32 reg_offset)
311 {
312 uint32_t val;
313
314 mutex_lock(&adev->grbm_idx_mutex);
315 if (se_num != 0xffffffff || sh_num != 0xffffffff)
316 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
317
318 val = RREG32(reg_offset);
319
320 if (se_num != 0xffffffff || sh_num != 0xffffffff)
321 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
322 mutex_unlock(&adev->grbm_idx_mutex);
323 return val;
324 }
325
soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)326 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
327 bool indexed, u32 se_num,
328 u32 sh_num, u32 reg_offset)
329 {
330 if (indexed) {
331 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
332 } else {
333 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
334 return adev->gfx.config.gb_addr_config;
335 return RREG32(reg_offset);
336 }
337 }
338
soc21_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)339 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
340 u32 sh_num, u32 reg_offset, u32 *value)
341 {
342 uint32_t i;
343 struct soc15_allowed_register_entry *en;
344
345 *value = 0;
346 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
347 en = &soc21_allowed_read_registers[i];
348 if (!adev->reg_offset[en->hwip][en->inst])
349 continue;
350 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
351 + en->reg_offset))
352 continue;
353
354 *value = soc21_get_register_value(adev,
355 soc21_allowed_read_registers[i].grbm_indexed,
356 se_num, sh_num, reg_offset);
357 return 0;
358 }
359 return -EINVAL;
360 }
361
362 #if 0
363 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
364 {
365 u32 i;
366 int ret = 0;
367
368 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
369
370 /* disable BM */
371 pci_clear_master(adev->pdev);
372
373 amdgpu_device_cache_pci_state(adev->pdev);
374
375 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
376 dev_info(adev->dev, "GPU smu mode1 reset\n");
377 ret = amdgpu_dpm_mode1_reset(adev);
378 } else {
379 dev_info(adev->dev, "GPU psp mode1 reset\n");
380 ret = psp_gpu_reset(adev);
381 }
382
383 if (ret)
384 dev_err(adev->dev, "GPU mode1 reset failed\n");
385 amdgpu_device_load_pci_state(adev->pdev);
386
387 /* wait for asic to come out of reset */
388 for (i = 0; i < adev->usec_timeout; i++) {
389 u32 memsize = adev->nbio.funcs->get_memsize(adev);
390
391 if (memsize != 0xffffffff)
392 break;
393 udelay(1);
394 }
395
396 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
397
398 return ret;
399 }
400 #endif
401
402 static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device * adev)403 soc21_asic_reset_method(struct amdgpu_device *adev)
404 {
405 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
406 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
407 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
408 return amdgpu_reset_method;
409
410 if (amdgpu_reset_method != -1)
411 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
412 amdgpu_reset_method);
413
414 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
415 case IP_VERSION(13, 0, 0):
416 case IP_VERSION(13, 0, 7):
417 case IP_VERSION(13, 0, 10):
418 return AMD_RESET_METHOD_MODE1;
419 case IP_VERSION(13, 0, 4):
420 case IP_VERSION(13, 0, 11):
421 case IP_VERSION(14, 0, 0):
422 case IP_VERSION(14, 0, 1):
423 case IP_VERSION(14, 0, 4):
424 case IP_VERSION(14, 0, 5):
425 case IP_VERSION(15, 0, 0):
426 return AMD_RESET_METHOD_MODE2;
427 default:
428 if (amdgpu_dpm_is_baco_supported(adev))
429 return AMD_RESET_METHOD_BACO;
430 else
431 return AMD_RESET_METHOD_MODE1;
432 }
433 }
434
soc21_asic_reset(struct amdgpu_device * adev)435 static int soc21_asic_reset(struct amdgpu_device *adev)
436 {
437 int ret = 0;
438
439 switch (soc21_asic_reset_method(adev)) {
440 case AMD_RESET_METHOD_PCI:
441 dev_info(adev->dev, "PCI reset\n");
442 ret = amdgpu_device_pci_reset(adev);
443 break;
444 case AMD_RESET_METHOD_BACO:
445 dev_info(adev->dev, "BACO reset\n");
446 ret = amdgpu_dpm_baco_reset(adev);
447 break;
448 case AMD_RESET_METHOD_MODE2:
449 dev_info(adev->dev, "MODE2 reset\n");
450 ret = amdgpu_dpm_mode2_reset(adev);
451 break;
452 default:
453 dev_info(adev->dev, "MODE1 reset\n");
454 ret = amdgpu_device_mode1_reset(adev);
455 break;
456 }
457
458 return ret;
459 }
460
soc21_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)461 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
462 {
463 /* todo */
464 return 0;
465 }
466
soc21_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)467 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
468 {
469 /* todo */
470 return 0;
471 }
472
soc21_program_aspm(struct amdgpu_device * adev)473 static void soc21_program_aspm(struct amdgpu_device *adev)
474 {
475 if (!amdgpu_device_should_use_aspm(adev))
476 return;
477
478 if (adev->nbio.funcs->program_aspm)
479 adev->nbio.funcs->program_aspm(adev);
480 }
481
482 const struct amdgpu_ip_block_version soc21_common_ip_block = {
483 .type = AMD_IP_BLOCK_TYPE_COMMON,
484 .major = 1,
485 .minor = 0,
486 .rev = 0,
487 .funcs = &soc21_common_ip_funcs,
488 };
489
soc21_need_full_reset(struct amdgpu_device * adev)490 static bool soc21_need_full_reset(struct amdgpu_device *adev)
491 {
492 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
493 case IP_VERSION(11, 0, 0):
494 case IP_VERSION(11, 0, 2):
495 case IP_VERSION(11, 0, 3):
496 default:
497 return true;
498 }
499 }
500
soc21_need_reset_on_init(struct amdgpu_device * adev)501 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
502 {
503 u32 sol_reg;
504
505 if (adev->flags & AMD_IS_APU)
506 return false;
507
508 /* Check sOS sign of life register to confirm sys driver and sOS
509 * are already been loaded.
510 */
511 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
512 if (sol_reg)
513 return true;
514
515 return false;
516 }
517
soc21_init_doorbell_index(struct amdgpu_device * adev)518 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
519 {
520 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
521 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
522 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
523 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
524 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
525 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
526 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
527 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
528 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
529 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
530 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
531 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
532 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
533 adev->doorbell_index.gfx_userqueue_start =
534 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
535 adev->doorbell_index.gfx_userqueue_end =
536 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
537 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
538 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
539 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
540 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
541 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
542 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
543 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
544 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
545 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
546 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE;
547 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
548 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
549
550 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
551 adev->doorbell_index.sdma_doorbell_range = 20;
552 }
553
soc21_update_umd_stable_pstate(struct amdgpu_device * adev,bool enter)554 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
555 bool enter)
556 {
557 if (enter)
558 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
559 else
560 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
561
562 if (adev->gfx.funcs->update_perfmon_mgcg)
563 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
564
565 return 0;
566 }
567
568 static const struct amdgpu_asic_funcs soc21_asic_funcs = {
569 .read_disabled_bios = &soc21_read_disabled_bios,
570 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
571 .read_register = &soc21_read_register,
572 .reset = &soc21_asic_reset,
573 .reset_method = &soc21_asic_reset_method,
574 .get_xclk = &soc21_get_xclk,
575 .set_uvd_clocks = &soc21_set_uvd_clocks,
576 .set_vce_clocks = &soc21_set_vce_clocks,
577 .get_config_memsize = &soc21_get_config_memsize,
578 .init_doorbell_index = &soc21_init_doorbell_index,
579 .need_full_reset = &soc21_need_full_reset,
580 .need_reset_on_init = &soc21_need_reset_on_init,
581 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
582 .supports_baco = &amdgpu_dpm_is_baco_supported,
583 .query_video_codecs = &soc21_query_video_codecs,
584 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
585 };
586
soc21_common_early_init(struct amdgpu_ip_block * ip_block)587 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
588 {
589 struct amdgpu_device *adev = ip_block->adev;
590
591 adev->nbio.funcs->set_reg_remap(adev);
592 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg;
593 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg;
594 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64;
595 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64;
596 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg;
597 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg;
598
599 adev->reg.didt.rreg = &soc21_didt_rreg;
600 adev->reg.didt.wreg = &soc21_didt_wreg;
601
602 adev->asic_funcs = &soc21_asic_funcs;
603
604 adev->rev_id = amdgpu_device_get_rev_id(adev);
605 adev->external_rev_id = 0xff;
606 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
607 case IP_VERSION(11, 0, 0):
608 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
609 AMD_CG_SUPPORT_GFX_CGLS |
610 #if 0
611 AMD_CG_SUPPORT_GFX_3D_CGCG |
612 AMD_CG_SUPPORT_GFX_3D_CGLS |
613 #endif
614 AMD_CG_SUPPORT_GFX_MGCG |
615 AMD_CG_SUPPORT_REPEATER_FGCG |
616 AMD_CG_SUPPORT_GFX_FGCG |
617 AMD_CG_SUPPORT_GFX_PERF_CLK |
618 AMD_CG_SUPPORT_VCN_MGCG |
619 AMD_CG_SUPPORT_JPEG_MGCG |
620 AMD_CG_SUPPORT_ATHUB_MGCG |
621 AMD_CG_SUPPORT_ATHUB_LS |
622 AMD_CG_SUPPORT_MC_MGCG |
623 AMD_CG_SUPPORT_MC_LS |
624 AMD_CG_SUPPORT_IH_CG |
625 AMD_CG_SUPPORT_HDP_SD;
626 adev->pg_flags = AMD_PG_SUPPORT_VCN |
627 AMD_PG_SUPPORT_VCN_DPG |
628 AMD_PG_SUPPORT_JPEG |
629 AMD_PG_SUPPORT_ATHUB |
630 AMD_PG_SUPPORT_MMHUB;
631 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
632 break;
633 case IP_VERSION(11, 0, 2):
634 adev->cg_flags =
635 AMD_CG_SUPPORT_GFX_CGCG |
636 AMD_CG_SUPPORT_GFX_CGLS |
637 AMD_CG_SUPPORT_REPEATER_FGCG |
638 AMD_CG_SUPPORT_VCN_MGCG |
639 AMD_CG_SUPPORT_JPEG_MGCG |
640 AMD_CG_SUPPORT_ATHUB_MGCG |
641 AMD_CG_SUPPORT_ATHUB_LS |
642 AMD_CG_SUPPORT_IH_CG |
643 AMD_CG_SUPPORT_HDP_SD;
644 adev->pg_flags =
645 AMD_PG_SUPPORT_VCN |
646 AMD_PG_SUPPORT_VCN_DPG |
647 AMD_PG_SUPPORT_JPEG |
648 AMD_PG_SUPPORT_ATHUB |
649 AMD_PG_SUPPORT_MMHUB;
650 adev->external_rev_id = adev->rev_id + 0x10;
651 break;
652 case IP_VERSION(11, 0, 1):
653 adev->cg_flags =
654 AMD_CG_SUPPORT_GFX_CGCG |
655 AMD_CG_SUPPORT_GFX_CGLS |
656 AMD_CG_SUPPORT_GFX_MGCG |
657 AMD_CG_SUPPORT_GFX_FGCG |
658 AMD_CG_SUPPORT_REPEATER_FGCG |
659 AMD_CG_SUPPORT_GFX_PERF_CLK |
660 AMD_CG_SUPPORT_MC_MGCG |
661 AMD_CG_SUPPORT_MC_LS |
662 AMD_CG_SUPPORT_HDP_MGCG |
663 AMD_CG_SUPPORT_HDP_LS |
664 AMD_CG_SUPPORT_ATHUB_MGCG |
665 AMD_CG_SUPPORT_ATHUB_LS |
666 AMD_CG_SUPPORT_IH_CG |
667 AMD_CG_SUPPORT_BIF_MGCG |
668 AMD_CG_SUPPORT_BIF_LS |
669 AMD_CG_SUPPORT_VCN_MGCG |
670 AMD_CG_SUPPORT_JPEG_MGCG;
671 adev->pg_flags =
672 AMD_PG_SUPPORT_GFX_PG |
673 AMD_PG_SUPPORT_VCN |
674 AMD_PG_SUPPORT_VCN_DPG |
675 AMD_PG_SUPPORT_JPEG;
676 adev->external_rev_id = adev->rev_id + 0x1;
677 break;
678 case IP_VERSION(11, 0, 3):
679 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
680 AMD_CG_SUPPORT_JPEG_MGCG |
681 AMD_CG_SUPPORT_GFX_CGCG |
682 AMD_CG_SUPPORT_GFX_CGLS |
683 AMD_CG_SUPPORT_REPEATER_FGCG |
684 AMD_CG_SUPPORT_GFX_MGCG |
685 AMD_CG_SUPPORT_HDP_SD |
686 AMD_CG_SUPPORT_ATHUB_MGCG |
687 AMD_CG_SUPPORT_ATHUB_LS;
688 adev->pg_flags = AMD_PG_SUPPORT_VCN |
689 AMD_PG_SUPPORT_VCN_DPG |
690 AMD_PG_SUPPORT_JPEG;
691 adev->external_rev_id = adev->rev_id + 0x20;
692 break;
693 case IP_VERSION(11, 0, 4):
694 adev->cg_flags =
695 AMD_CG_SUPPORT_GFX_CGCG |
696 AMD_CG_SUPPORT_GFX_CGLS |
697 AMD_CG_SUPPORT_GFX_MGCG |
698 AMD_CG_SUPPORT_GFX_FGCG |
699 AMD_CG_SUPPORT_REPEATER_FGCG |
700 AMD_CG_SUPPORT_GFX_PERF_CLK |
701 AMD_CG_SUPPORT_MC_MGCG |
702 AMD_CG_SUPPORT_MC_LS |
703 AMD_CG_SUPPORT_HDP_MGCG |
704 AMD_CG_SUPPORT_HDP_LS |
705 AMD_CG_SUPPORT_ATHUB_MGCG |
706 AMD_CG_SUPPORT_ATHUB_LS |
707 AMD_CG_SUPPORT_IH_CG |
708 AMD_CG_SUPPORT_BIF_MGCG |
709 AMD_CG_SUPPORT_BIF_LS |
710 AMD_CG_SUPPORT_VCN_MGCG |
711 AMD_CG_SUPPORT_JPEG_MGCG;
712 adev->pg_flags = AMD_PG_SUPPORT_VCN |
713 AMD_PG_SUPPORT_VCN_DPG |
714 AMD_PG_SUPPORT_GFX_PG |
715 AMD_PG_SUPPORT_JPEG;
716 adev->external_rev_id = adev->rev_id + 0x80;
717 break;
718 case IP_VERSION(11, 5, 0):
719 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
720 AMD_CG_SUPPORT_JPEG_MGCG |
721 AMD_CG_SUPPORT_GFX_CGCG |
722 AMD_CG_SUPPORT_GFX_CGLS |
723 AMD_CG_SUPPORT_GFX_MGCG |
724 AMD_CG_SUPPORT_GFX_FGCG |
725 AMD_CG_SUPPORT_REPEATER_FGCG |
726 AMD_CG_SUPPORT_GFX_PERF_CLK |
727 AMD_CG_SUPPORT_GFX_3D_CGCG |
728 AMD_CG_SUPPORT_GFX_3D_CGLS |
729 AMD_CG_SUPPORT_MC_MGCG |
730 AMD_CG_SUPPORT_MC_LS |
731 AMD_CG_SUPPORT_HDP_LS |
732 AMD_CG_SUPPORT_HDP_DS |
733 AMD_CG_SUPPORT_HDP_SD |
734 AMD_CG_SUPPORT_ATHUB_MGCG |
735 AMD_CG_SUPPORT_ATHUB_LS |
736 AMD_CG_SUPPORT_IH_CG |
737 AMD_CG_SUPPORT_BIF_MGCG |
738 AMD_CG_SUPPORT_BIF_LS;
739 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
740 AMD_PG_SUPPORT_JPEG_DPG |
741 AMD_PG_SUPPORT_VCN |
742 AMD_PG_SUPPORT_JPEG |
743 AMD_PG_SUPPORT_GFX_PG;
744 if (adev->rev_id == 0)
745 adev->external_rev_id = 0x1;
746 else
747 adev->external_rev_id = adev->rev_id + 0x10;
748 break;
749 case IP_VERSION(11, 5, 1):
750 adev->cg_flags =
751 AMD_CG_SUPPORT_GFX_CGCG |
752 AMD_CG_SUPPORT_GFX_CGLS |
753 AMD_CG_SUPPORT_GFX_MGCG |
754 AMD_CG_SUPPORT_GFX_FGCG |
755 AMD_CG_SUPPORT_REPEATER_FGCG |
756 AMD_CG_SUPPORT_GFX_PERF_CLK |
757 AMD_CG_SUPPORT_GFX_3D_CGCG |
758 AMD_CG_SUPPORT_GFX_3D_CGLS |
759 AMD_CG_SUPPORT_MC_MGCG |
760 AMD_CG_SUPPORT_MC_LS |
761 AMD_CG_SUPPORT_HDP_LS |
762 AMD_CG_SUPPORT_HDP_DS |
763 AMD_CG_SUPPORT_HDP_SD |
764 AMD_CG_SUPPORT_ATHUB_MGCG |
765 AMD_CG_SUPPORT_ATHUB_LS |
766 AMD_CG_SUPPORT_IH_CG |
767 AMD_CG_SUPPORT_BIF_MGCG |
768 AMD_CG_SUPPORT_BIF_LS |
769 AMD_CG_SUPPORT_VCN_MGCG |
770 AMD_CG_SUPPORT_JPEG_MGCG;
771 adev->pg_flags =
772 AMD_PG_SUPPORT_GFX_PG |
773 AMD_PG_SUPPORT_VCN |
774 AMD_PG_SUPPORT_VCN_DPG |
775 AMD_PG_SUPPORT_JPEG;
776 adev->external_rev_id = adev->rev_id + 0xc1;
777 break;
778 case IP_VERSION(11, 5, 2):
779 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
780 AMD_CG_SUPPORT_JPEG_MGCG |
781 AMD_CG_SUPPORT_GFX_CGCG |
782 AMD_CG_SUPPORT_GFX_CGLS |
783 AMD_CG_SUPPORT_GFX_MGCG |
784 AMD_CG_SUPPORT_GFX_FGCG |
785 AMD_CG_SUPPORT_REPEATER_FGCG |
786 AMD_CG_SUPPORT_GFX_PERF_CLK |
787 AMD_CG_SUPPORT_GFX_3D_CGCG |
788 AMD_CG_SUPPORT_GFX_3D_CGLS |
789 AMD_CG_SUPPORT_MC_MGCG |
790 AMD_CG_SUPPORT_MC_LS |
791 AMD_CG_SUPPORT_HDP_LS |
792 AMD_CG_SUPPORT_HDP_DS |
793 AMD_CG_SUPPORT_HDP_SD |
794 AMD_CG_SUPPORT_ATHUB_MGCG |
795 AMD_CG_SUPPORT_ATHUB_LS |
796 AMD_CG_SUPPORT_IH_CG |
797 AMD_CG_SUPPORT_BIF_MGCG |
798 AMD_CG_SUPPORT_BIF_LS;
799 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
800 AMD_PG_SUPPORT_VCN |
801 AMD_PG_SUPPORT_JPEG_DPG |
802 AMD_PG_SUPPORT_JPEG |
803 AMD_PG_SUPPORT_GFX_PG;
804 adev->external_rev_id = adev->rev_id + 0x40;
805 break;
806 case IP_VERSION(11, 5, 3):
807 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
808 AMD_CG_SUPPORT_JPEG_MGCG |
809 AMD_CG_SUPPORT_GFX_CGCG |
810 AMD_CG_SUPPORT_GFX_CGLS |
811 AMD_CG_SUPPORT_GFX_MGCG |
812 AMD_CG_SUPPORT_GFX_FGCG |
813 AMD_CG_SUPPORT_REPEATER_FGCG |
814 AMD_CG_SUPPORT_GFX_PERF_CLK |
815 AMD_CG_SUPPORT_GFX_3D_CGCG |
816 AMD_CG_SUPPORT_GFX_3D_CGLS |
817 AMD_CG_SUPPORT_MC_MGCG |
818 AMD_CG_SUPPORT_MC_LS |
819 AMD_CG_SUPPORT_HDP_LS |
820 AMD_CG_SUPPORT_HDP_DS |
821 AMD_CG_SUPPORT_HDP_SD |
822 AMD_CG_SUPPORT_ATHUB_MGCG |
823 AMD_CG_SUPPORT_ATHUB_LS |
824 AMD_CG_SUPPORT_IH_CG |
825 AMD_CG_SUPPORT_BIF_MGCG |
826 AMD_CG_SUPPORT_BIF_LS;
827 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
828 AMD_PG_SUPPORT_VCN |
829 AMD_PG_SUPPORT_JPEG_DPG |
830 AMD_PG_SUPPORT_JPEG |
831 AMD_PG_SUPPORT_GFX_PG;
832 adev->external_rev_id = adev->rev_id + 0x50;
833 break;
834 case IP_VERSION(11, 5, 4):
835 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
836 AMD_CG_SUPPORT_JPEG_MGCG |
837 AMD_CG_SUPPORT_GFX_CGCG |
838 AMD_CG_SUPPORT_GFX_CGLS |
839 AMD_CG_SUPPORT_GFX_MGCG |
840 AMD_CG_SUPPORT_GFX_FGCG |
841 AMD_CG_SUPPORT_REPEATER_FGCG |
842 AMD_CG_SUPPORT_GFX_PERF_CLK |
843 AMD_CG_SUPPORT_GFX_3D_CGCG |
844 AMD_CG_SUPPORT_GFX_3D_CGLS |
845 AMD_CG_SUPPORT_MC_MGCG |
846 AMD_CG_SUPPORT_MC_LS |
847 AMD_CG_SUPPORT_HDP_LS |
848 AMD_CG_SUPPORT_HDP_DS |
849 AMD_CG_SUPPORT_HDP_SD |
850 AMD_CG_SUPPORT_ATHUB_MGCG |
851 AMD_CG_SUPPORT_ATHUB_LS |
852 AMD_CG_SUPPORT_IH_CG |
853 AMD_CG_SUPPORT_BIF_MGCG |
854 AMD_CG_SUPPORT_BIF_LS;
855 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
856 AMD_PG_SUPPORT_VCN |
857 AMD_PG_SUPPORT_JPEG_DPG |
858 AMD_PG_SUPPORT_JPEG |
859 AMD_PG_SUPPORT_GFX_PG;
860 adev->external_rev_id = adev->rev_id + 0x1;
861 break;
862 default:
863 /* FIXME: not supported yet */
864 return -EINVAL;
865 }
866
867 if (amdgpu_sriov_vf(adev)) {
868 amdgpu_virt_init_setting(adev);
869 xgpu_nv_mailbox_set_irq_funcs(adev);
870 }
871
872 return 0;
873 }
874
soc21_common_late_init(struct amdgpu_ip_block * ip_block)875 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block)
876 {
877 struct amdgpu_device *adev = ip_block->adev;
878
879 if (amdgpu_sriov_vf(adev)) {
880 xgpu_nv_mailbox_get_irq(adev);
881 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
882 !amdgpu_sriov_is_av1_support(adev)) {
883 amdgpu_virt_update_sriov_video_codec(adev,
884 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
885 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
886 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
887 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
888 } else {
889 amdgpu_virt_update_sriov_video_codec(adev,
890 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
891 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
892 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
893 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
894 }
895 } else {
896 if (adev->nbio.ras &&
897 adev->nbio.ras_err_event_athub_irq.funcs)
898 /* don't need to fail gpu late init
899 * if enabling athub_err_event interrupt failed
900 * nbio v4_3 only support fatal error hanlding
901 * just enable the interrupt directly */
902 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
903 }
904
905 /* Enable selfring doorbell aperture late because doorbell BAR
906 * aperture will change if resize BAR successfully in gmc sw_init.
907 */
908 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
909
910 return 0;
911 }
912
soc21_common_sw_init(struct amdgpu_ip_block * ip_block)913 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block)
914 {
915 struct amdgpu_device *adev = ip_block->adev;
916
917 if (amdgpu_sriov_vf(adev))
918 xgpu_nv_mailbox_add_irq_id(adev);
919
920 return 0;
921 }
922
soc21_common_hw_init(struct amdgpu_ip_block * ip_block)923 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block)
924 {
925 struct amdgpu_device *adev = ip_block->adev;
926
927 /* enable aspm */
928 soc21_program_aspm(adev);
929 /* setup nbio registers */
930 adev->nbio.funcs->init_registers(adev);
931 /* remap HDP registers to a hole in mmio space,
932 * for the purpose of expose those registers
933 * to process space
934 */
935 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
936 adev->nbio.funcs->remap_hdp_registers(adev);
937 /* enable the doorbell aperture */
938 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
939
940 return 0;
941 }
942
soc21_common_hw_fini(struct amdgpu_ip_block * ip_block)943 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block)
944 {
945 struct amdgpu_device *adev = ip_block->adev;
946
947 /* Disable the doorbell aperture and selfring doorbell aperture
948 * separately in hw_fini because soc21_enable_doorbell_aperture
949 * has been removed and there is no need to delay disabling
950 * selfring doorbell.
951 */
952 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
953 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
954
955 if (amdgpu_sriov_vf(adev)) {
956 xgpu_nv_mailbox_put_irq(adev);
957 } else {
958 if (adev->nbio.ras &&
959 adev->nbio.ras_err_event_athub_irq.funcs)
960 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
961 }
962
963 return 0;
964 }
965
soc21_common_suspend(struct amdgpu_ip_block * ip_block)966 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block)
967 {
968 return soc21_common_hw_fini(ip_block);
969 }
970
soc21_need_reset_on_resume(struct amdgpu_device * adev)971 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
972 {
973 u32 sol_reg1, sol_reg2;
974
975 /* Will reset for the following suspend abort cases.
976 * 1) Only reset dGPU side.
977 * 2) S3 suspend got aborted and TOS is active.
978 * As for dGPU suspend abort cases the SOL value
979 * will be kept as zero at this resume point.
980 */
981 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) {
982 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
983 msleep(100);
984 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
985
986 return (sol_reg1 != sol_reg2);
987 }
988
989 return false;
990 }
991
soc21_common_resume(struct amdgpu_ip_block * ip_block)992 static int soc21_common_resume(struct amdgpu_ip_block *ip_block)
993 {
994 struct amdgpu_device *adev = ip_block->adev;
995
996 if (soc21_need_reset_on_resume(adev)) {
997 dev_info(adev->dev, "S3 suspend aborted, resetting...");
998 soc21_asic_reset(adev);
999 }
1000
1001 return soc21_common_hw_init(ip_block);
1002 }
1003
soc21_common_is_idle(struct amdgpu_ip_block * ip_block)1004 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
1005 {
1006 return true;
1007 }
1008
soc21_common_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1009 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1010 enum amd_clockgating_state state)
1011 {
1012 struct amdgpu_device *adev = ip_block->adev;
1013
1014 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1015 case IP_VERSION(4, 3, 0):
1016 case IP_VERSION(4, 3, 1):
1017 case IP_VERSION(7, 7, 0):
1018 case IP_VERSION(7, 7, 1):
1019 case IP_VERSION(7, 11, 0):
1020 case IP_VERSION(7, 11, 1):
1021 case IP_VERSION(7, 11, 2):
1022 case IP_VERSION(7, 11, 3):
1023 case IP_VERSION(7, 11, 4):
1024 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1025 state == AMD_CG_STATE_GATE);
1026 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1027 state == AMD_CG_STATE_GATE);
1028 adev->hdp.funcs->update_clock_gating(adev,
1029 state == AMD_CG_STATE_GATE);
1030 break;
1031 default:
1032 break;
1033 }
1034 return 0;
1035 }
1036
soc21_common_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)1037 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1038 enum amd_powergating_state state)
1039 {
1040 struct amdgpu_device *adev = ip_block->adev;
1041
1042 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
1043 case IP_VERSION(6, 0, 0):
1044 case IP_VERSION(6, 0, 2):
1045 adev->lsdma.funcs->update_memory_power_gating(adev,
1046 state == AMD_PG_STATE_GATE);
1047 break;
1048 default:
1049 break;
1050 }
1051
1052 return 0;
1053 }
1054
soc21_common_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)1055 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1056 {
1057 struct amdgpu_device *adev = ip_block->adev;
1058
1059 adev->nbio.funcs->get_clockgating_state(adev, flags);
1060
1061 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1062 }
1063
1064 static const struct amd_ip_funcs soc21_common_ip_funcs = {
1065 .name = "soc21_common",
1066 .early_init = soc21_common_early_init,
1067 .late_init = soc21_common_late_init,
1068 .sw_init = soc21_common_sw_init,
1069 .hw_init = soc21_common_hw_init,
1070 .hw_fini = soc21_common_hw_fini,
1071 .suspend = soc21_common_suspend,
1072 .resume = soc21_common_resume,
1073 .is_idle = soc21_common_is_idle,
1074 .set_clockgating_state = soc21_common_set_clockgating_state,
1075 .set_powergating_state = soc21_common_set_powergating_state,
1076 .get_clockgating_state = soc21_common_get_clockgating_state,
1077 };
1078