1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SWSMU_CODE_LAYER_L3
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v14_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "amdgpu_ras.h"
39 #include "smu_cmn.h"
40
41 #include "asic_reg/thm/thm_14_0_2_offset.h"
42 #include "asic_reg/thm/thm_14_0_2_sh_mask.h"
43 #include "asic_reg/mp/mp_14_0_2_offset.h"
44 #include "asic_reg/mp/mp_14_0_2_sh_mask.h"
45
46 #define regMP1_SMN_IH_SW_INT_mp1_14_0_0 0x0341
47 #define regMP1_SMN_IH_SW_INT_mp1_14_0_0_BASE_IDX 0
48 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0 0x0342
49 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0
50
51 const int decoded_link_speed[5] = {1, 2, 3, 4, 5};
52 const int decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
53 /*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58 #undef pr_err
59 #undef pr_warn
60 #undef pr_info
61 #undef pr_debug
62
63 MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
64 MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin");
65
66 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
67
smu_v14_0_init_microcode(struct smu_context * smu)68 int smu_v14_0_init_microcode(struct smu_context *smu)
69 {
70 struct amdgpu_device *adev = smu->adev;
71 char ucode_prefix[15];
72 int err = 0;
73 const struct smc_firmware_header_v1_0 *hdr;
74 const struct common_firmware_header *header;
75 struct amdgpu_firmware_info *ucode = NULL;
76
77 /* doesn't need to load smu firmware in IOV mode */
78 if (amdgpu_sriov_vf(adev))
79 return 0;
80
81 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
82 err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
83 if (err)
84 goto out;
85
86 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
87 amdgpu_ucode_print_smc_hdr(&hdr->header);
88 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
89
90 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
91 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
92 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
93 ucode->fw = adev->pm.fw;
94 header = (const struct common_firmware_header *)ucode->fw->data;
95 adev->firmware.fw_size +=
96 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
97 }
98
99 out:
100 if (err)
101 amdgpu_ucode_release(&adev->pm.fw);
102 return err;
103 }
104
smu_v14_0_fini_microcode(struct smu_context * smu)105 void smu_v14_0_fini_microcode(struct smu_context *smu)
106 {
107 struct amdgpu_device *adev = smu->adev;
108
109 amdgpu_ucode_release(&adev->pm.fw);
110 adev->pm.fw_version = 0;
111 }
112
smu_v14_0_load_microcode(struct smu_context * smu)113 int smu_v14_0_load_microcode(struct smu_context *smu)
114 {
115 struct amdgpu_device *adev = smu->adev;
116 const uint32_t *src;
117 const struct smc_firmware_header_v1_0 *hdr;
118 uint32_t addr_start = MP1_SRAM;
119 uint32_t i;
120 uint32_t smc_fw_size;
121 uint32_t mp1_fw_flags;
122
123 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
124 src = (const uint32_t *)(adev->pm.fw->data +
125 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
126 smc_fw_size = hdr->header.ucode_size_bytes;
127
128 for (i = 1; i < smc_fw_size/4 - 1; i++) {
129 WREG32_PCIE(addr_start, src[i]);
130 addr_start += 4;
131 }
132
133 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
134 1 & MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
135 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
136 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
137
138 for (i = 0; i < adev->usec_timeout; i++) {
139 if (smu->is_apu)
140 mp1_fw_flags = RREG32_PCIE(MP1_Public |
141 (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
142 else
143 mp1_fw_flags = RREG32_PCIE(MP1_Public |
144 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
145 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
146 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
147 break;
148 udelay(1);
149 }
150
151 if (i == adev->usec_timeout)
152 return -ETIME;
153
154 return 0;
155 }
156
smu_v14_0_init_pptable_microcode(struct smu_context * smu)157 int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
158 {
159 struct amdgpu_device *adev = smu->adev;
160 struct amdgpu_firmware_info *ucode = NULL;
161 uint32_t size = 0, pptable_id = 0;
162 int ret = 0;
163 void *table;
164
165 /* doesn't need to load smu firmware in IOV mode */
166 if (amdgpu_sriov_vf(adev))
167 return 0;
168
169 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
170 return 0;
171
172 if (!adev->scpm_enabled)
173 return 0;
174
175 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2)) ||
176 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 3)))
177 return 0;
178
179 /* override pptable_id from driver parameter */
180 if (amdgpu_smu_pptable_id >= 0) {
181 pptable_id = amdgpu_smu_pptable_id;
182 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
183 } else {
184 pptable_id = smu->smu_table.boot_values.pp_table_id;
185 }
186
187 /* "pptable_id == 0" means vbios carries the pptable. */
188 if (!pptable_id)
189 return 0;
190
191 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
192 if (ret)
193 return ret;
194
195 smu->pptable_firmware.data = table;
196 smu->pptable_firmware.size = size;
197
198 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
199 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
200 ucode->fw = &smu->pptable_firmware;
201 adev->firmware.fw_size +=
202 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
203
204 return 0;
205 }
206
smu_v14_0_check_fw_status(struct smu_context * smu)207 int smu_v14_0_check_fw_status(struct smu_context *smu)
208 {
209 struct amdgpu_device *adev = smu->adev;
210 uint32_t mp1_fw_flags;
211
212 if (smu->is_apu)
213 mp1_fw_flags = RREG32_PCIE(MP1_Public |
214 (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
215 else
216 mp1_fw_flags = RREG32_PCIE(MP1_Public |
217 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
218
219 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
220 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
221 return 0;
222
223 return -EIO;
224 }
225
smu_v14_0_check_fw_version(struct smu_context * smu)226 int smu_v14_0_check_fw_version(struct smu_context *smu)
227 {
228 struct amdgpu_device *adev = smu->adev;
229 uint32_t if_version = 0xff, smu_version = 0xff;
230 uint8_t smu_program, smu_major, smu_minor, smu_debug;
231 int ret = 0;
232
233 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
234 if (ret)
235 return ret;
236
237 smu_program = (smu_version >> 24) & 0xff;
238 smu_major = (smu_version >> 16) & 0xff;
239 smu_minor = (smu_version >> 8) & 0xff;
240 smu_debug = (smu_version >> 0) & 0xff;
241 if (smu->is_apu)
242 adev->pm.fw_version = smu_version;
243
244 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
245 case IP_VERSION(14, 0, 0):
246 case IP_VERSION(14, 0, 4):
247 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
248 break;
249 case IP_VERSION(14, 0, 1):
250 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;
251 break;
252 case IP_VERSION(14, 0, 2):
253 case IP_VERSION(14, 0, 3):
254 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
255 break;
256 default:
257 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
258 amdgpu_ip_version(adev, MP1_HWIP, 0));
259 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;
260 break;
261 }
262
263 if (adev->pm.fw)
264 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
265 smu_program, smu_version, smu_major, smu_minor, smu_debug);
266
267 /*
268 * 1. if_version mismatch is not critical as our fw is designed
269 * to be backward compatible.
270 * 2. New fw usually brings some optimizations. But that's visible
271 * only on the paired driver.
272 * Considering above, we just leave user a verbal message instead
273 * of halt driver loading.
274 */
275 if (if_version != smu->smc_driver_if_version) {
276 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
277 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
278 smu->smc_driver_if_version, if_version,
279 smu_program, smu_version, smu_major, smu_minor, smu_debug);
280 dev_info(adev->dev, "SMU driver if version not matched\n");
281 }
282
283 return ret;
284 }
285
smu_v14_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)286 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
287 {
288 struct amdgpu_device *adev = smu->adev;
289 uint32_t ppt_offset_bytes;
290 const struct smc_firmware_header_v2_0 *v2;
291
292 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
293
294 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
295 *size = le32_to_cpu(v2->ppt_size_bytes);
296 *table = (uint8_t *)v2 + ppt_offset_bytes;
297
298 return 0;
299 }
300
smu_v14_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)301 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table,
302 uint32_t *size, uint32_t pptable_id)
303 {
304 struct amdgpu_device *adev = smu->adev;
305 const struct smc_firmware_header_v2_1 *v2_1;
306 struct smc_soft_pptable_entry *entries;
307 uint32_t pptable_count = 0;
308 int i = 0;
309
310 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
311 entries = (struct smc_soft_pptable_entry *)
312 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
313 pptable_count = le32_to_cpu(v2_1->pptable_count);
314 for (i = 0; i < pptable_count; i++) {
315 if (le32_to_cpu(entries[i].id) == pptable_id) {
316 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
317 *size = le32_to_cpu(entries[i].ppt_size_bytes);
318 break;
319 }
320 }
321
322 if (i == pptable_count)
323 return -EINVAL;
324
325 return 0;
326 }
327
smu_v14_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)328 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
329 {
330 struct amdgpu_device *adev = smu->adev;
331 uint16_t atom_table_size;
332 uint8_t frev, crev;
333 int ret, index;
334
335 dev_info(adev->dev, "use vbios provided pptable\n");
336 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
337 powerplayinfo);
338
339 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
340 (uint8_t **)table);
341 if (ret)
342 return ret;
343
344 if (size)
345 *size = atom_table_size;
346
347 return 0;
348 }
349
smu_v14_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)350 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
351 void **table,
352 uint32_t *size,
353 uint32_t pptable_id)
354 {
355 const struct smc_firmware_header_v1_0 *hdr;
356 struct amdgpu_device *adev = smu->adev;
357 uint16_t version_major, version_minor;
358 int ret;
359
360 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
361 if (!hdr)
362 return -EINVAL;
363
364 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
365
366 version_major = le16_to_cpu(hdr->header.header_version_major);
367 version_minor = le16_to_cpu(hdr->header.header_version_minor);
368 if (version_major != 2) {
369 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
370 version_major, version_minor);
371 return -EINVAL;
372 }
373
374 switch (version_minor) {
375 case 0:
376 ret = smu_v14_0_set_pptable_v2_0(smu, table, size);
377 break;
378 case 1:
379 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id);
380 break;
381 default:
382 ret = -EINVAL;
383 break;
384 }
385
386 return ret;
387 }
388
smu_v14_0_setup_pptable(struct smu_context * smu)389 int smu_v14_0_setup_pptable(struct smu_context *smu)
390 {
391 struct amdgpu_device *adev = smu->adev;
392 uint32_t size = 0, pptable_id = 0;
393 void *table;
394 int ret = 0;
395
396 /* override pptable_id from driver parameter */
397 if (amdgpu_smu_pptable_id >= 0) {
398 pptable_id = amdgpu_smu_pptable_id;
399 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
400 } else {
401 pptable_id = smu->smu_table.boot_values.pp_table_id;
402 }
403
404 /* force using vbios pptable in sriov mode */
405 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
406 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size);
407 else
408 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
409
410 if (ret)
411 return ret;
412
413 if (!smu->smu_table.power_play_table)
414 smu->smu_table.power_play_table = table;
415 if (!smu->smu_table.power_play_table_size)
416 smu->smu_table.power_play_table_size = size;
417
418 return 0;
419 }
420
smu_v14_0_init_smc_tables(struct smu_context * smu)421 int smu_v14_0_init_smc_tables(struct smu_context *smu)
422 {
423 struct smu_table_context *smu_table = &smu->smu_table;
424 struct smu_table *tables = smu_table->tables;
425 int ret = 0;
426
427 smu_table->driver_pptable =
428 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
429 if (!smu_table->driver_pptable) {
430 ret = -ENOMEM;
431 goto err0_out;
432 }
433
434 smu_table->max_sustainable_clocks =
435 kzalloc(sizeof(struct smu_14_0_max_sustainable_clocks), GFP_KERNEL);
436 if (!smu_table->max_sustainable_clocks) {
437 ret = -ENOMEM;
438 goto err1_out;
439 }
440
441 if (tables[SMU_TABLE_OVERDRIVE].size) {
442 smu_table->overdrive_table =
443 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
444 if (!smu_table->overdrive_table) {
445 ret = -ENOMEM;
446 goto err2_out;
447 }
448
449 smu_table->boot_overdrive_table =
450 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
451 if (!smu_table->boot_overdrive_table) {
452 ret = -ENOMEM;
453 goto err3_out;
454 }
455
456 smu_table->user_overdrive_table =
457 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
458 if (!smu_table->user_overdrive_table) {
459 ret = -ENOMEM;
460 goto err4_out;
461 }
462 }
463
464 smu_table->combo_pptable =
465 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
466 if (!smu_table->combo_pptable) {
467 ret = -ENOMEM;
468 goto err5_out;
469 }
470
471 return 0;
472
473 err5_out:
474 kfree(smu_table->user_overdrive_table);
475 err4_out:
476 kfree(smu_table->boot_overdrive_table);
477 err3_out:
478 kfree(smu_table->overdrive_table);
479 err2_out:
480 kfree(smu_table->max_sustainable_clocks);
481 err1_out:
482 kfree(smu_table->driver_pptable);
483 err0_out:
484 return ret;
485 }
486
smu_v14_0_fini_smc_tables(struct smu_context * smu)487 int smu_v14_0_fini_smc_tables(struct smu_context *smu)
488 {
489 struct smu_table_context *smu_table = &smu->smu_table;
490 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
491
492 kfree(smu_table->gpu_metrics_table);
493 kfree(smu_table->combo_pptable);
494 kfree(smu_table->boot_overdrive_table);
495 kfree(smu_table->overdrive_table);
496 kfree(smu_table->max_sustainable_clocks);
497 kfree(smu_table->driver_pptable);
498 smu_table->gpu_metrics_table = NULL;
499 smu_table->combo_pptable = NULL;
500 smu_table->boot_overdrive_table = NULL;
501 smu_table->overdrive_table = NULL;
502 smu_table->max_sustainable_clocks = NULL;
503 smu_table->driver_pptable = NULL;
504 kfree(smu_table->hardcode_pptable);
505 smu_table->hardcode_pptable = NULL;
506
507 kfree(smu_table->ecc_table);
508 kfree(smu_table->metrics_table);
509 kfree(smu_table->watermarks_table);
510 smu_table->ecc_table = NULL;
511 smu_table->metrics_table = NULL;
512 smu_table->watermarks_table = NULL;
513 smu_table->metrics_time = 0;
514
515 kfree(smu_dpm->dpm_context);
516 kfree(smu_dpm->golden_dpm_context);
517 kfree(smu_dpm->dpm_current_power_state);
518 kfree(smu_dpm->dpm_request_power_state);
519 smu_dpm->dpm_context = NULL;
520 smu_dpm->golden_dpm_context = NULL;
521 smu_dpm->dpm_context_size = 0;
522 smu_dpm->dpm_current_power_state = NULL;
523 smu_dpm->dpm_request_power_state = NULL;
524
525 return 0;
526 }
527
smu_v14_0_init_power(struct smu_context * smu)528 int smu_v14_0_init_power(struct smu_context *smu)
529 {
530 struct smu_power_context *smu_power = &smu->smu_power;
531
532 if (smu_power->power_context || smu_power->power_context_size != 0)
533 return -EINVAL;
534
535 smu_power->power_context = kzalloc(sizeof(struct smu_14_0_dpm_context),
536 GFP_KERNEL);
537 if (!smu_power->power_context)
538 return -ENOMEM;
539 smu_power->power_context_size = sizeof(struct smu_14_0_dpm_context);
540
541 return 0;
542 }
543
smu_v14_0_fini_power(struct smu_context * smu)544 int smu_v14_0_fini_power(struct smu_context *smu)
545 {
546 struct smu_power_context *smu_power = &smu->smu_power;
547
548 if (!smu_power->power_context || smu_power->power_context_size == 0)
549 return -EINVAL;
550
551 kfree(smu_power->power_context);
552 smu_power->power_context = NULL;
553 smu_power->power_context_size = 0;
554
555 return 0;
556 }
557
smu_v14_0_get_vbios_bootup_values(struct smu_context * smu)558 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu)
559 {
560 int ret, index;
561 uint16_t size;
562 uint8_t frev, crev;
563 struct atom_common_table_header *header;
564 struct atom_firmware_info_v3_4 *v_3_4;
565 struct atom_firmware_info_v3_3 *v_3_3;
566 struct atom_firmware_info_v3_1 *v_3_1;
567 struct atom_smu_info_v3_6 *smu_info_v3_6;
568 struct atom_smu_info_v4_0 *smu_info_v4_0;
569
570 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
571 firmwareinfo);
572
573 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
574 (uint8_t **)&header);
575 if (ret)
576 return ret;
577
578 if (header->format_revision != 3) {
579 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n");
580 return -EINVAL;
581 }
582
583 switch (header->content_revision) {
584 case 0:
585 case 1:
586 case 2:
587 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
588 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
589 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
590 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
591 smu->smu_table.boot_values.socclk = 0;
592 smu->smu_table.boot_values.dcefclk = 0;
593 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
594 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
595 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
596 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
597 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
598 smu->smu_table.boot_values.pp_table_id = 0;
599 break;
600 case 3:
601 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
602 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
603 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
604 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
605 smu->smu_table.boot_values.socclk = 0;
606 smu->smu_table.boot_values.dcefclk = 0;
607 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
608 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
609 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
610 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
611 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
612 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
613 break;
614 case 4:
615 default:
616 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
617 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
618 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
619 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
620 smu->smu_table.boot_values.socclk = 0;
621 smu->smu_table.boot_values.dcefclk = 0;
622 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
623 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
624 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
625 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
626 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
627 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
628 break;
629 }
630
631 smu->smu_table.boot_values.format_revision = header->format_revision;
632 smu->smu_table.boot_values.content_revision = header->content_revision;
633
634 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
635 smu_info);
636 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
637 (uint8_t **)&header)) {
638
639 if ((frev == 3) && (crev == 6)) {
640 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
641
642 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
643 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
644 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
645 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
646 } else if ((frev == 3) && (crev == 1)) {
647 return 0;
648 } else if ((frev == 4) && (crev == 0)) {
649 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
650
651 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
652 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
653 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
654 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
655 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
656 } else {
657 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
658 (uint32_t)frev, (uint32_t)crev);
659 }
660 }
661
662 return 0;
663 }
664
665
smu_v14_0_notify_memory_pool_location(struct smu_context * smu)666 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu)
667 {
668 struct smu_table_context *smu_table = &smu->smu_table;
669 struct smu_table *memory_pool = &smu_table->memory_pool;
670 int ret = 0;
671 uint64_t address;
672 uint32_t address_low, address_high;
673
674 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
675 return ret;
676
677 address = memory_pool->mc_address;
678 address_high = (uint32_t)upper_32_bits(address);
679 address_low = (uint32_t)lower_32_bits(address);
680
681 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
682 address_high, NULL);
683 if (ret)
684 return ret;
685 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
686 address_low, NULL);
687 if (ret)
688 return ret;
689 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
690 (uint32_t)memory_pool->size, NULL);
691 if (ret)
692 return ret;
693
694 return ret;
695 }
696
smu_v14_0_set_driver_table_location(struct smu_context * smu)697 int smu_v14_0_set_driver_table_location(struct smu_context *smu)
698 {
699 struct smu_table *driver_table = &smu->smu_table.driver_table;
700 int ret = 0;
701
702 if (driver_table->mc_address) {
703 ret = smu_cmn_send_smc_msg_with_param(smu,
704 SMU_MSG_SetDriverDramAddrHigh,
705 upper_32_bits(driver_table->mc_address),
706 NULL);
707 if (!ret)
708 ret = smu_cmn_send_smc_msg_with_param(smu,
709 SMU_MSG_SetDriverDramAddrLow,
710 lower_32_bits(driver_table->mc_address),
711 NULL);
712 }
713
714 return ret;
715 }
716
smu_v14_0_set_tool_table_location(struct smu_context * smu)717 int smu_v14_0_set_tool_table_location(struct smu_context *smu)
718 {
719 int ret = 0;
720 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
721
722 if (tool_table->mc_address) {
723 ret = smu_cmn_send_smc_msg_with_param(smu,
724 SMU_MSG_SetToolsDramAddrHigh,
725 upper_32_bits(tool_table->mc_address),
726 NULL);
727 if (!ret)
728 ret = smu_cmn_send_smc_msg_with_param(smu,
729 SMU_MSG_SetToolsDramAddrLow,
730 lower_32_bits(tool_table->mc_address),
731 NULL);
732 }
733
734 return ret;
735 }
736
smu_v14_0_set_allowed_mask(struct smu_context * smu)737 int smu_v14_0_set_allowed_mask(struct smu_context *smu)
738 {
739 struct smu_feature *feature = &smu->smu_feature;
740 int ret = 0;
741 uint32_t feature_mask[2];
742
743 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
744 feature->feature_num < 64)
745 return -EINVAL;
746
747 bitmap_to_arr32(feature_mask, feature->allowed, 64);
748
749 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
750 feature_mask[1], NULL);
751 if (ret)
752 return ret;
753
754 return smu_cmn_send_smc_msg_with_param(smu,
755 SMU_MSG_SetAllowedFeaturesMaskLow,
756 feature_mask[0],
757 NULL);
758 }
759
smu_v14_0_gfx_off_control(struct smu_context * smu,bool enable)760 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
761 {
762 int ret = 0;
763 struct amdgpu_device *adev = smu->adev;
764
765 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
766 case IP_VERSION(14, 0, 0):
767 case IP_VERSION(14, 0, 1):
768 case IP_VERSION(14, 0, 2):
769 case IP_VERSION(14, 0, 3):
770 case IP_VERSION(14, 0, 4):
771 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
772 return 0;
773 if (enable)
774 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
775 else
776 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
777 break;
778 default:
779 break;
780 }
781
782 return ret;
783 }
784
smu_v14_0_system_features_control(struct smu_context * smu,bool en)785 int smu_v14_0_system_features_control(struct smu_context *smu,
786 bool en)
787 {
788 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
789 SMU_MSG_DisableAllSmuFeatures), NULL);
790 }
791
smu_v14_0_notify_display_change(struct smu_context * smu)792 int smu_v14_0_notify_display_change(struct smu_context *smu)
793 {
794 int ret = 0;
795
796 if (!smu->pm_enabled)
797 return ret;
798
799 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
800 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
801 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
802
803 return ret;
804 }
805
smu_v14_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)806 int smu_v14_0_get_current_power_limit(struct smu_context *smu,
807 uint32_t *power_limit)
808 {
809 int power_src;
810 int ret = 0;
811
812 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
813 return -EINVAL;
814
815 power_src = smu_cmn_to_asic_specific_index(smu,
816 CMN2ASIC_MAPPING_PWR,
817 smu->adev->pm.ac_power ?
818 SMU_POWER_SOURCE_AC :
819 SMU_POWER_SOURCE_DC);
820 if (power_src < 0)
821 return -EINVAL;
822
823 ret = smu_cmn_send_smc_msg_with_param(smu,
824 SMU_MSG_GetPptLimit,
825 power_src << 16,
826 power_limit);
827 if (ret)
828 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
829
830 return ret;
831 }
832
smu_v14_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)833 int smu_v14_0_set_power_limit(struct smu_context *smu,
834 enum smu_ppt_limit_type limit_type,
835 uint32_t limit)
836 {
837 int ret = 0;
838
839 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
840 return -EINVAL;
841
842 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
843 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
844 return -EOPNOTSUPP;
845 }
846
847 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
848 if (ret) {
849 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
850 return ret;
851 }
852
853 smu->current_power_limit = limit;
854
855 return 0;
856 }
857
smu_v14_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)858 static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
859 struct amdgpu_irq_src *source,
860 unsigned tyep,
861 enum amdgpu_interrupt_state state)
862 {
863 struct smu_context *smu = adev->powerplay.pp_handle;
864 uint32_t low, high;
865 uint32_t val = 0;
866
867 switch (state) {
868 case AMDGPU_IRQ_STATE_DISABLE:
869 /* For THM irqs */
870 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
871 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
872 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
873 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
874
875 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
876
877 /* For MP1 SW irqs */
878 if (smu->is_apu) {
879 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
880 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
881 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
882 } else {
883 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
884 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
885 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
886 }
887
888 break;
889 case AMDGPU_IRQ_STATE_ENABLE:
890 /* For THM irqs */
891 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
892 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
893 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
894 smu->thermal_range.software_shutdown_temp);
895 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
896 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
897 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
898 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
899 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
900 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
901 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
902 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
903 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
904
905 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
906 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
907 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
908 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
909
910 /* For MP1 SW irqs */
911 if (smu->is_apu) {
912 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
913 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
914 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
915 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0, val);
916
917 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
918 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
919 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
920 } else {
921 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
922 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
923 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
924 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
925
926 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
927 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
928 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
929 }
930
931 break;
932 default:
933 break;
934 }
935
936 return 0;
937 }
938
939 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
940 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
941
smu_v14_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)942 static int smu_v14_0_irq_process(struct amdgpu_device *adev,
943 struct amdgpu_irq_src *source,
944 struct amdgpu_iv_entry *entry)
945 {
946 struct smu_context *smu = adev->powerplay.pp_handle;
947 uint32_t client_id = entry->client_id;
948 uint32_t src_id = entry->src_id;
949
950 if (client_id == SOC15_IH_CLIENTID_THM) {
951 switch (src_id) {
952 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
953 schedule_delayed_work(&smu->swctf_delayed_work,
954 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
955 break;
956 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
957 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
958 break;
959 default:
960 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
961 src_id);
962 break;
963 }
964 }
965
966 return 0;
967 }
968
969 static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = {
970 .set = smu_v14_0_set_irq_state,
971 .process = smu_v14_0_irq_process,
972 };
973
smu_v14_0_register_irq_handler(struct smu_context * smu)974 int smu_v14_0_register_irq_handler(struct smu_context *smu)
975 {
976 struct amdgpu_device *adev = smu->adev;
977 struct amdgpu_irq_src *irq_src = &smu->irq_source;
978 int ret = 0;
979
980 if (amdgpu_sriov_vf(adev))
981 return 0;
982
983 irq_src->num_types = 1;
984 irq_src->funcs = &smu_v14_0_irq_funcs;
985
986 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
987 THM_11_0__SRCID__THM_DIG_THERM_L2H,
988 irq_src);
989 if (ret)
990 return ret;
991
992 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
993 THM_11_0__SRCID__THM_DIG_THERM_H2L,
994 irq_src);
995 if (ret)
996 return ret;
997
998 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
999 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1000 irq_src);
1001 if (ret)
1002 return ret;
1003
1004 return ret;
1005 }
1006
smu_v14_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1007 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu,
1008 uint64_t event_arg)
1009 {
1010 int ret = 0;
1011
1012 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1013 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1014
1015 return ret;
1016 }
1017
smu_v14_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1018 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1019 uint64_t event_arg)
1020 {
1021 int ret = -EINVAL;
1022
1023 switch (event) {
1024 case SMU_EVENT_RESET_COMPLETE:
1025 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg);
1026 break;
1027 default:
1028 break;
1029 }
1030
1031 return ret;
1032 }
1033
smu_v14_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1034 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1035 uint32_t *min, uint32_t *max)
1036 {
1037 int ret = 0, clk_id = 0;
1038 uint32_t param = 0;
1039 uint32_t clock_limit;
1040
1041 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1042 switch (clk_type) {
1043 case SMU_MCLK:
1044 case SMU_UCLK:
1045 clock_limit = smu->smu_table.boot_values.uclk;
1046 break;
1047 case SMU_GFXCLK:
1048 case SMU_SCLK:
1049 clock_limit = smu->smu_table.boot_values.gfxclk;
1050 break;
1051 case SMU_SOCCLK:
1052 clock_limit = smu->smu_table.boot_values.socclk;
1053 break;
1054 default:
1055 clock_limit = 0;
1056 break;
1057 }
1058
1059 /* clock in Mhz unit */
1060 if (min)
1061 *min = clock_limit / 100;
1062 if (max)
1063 *max = clock_limit / 100;
1064
1065 return 0;
1066 }
1067
1068 clk_id = smu_cmn_to_asic_specific_index(smu,
1069 CMN2ASIC_MAPPING_CLK,
1070 clk_type);
1071 if (clk_id < 0) {
1072 ret = -EINVAL;
1073 goto failed;
1074 }
1075 param = (clk_id & 0xffff) << 16;
1076
1077 if (max) {
1078 if (smu->adev->pm.ac_power)
1079 ret = smu_cmn_send_smc_msg_with_param(smu,
1080 SMU_MSG_GetMaxDpmFreq,
1081 param,
1082 max);
1083 else
1084 ret = smu_cmn_send_smc_msg_with_param(smu,
1085 SMU_MSG_GetDcModeMaxDpmFreq,
1086 param,
1087 max);
1088 if (ret)
1089 goto failed;
1090 }
1091
1092 if (min) {
1093 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1094 if (ret)
1095 goto failed;
1096 }
1097
1098 failed:
1099 return ret;
1100 }
1101
smu_v14_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1102 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
1103 enum smu_clk_type clk_type,
1104 uint32_t min,
1105 uint32_t max)
1106 {
1107 int ret = 0, clk_id = 0;
1108 uint32_t param;
1109
1110 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1111 return 0;
1112
1113 clk_id = smu_cmn_to_asic_specific_index(smu,
1114 CMN2ASIC_MAPPING_CLK,
1115 clk_type);
1116 if (clk_id < 0)
1117 return clk_id;
1118
1119 if (max > 0) {
1120 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1121 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1122 param, NULL);
1123 if (ret)
1124 goto out;
1125 }
1126
1127 if (min > 0) {
1128 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1129 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1130 param, NULL);
1131 if (ret)
1132 goto out;
1133 }
1134
1135 out:
1136 return ret;
1137 }
1138
smu_v14_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1139 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
1140 enum smu_clk_type clk_type,
1141 uint32_t min,
1142 uint32_t max)
1143 {
1144 int ret = 0, clk_id = 0;
1145 uint32_t param;
1146
1147 if (min <= 0 && max <= 0)
1148 return -EINVAL;
1149
1150 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1151 return 0;
1152
1153 clk_id = smu_cmn_to_asic_specific_index(smu,
1154 CMN2ASIC_MAPPING_CLK,
1155 clk_type);
1156 if (clk_id < 0)
1157 return clk_id;
1158
1159 if (max > 0) {
1160 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1161 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1162 param, NULL);
1163 if (ret)
1164 return ret;
1165 }
1166
1167 if (min > 0) {
1168 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1169 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1170 param, NULL);
1171 if (ret)
1172 return ret;
1173 }
1174
1175 return ret;
1176 }
1177
smu_v14_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1178 int smu_v14_0_set_performance_level(struct smu_context *smu,
1179 enum amd_dpm_forced_level level)
1180 {
1181 struct smu_14_0_dpm_context *dpm_context =
1182 smu->smu_dpm.dpm_context;
1183 struct smu_14_0_dpm_table *gfx_table =
1184 &dpm_context->dpm_tables.gfx_table;
1185 struct smu_14_0_dpm_table *mem_table =
1186 &dpm_context->dpm_tables.uclk_table;
1187 struct smu_14_0_dpm_table *soc_table =
1188 &dpm_context->dpm_tables.soc_table;
1189 struct smu_14_0_dpm_table *vclk_table =
1190 &dpm_context->dpm_tables.vclk_table;
1191 struct smu_14_0_dpm_table *dclk_table =
1192 &dpm_context->dpm_tables.dclk_table;
1193 struct smu_14_0_dpm_table *fclk_table =
1194 &dpm_context->dpm_tables.fclk_table;
1195 struct smu_umd_pstate_table *pstate_table =
1196 &smu->pstate_table;
1197 struct amdgpu_device *adev = smu->adev;
1198 uint32_t sclk_min = 0, sclk_max = 0;
1199 uint32_t mclk_min = 0, mclk_max = 0;
1200 uint32_t socclk_min = 0, socclk_max = 0;
1201 uint32_t vclk_min = 0, vclk_max = 0;
1202 uint32_t dclk_min = 0, dclk_max = 0;
1203 uint32_t fclk_min = 0, fclk_max = 0;
1204 int ret = 0, i;
1205
1206 switch (level) {
1207 case AMD_DPM_FORCED_LEVEL_HIGH:
1208 sclk_min = sclk_max = gfx_table->max;
1209 mclk_min = mclk_max = mem_table->max;
1210 socclk_min = socclk_max = soc_table->max;
1211 vclk_min = vclk_max = vclk_table->max;
1212 dclk_min = dclk_max = dclk_table->max;
1213 fclk_min = fclk_max = fclk_table->max;
1214 break;
1215 case AMD_DPM_FORCED_LEVEL_LOW:
1216 sclk_min = sclk_max = gfx_table->min;
1217 mclk_min = mclk_max = mem_table->min;
1218 socclk_min = socclk_max = soc_table->min;
1219 vclk_min = vclk_max = vclk_table->min;
1220 dclk_min = dclk_max = dclk_table->min;
1221 fclk_min = fclk_max = fclk_table->min;
1222 break;
1223 case AMD_DPM_FORCED_LEVEL_AUTO:
1224 sclk_min = gfx_table->min;
1225 sclk_max = gfx_table->max;
1226 mclk_min = mem_table->min;
1227 mclk_max = mem_table->max;
1228 socclk_min = soc_table->min;
1229 socclk_max = soc_table->max;
1230 vclk_min = vclk_table->min;
1231 vclk_max = vclk_table->max;
1232 dclk_min = dclk_table->min;
1233 dclk_max = dclk_table->max;
1234 fclk_min = fclk_table->min;
1235 fclk_max = fclk_table->max;
1236 break;
1237 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1238 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1239 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1240 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1241 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1242 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1243 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1244 break;
1245 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1246 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1247 break;
1248 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1249 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1250 break;
1251 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1252 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1253 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1254 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1255 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1256 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1257 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1258 break;
1259 case AMD_DPM_FORCED_LEVEL_MANUAL:
1260 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1261 return 0;
1262 default:
1263 dev_err(adev->dev, "Invalid performance level %d\n", level);
1264 return -EINVAL;
1265 }
1266
1267 if (sclk_min && sclk_max) {
1268 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1269 SMU_GFXCLK,
1270 sclk_min,
1271 sclk_max);
1272 if (ret)
1273 return ret;
1274
1275 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1276 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1277 }
1278
1279 if (mclk_min && mclk_max) {
1280 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1281 SMU_MCLK,
1282 mclk_min,
1283 mclk_max);
1284 if (ret)
1285 return ret;
1286
1287 pstate_table->uclk_pstate.curr.min = mclk_min;
1288 pstate_table->uclk_pstate.curr.max = mclk_max;
1289 }
1290
1291 if (socclk_min && socclk_max) {
1292 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1293 SMU_SOCCLK,
1294 socclk_min,
1295 socclk_max);
1296 if (ret)
1297 return ret;
1298
1299 pstate_table->socclk_pstate.curr.min = socclk_min;
1300 pstate_table->socclk_pstate.curr.max = socclk_max;
1301 }
1302
1303 if (vclk_min && vclk_max) {
1304 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1305 if (adev->vcn.harvest_config & (1 << i))
1306 continue;
1307 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1308 i ? SMU_VCLK1 : SMU_VCLK,
1309 vclk_min,
1310 vclk_max);
1311 if (ret)
1312 return ret;
1313 }
1314 pstate_table->vclk_pstate.curr.min = vclk_min;
1315 pstate_table->vclk_pstate.curr.max = vclk_max;
1316 }
1317
1318 if (dclk_min && dclk_max) {
1319 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1320 if (adev->vcn.harvest_config & (1 << i))
1321 continue;
1322 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1323 i ? SMU_DCLK1 : SMU_DCLK,
1324 dclk_min,
1325 dclk_max);
1326 if (ret)
1327 return ret;
1328 }
1329 pstate_table->dclk_pstate.curr.min = dclk_min;
1330 pstate_table->dclk_pstate.curr.max = dclk_max;
1331 }
1332
1333 if (fclk_min && fclk_max) {
1334 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1335 SMU_FCLK,
1336 fclk_min,
1337 fclk_max);
1338 if (ret)
1339 return ret;
1340
1341 pstate_table->fclk_pstate.curr.min = fclk_min;
1342 pstate_table->fclk_pstate.curr.max = fclk_max;
1343 }
1344
1345 return ret;
1346 }
1347
smu_v14_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1348 int smu_v14_0_set_power_source(struct smu_context *smu,
1349 enum smu_power_src_type power_src)
1350 {
1351 int pwr_source;
1352
1353 pwr_source = smu_cmn_to_asic_specific_index(smu,
1354 CMN2ASIC_MAPPING_PWR,
1355 (uint32_t)power_src);
1356 if (pwr_source < 0)
1357 return -EINVAL;
1358
1359 return smu_cmn_send_smc_msg_with_param(smu,
1360 SMU_MSG_NotifyPowerSource,
1361 pwr_source,
1362 NULL);
1363 }
1364
smu_v14_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1365 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu,
1366 enum smu_clk_type clk_type,
1367 uint16_t level,
1368 uint32_t *value)
1369 {
1370 int ret = 0, clk_id = 0;
1371 uint32_t param;
1372
1373 if (!value)
1374 return -EINVAL;
1375
1376 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1377 return 0;
1378
1379 clk_id = smu_cmn_to_asic_specific_index(smu,
1380 CMN2ASIC_MAPPING_CLK,
1381 clk_type);
1382 if (clk_id < 0)
1383 return clk_id;
1384
1385 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1386
1387 ret = smu_cmn_send_smc_msg_with_param(smu,
1388 SMU_MSG_GetDpmFreqByIndex,
1389 param,
1390 value);
1391 if (ret)
1392 return ret;
1393
1394 *value = *value & 0x7fffffff;
1395
1396 return ret;
1397 }
1398
smu_v14_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1399 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu,
1400 enum smu_clk_type clk_type,
1401 uint32_t *value)
1402 {
1403 int ret;
1404
1405 ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1406
1407 return ret;
1408 }
1409
smu_v14_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1410 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu,
1411 enum smu_clk_type clk_type,
1412 bool *is_fine_grained_dpm)
1413 {
1414 int ret = 0, clk_id = 0;
1415 uint32_t param;
1416 uint32_t value;
1417
1418 if (!is_fine_grained_dpm)
1419 return -EINVAL;
1420
1421 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1422 return 0;
1423
1424 clk_id = smu_cmn_to_asic_specific_index(smu,
1425 CMN2ASIC_MAPPING_CLK,
1426 clk_type);
1427 if (clk_id < 0)
1428 return clk_id;
1429
1430 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1431
1432 ret = smu_cmn_send_smc_msg_with_param(smu,
1433 SMU_MSG_GetDpmFreqByIndex,
1434 param,
1435 &value);
1436 if (ret)
1437 return ret;
1438
1439 /*
1440 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1441 * now, we un-support it
1442 */
1443 *is_fine_grained_dpm = value & 0x80000000;
1444
1445 return 0;
1446 }
1447
smu_v14_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_14_0_dpm_table * single_dpm_table)1448 int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
1449 enum smu_clk_type clk_type,
1450 struct smu_14_0_dpm_table *single_dpm_table)
1451 {
1452 int ret = 0;
1453 uint32_t clk;
1454 int i;
1455
1456 ret = smu_v14_0_get_dpm_level_count(smu,
1457 clk_type,
1458 &single_dpm_table->count);
1459 if (ret) {
1460 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1461 return ret;
1462 }
1463
1464 ret = smu_v14_0_get_fine_grained_status(smu,
1465 clk_type,
1466 &single_dpm_table->is_fine_grained);
1467 if (ret) {
1468 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1469 return ret;
1470 }
1471
1472 for (i = 0; i < single_dpm_table->count; i++) {
1473 ret = smu_v14_0_get_dpm_freq_by_index(smu,
1474 clk_type,
1475 i,
1476 &clk);
1477 if (ret) {
1478 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1479 return ret;
1480 }
1481
1482 single_dpm_table->dpm_levels[i].value = clk;
1483 single_dpm_table->dpm_levels[i].enabled = true;
1484
1485 if (i == 0)
1486 single_dpm_table->min = clk;
1487 else if (i == single_dpm_table->count - 1)
1488 single_dpm_table->max = clk;
1489 }
1490
1491 return 0;
1492 }
1493
smu_v14_0_set_vcn_enable(struct smu_context * smu,bool enable)1494 int smu_v14_0_set_vcn_enable(struct smu_context *smu,
1495 bool enable)
1496 {
1497 struct amdgpu_device *adev = smu->adev;
1498 int i, ret = 0;
1499
1500 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1501 if (adev->vcn.harvest_config & (1 << i))
1502 continue;
1503
1504 if (smu->is_apu) {
1505 if (i == 0)
1506 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1507 SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
1508 i << 16U, NULL);
1509 else if (i == 1)
1510 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1511 SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
1512 i << 16U, NULL);
1513 } else {
1514 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1515 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1516 i << 16U, NULL);
1517 }
1518
1519 if (ret)
1520 return ret;
1521 }
1522
1523 return ret;
1524 }
1525
smu_v14_0_set_jpeg_enable(struct smu_context * smu,bool enable)1526 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
1527 bool enable)
1528 {
1529 struct amdgpu_device *adev = smu->adev;
1530 int i, ret = 0;
1531
1532 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
1533 if (adev->jpeg.harvest_config & (1 << i))
1534 continue;
1535
1536 if (smu->is_apu) {
1537 if (i == 0)
1538 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1539 SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0,
1540 i << 16U, NULL);
1541 else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1542 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1543 SMU_MSG_PowerUpJpeg1 : SMU_MSG_PowerDownJpeg1,
1544 i << 16U, NULL);
1545 } else {
1546 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1547 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1548 i << 16U, NULL);
1549 }
1550
1551 if (ret)
1552 return ret;
1553 }
1554
1555 return ret;
1556 }
1557
smu_v14_0_run_btc(struct smu_context * smu)1558 int smu_v14_0_run_btc(struct smu_context *smu)
1559 {
1560 int res;
1561
1562 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1563 if (res)
1564 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
1565
1566 return res;
1567 }
1568
smu_v14_0_gpo_control(struct smu_context * smu,bool enablement)1569 int smu_v14_0_gpo_control(struct smu_context *smu,
1570 bool enablement)
1571 {
1572 int res;
1573
1574 res = smu_cmn_send_smc_msg_with_param(smu,
1575 SMU_MSG_AllowGpo,
1576 enablement ? 1 : 0,
1577 NULL);
1578 if (res)
1579 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
1580
1581 return res;
1582 }
1583
smu_v14_0_deep_sleep_control(struct smu_context * smu,bool enablement)1584 int smu_v14_0_deep_sleep_control(struct smu_context *smu,
1585 bool enablement)
1586 {
1587 struct amdgpu_device *adev = smu->adev;
1588 int ret = 0;
1589
1590 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1591 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1592 if (ret) {
1593 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
1594 return ret;
1595 }
1596 }
1597
1598 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
1599 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
1600 if (ret) {
1601 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
1602 return ret;
1603 }
1604 }
1605
1606 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
1607 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
1608 if (ret) {
1609 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
1610 return ret;
1611 }
1612 }
1613
1614 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
1615 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
1616 if (ret) {
1617 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
1618 return ret;
1619 }
1620 }
1621
1622 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
1623 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
1624 if (ret) {
1625 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
1626 return ret;
1627 }
1628 }
1629
1630 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
1631 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
1632 if (ret) {
1633 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
1634 return ret;
1635 }
1636 }
1637
1638 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
1639 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
1640 if (ret) {
1641 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
1642 return ret;
1643 }
1644 }
1645
1646 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
1647 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
1648 if (ret) {
1649 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
1650 return ret;
1651 }
1652 }
1653
1654 return ret;
1655 }
1656
smu_v14_0_gfx_ulv_control(struct smu_context * smu,bool enablement)1657 int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
1658 bool enablement)
1659 {
1660 int ret = 0;
1661
1662 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1663 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1664
1665 return ret;
1666 }
1667
smu_v14_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1668 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
1669 enum smu_baco_seq baco_seq)
1670 {
1671 struct smu_baco_context *smu_baco = &smu->smu_baco;
1672 int ret;
1673
1674 ret = smu_cmn_send_smc_msg_with_param(smu,
1675 SMU_MSG_ArmD3,
1676 baco_seq,
1677 NULL);
1678 if (ret)
1679 return ret;
1680
1681 if (baco_seq == BACO_SEQ_BAMACO ||
1682 baco_seq == BACO_SEQ_BACO)
1683 smu_baco->state = SMU_BACO_STATE_ENTER;
1684 else
1685 smu_baco->state = SMU_BACO_STATE_EXIT;
1686
1687 return 0;
1688 }
1689
smu_v14_0_get_bamaco_support(struct smu_context * smu)1690 int smu_v14_0_get_bamaco_support(struct smu_context *smu)
1691 {
1692 struct smu_baco_context *smu_baco = &smu->smu_baco;
1693 int bamaco_support = 0;
1694
1695 if (amdgpu_sriov_vf(smu->adev) ||
1696 !smu_baco->platform_support)
1697 return 0;
1698
1699 if (smu_baco->maco_support)
1700 bamaco_support |= MACO_SUPPORT;
1701
1702 /* return true if ASIC is in BACO state already */
1703 if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1704 return (bamaco_support |= BACO_SUPPORT);
1705
1706 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1707 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1708 return 0;
1709
1710 return (bamaco_support |= BACO_SUPPORT);
1711 }
1712
smu_v14_0_baco_get_state(struct smu_context * smu)1713 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu)
1714 {
1715 struct smu_baco_context *smu_baco = &smu->smu_baco;
1716
1717 return smu_baco->state;
1718 }
1719
smu_v14_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1720 int smu_v14_0_baco_set_state(struct smu_context *smu,
1721 enum smu_baco_state state)
1722 {
1723 struct smu_baco_context *smu_baco = &smu->smu_baco;
1724 struct amdgpu_device *adev = smu->adev;
1725 int ret = 0;
1726
1727 if (smu_v14_0_baco_get_state(smu) == state)
1728 return 0;
1729
1730 if (state == SMU_BACO_STATE_ENTER) {
1731 ret = smu_cmn_send_smc_msg_with_param(smu,
1732 SMU_MSG_EnterBaco,
1733 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
1734 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
1735 NULL);
1736 } else {
1737 ret = smu_cmn_send_smc_msg(smu,
1738 SMU_MSG_ExitBaco,
1739 NULL);
1740 if (ret)
1741 return ret;
1742
1743 /* clear vbios scratch 6 and 7 for coming asic reinit */
1744 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1745 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1746 }
1747
1748 if (!ret)
1749 smu_baco->state = state;
1750
1751 return ret;
1752 }
1753
smu_v14_0_baco_enter(struct smu_context * smu)1754 int smu_v14_0_baco_enter(struct smu_context *smu)
1755 {
1756 int ret = 0;
1757
1758 ret = smu_v14_0_baco_set_state(smu,
1759 SMU_BACO_STATE_ENTER);
1760 if (ret)
1761 return ret;
1762
1763 msleep(10);
1764
1765 return ret;
1766 }
1767
smu_v14_0_baco_exit(struct smu_context * smu)1768 int smu_v14_0_baco_exit(struct smu_context *smu)
1769 {
1770 return smu_v14_0_baco_set_state(smu,
1771 SMU_BACO_STATE_EXIT);
1772 }
1773
smu_v14_0_set_gfx_power_up_by_imu(struct smu_context * smu)1774 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
1775 {
1776 uint16_t index;
1777 struct amdgpu_device *adev = smu->adev;
1778
1779 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1780 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
1781 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
1782 }
1783
1784 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1785 SMU_MSG_EnableGfxImu);
1786 return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE);
1787 }
1788
smu_v14_0_set_default_dpm_tables(struct smu_context * smu)1789 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)
1790 {
1791 struct smu_table_context *smu_table = &smu->smu_table;
1792
1793 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
1794 smu_table->clocks_table, false);
1795 }
1796
smu_v14_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1797 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
1798 enum PP_OD_DPM_TABLE_COMMAND type,
1799 long input[], uint32_t size)
1800 {
1801 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1802 int ret = 0;
1803
1804 /* Only allowed in manual mode */
1805 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1806 return -EINVAL;
1807
1808 switch (type) {
1809 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1810 if (size != 2) {
1811 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1812 return -EINVAL;
1813 }
1814
1815 if (input[0] == 0) {
1816 if (input[1] < smu->gfx_default_hard_min_freq) {
1817 dev_warn(smu->adev->dev,
1818 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1819 input[1], smu->gfx_default_hard_min_freq);
1820 return -EINVAL;
1821 }
1822 smu->gfx_actual_hard_min_freq = input[1];
1823 } else if (input[0] == 1) {
1824 if (input[1] > smu->gfx_default_soft_max_freq) {
1825 dev_warn(smu->adev->dev,
1826 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1827 input[1], smu->gfx_default_soft_max_freq);
1828 return -EINVAL;
1829 }
1830 smu->gfx_actual_soft_max_freq = input[1];
1831 } else {
1832 return -EINVAL;
1833 }
1834 break;
1835 case PP_OD_RESTORE_DEFAULT_TABLE:
1836 if (size != 0) {
1837 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1838 return -EINVAL;
1839 }
1840 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1841 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1842 break;
1843 case PP_OD_COMMIT_DPM_TABLE:
1844 if (size != 0) {
1845 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1846 return -EINVAL;
1847 }
1848 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1849 dev_err(smu->adev->dev,
1850 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1851 smu->gfx_actual_hard_min_freq,
1852 smu->gfx_actual_soft_max_freq);
1853 return -EINVAL;
1854 }
1855
1856 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1857 smu->gfx_actual_hard_min_freq,
1858 NULL);
1859 if (ret) {
1860 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1861 return ret;
1862 }
1863
1864 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1865 smu->gfx_actual_soft_max_freq,
1866 NULL);
1867 if (ret) {
1868 dev_err(smu->adev->dev, "Set soft max sclk failed!");
1869 return ret;
1870 }
1871 break;
1872 default:
1873 return -ENOSYS;
1874 }
1875
1876 return ret;
1877 }
1878
smu_v14_0_allow_ih_interrupt(struct smu_context * smu)1879 static int smu_v14_0_allow_ih_interrupt(struct smu_context *smu)
1880 {
1881 return smu_cmn_send_smc_msg(smu,
1882 SMU_MSG_AllowIHHostInterrupt,
1883 NULL);
1884 }
1885
smu_v14_0_process_pending_interrupt(struct smu_context * smu)1886 static int smu_v14_0_process_pending_interrupt(struct smu_context *smu)
1887 {
1888 int ret = 0;
1889
1890 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1891 ret = smu_v14_0_allow_ih_interrupt(smu);
1892
1893 return ret;
1894 }
1895
smu_v14_0_enable_thermal_alert(struct smu_context * smu)1896 int smu_v14_0_enable_thermal_alert(struct smu_context *smu)
1897 {
1898 int ret = 0;
1899
1900 if (!smu->irq_source.num_types)
1901 return 0;
1902
1903 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1904 if (ret)
1905 return ret;
1906
1907 return smu_v14_0_process_pending_interrupt(smu);
1908 }
1909
smu_v14_0_disable_thermal_alert(struct smu_context * smu)1910 int smu_v14_0_disable_thermal_alert(struct smu_context *smu)
1911 {
1912 if (!smu->irq_source.num_types)
1913 return 0;
1914
1915 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1916 }
1917