1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SWSMU_CODE_LAYER_L3 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v14_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "amdgpu_ras.h" 39 #include "smu_cmn.h" 40 41 #include "asic_reg/thm/thm_14_0_2_offset.h" 42 #include "asic_reg/thm/thm_14_0_2_sh_mask.h" 43 #include "asic_reg/mp/mp_14_0_2_offset.h" 44 #include "asic_reg/mp/mp_14_0_2_sh_mask.h" 45 46 #define regMP1_SMN_IH_SW_INT_mp1_14_0_0 0x0341 47 #define regMP1_SMN_IH_SW_INT_mp1_14_0_0_BASE_IDX 0 48 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0 0x0342 49 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0 50 51 const int decoded_link_speed[5] = {1, 2, 3, 4, 5}; 52 const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32}; 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin"); 64 MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin"); 65 MODULE_FIRMWARE("amdgpu/smu_14_0_3_kicker.bin"); 66 67 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1 68 69 int smu_v14_0_init_microcode(struct smu_context *smu) 70 { 71 struct amdgpu_device *adev = smu->adev; 72 char ucode_prefix[30]; 73 int err = 0; 74 const struct smc_firmware_header_v1_0 *hdr; 75 const struct common_firmware_header *header; 76 struct amdgpu_firmware_info *ucode = NULL; 77 78 /* doesn't need to load smu firmware in IOV mode */ 79 if (amdgpu_sriov_vf(adev)) 80 return 0; 81 82 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); 83 if (amdgpu_is_kicker_fw(adev)) 84 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 85 "amdgpu/%s_kicker.bin", ucode_prefix); 86 else 87 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 88 "amdgpu/%s.bin", ucode_prefix); 89 if (err) 90 goto out; 91 92 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 93 amdgpu_ucode_print_smc_hdr(&hdr->header); 94 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 95 96 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 97 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 98 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 99 ucode->fw = adev->pm.fw; 100 header = (const struct common_firmware_header *)ucode->fw->data; 101 adev->firmware.fw_size += 102 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 103 } 104 105 out: 106 if (err) 107 amdgpu_ucode_release(&adev->pm.fw); 108 return err; 109 } 110 111 void smu_v14_0_fini_microcode(struct smu_context *smu) 112 { 113 struct amdgpu_device *adev = smu->adev; 114 115 amdgpu_ucode_release(&adev->pm.fw); 116 adev->pm.fw_version = 0; 117 } 118 119 int smu_v14_0_load_microcode(struct smu_context *smu) 120 { 121 struct amdgpu_device *adev = smu->adev; 122 const uint32_t *src; 123 const struct smc_firmware_header_v1_0 *hdr; 124 uint32_t addr_start = MP1_SRAM; 125 uint32_t i; 126 uint32_t smc_fw_size; 127 uint32_t mp1_fw_flags; 128 129 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 130 src = (const uint32_t *)(adev->pm.fw->data + 131 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 132 smc_fw_size = hdr->header.ucode_size_bytes; 133 134 for (i = 1; i < smc_fw_size/4 - 1; i++) { 135 WREG32_PCIE(addr_start, src[i]); 136 addr_start += 4; 137 } 138 139 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 140 1 & MP1_SMN_PUB_CTRL__LX3_RESET_MASK); 141 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 142 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK); 143 144 for (i = 0; i < adev->usec_timeout; i++) { 145 if (smu->is_apu) 146 mp1_fw_flags = RREG32_PCIE(MP1_Public | 147 (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff)); 148 else 149 mp1_fw_flags = RREG32_PCIE(MP1_Public | 150 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 151 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 152 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 153 break; 154 udelay(1); 155 } 156 157 if (i == adev->usec_timeout) 158 return -ETIME; 159 160 return 0; 161 } 162 163 int smu_v14_0_init_pptable_microcode(struct smu_context *smu) 164 { 165 struct amdgpu_device *adev = smu->adev; 166 struct amdgpu_firmware_info *ucode = NULL; 167 uint32_t size = 0, pptable_id = 0; 168 int ret = 0; 169 void *table; 170 171 /* doesn't need to load smu firmware in IOV mode */ 172 if (amdgpu_sriov_vf(adev)) 173 return 0; 174 175 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 176 return 0; 177 178 if (!adev->scpm_enabled) 179 return 0; 180 181 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2)) || 182 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 3))) 183 return 0; 184 185 /* override pptable_id from driver parameter */ 186 if (amdgpu_smu_pptable_id >= 0) { 187 pptable_id = amdgpu_smu_pptable_id; 188 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 189 } else { 190 pptable_id = smu->smu_table.boot_values.pp_table_id; 191 } 192 193 /* "pptable_id == 0" means vbios carries the pptable. */ 194 if (!pptable_id) 195 return 0; 196 197 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 198 if (ret) 199 return ret; 200 201 smu->pptable_firmware.data = table; 202 smu->pptable_firmware.size = size; 203 204 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; 205 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; 206 ucode->fw = &smu->pptable_firmware; 207 adev->firmware.fw_size += 208 ALIGN(smu->pptable_firmware.size, PAGE_SIZE); 209 210 return 0; 211 } 212 213 int smu_v14_0_check_fw_status(struct smu_context *smu) 214 { 215 struct amdgpu_device *adev = smu->adev; 216 uint32_t mp1_fw_flags; 217 218 if (smu->is_apu) 219 mp1_fw_flags = RREG32_PCIE(MP1_Public | 220 (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff)); 221 else 222 mp1_fw_flags = RREG32_PCIE(MP1_Public | 223 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 224 225 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 226 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 227 return 0; 228 229 return -EIO; 230 } 231 232 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 233 { 234 struct amdgpu_device *adev = smu->adev; 235 uint32_t ppt_offset_bytes; 236 const struct smc_firmware_header_v2_0 *v2; 237 238 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 239 240 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 241 *size = le32_to_cpu(v2->ppt_size_bytes); 242 *table = (uint8_t *)v2 + ppt_offset_bytes; 243 244 return 0; 245 } 246 247 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table, 248 uint32_t *size, uint32_t pptable_id) 249 { 250 struct amdgpu_device *adev = smu->adev; 251 const struct smc_firmware_header_v2_1 *v2_1; 252 struct smc_soft_pptable_entry *entries; 253 uint32_t pptable_count = 0; 254 int i = 0; 255 256 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 257 entries = (struct smc_soft_pptable_entry *) 258 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 259 pptable_count = le32_to_cpu(v2_1->pptable_count); 260 for (i = 0; i < pptable_count; i++) { 261 if (le32_to_cpu(entries[i].id) == pptable_id) { 262 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 263 *size = le32_to_cpu(entries[i].ppt_size_bytes); 264 break; 265 } 266 } 267 268 if (i == pptable_count) 269 return -EINVAL; 270 271 return 0; 272 } 273 274 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) 275 { 276 struct amdgpu_device *adev = smu->adev; 277 uint16_t atom_table_size; 278 uint8_t frev, crev; 279 int ret, index; 280 281 dev_info(adev->dev, "use vbios provided pptable\n"); 282 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 283 powerplayinfo); 284 285 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 286 (uint8_t **)table); 287 if (ret) 288 return ret; 289 290 if (size) 291 *size = atom_table_size; 292 293 return 0; 294 } 295 296 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu, 297 void **table, 298 uint32_t *size, 299 uint32_t pptable_id) 300 { 301 const struct smc_firmware_header_v1_0 *hdr; 302 struct amdgpu_device *adev = smu->adev; 303 uint16_t version_major, version_minor; 304 int ret; 305 306 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 307 if (!hdr) 308 return -EINVAL; 309 310 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); 311 312 version_major = le16_to_cpu(hdr->header.header_version_major); 313 version_minor = le16_to_cpu(hdr->header.header_version_minor); 314 if (version_major != 2) { 315 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", 316 version_major, version_minor); 317 return -EINVAL; 318 } 319 320 switch (version_minor) { 321 case 0: 322 ret = smu_v14_0_set_pptable_v2_0(smu, table, size); 323 break; 324 case 1: 325 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id); 326 break; 327 default: 328 ret = -EINVAL; 329 break; 330 } 331 332 return ret; 333 } 334 335 int smu_v14_0_setup_pptable(struct smu_context *smu) 336 { 337 struct amdgpu_device *adev = smu->adev; 338 uint32_t size = 0, pptable_id = 0; 339 void *table; 340 int ret = 0; 341 342 /* override pptable_id from driver parameter */ 343 if (amdgpu_smu_pptable_id >= 0) { 344 pptable_id = amdgpu_smu_pptable_id; 345 dev_info(adev->dev, "override pptable id %d\n", pptable_id); 346 } else { 347 pptable_id = smu->smu_table.boot_values.pp_table_id; 348 } 349 350 /* force using vbios pptable in sriov mode */ 351 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) 352 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size); 353 else 354 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); 355 356 if (ret) 357 return ret; 358 359 if (!smu->smu_table.power_play_table) 360 smu->smu_table.power_play_table = table; 361 if (!smu->smu_table.power_play_table_size) 362 smu->smu_table.power_play_table_size = size; 363 364 return 0; 365 } 366 367 int smu_v14_0_init_smc_tables(struct smu_context *smu) 368 { 369 struct smu_table_context *smu_table = &smu->smu_table; 370 struct smu_table *tables = smu_table->tables; 371 int ret = 0; 372 373 smu_table->driver_pptable = 374 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 375 if (!smu_table->driver_pptable) { 376 ret = -ENOMEM; 377 goto err0_out; 378 } 379 380 smu_table->max_sustainable_clocks = 381 kzalloc_obj(struct smu_14_0_max_sustainable_clocks); 382 if (!smu_table->max_sustainable_clocks) { 383 ret = -ENOMEM; 384 goto err1_out; 385 } 386 387 if (tables[SMU_TABLE_OVERDRIVE].size) { 388 smu_table->overdrive_table = 389 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 390 if (!smu_table->overdrive_table) { 391 ret = -ENOMEM; 392 goto err2_out; 393 } 394 395 smu_table->boot_overdrive_table = 396 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 397 if (!smu_table->boot_overdrive_table) { 398 ret = -ENOMEM; 399 goto err3_out; 400 } 401 402 smu_table->user_overdrive_table = 403 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 404 if (!smu_table->user_overdrive_table) { 405 ret = -ENOMEM; 406 goto err4_out; 407 } 408 } 409 410 smu_table->combo_pptable = 411 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); 412 if (!smu_table->combo_pptable) { 413 ret = -ENOMEM; 414 goto err5_out; 415 } 416 417 return 0; 418 419 err5_out: 420 kfree(smu_table->user_overdrive_table); 421 err4_out: 422 kfree(smu_table->boot_overdrive_table); 423 err3_out: 424 kfree(smu_table->overdrive_table); 425 err2_out: 426 kfree(smu_table->max_sustainable_clocks); 427 err1_out: 428 kfree(smu_table->driver_pptable); 429 err0_out: 430 return ret; 431 } 432 433 int smu_v14_0_fini_smc_tables(struct smu_context *smu) 434 { 435 struct smu_table_context *smu_table = &smu->smu_table; 436 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 437 438 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); 439 kfree(smu_table->combo_pptable); 440 kfree(smu_table->boot_overdrive_table); 441 kfree(smu_table->overdrive_table); 442 kfree(smu_table->max_sustainable_clocks); 443 kfree(smu_table->driver_pptable); 444 smu_table->combo_pptable = NULL; 445 smu_table->boot_overdrive_table = NULL; 446 smu_table->overdrive_table = NULL; 447 smu_table->max_sustainable_clocks = NULL; 448 smu_table->driver_pptable = NULL; 449 kfree(smu_table->hardcode_pptable); 450 smu_table->hardcode_pptable = NULL; 451 452 kfree(smu_table->ecc_table); 453 kfree(smu_table->metrics_table); 454 kfree(smu_table->watermarks_table); 455 smu_table->ecc_table = NULL; 456 smu_table->metrics_table = NULL; 457 smu_table->watermarks_table = NULL; 458 smu_table->metrics_time = 0; 459 460 kfree(smu_dpm->dpm_context); 461 kfree(smu_dpm->golden_dpm_context); 462 kfree(smu_dpm->dpm_current_power_state); 463 kfree(smu_dpm->dpm_request_power_state); 464 smu_dpm->dpm_context = NULL; 465 smu_dpm->golden_dpm_context = NULL; 466 smu_dpm->dpm_context_size = 0; 467 smu_dpm->dpm_current_power_state = NULL; 468 smu_dpm->dpm_request_power_state = NULL; 469 470 return 0; 471 } 472 473 int smu_v14_0_init_power(struct smu_context *smu) 474 { 475 struct smu_power_context *smu_power = &smu->smu_power; 476 477 if (smu_power->power_context || smu_power->power_context_size != 0) 478 return -EINVAL; 479 480 smu_power->power_context = kzalloc_obj(struct smu_14_0_dpm_context); 481 if (!smu_power->power_context) 482 return -ENOMEM; 483 smu_power->power_context_size = sizeof(struct smu_14_0_dpm_context); 484 485 return 0; 486 } 487 488 int smu_v14_0_fini_power(struct smu_context *smu) 489 { 490 struct smu_power_context *smu_power = &smu->smu_power; 491 492 if (!smu_power->power_context || smu_power->power_context_size == 0) 493 return -EINVAL; 494 495 kfree(smu_power->power_context); 496 smu_power->power_context = NULL; 497 smu_power->power_context_size = 0; 498 499 return 0; 500 } 501 502 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu) 503 { 504 int ret, index; 505 uint16_t size; 506 uint8_t frev, crev; 507 struct atom_common_table_header *header; 508 struct atom_firmware_info_v3_4 *v_3_4; 509 struct atom_firmware_info_v3_3 *v_3_3; 510 struct atom_firmware_info_v3_1 *v_3_1; 511 struct atom_smu_info_v3_6 *smu_info_v3_6; 512 struct atom_smu_info_v4_0 *smu_info_v4_0; 513 514 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 515 firmwareinfo); 516 517 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 518 (uint8_t **)&header); 519 if (ret) 520 return ret; 521 522 if (header->format_revision != 3) { 523 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n"); 524 return -EINVAL; 525 } 526 527 switch (header->content_revision) { 528 case 0: 529 case 1: 530 case 2: 531 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 532 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 533 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 534 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 535 smu->smu_table.boot_values.socclk = 0; 536 smu->smu_table.boot_values.dcefclk = 0; 537 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 538 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 539 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 540 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 541 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 542 smu->smu_table.boot_values.pp_table_id = 0; 543 break; 544 case 3: 545 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 546 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 547 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 548 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 549 smu->smu_table.boot_values.socclk = 0; 550 smu->smu_table.boot_values.dcefclk = 0; 551 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 552 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 553 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 554 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 555 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 556 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 557 break; 558 case 4: 559 default: 560 v_3_4 = (struct atom_firmware_info_v3_4 *)header; 561 smu->smu_table.boot_values.revision = v_3_4->firmware_revision; 562 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; 563 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; 564 smu->smu_table.boot_values.socclk = 0; 565 smu->smu_table.boot_values.dcefclk = 0; 566 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; 567 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; 568 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; 569 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; 570 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; 571 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; 572 break; 573 } 574 575 smu->smu_table.boot_values.format_revision = header->format_revision; 576 smu->smu_table.boot_values.content_revision = header->content_revision; 577 578 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 579 smu_info); 580 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 581 (uint8_t **)&header)) { 582 583 if ((frev == 3) && (crev == 6)) { 584 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; 585 586 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; 587 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; 588 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; 589 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; 590 } else if ((frev == 3) && (crev == 1)) { 591 return 0; 592 } else if ((frev == 4) && (crev == 0)) { 593 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; 594 595 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; 596 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; 597 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; 598 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; 599 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; 600 } else { 601 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", 602 (uint32_t)frev, (uint32_t)crev); 603 } 604 } 605 606 return 0; 607 } 608 609 610 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu) 611 { 612 struct smu_table_context *smu_table = &smu->smu_table; 613 struct smu_table *memory_pool = &smu_table->memory_pool; 614 int ret = 0; 615 uint64_t address; 616 uint32_t address_low, address_high; 617 618 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 619 return ret; 620 621 address = memory_pool->mc_address; 622 address_high = (uint32_t)upper_32_bits(address); 623 address_low = (uint32_t)lower_32_bits(address); 624 625 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 626 address_high, NULL); 627 if (ret) 628 return ret; 629 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 630 address_low, NULL); 631 if (ret) 632 return ret; 633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 634 (uint32_t)memory_pool->size, NULL); 635 if (ret) 636 return ret; 637 638 return ret; 639 } 640 641 int smu_v14_0_set_driver_table_location(struct smu_context *smu) 642 { 643 struct smu_table *driver_table = &smu->smu_table.driver_table; 644 int ret = 0; 645 646 if (driver_table->mc_address) { 647 ret = smu_cmn_send_smc_msg_with_param(smu, 648 SMU_MSG_SetDriverDramAddrHigh, 649 upper_32_bits(driver_table->mc_address), 650 NULL); 651 if (!ret) 652 ret = smu_cmn_send_smc_msg_with_param(smu, 653 SMU_MSG_SetDriverDramAddrLow, 654 lower_32_bits(driver_table->mc_address), 655 NULL); 656 } 657 658 return ret; 659 } 660 661 int smu_v14_0_set_tool_table_location(struct smu_context *smu) 662 { 663 int ret = 0; 664 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 665 666 if (tool_table->mc_address) { 667 ret = smu_cmn_send_smc_msg_with_param(smu, 668 SMU_MSG_SetToolsDramAddrHigh, 669 upper_32_bits(tool_table->mc_address), 670 NULL); 671 if (!ret) 672 ret = smu_cmn_send_smc_msg_with_param(smu, 673 SMU_MSG_SetToolsDramAddrLow, 674 lower_32_bits(tool_table->mc_address), 675 NULL); 676 } 677 678 return ret; 679 } 680 681 int smu_v14_0_set_allowed_mask(struct smu_context *smu) 682 { 683 struct smu_feature *feature = &smu->smu_feature; 684 int ret = 0; 685 uint32_t feature_mask[2]; 686 687 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 688 feature->feature_num < SMU_FEATURE_NUM_DEFAULT) 689 return -EINVAL; 690 691 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); 692 693 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 694 feature_mask[1], NULL); 695 if (ret) 696 return ret; 697 698 return smu_cmn_send_smc_msg_with_param(smu, 699 SMU_MSG_SetAllowedFeaturesMaskLow, 700 feature_mask[0], 701 NULL); 702 } 703 704 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable) 705 { 706 int ret = 0; 707 struct amdgpu_device *adev = smu->adev; 708 709 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 710 case IP_VERSION(14, 0, 0): 711 case IP_VERSION(14, 0, 1): 712 case IP_VERSION(14, 0, 2): 713 case IP_VERSION(14, 0, 3): 714 case IP_VERSION(14, 0, 4): 715 case IP_VERSION(14, 0, 5): 716 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 717 return 0; 718 if (enable) 719 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 720 else 721 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 722 break; 723 default: 724 break; 725 } 726 727 return ret; 728 } 729 730 int smu_v14_0_system_features_control(struct smu_context *smu, 731 bool en) 732 { 733 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 734 SMU_MSG_DisableAllSmuFeatures), NULL); 735 } 736 737 int smu_v14_0_notify_display_change(struct smu_context *smu) 738 { 739 int ret = 0; 740 741 if (!smu->pm_enabled) 742 return ret; 743 744 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 745 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 746 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 747 748 return ret; 749 } 750 751 int smu_v14_0_get_current_power_limit(struct smu_context *smu, 752 uint32_t *power_limit) 753 { 754 int power_src; 755 int ret = 0; 756 757 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 758 return -EINVAL; 759 760 power_src = smu_cmn_to_asic_specific_index(smu, 761 CMN2ASIC_MAPPING_PWR, 762 smu->adev->pm.ac_power ? 763 SMU_POWER_SOURCE_AC : 764 SMU_POWER_SOURCE_DC); 765 if (power_src < 0) 766 return -EINVAL; 767 768 ret = smu_cmn_send_smc_msg_with_param(smu, 769 SMU_MSG_GetPptLimit, 770 power_src << 16, 771 power_limit); 772 if (ret) 773 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 774 775 return ret; 776 } 777 778 int smu_v14_0_set_power_limit(struct smu_context *smu, 779 enum smu_ppt_limit_type limit_type, 780 uint32_t limit) 781 { 782 int ret = 0; 783 784 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 785 return -EINVAL; 786 787 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 788 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 789 return -EOPNOTSUPP; 790 } 791 792 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); 793 if (ret) { 794 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 795 return ret; 796 } 797 798 smu->current_power_limit = limit; 799 800 return 0; 801 } 802 803 static int smu_v14_0_set_irq_state(struct amdgpu_device *adev, 804 struct amdgpu_irq_src *source, 805 unsigned tyep, 806 enum amdgpu_interrupt_state state) 807 { 808 struct smu_context *smu = adev->powerplay.pp_handle; 809 uint32_t low, high; 810 uint32_t val = 0; 811 812 switch (state) { 813 case AMDGPU_IRQ_STATE_DISABLE: 814 /* For THM irqs */ 815 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 816 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 817 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 818 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 819 820 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0); 821 822 /* For MP1 SW irqs */ 823 if (smu->is_apu) { 824 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0); 825 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 826 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val); 827 } else { 828 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 829 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 830 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 831 } 832 833 break; 834 case AMDGPU_IRQ_STATE_ENABLE: 835 /* For THM irqs */ 836 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 837 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 838 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 839 smu->thermal_range.software_shutdown_temp); 840 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 841 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 842 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 843 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 844 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 845 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 846 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 847 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 848 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val); 849 850 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 851 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 852 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 853 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val); 854 855 /* For MP1 SW irqs */ 856 if (smu->is_apu) { 857 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0); 858 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 859 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 860 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0, val); 861 862 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0); 863 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 864 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val); 865 } else { 866 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); 867 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 868 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 869 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); 870 871 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 872 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 873 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); 874 } 875 876 break; 877 default: 878 break; 879 } 880 881 return 0; 882 } 883 884 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 885 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 886 887 static int smu_v14_0_irq_process(struct amdgpu_device *adev, 888 struct amdgpu_irq_src *source, 889 struct amdgpu_iv_entry *entry) 890 { 891 struct smu_context *smu = adev->powerplay.pp_handle; 892 uint32_t client_id = entry->client_id; 893 uint32_t src_id = entry->src_id; 894 895 /* 896 * ctxid is used to distinguish different 897 * events for SMCToHost interrupt. 898 */ 899 uint32_t ctxid = entry->src_data[0]; 900 uint32_t data; 901 uint32_t high; 902 903 if (client_id == SOC15_IH_CLIENTID_THM) { 904 switch (src_id) { 905 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 906 schedule_delayed_work(&smu->swctf_delayed_work, 907 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY)); 908 break; 909 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 910 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 911 break; 912 default: 913 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 914 src_id); 915 break; 916 } 917 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 918 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) { 919 /* ACK SMUToHost interrupt */ 920 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); 921 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 922 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); 923 924 switch (ctxid) { 925 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL: 926 high = smu->thermal_range.software_shutdown_temp + 927 smu->thermal_range.software_shutdown_temp_offset; 928 high = min_t(typeof(high), 929 SMU_THERMAL_MAXIMUM_ALERT_TEMP, 930 high); 931 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n", 932 high, 933 smu->thermal_range.software_shutdown_temp_offset); 934 935 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 936 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, 937 DIG_THERM_INTH, 938 (high & 0xff)); 939 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 940 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); 941 break; 942 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY: 943 high = min_t(typeof(high), 944 SMU_THERMAL_MAXIMUM_ALERT_TEMP, 945 smu->thermal_range.software_shutdown_temp); 946 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high); 947 948 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); 949 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, 950 DIG_THERM_INTH, 951 (high & 0xff)); 952 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 953 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); 954 break; 955 default: 956 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n", 957 ctxid, client_id); 958 break; 959 } 960 } 961 } 962 963 return 0; 964 } 965 966 static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = { 967 .set = smu_v14_0_set_irq_state, 968 .process = smu_v14_0_irq_process, 969 }; 970 971 int smu_v14_0_register_irq_handler(struct smu_context *smu) 972 { 973 struct amdgpu_device *adev = smu->adev; 974 struct amdgpu_irq_src *irq_src = &smu->irq_source; 975 int ret = 0; 976 977 if (amdgpu_sriov_vf(adev)) 978 return 0; 979 980 irq_src->num_types = 1; 981 irq_src->funcs = &smu_v14_0_irq_funcs; 982 983 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 984 THM_11_0__SRCID__THM_DIG_THERM_L2H, 985 irq_src); 986 if (ret) 987 return ret; 988 989 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 990 THM_11_0__SRCID__THM_DIG_THERM_H2L, 991 irq_src); 992 if (ret) 993 return ret; 994 995 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 996 SMU_IH_INTERRUPT_ID_TO_DRIVER, 997 irq_src); 998 if (ret) 999 return ret; 1000 1001 return ret; 1002 } 1003 1004 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu, 1005 uint64_t event_arg) 1006 { 1007 int ret = 0; 1008 1009 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); 1010 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); 1011 1012 return ret; 1013 } 1014 1015 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1016 uint64_t event_arg) 1017 { 1018 int ret = -EINVAL; 1019 1020 switch (event) { 1021 case SMU_EVENT_RESET_COMPLETE: 1022 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg); 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 return ret; 1029 } 1030 1031 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1032 uint32_t *min, uint32_t *max) 1033 { 1034 int ret = 0, clk_id = 0; 1035 uint32_t param = 0; 1036 uint32_t clock_limit; 1037 1038 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1039 switch (clk_type) { 1040 case SMU_MCLK: 1041 case SMU_UCLK: 1042 clock_limit = smu->smu_table.boot_values.uclk; 1043 break; 1044 case SMU_GFXCLK: 1045 case SMU_SCLK: 1046 clock_limit = smu->smu_table.boot_values.gfxclk; 1047 break; 1048 case SMU_SOCCLK: 1049 clock_limit = smu->smu_table.boot_values.socclk; 1050 break; 1051 default: 1052 clock_limit = 0; 1053 break; 1054 } 1055 1056 /* clock in Mhz unit */ 1057 if (min) 1058 *min = clock_limit / 100; 1059 if (max) 1060 *max = clock_limit / 100; 1061 1062 return 0; 1063 } 1064 1065 clk_id = smu_cmn_to_asic_specific_index(smu, 1066 CMN2ASIC_MAPPING_CLK, 1067 clk_type); 1068 if (clk_id < 0) { 1069 ret = -EINVAL; 1070 goto failed; 1071 } 1072 param = (clk_id & 0xffff) << 16; 1073 1074 if (max) { 1075 if (smu->adev->pm.ac_power) 1076 ret = smu_cmn_send_smc_msg_with_param(smu, 1077 SMU_MSG_GetMaxDpmFreq, 1078 param, 1079 max); 1080 else 1081 ret = smu_cmn_send_smc_msg_with_param(smu, 1082 SMU_MSG_GetDcModeMaxDpmFreq, 1083 param, 1084 max); 1085 if (ret) 1086 goto failed; 1087 } 1088 1089 if (min) { 1090 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1091 if (ret) 1092 goto failed; 1093 } 1094 1095 failed: 1096 return ret; 1097 } 1098 1099 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, 1100 enum smu_clk_type clk_type, 1101 uint32_t min, 1102 uint32_t max, 1103 bool automatic) 1104 { 1105 int ret = 0, clk_id = 0; 1106 uint32_t param; 1107 1108 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1109 return 0; 1110 1111 clk_id = smu_cmn_to_asic_specific_index(smu, 1112 CMN2ASIC_MAPPING_CLK, 1113 clk_type); 1114 if (clk_id < 0) 1115 return clk_id; 1116 1117 if (max > 0) { 1118 max = SMU_V14_SOFT_FREQ_ROUND(max); 1119 if (automatic) 1120 param = (uint32_t)((clk_id << 16) | 0xffff); 1121 else 1122 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1123 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1124 param, NULL); 1125 if (ret) 1126 goto out; 1127 } 1128 1129 if (min > 0) { 1130 if (automatic) 1131 param = (uint32_t)((clk_id << 16) | 0); 1132 else 1133 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1134 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1135 param, NULL); 1136 if (ret) 1137 goto out; 1138 } 1139 1140 out: 1141 return ret; 1142 } 1143 1144 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu, 1145 enum smu_clk_type clk_type, 1146 uint32_t min, 1147 uint32_t max) 1148 { 1149 int ret = 0, clk_id = 0; 1150 uint32_t param; 1151 1152 if (min <= 0 && max <= 0) 1153 return -EINVAL; 1154 1155 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1156 return 0; 1157 1158 clk_id = smu_cmn_to_asic_specific_index(smu, 1159 CMN2ASIC_MAPPING_CLK, 1160 clk_type); 1161 if (clk_id < 0) 1162 return clk_id; 1163 1164 if (max > 0) { 1165 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1166 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1167 param, NULL); 1168 if (ret) 1169 return ret; 1170 } 1171 1172 if (min > 0) { 1173 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1174 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1175 param, NULL); 1176 if (ret) 1177 return ret; 1178 } 1179 1180 return ret; 1181 } 1182 1183 int smu_v14_0_set_performance_level(struct smu_context *smu, 1184 enum amd_dpm_forced_level level) 1185 { 1186 struct smu_14_0_dpm_context *dpm_context = 1187 smu->smu_dpm.dpm_context; 1188 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; 1189 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; 1190 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; 1191 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; 1192 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; 1193 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; 1194 struct smu_umd_pstate_table *pstate_table = 1195 &smu->pstate_table; 1196 struct amdgpu_device *adev = smu->adev; 1197 uint32_t sclk_min = 0, sclk_max = 0; 1198 uint32_t mclk_min = 0, mclk_max = 0; 1199 uint32_t socclk_min = 0, socclk_max = 0; 1200 uint32_t vclk_min = 0, vclk_max = 0; 1201 uint32_t dclk_min = 0, dclk_max = 0; 1202 uint32_t fclk_min = 0, fclk_max = 0; 1203 int ret = 0, i; 1204 bool auto_level = false; 1205 1206 switch (level) { 1207 case AMD_DPM_FORCED_LEVEL_HIGH: 1208 sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); 1209 mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); 1210 socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); 1211 vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table); 1212 dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table); 1213 fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table); 1214 break; 1215 case AMD_DPM_FORCED_LEVEL_LOW: 1216 sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); 1217 mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); 1218 socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); 1219 vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table); 1220 dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table); 1221 fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table); 1222 break; 1223 case AMD_DPM_FORCED_LEVEL_AUTO: 1224 sclk_min = SMU_DPM_TABLE_MIN(gfx_table); 1225 sclk_max = SMU_DPM_TABLE_MAX(gfx_table); 1226 mclk_min = SMU_DPM_TABLE_MIN(mem_table); 1227 mclk_max = SMU_DPM_TABLE_MAX(mem_table); 1228 socclk_min = SMU_DPM_TABLE_MIN(soc_table); 1229 socclk_max = SMU_DPM_TABLE_MAX(soc_table); 1230 vclk_min = SMU_DPM_TABLE_MIN(vclk_table); 1231 vclk_max = SMU_DPM_TABLE_MAX(vclk_table); 1232 dclk_min = SMU_DPM_TABLE_MIN(dclk_table); 1233 dclk_max = SMU_DPM_TABLE_MAX(dclk_table); 1234 fclk_min = SMU_DPM_TABLE_MIN(fclk_table); 1235 fclk_max = SMU_DPM_TABLE_MAX(fclk_table); 1236 auto_level = true; 1237 break; 1238 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1239 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1240 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1241 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1242 vclk_min = vclk_max = pstate_table->vclk_pstate.standard; 1243 dclk_min = dclk_max = pstate_table->dclk_pstate.standard; 1244 fclk_min = fclk_max = pstate_table->fclk_pstate.standard; 1245 break; 1246 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1247 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1248 break; 1249 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1250 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1251 break; 1252 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1253 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1254 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1255 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1256 vclk_min = vclk_max = pstate_table->vclk_pstate.peak; 1257 dclk_min = dclk_max = pstate_table->dclk_pstate.peak; 1258 fclk_min = fclk_max = pstate_table->fclk_pstate.peak; 1259 break; 1260 case AMD_DPM_FORCED_LEVEL_MANUAL: 1261 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1262 return 0; 1263 default: 1264 dev_err(adev->dev, "Invalid performance level %d\n", level); 1265 return -EINVAL; 1266 } 1267 1268 if (sclk_min && sclk_max) { 1269 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1270 SMU_GFXCLK, 1271 sclk_min, 1272 sclk_max, 1273 auto_level); 1274 if (ret) 1275 return ret; 1276 1277 pstate_table->gfxclk_pstate.curr.min = sclk_min; 1278 pstate_table->gfxclk_pstate.curr.max = sclk_max; 1279 } 1280 1281 if (mclk_min && mclk_max) { 1282 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1283 SMU_MCLK, 1284 mclk_min, 1285 mclk_max, 1286 auto_level); 1287 if (ret) 1288 return ret; 1289 1290 pstate_table->uclk_pstate.curr.min = mclk_min; 1291 pstate_table->uclk_pstate.curr.max = mclk_max; 1292 } 1293 1294 if (socclk_min && socclk_max) { 1295 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1296 SMU_SOCCLK, 1297 socclk_min, 1298 socclk_max, 1299 auto_level); 1300 if (ret) 1301 return ret; 1302 1303 pstate_table->socclk_pstate.curr.min = socclk_min; 1304 pstate_table->socclk_pstate.curr.max = socclk_max; 1305 } 1306 1307 if (vclk_min && vclk_max) { 1308 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1309 if (adev->vcn.harvest_config & (1 << i)) 1310 continue; 1311 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1312 i ? SMU_VCLK1 : SMU_VCLK, 1313 vclk_min, 1314 vclk_max, 1315 auto_level); 1316 if (ret) 1317 return ret; 1318 } 1319 pstate_table->vclk_pstate.curr.min = vclk_min; 1320 pstate_table->vclk_pstate.curr.max = vclk_max; 1321 } 1322 1323 if (dclk_min && dclk_max) { 1324 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1325 if (adev->vcn.harvest_config & (1 << i)) 1326 continue; 1327 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1328 i ? SMU_DCLK1 : SMU_DCLK, 1329 dclk_min, 1330 dclk_max, 1331 auto_level); 1332 if (ret) 1333 return ret; 1334 } 1335 pstate_table->dclk_pstate.curr.min = dclk_min; 1336 pstate_table->dclk_pstate.curr.max = dclk_max; 1337 } 1338 1339 if (fclk_min && fclk_max) { 1340 ret = smu_v14_0_set_soft_freq_limited_range(smu, 1341 SMU_FCLK, 1342 fclk_min, 1343 fclk_max, 1344 auto_level); 1345 if (ret) 1346 return ret; 1347 1348 pstate_table->fclk_pstate.curr.min = fclk_min; 1349 pstate_table->fclk_pstate.curr.max = fclk_max; 1350 } 1351 1352 return ret; 1353 } 1354 1355 int smu_v14_0_set_power_source(struct smu_context *smu, 1356 enum smu_power_src_type power_src) 1357 { 1358 int pwr_source; 1359 1360 pwr_source = smu_cmn_to_asic_specific_index(smu, 1361 CMN2ASIC_MAPPING_PWR, 1362 (uint32_t)power_src); 1363 if (pwr_source < 0) 1364 return -EINVAL; 1365 1366 return smu_cmn_send_smc_msg_with_param(smu, 1367 SMU_MSG_NotifyPowerSource, 1368 pwr_source, 1369 NULL); 1370 } 1371 1372 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu, 1373 enum smu_clk_type clk_type, 1374 uint16_t level, 1375 uint32_t *value) 1376 { 1377 int ret = 0, clk_id = 0; 1378 uint32_t param; 1379 1380 if (!value) 1381 return -EINVAL; 1382 1383 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1384 return 0; 1385 1386 clk_id = smu_cmn_to_asic_specific_index(smu, 1387 CMN2ASIC_MAPPING_CLK, 1388 clk_type); 1389 if (clk_id < 0) 1390 return clk_id; 1391 1392 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1393 1394 ret = smu_cmn_send_smc_msg_with_param(smu, 1395 SMU_MSG_GetDpmFreqByIndex, 1396 param, 1397 value); 1398 if (ret) 1399 return ret; 1400 1401 *value = *value & 0x7fffffff; 1402 1403 return ret; 1404 } 1405 1406 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu, 1407 enum smu_clk_type clk_type, 1408 uint32_t *value) 1409 { 1410 int ret; 1411 1412 ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); 1413 1414 return ret; 1415 } 1416 1417 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu, 1418 enum smu_clk_type clk_type, 1419 bool *is_fine_grained_dpm) 1420 { 1421 int ret = 0, clk_id = 0; 1422 uint32_t param; 1423 uint32_t value; 1424 1425 if (!is_fine_grained_dpm) 1426 return -EINVAL; 1427 1428 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1429 return 0; 1430 1431 clk_id = smu_cmn_to_asic_specific_index(smu, 1432 CMN2ASIC_MAPPING_CLK, 1433 clk_type); 1434 if (clk_id < 0) 1435 return clk_id; 1436 1437 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); 1438 1439 ret = smu_cmn_send_smc_msg_with_param(smu, 1440 SMU_MSG_GetDpmFreqByIndex, 1441 param, 1442 &value); 1443 if (ret) 1444 return ret; 1445 1446 /* 1447 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM 1448 * now, we un-support it 1449 */ 1450 *is_fine_grained_dpm = value & 0x80000000; 1451 1452 return 0; 1453 } 1454 1455 int smu_v14_0_set_single_dpm_table(struct smu_context *smu, 1456 enum smu_clk_type clk_type, 1457 struct smu_dpm_table *single_dpm_table) 1458 { 1459 int ret = 0; 1460 uint32_t clk; 1461 int i; 1462 bool is_fine_grained; 1463 1464 ret = smu_v14_0_get_dpm_level_count(smu, 1465 clk_type, 1466 &single_dpm_table->count); 1467 if (ret) { 1468 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 1469 return ret; 1470 } 1471 1472 ret = smu_v14_0_get_fine_grained_status(smu, clk_type, 1473 &is_fine_grained); 1474 if (ret) { 1475 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); 1476 return ret; 1477 } 1478 if (is_fine_grained) 1479 single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; 1480 1481 for (i = 0; i < single_dpm_table->count; i++) { 1482 ret = smu_v14_0_get_dpm_freq_by_index(smu, 1483 clk_type, 1484 i, 1485 &clk); 1486 if (ret) { 1487 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 1488 return ret; 1489 } 1490 1491 single_dpm_table->dpm_levels[i].value = clk; 1492 single_dpm_table->dpm_levels[i].enabled = true; 1493 } 1494 1495 return 0; 1496 } 1497 1498 int smu_v14_0_set_vcn_enable(struct smu_context *smu, 1499 bool enable, 1500 int inst) 1501 { 1502 struct amdgpu_device *adev = smu->adev; 1503 int ret = 0; 1504 1505 if (adev->vcn.harvest_config & (1 << inst)) 1506 return ret; 1507 1508 if (smu->is_apu) { 1509 if (inst == 0) 1510 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1511 SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0, 1512 inst << 16U, NULL); 1513 else if (inst == 1) 1514 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1515 SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1, 1516 inst << 16U, NULL); 1517 } else { 1518 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1519 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1520 inst << 16U, NULL); 1521 } 1522 1523 return ret; 1524 } 1525 1526 int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 1527 bool enable) 1528 { 1529 struct amdgpu_device *adev = smu->adev; 1530 int i, ret = 0; 1531 1532 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 1533 if (adev->jpeg.harvest_config & (1 << i)) 1534 continue; 1535 1536 if (smu->is_apu) { 1537 if (i == 0) 1538 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1539 SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0, 1540 i << 16U, NULL); 1541 else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) 1542 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1543 SMU_MSG_PowerUpJpeg1 : SMU_MSG_PowerDownJpeg1, 1544 i << 16U, NULL); 1545 } else { 1546 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1547 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, 1548 i << 16U, NULL); 1549 } 1550 1551 if (ret) 1552 return ret; 1553 } 1554 1555 return ret; 1556 } 1557 1558 int smu_v14_0_run_btc(struct smu_context *smu) 1559 { 1560 int res; 1561 1562 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 1563 if (res) 1564 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 1565 1566 return res; 1567 } 1568 1569 int smu_v14_0_gpo_control(struct smu_context *smu, 1570 bool enablement) 1571 { 1572 int res; 1573 1574 res = smu_cmn_send_smc_msg_with_param(smu, 1575 SMU_MSG_AllowGpo, 1576 enablement ? 1 : 0, 1577 NULL); 1578 if (res) 1579 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); 1580 1581 return res; 1582 } 1583 1584 int smu_v14_0_deep_sleep_control(struct smu_context *smu, 1585 bool enablement) 1586 { 1587 struct amdgpu_device *adev = smu->adev; 1588 int ret = 0; 1589 1590 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 1591 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 1592 if (ret) { 1593 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 1594 return ret; 1595 } 1596 } 1597 1598 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 1599 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 1600 if (ret) { 1601 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 1602 return ret; 1603 } 1604 } 1605 1606 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 1607 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 1608 if (ret) { 1609 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 1610 return ret; 1611 } 1612 } 1613 1614 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 1615 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 1616 if (ret) { 1617 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 1618 return ret; 1619 } 1620 } 1621 1622 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 1623 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 1624 if (ret) { 1625 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 1626 return ret; 1627 } 1628 } 1629 1630 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { 1631 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); 1632 if (ret) { 1633 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); 1634 return ret; 1635 } 1636 } 1637 1638 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { 1639 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); 1640 if (ret) { 1641 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); 1642 return ret; 1643 } 1644 } 1645 1646 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { 1647 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); 1648 if (ret) { 1649 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); 1650 return ret; 1651 } 1652 } 1653 1654 return ret; 1655 } 1656 1657 int smu_v14_0_gfx_ulv_control(struct smu_context *smu, 1658 bool enablement) 1659 { 1660 int ret = 0; 1661 1662 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 1663 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 1664 1665 return ret; 1666 } 1667 1668 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu, 1669 enum smu_baco_seq baco_seq) 1670 { 1671 struct smu_baco_context *smu_baco = &smu->smu_baco; 1672 int ret; 1673 1674 ret = smu_cmn_send_smc_msg_with_param(smu, 1675 SMU_MSG_ArmD3, 1676 baco_seq, 1677 NULL); 1678 if (ret) 1679 return ret; 1680 1681 if (baco_seq == BACO_SEQ_BAMACO || 1682 baco_seq == BACO_SEQ_BACO) 1683 smu_baco->state = SMU_BACO_STATE_ENTER; 1684 else 1685 smu_baco->state = SMU_BACO_STATE_EXIT; 1686 1687 return 0; 1688 } 1689 1690 int smu_v14_0_get_bamaco_support(struct smu_context *smu) 1691 { 1692 struct smu_baco_context *smu_baco = &smu->smu_baco; 1693 int bamaco_support = 0; 1694 1695 if (amdgpu_sriov_vf(smu->adev) || 1696 !smu_baco->platform_support) 1697 return 0; 1698 1699 if (smu_baco->maco_support) 1700 bamaco_support |= MACO_SUPPORT; 1701 1702 /* return true if ASIC is in BACO state already */ 1703 if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) 1704 return (bamaco_support |= BACO_SUPPORT); 1705 1706 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1707 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1708 return 0; 1709 1710 return (bamaco_support |= BACO_SUPPORT); 1711 } 1712 1713 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu) 1714 { 1715 struct smu_baco_context *smu_baco = &smu->smu_baco; 1716 1717 return smu_baco->state; 1718 } 1719 1720 int smu_v14_0_baco_set_state(struct smu_context *smu, 1721 enum smu_baco_state state) 1722 { 1723 struct smu_baco_context *smu_baco = &smu->smu_baco; 1724 struct amdgpu_device *adev = smu->adev; 1725 int ret = 0; 1726 1727 if (smu_v14_0_baco_get_state(smu) == state) 1728 return 0; 1729 1730 if (state == SMU_BACO_STATE_ENTER) { 1731 ret = smu_cmn_send_smc_msg_with_param(smu, 1732 SMU_MSG_EnterBaco, 1733 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ? 1734 BACO_SEQ_BAMACO : BACO_SEQ_BACO, 1735 NULL); 1736 } else { 1737 ret = smu_cmn_send_smc_msg(smu, 1738 SMU_MSG_ExitBaco, 1739 NULL); 1740 if (ret) 1741 return ret; 1742 1743 /* clear vbios scratch 6 and 7 for coming asic reinit */ 1744 WREG32(adev->bios_scratch_reg_offset + 6, 0); 1745 WREG32(adev->bios_scratch_reg_offset + 7, 0); 1746 } 1747 1748 if (!ret) 1749 smu_baco->state = state; 1750 1751 return ret; 1752 } 1753 1754 int smu_v14_0_baco_enter(struct smu_context *smu) 1755 { 1756 int ret = 0; 1757 1758 ret = smu_v14_0_baco_set_state(smu, 1759 SMU_BACO_STATE_ENTER); 1760 if (ret) 1761 return ret; 1762 1763 msleep(10); 1764 1765 return ret; 1766 } 1767 1768 int smu_v14_0_baco_exit(struct smu_context *smu) 1769 { 1770 return smu_v14_0_baco_set_state(smu, 1771 SMU_BACO_STATE_EXIT); 1772 } 1773 1774 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu) 1775 { 1776 struct smu_msg_ctl *ctl = &smu->msg_ctl; 1777 struct amdgpu_device *adev = smu->adev; 1778 int ret; 1779 1780 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1781 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, 1782 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); 1783 } 1784 1785 mutex_lock(&ctl->lock); 1786 ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, 1787 ENABLE_IMU_ARG_GFXOFF_ENABLE); 1788 mutex_unlock(&ctl->lock); 1789 1790 return ret; 1791 } 1792 1793 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu) 1794 { 1795 struct smu_table_context *smu_table = &smu->smu_table; 1796 1797 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, 1798 smu_table->clocks_table, false); 1799 } 1800 1801 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu, 1802 enum PP_OD_DPM_TABLE_COMMAND type, 1803 long input[], uint32_t size) 1804 { 1805 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); 1806 int ret = 0; 1807 1808 /* Only allowed in manual mode */ 1809 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1810 return -EINVAL; 1811 1812 switch (type) { 1813 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1814 if (size != 2) { 1815 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1816 return -EINVAL; 1817 } 1818 1819 if (input[0] == 0) { 1820 if (input[1] < smu->gfx_default_hard_min_freq) { 1821 dev_warn(smu->adev->dev, 1822 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1823 input[1], smu->gfx_default_hard_min_freq); 1824 return -EINVAL; 1825 } 1826 smu->gfx_actual_hard_min_freq = input[1]; 1827 } else if (input[0] == 1) { 1828 if (input[1] > smu->gfx_default_soft_max_freq) { 1829 dev_warn(smu->adev->dev, 1830 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1831 input[1], smu->gfx_default_soft_max_freq); 1832 return -EINVAL; 1833 } 1834 smu->gfx_actual_soft_max_freq = input[1]; 1835 } else { 1836 return -EINVAL; 1837 } 1838 break; 1839 case PP_OD_RESTORE_DEFAULT_TABLE: 1840 if (size != 0) { 1841 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1842 return -EINVAL; 1843 } 1844 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1845 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1846 break; 1847 case PP_OD_COMMIT_DPM_TABLE: 1848 if (size != 0) { 1849 dev_err(smu->adev->dev, "Input parameter number not correct\n"); 1850 return -EINVAL; 1851 } 1852 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { 1853 dev_err(smu->adev->dev, 1854 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1855 smu->gfx_actual_hard_min_freq, 1856 smu->gfx_actual_soft_max_freq); 1857 return -EINVAL; 1858 } 1859 1860 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1861 smu->gfx_actual_hard_min_freq, 1862 NULL); 1863 if (ret) { 1864 dev_err(smu->adev->dev, "Set hard min sclk failed!"); 1865 return ret; 1866 } 1867 1868 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1869 smu->gfx_actual_soft_max_freq, 1870 NULL); 1871 if (ret) { 1872 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1873 return ret; 1874 } 1875 if (smu->gfx_actual_hard_min_freq != smu->gfx_default_hard_min_freq || 1876 smu->gfx_actual_soft_max_freq != smu->gfx_default_soft_max_freq) 1877 smu->user_dpm_profile.user_od = true; 1878 else 1879 smu->user_dpm_profile.user_od = false; 1880 break; 1881 default: 1882 return -ENOSYS; 1883 } 1884 1885 return ret; 1886 } 1887 1888 static int smu_v14_0_allow_ih_interrupt(struct smu_context *smu) 1889 { 1890 return smu_cmn_send_smc_msg(smu, 1891 SMU_MSG_AllowIHHostInterrupt, 1892 NULL); 1893 } 1894 1895 int smu_v14_0_enable_thermal_alert(struct smu_context *smu) 1896 { 1897 int ret = 0; 1898 1899 if (!smu->irq_source.num_types) 1900 return 0; 1901 1902 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1903 if (ret) 1904 return ret; 1905 1906 return smu_v14_0_allow_ih_interrupt(smu); 1907 } 1908 1909 int smu_v14_0_disable_thermal_alert(struct smu_context *smu) 1910 { 1911 if (!smu->irq_source.num_types) 1912 return 0; 1913 1914 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1915 } 1916