1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63
64 #define mmMP1_SMN_C2PMSG_66 0x0282
65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
66
67 #define mmMP1_SMN_C2PMSG_82 0x0292
68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
69
70 #define mmMP1_SMN_C2PMSG_90 0x029a
71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
72
73 #define SMU13_VOLTAGE_SCALE 4
74
75 #define LINK_WIDTH_MAX 6
76 #define LINK_SPEED_MAX 3
77
78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 #define smnPCIE_LC_SPEED_CNTL 0x11140290
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
84
85 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
86
87 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
88
89 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
90 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
91
smu_v13_0_init_microcode(struct smu_context * smu)92 int smu_v13_0_init_microcode(struct smu_context *smu)
93 {
94 struct amdgpu_device *adev = smu->adev;
95 char ucode_prefix[15];
96 int err = 0;
97 const struct smc_firmware_header_v1_0 *hdr;
98 const struct common_firmware_header *header;
99 struct amdgpu_firmware_info *ucode = NULL;
100
101 /* doesn't need to load smu firmware in IOV mode */
102 if (amdgpu_sriov_vf(adev))
103 return 0;
104
105 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
106 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
107 "amdgpu/%s.bin", ucode_prefix);
108 if (err)
109 goto out;
110
111 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
112 amdgpu_ucode_print_smc_hdr(&hdr->header);
113 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
114
115 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
116 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
117 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
118 ucode->fw = adev->pm.fw;
119 header = (const struct common_firmware_header *)ucode->fw->data;
120 adev->firmware.fw_size +=
121 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
122 }
123
124 out:
125 if (err)
126 amdgpu_ucode_release(&adev->pm.fw);
127 return err;
128 }
129
smu_v13_0_fini_microcode(struct smu_context * smu)130 void smu_v13_0_fini_microcode(struct smu_context *smu)
131 {
132 struct amdgpu_device *adev = smu->adev;
133
134 amdgpu_ucode_release(&adev->pm.fw);
135 adev->pm.fw_version = 0;
136 }
137
smu_v13_0_load_microcode(struct smu_context * smu)138 int smu_v13_0_load_microcode(struct smu_context *smu)
139 {
140 #if 0
141 struct amdgpu_device *adev = smu->adev;
142 const uint32_t *src;
143 const struct smc_firmware_header_v1_0 *hdr;
144 uint32_t addr_start = MP1_SRAM;
145 uint32_t i;
146 uint32_t smc_fw_size;
147 uint32_t mp1_fw_flags;
148
149 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
150 src = (const uint32_t *)(adev->pm.fw->data +
151 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
152 smc_fw_size = hdr->header.ucode_size_bytes;
153
154 for (i = 1; i < smc_fw_size/4 - 1; i++) {
155 WREG32_PCIE(addr_start, src[i]);
156 addr_start += 4;
157 }
158
159 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
160 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
161 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
162 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
163
164 for (i = 0; i < adev->usec_timeout; i++) {
165 mp1_fw_flags = RREG32_PCIE(MP1_Public |
166 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
167 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
168 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
169 break;
170 udelay(1);
171 }
172
173 if (i == adev->usec_timeout)
174 return -ETIME;
175 #endif
176
177 return 0;
178 }
179
smu_v13_0_init_pptable_microcode(struct smu_context * smu)180 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
181 {
182 struct amdgpu_device *adev = smu->adev;
183 struct amdgpu_firmware_info *ucode = NULL;
184 uint32_t size = 0, pptable_id = 0;
185 int ret = 0;
186 void *table;
187
188 /* doesn't need to load smu firmware in IOV mode */
189 if (amdgpu_sriov_vf(adev))
190 return 0;
191
192 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
193 return 0;
194
195 if (!adev->scpm_enabled)
196 return 0;
197
198 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 7)) ||
199 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) ||
200 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)))
201 return 0;
202
203 /* override pptable_id from driver parameter */
204 if (amdgpu_smu_pptable_id >= 0) {
205 pptable_id = amdgpu_smu_pptable_id;
206 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
207 } else {
208 pptable_id = smu->smu_table.boot_values.pp_table_id;
209 }
210
211 /* "pptable_id == 0" means vbios carries the pptable. */
212 if (!pptable_id)
213 return 0;
214
215 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
216 if (ret)
217 return ret;
218
219 smu->pptable_firmware.data = table;
220 smu->pptable_firmware.size = size;
221
222 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
223 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
224 ucode->fw = &smu->pptable_firmware;
225 adev->firmware.fw_size +=
226 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
227
228 return 0;
229 }
230
smu_v13_0_check_fw_status(struct smu_context * smu)231 int smu_v13_0_check_fw_status(struct smu_context *smu)
232 {
233 struct amdgpu_device *adev = smu->adev;
234 uint32_t mp1_fw_flags;
235
236 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
237 case IP_VERSION(13, 0, 4):
238 case IP_VERSION(13, 0, 11):
239 mp1_fw_flags = RREG32_PCIE(MP1_Public |
240 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
241 break;
242 default:
243 mp1_fw_flags = RREG32_PCIE(MP1_Public |
244 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
245 break;
246 }
247
248 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
249 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
250 return 0;
251
252 return -EIO;
253 }
254
smu_v13_0_check_fw_version(struct smu_context * smu)255 int smu_v13_0_check_fw_version(struct smu_context *smu)
256 {
257 struct amdgpu_device *adev = smu->adev;
258 uint32_t if_version = 0xff, smu_version = 0xff;
259 uint8_t smu_program, smu_major, smu_minor, smu_debug;
260 int ret = 0;
261
262 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
263 if (ret)
264 return ret;
265
266 smu_program = (smu_version >> 24) & 0xff;
267 smu_major = (smu_version >> 16) & 0xff;
268 smu_minor = (smu_version >> 8) & 0xff;
269 smu_debug = (smu_version >> 0) & 0xff;
270 if (smu->is_apu ||
271 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||
272 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))
273 adev->pm.fw_version = smu_version;
274
275 /* only for dGPU w/ SMU13*/
276 if (adev->pm.fw)
277 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
278 smu_program, smu_version, smu_major, smu_minor, smu_debug);
279
280 /*
281 * 1. if_version mismatch is not critical as our fw is designed
282 * to be backward compatible.
283 * 2. New fw usually brings some optimizations. But that's visible
284 * only on the paired driver.
285 * Considering above, we just leave user a verbal message instead
286 * of halt driver loading.
287 */
288 if (if_version != smu->smc_driver_if_version) {
289 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
290 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
291 smu->smc_driver_if_version, if_version,
292 smu_program, smu_version, smu_major, smu_minor, smu_debug);
293 dev_info(adev->dev, "SMU driver if version not matched\n");
294 }
295
296 return ret;
297 }
298
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)299 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
300 {
301 struct amdgpu_device *adev = smu->adev;
302 uint32_t ppt_offset_bytes;
303 const struct smc_firmware_header_v2_0 *v2;
304
305 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
306
307 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
308 *size = le32_to_cpu(v2->ppt_size_bytes);
309 *table = (uint8_t *)v2 + ppt_offset_bytes;
310
311 return 0;
312 }
313
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)314 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
315 uint32_t *size, uint32_t pptable_id)
316 {
317 struct amdgpu_device *adev = smu->adev;
318 const struct smc_firmware_header_v2_1 *v2_1;
319 struct smc_soft_pptable_entry *entries;
320 uint32_t pptable_count = 0;
321 int i = 0;
322
323 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
324 entries = (struct smc_soft_pptable_entry *)
325 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
326 pptable_count = le32_to_cpu(v2_1->pptable_count);
327 for (i = 0; i < pptable_count; i++) {
328 if (le32_to_cpu(entries[i].id) == pptable_id) {
329 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
330 *size = le32_to_cpu(entries[i].ppt_size_bytes);
331 break;
332 }
333 }
334
335 if (i == pptable_count)
336 return -EINVAL;
337
338 return 0;
339 }
340
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)341 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
342 {
343 struct amdgpu_device *adev = smu->adev;
344 uint16_t atom_table_size;
345 uint8_t frev, crev;
346 int ret, index;
347
348 dev_info(adev->dev, "use vbios provided pptable\n");
349 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
350 powerplayinfo);
351
352 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
353 (uint8_t **)table);
354 if (ret)
355 return ret;
356
357 if (size)
358 *size = atom_table_size;
359
360 return 0;
361 }
362
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)363 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
364 void **table,
365 uint32_t *size,
366 uint32_t pptable_id)
367 {
368 const struct smc_firmware_header_v1_0 *hdr;
369 struct amdgpu_device *adev = smu->adev;
370 uint16_t version_major, version_minor;
371 int ret;
372
373 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
374 if (!hdr)
375 return -EINVAL;
376
377 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
378
379 version_major = le16_to_cpu(hdr->header.header_version_major);
380 version_minor = le16_to_cpu(hdr->header.header_version_minor);
381 if (version_major != 2) {
382 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
383 version_major, version_minor);
384 return -EINVAL;
385 }
386
387 switch (version_minor) {
388 case 0:
389 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
390 break;
391 case 1:
392 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
393 break;
394 default:
395 ret = -EINVAL;
396 break;
397 }
398
399 return ret;
400 }
401
smu_v13_0_setup_pptable(struct smu_context * smu)402 int smu_v13_0_setup_pptable(struct smu_context *smu)
403 {
404 struct amdgpu_device *adev = smu->adev;
405 uint32_t size = 0, pptable_id = 0;
406 void *table;
407 int ret = 0;
408
409 /* override pptable_id from driver parameter */
410 if (amdgpu_smu_pptable_id >= 0) {
411 pptable_id = amdgpu_smu_pptable_id;
412 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
413 } else {
414 pptable_id = smu->smu_table.boot_values.pp_table_id;
415 }
416
417 /* force using vbios pptable in sriov mode */
418 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
419 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
420 else
421 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
422
423 if (ret)
424 return ret;
425
426 if (!smu->smu_table.power_play_table)
427 smu->smu_table.power_play_table = table;
428 if (!smu->smu_table.power_play_table_size)
429 smu->smu_table.power_play_table_size = size;
430
431 return 0;
432 }
433
smu_v13_0_init_smc_tables(struct smu_context * smu)434 int smu_v13_0_init_smc_tables(struct smu_context *smu)
435 {
436 struct smu_table_context *smu_table = &smu->smu_table;
437 struct smu_table *tables = smu_table->tables;
438 int ret = 0;
439
440 smu_table->driver_pptable =
441 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
442 if (!smu_table->driver_pptable) {
443 ret = -ENOMEM;
444 goto err0_out;
445 }
446
447 smu_table->max_sustainable_clocks =
448 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
449 if (!smu_table->max_sustainable_clocks) {
450 ret = -ENOMEM;
451 goto err1_out;
452 }
453
454 /* Aldebaran does not support OVERDRIVE */
455 if (tables[SMU_TABLE_OVERDRIVE].size) {
456 smu_table->overdrive_table =
457 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
458 if (!smu_table->overdrive_table) {
459 ret = -ENOMEM;
460 goto err2_out;
461 }
462
463 smu_table->boot_overdrive_table =
464 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
465 if (!smu_table->boot_overdrive_table) {
466 ret = -ENOMEM;
467 goto err3_out;
468 }
469
470 smu_table->user_overdrive_table =
471 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
472 if (!smu_table->user_overdrive_table) {
473 ret = -ENOMEM;
474 goto err4_out;
475 }
476 }
477
478 smu_table->combo_pptable =
479 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
480 if (!smu_table->combo_pptable) {
481 ret = -ENOMEM;
482 goto err5_out;
483 }
484
485 return 0;
486
487 err5_out:
488 kfree(smu_table->user_overdrive_table);
489 err4_out:
490 kfree(smu_table->boot_overdrive_table);
491 err3_out:
492 kfree(smu_table->overdrive_table);
493 err2_out:
494 kfree(smu_table->max_sustainable_clocks);
495 err1_out:
496 kfree(smu_table->driver_pptable);
497 err0_out:
498 return ret;
499 }
500
smu_v13_0_fini_smc_tables(struct smu_context * smu)501 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
502 {
503 struct smu_table_context *smu_table = &smu->smu_table;
504 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
505
506 kfree(smu_table->gpu_metrics_table);
507 kfree(smu_table->combo_pptable);
508 kfree(smu_table->user_overdrive_table);
509 kfree(smu_table->boot_overdrive_table);
510 kfree(smu_table->overdrive_table);
511 kfree(smu_table->max_sustainable_clocks);
512 kfree(smu_table->driver_pptable);
513 smu_table->gpu_metrics_table = NULL;
514 smu_table->combo_pptable = NULL;
515 smu_table->user_overdrive_table = NULL;
516 smu_table->boot_overdrive_table = NULL;
517 smu_table->overdrive_table = NULL;
518 smu_table->max_sustainable_clocks = NULL;
519 smu_table->driver_pptable = NULL;
520 kfree(smu_table->hardcode_pptable);
521 smu_table->hardcode_pptable = NULL;
522
523 kfree(smu_table->ecc_table);
524 kfree(smu_table->metrics_table);
525 kfree(smu_table->watermarks_table);
526 smu_table->ecc_table = NULL;
527 smu_table->metrics_table = NULL;
528 smu_table->watermarks_table = NULL;
529 smu_table->metrics_time = 0;
530
531 kfree(smu_dpm->dpm_policies);
532 kfree(smu_dpm->dpm_context);
533 kfree(smu_dpm->golden_dpm_context);
534 kfree(smu_dpm->dpm_current_power_state);
535 kfree(smu_dpm->dpm_request_power_state);
536 smu_dpm->dpm_policies = NULL;
537 smu_dpm->dpm_context = NULL;
538 smu_dpm->golden_dpm_context = NULL;
539 smu_dpm->dpm_context_size = 0;
540 smu_dpm->dpm_current_power_state = NULL;
541 smu_dpm->dpm_request_power_state = NULL;
542
543 return 0;
544 }
545
smu_v13_0_init_power(struct smu_context * smu)546 int smu_v13_0_init_power(struct smu_context *smu)
547 {
548 struct smu_power_context *smu_power = &smu->smu_power;
549
550 if (smu_power->power_context || smu_power->power_context_size != 0)
551 return -EINVAL;
552
553 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
554 GFP_KERNEL);
555 if (!smu_power->power_context)
556 return -ENOMEM;
557 smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
558
559 return 0;
560 }
561
smu_v13_0_fini_power(struct smu_context * smu)562 int smu_v13_0_fini_power(struct smu_context *smu)
563 {
564 struct smu_power_context *smu_power = &smu->smu_power;
565
566 if (!smu_power->power_context || smu_power->power_context_size == 0)
567 return -EINVAL;
568
569 kfree(smu_power->power_context);
570 smu_power->power_context = NULL;
571 smu_power->power_context_size = 0;
572
573 return 0;
574 }
575
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)576 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
577 {
578 int ret, index;
579 uint16_t size;
580 uint8_t frev, crev;
581 struct atom_common_table_header *header;
582 struct atom_firmware_info_v3_4 *v_3_4;
583 struct atom_firmware_info_v3_3 *v_3_3;
584 struct atom_firmware_info_v3_1 *v_3_1;
585 struct atom_smu_info_v3_6 *smu_info_v3_6;
586 struct atom_smu_info_v4_0 *smu_info_v4_0;
587
588 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
589 firmwareinfo);
590
591 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
592 (uint8_t **)&header);
593 if (ret)
594 return ret;
595
596 if (header->format_revision != 3) {
597 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
598 return -EINVAL;
599 }
600
601 switch (header->content_revision) {
602 case 0:
603 case 1:
604 case 2:
605 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
606 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
607 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
608 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
609 smu->smu_table.boot_values.socclk = 0;
610 smu->smu_table.boot_values.dcefclk = 0;
611 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
612 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
613 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
614 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
615 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
616 smu->smu_table.boot_values.pp_table_id = 0;
617 break;
618 case 3:
619 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
620 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
621 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
622 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
623 smu->smu_table.boot_values.socclk = 0;
624 smu->smu_table.boot_values.dcefclk = 0;
625 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
626 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
627 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
628 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
629 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
630 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
631 break;
632 case 4:
633 default:
634 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
635 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
636 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
637 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
638 smu->smu_table.boot_values.socclk = 0;
639 smu->smu_table.boot_values.dcefclk = 0;
640 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
641 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
642 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
643 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
644 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
645 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
646 break;
647 }
648
649 smu->smu_table.boot_values.format_revision = header->format_revision;
650 smu->smu_table.boot_values.content_revision = header->content_revision;
651
652 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
653 smu_info);
654 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
655 (uint8_t **)&header)) {
656
657 if ((frev == 3) && (crev == 6)) {
658 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
659
660 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
661 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
662 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
663 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
664 } else if ((frev == 3) && (crev == 1)) {
665 return 0;
666 } else if ((frev == 4) && (crev == 0)) {
667 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
668
669 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
670 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
671 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
672 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
673 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
674 } else {
675 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
676 (uint32_t)frev, (uint32_t)crev);
677 }
678 }
679
680 return 0;
681 }
682
683
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)684 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
685 {
686 struct smu_table_context *smu_table = &smu->smu_table;
687 struct smu_table *memory_pool = &smu_table->memory_pool;
688 int ret = 0;
689 uint64_t address;
690 uint32_t address_low, address_high;
691
692 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
693 return ret;
694
695 address = memory_pool->mc_address;
696 address_high = (uint32_t)upper_32_bits(address);
697 address_low = (uint32_t)lower_32_bits(address);
698
699 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
700 address_high, NULL);
701 if (ret)
702 return ret;
703 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
704 address_low, NULL);
705 if (ret)
706 return ret;
707 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
708 (uint32_t)memory_pool->size, NULL);
709 if (ret)
710 return ret;
711
712 return ret;
713 }
714
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)715 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
716 {
717 int ret;
718
719 ret = smu_cmn_send_smc_msg_with_param(smu,
720 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
721 if (ret)
722 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
723
724 return ret;
725 }
726
smu_v13_0_set_driver_table_location(struct smu_context * smu)727 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
728 {
729 struct smu_table *driver_table = &smu->smu_table.driver_table;
730 int ret = 0;
731
732 if (driver_table->mc_address) {
733 ret = smu_cmn_send_smc_msg_with_param(smu,
734 SMU_MSG_SetDriverDramAddrHigh,
735 upper_32_bits(driver_table->mc_address),
736 NULL);
737 if (!ret)
738 ret = smu_cmn_send_smc_msg_with_param(smu,
739 SMU_MSG_SetDriverDramAddrLow,
740 lower_32_bits(driver_table->mc_address),
741 NULL);
742 }
743
744 return ret;
745 }
746
smu_v13_0_set_tool_table_location(struct smu_context * smu)747 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
748 {
749 int ret = 0;
750 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
751
752 if (tool_table->mc_address) {
753 ret = smu_cmn_send_smc_msg_with_param(smu,
754 SMU_MSG_SetToolsDramAddrHigh,
755 upper_32_bits(tool_table->mc_address),
756 NULL);
757 if (!ret)
758 ret = smu_cmn_send_smc_msg_with_param(smu,
759 SMU_MSG_SetToolsDramAddrLow,
760 lower_32_bits(tool_table->mc_address),
761 NULL);
762 }
763
764 return ret;
765 }
766
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)767 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
768 {
769 int ret = 0;
770
771 if (!smu->pm_enabled)
772 return ret;
773
774 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
775
776 return ret;
777 }
778
smu_v13_0_set_allowed_mask(struct smu_context * smu)779 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
780 {
781 struct smu_feature *feature = &smu->smu_feature;
782 int ret = 0;
783 uint32_t feature_mask[2];
784
785 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
786 feature->feature_num < 64)
787 return -EINVAL;
788
789 bitmap_to_arr32(feature_mask, feature->allowed, 64);
790
791 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
792 feature_mask[1], NULL);
793 if (ret)
794 return ret;
795
796 return smu_cmn_send_smc_msg_with_param(smu,
797 SMU_MSG_SetAllowedFeaturesMaskLow,
798 feature_mask[0],
799 NULL);
800 }
801
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)802 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
803 {
804 int ret = 0;
805 struct amdgpu_device *adev = smu->adev;
806
807 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
808 case IP_VERSION(13, 0, 0):
809 case IP_VERSION(13, 0, 1):
810 case IP_VERSION(13, 0, 3):
811 case IP_VERSION(13, 0, 4):
812 case IP_VERSION(13, 0, 5):
813 case IP_VERSION(13, 0, 7):
814 case IP_VERSION(13, 0, 8):
815 case IP_VERSION(13, 0, 10):
816 case IP_VERSION(13, 0, 11):
817 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
818 return 0;
819 if (enable)
820 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
821 else
822 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
823 break;
824 default:
825 break;
826 }
827
828 return ret;
829 }
830
smu_v13_0_system_features_control(struct smu_context * smu,bool en)831 int smu_v13_0_system_features_control(struct smu_context *smu,
832 bool en)
833 {
834 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
835 SMU_MSG_DisableAllSmuFeatures), NULL);
836 }
837
smu_v13_0_notify_display_change(struct smu_context * smu)838 int smu_v13_0_notify_display_change(struct smu_context *smu)
839 {
840 int ret = 0;
841
842 if (!amdgpu_device_has_dc_support(smu->adev))
843 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL);
844
845 return ret;
846 }
847
848 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)849 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
850 enum smu_clk_type clock_select)
851 {
852 int ret = 0;
853 int clk_id;
854
855 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
856 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
857 return 0;
858
859 clk_id = smu_cmn_to_asic_specific_index(smu,
860 CMN2ASIC_MAPPING_CLK,
861 clock_select);
862 if (clk_id < 0)
863 return -EINVAL;
864
865 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
866 clk_id << 16, clock);
867 if (ret) {
868 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
869 return ret;
870 }
871
872 if (*clock != 0)
873 return 0;
874
875 /* if DC limit is zero, return AC limit */
876 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
877 clk_id << 16, clock);
878 if (ret) {
879 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
880 return ret;
881 }
882
883 return 0;
884 }
885
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)886 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
887 {
888 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
889 smu->smu_table.max_sustainable_clocks;
890 int ret = 0;
891
892 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
893 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
894 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
895 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
896 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
897 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
898
899 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
900 ret = smu_v13_0_get_max_sustainable_clock(smu,
901 &(max_sustainable_clocks->uclock),
902 SMU_UCLK);
903 if (ret) {
904 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
905 __func__);
906 return ret;
907 }
908 }
909
910 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
911 ret = smu_v13_0_get_max_sustainable_clock(smu,
912 &(max_sustainable_clocks->soc_clock),
913 SMU_SOCCLK);
914 if (ret) {
915 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
916 __func__);
917 return ret;
918 }
919 }
920
921 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
922 ret = smu_v13_0_get_max_sustainable_clock(smu,
923 &(max_sustainable_clocks->dcef_clock),
924 SMU_DCEFCLK);
925 if (ret) {
926 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
927 __func__);
928 return ret;
929 }
930
931 ret = smu_v13_0_get_max_sustainable_clock(smu,
932 &(max_sustainable_clocks->display_clock),
933 SMU_DISPCLK);
934 if (ret) {
935 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
936 __func__);
937 return ret;
938 }
939 ret = smu_v13_0_get_max_sustainable_clock(smu,
940 &(max_sustainable_clocks->phy_clock),
941 SMU_PHYCLK);
942 if (ret) {
943 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
944 __func__);
945 return ret;
946 }
947 ret = smu_v13_0_get_max_sustainable_clock(smu,
948 &(max_sustainable_clocks->pixel_clock),
949 SMU_PIXCLK);
950 if (ret) {
951 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
952 __func__);
953 return ret;
954 }
955 }
956
957 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
958 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
959
960 return 0;
961 }
962
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)963 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
964 uint32_t *power_limit)
965 {
966 int power_src;
967 int ret = 0;
968
969 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
970 return -EINVAL;
971
972 power_src = smu_cmn_to_asic_specific_index(smu,
973 CMN2ASIC_MAPPING_PWR,
974 smu->adev->pm.ac_power ?
975 SMU_POWER_SOURCE_AC :
976 SMU_POWER_SOURCE_DC);
977 if (power_src < 0)
978 return -EINVAL;
979
980 ret = smu_cmn_send_smc_msg_with_param(smu,
981 SMU_MSG_GetPptLimit,
982 power_src << 16,
983 power_limit);
984 if (ret)
985 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
986
987 return ret;
988 }
989
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)990 int smu_v13_0_set_power_limit(struct smu_context *smu,
991 enum smu_ppt_limit_type limit_type,
992 uint32_t limit)
993 {
994 int ret = 0;
995
996 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
997 return -EINVAL;
998
999 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1000 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1001 return -EOPNOTSUPP;
1002 }
1003
1004 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1005 if (ret) {
1006 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1007 return ret;
1008 }
1009
1010 smu->current_power_limit = limit;
1011
1012 return 0;
1013 }
1014
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)1015 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1016 {
1017 return smu_cmn_send_smc_msg(smu,
1018 SMU_MSG_AllowIHHostInterrupt,
1019 NULL);
1020 }
1021
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1022 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1023 {
1024 int ret = 0;
1025
1026 if (smu->dc_controlled_by_gpio &&
1027 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1028 ret = smu_v13_0_allow_ih_interrupt(smu);
1029
1030 return ret;
1031 }
1032
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1033 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1034 {
1035 int ret = 0;
1036
1037 if (!smu->irq_source.num_types)
1038 return 0;
1039
1040 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1041 if (ret)
1042 return ret;
1043
1044 return smu_v13_0_process_pending_interrupt(smu);
1045 }
1046
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1047 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1048 {
1049 if (!smu->irq_source.num_types)
1050 return 0;
1051
1052 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1053 }
1054
convert_to_vddc(uint8_t vid)1055 static uint16_t convert_to_vddc(uint8_t vid)
1056 {
1057 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1058 }
1059
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1060 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1061 {
1062 struct amdgpu_device *adev = smu->adev;
1063 uint32_t vdd = 0, val_vid = 0;
1064
1065 if (!value)
1066 return -EINVAL;
1067 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1068 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1069 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1070
1071 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1072
1073 *value = vdd;
1074
1075 return 0;
1076
1077 }
1078
1079 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1080 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1081 struct pp_display_clock_request
1082 *clock_req)
1083 {
1084 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1085 int ret = 0;
1086 enum smu_clk_type clk_select = 0;
1087 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1088
1089 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1090 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1091 switch (clk_type) {
1092 case amd_pp_dcef_clock:
1093 clk_select = SMU_DCEFCLK;
1094 break;
1095 case amd_pp_disp_clock:
1096 clk_select = SMU_DISPCLK;
1097 break;
1098 case amd_pp_pixel_clock:
1099 clk_select = SMU_PIXCLK;
1100 break;
1101 case amd_pp_phy_clock:
1102 clk_select = SMU_PHYCLK;
1103 break;
1104 case amd_pp_mem_clock:
1105 clk_select = SMU_UCLK;
1106 break;
1107 default:
1108 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1109 ret = -EINVAL;
1110 break;
1111 }
1112
1113 if (ret)
1114 goto failed;
1115
1116 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1117 return 0;
1118
1119 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1120
1121 if (clk_select == SMU_UCLK)
1122 smu->hard_min_uclk_req_from_dal = clk_freq;
1123 }
1124
1125 failed:
1126 return ret;
1127 }
1128
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1129 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1130 {
1131 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1132 return AMD_FAN_CTRL_MANUAL;
1133 else
1134 return AMD_FAN_CTRL_AUTO;
1135 }
1136
1137 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1138 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1139 {
1140 int ret = 0;
1141
1142 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1143 return 0;
1144
1145 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1146 if (ret)
1147 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1148 __func__, (auto_fan_control ? "Start" : "Stop"));
1149
1150 return ret;
1151 }
1152
1153 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1154 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1155 {
1156 struct amdgpu_device *adev = smu->adev;
1157
1158 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1159 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1160 CG_FDO_CTRL2, TMIN, 0));
1161 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1162 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1163 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1164
1165 return 0;
1166 }
1167
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1168 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1169 uint32_t speed)
1170 {
1171 struct amdgpu_device *adev = smu->adev;
1172 uint32_t duty100, duty;
1173 uint64_t tmp64;
1174
1175 speed = min_t(uint32_t, speed, 255);
1176
1177 if (smu_v13_0_auto_fan_control(smu, 0))
1178 return -EINVAL;
1179
1180 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1181 CG_FDO_CTRL1, FMAX_DUTY100);
1182 if (!duty100)
1183 return -EINVAL;
1184
1185 tmp64 = (uint64_t)speed * duty100;
1186 do_div(tmp64, 255);
1187 duty = (uint32_t)tmp64;
1188
1189 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1190 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1191 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1192
1193 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1194 }
1195
1196 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1197 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1198 uint32_t mode)
1199 {
1200 int ret = 0;
1201
1202 switch (mode) {
1203 case AMD_FAN_CTRL_NONE:
1204 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1205 break;
1206 case AMD_FAN_CTRL_MANUAL:
1207 ret = smu_v13_0_auto_fan_control(smu, 0);
1208 break;
1209 case AMD_FAN_CTRL_AUTO:
1210 ret = smu_v13_0_auto_fan_control(smu, 1);
1211 break;
1212 default:
1213 break;
1214 }
1215
1216 if (ret) {
1217 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1218 return -EINVAL;
1219 }
1220
1221 return ret;
1222 }
1223
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1224 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1225 uint32_t speed)
1226 {
1227 struct amdgpu_device *adev = smu->adev;
1228 uint32_t crystal_clock_freq = 2500;
1229 uint32_t tach_period;
1230 int ret;
1231
1232 if (!speed)
1233 return -EINVAL;
1234
1235 ret = smu_v13_0_auto_fan_control(smu, 0);
1236 if (ret)
1237 return ret;
1238
1239 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1240 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1241 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1242 CG_TACH_CTRL, TARGET_PERIOD,
1243 tach_period));
1244
1245 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1246 }
1247
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1248 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1249 uint32_t pstate)
1250 {
1251 int ret = 0;
1252 ret = smu_cmn_send_smc_msg_with_param(smu,
1253 SMU_MSG_SetXgmiMode,
1254 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1255 NULL);
1256 return ret;
1257 }
1258
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1259 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1260 struct amdgpu_irq_src *source,
1261 unsigned tyep,
1262 enum amdgpu_interrupt_state state)
1263 {
1264 struct smu_context *smu = adev->powerplay.pp_handle;
1265 uint32_t low, high;
1266 uint32_t val = 0;
1267
1268 switch (state) {
1269 case AMDGPU_IRQ_STATE_DISABLE:
1270 /* For THM irqs */
1271 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1272 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1273 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1274 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1275
1276 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1277
1278 /* For MP1 SW irqs */
1279 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1280 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1281 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1282
1283 break;
1284 case AMDGPU_IRQ_STATE_ENABLE:
1285 /* For THM irqs */
1286 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1287 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1288 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1289 smu->thermal_range.software_shutdown_temp);
1290
1291 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1292 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1293 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1294 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1295 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1296 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1297 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1298 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1299 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1300
1301 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1302 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1303 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1304 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1305
1306 /* For MP1 SW irqs */
1307 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1308 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1309 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1310 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1311
1312 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1313 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1314 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1315
1316 break;
1317 default:
1318 break;
1319 }
1320
1321 return 0;
1322 }
1323
smu_v13_0_interrupt_work(struct smu_context * smu)1324 void smu_v13_0_interrupt_work(struct smu_context *smu)
1325 {
1326 smu_cmn_send_smc_msg(smu,
1327 SMU_MSG_ReenableAcDcInterrupt,
1328 NULL);
1329 }
1330
1331 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1332 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1333 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1334
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1335 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1336 struct amdgpu_irq_src *source,
1337 struct amdgpu_iv_entry *entry)
1338 {
1339 struct smu_context *smu = adev->powerplay.pp_handle;
1340 uint32_t client_id = entry->client_id;
1341 uint32_t src_id = entry->src_id;
1342 /*
1343 * ctxid is used to distinguish different
1344 * events for SMCToHost interrupt.
1345 */
1346 uint32_t ctxid = entry->src_data[0];
1347 uint32_t data;
1348 uint32_t high;
1349
1350 if (client_id == SOC15_IH_CLIENTID_THM) {
1351 switch (src_id) {
1352 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1353 schedule_delayed_work(&smu->swctf_delayed_work,
1354 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1355 break;
1356 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1357 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1358 break;
1359 default:
1360 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1361 src_id);
1362 break;
1363 }
1364 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1365 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1366 /*
1367 * HW CTF just occurred. Shutdown to prevent further damage.
1368 */
1369 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1370 orderly_poweroff(true);
1371 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1372 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1373 /* ACK SMUToHost interrupt */
1374 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1375 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1376 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1377
1378 switch (ctxid) {
1379 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1380 dev_dbg(adev->dev, "Switched to AC mode!\n");
1381 schedule_work(&smu->interrupt_work);
1382 adev->pm.ac_power = true;
1383 break;
1384 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1385 dev_dbg(adev->dev, "Switched to DC mode!\n");
1386 schedule_work(&smu->interrupt_work);
1387 adev->pm.ac_power = false;
1388 break;
1389 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1390 /*
1391 * Increment the throttle interrupt counter
1392 */
1393 atomic64_inc(&smu->throttle_int_counter);
1394
1395 if (!atomic_read(&adev->throttling_logging_enabled))
1396 return 0;
1397
1398 if (__ratelimit(&adev->throttling_logging_rs))
1399 schedule_work(&smu->throttling_logging_work);
1400
1401 break;
1402 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL:
1403 high = smu->thermal_range.software_shutdown_temp +
1404 smu->thermal_range.software_shutdown_temp_offset;
1405 high = min_t(typeof(high),
1406 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1407 high);
1408 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1409 high,
1410 smu->thermal_range.software_shutdown_temp_offset);
1411
1412 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1413 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1414 DIG_THERM_INTH,
1415 (high & 0xff));
1416 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1417 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1418 break;
1419 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY:
1420 high = min_t(typeof(high),
1421 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1422 smu->thermal_range.software_shutdown_temp);
1423 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1424
1425 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1426 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1427 DIG_THERM_INTH,
1428 (high & 0xff));
1429 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1430 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1431 break;
1432 default:
1433 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1434 ctxid, client_id);
1435 break;
1436 }
1437 }
1438 }
1439
1440 return 0;
1441 }
1442
1443 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1444 .set = smu_v13_0_set_irq_state,
1445 .process = smu_v13_0_irq_process,
1446 };
1447
smu_v13_0_register_irq_handler(struct smu_context * smu)1448 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1449 {
1450 struct amdgpu_device *adev = smu->adev;
1451 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1452 int ret = 0;
1453
1454 if (amdgpu_sriov_vf(adev))
1455 return 0;
1456
1457 irq_src->num_types = 1;
1458 irq_src->funcs = &smu_v13_0_irq_funcs;
1459
1460 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1461 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1462 irq_src);
1463 if (ret)
1464 return ret;
1465
1466 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1467 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1468 irq_src);
1469 if (ret)
1470 return ret;
1471
1472 /* Register CTF(GPIO_19) interrupt */
1473 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1474 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1475 irq_src);
1476 if (ret)
1477 return ret;
1478
1479 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1480 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1481 irq_src);
1482 if (ret)
1483 return ret;
1484
1485 return ret;
1486 }
1487
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1488 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1489 struct pp_smu_nv_clock_table *max_clocks)
1490 {
1491 struct smu_table_context *table_context = &smu->smu_table;
1492 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1493
1494 if (!max_clocks || !table_context->max_sustainable_clocks)
1495 return -EINVAL;
1496
1497 sustainable_clocks = table_context->max_sustainable_clocks;
1498
1499 max_clocks->dcfClockInKhz =
1500 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1501 max_clocks->displayClockInKhz =
1502 (unsigned int) sustainable_clocks->display_clock * 1000;
1503 max_clocks->phyClockInKhz =
1504 (unsigned int) sustainable_clocks->phy_clock * 1000;
1505 max_clocks->pixelClockInKhz =
1506 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1507 max_clocks->uClockInKhz =
1508 (unsigned int) sustainable_clocks->uclock * 1000;
1509 max_clocks->socClockInKhz =
1510 (unsigned int) sustainable_clocks->soc_clock * 1000;
1511 max_clocks->dscClockInKhz = 0;
1512 max_clocks->dppClockInKhz = 0;
1513 max_clocks->fabricClockInKhz = 0;
1514
1515 return 0;
1516 }
1517
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1518 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1519 {
1520 int ret = 0;
1521
1522 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1523
1524 return ret;
1525 }
1526
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1527 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1528 uint64_t event_arg)
1529 {
1530 int ret = 0;
1531
1532 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1533 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1534
1535 return ret;
1536 }
1537
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1538 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1539 uint64_t event_arg)
1540 {
1541 int ret = -EINVAL;
1542
1543 switch (event) {
1544 case SMU_EVENT_RESET_COMPLETE:
1545 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1546 break;
1547 default:
1548 break;
1549 }
1550
1551 return ret;
1552 }
1553
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1554 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1555 uint32_t *min, uint32_t *max)
1556 {
1557 int ret = 0, clk_id = 0;
1558 uint32_t param = 0;
1559 uint32_t clock_limit;
1560
1561 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1562 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
1563 if (ret)
1564 return ret;
1565
1566 /* clock in Mhz unit */
1567 if (min)
1568 *min = clock_limit / 100;
1569 if (max)
1570 *max = clock_limit / 100;
1571
1572 return 0;
1573 }
1574
1575 clk_id = smu_cmn_to_asic_specific_index(smu,
1576 CMN2ASIC_MAPPING_CLK,
1577 clk_type);
1578 if (clk_id < 0) {
1579 ret = -EINVAL;
1580 goto failed;
1581 }
1582 param = (clk_id & 0xffff) << 16;
1583
1584 if (max) {
1585 if (smu->adev->pm.ac_power)
1586 ret = smu_cmn_send_smc_msg_with_param(smu,
1587 SMU_MSG_GetMaxDpmFreq,
1588 param,
1589 max);
1590 else
1591 ret = smu_cmn_send_smc_msg_with_param(smu,
1592 SMU_MSG_GetDcModeMaxDpmFreq,
1593 param,
1594 max);
1595 if (ret)
1596 goto failed;
1597 }
1598
1599 if (min) {
1600 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1601 if (ret)
1602 goto failed;
1603 }
1604
1605 failed:
1606 return ret;
1607 }
1608
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1609 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1610 enum smu_clk_type clk_type,
1611 uint32_t min,
1612 uint32_t max,
1613 bool automatic)
1614 {
1615 int ret = 0, clk_id = 0;
1616 uint32_t param;
1617
1618 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1619 return 0;
1620
1621 clk_id = smu_cmn_to_asic_specific_index(smu,
1622 CMN2ASIC_MAPPING_CLK,
1623 clk_type);
1624 if (clk_id < 0)
1625 return clk_id;
1626
1627 if (max > 0) {
1628 if (automatic)
1629 param = (uint32_t)((clk_id << 16) | 0xffff);
1630 else
1631 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1632 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1633 param, NULL);
1634 if (ret)
1635 goto out;
1636 }
1637
1638 if (min > 0) {
1639 if (automatic)
1640 param = (uint32_t)((clk_id << 16) | 0);
1641 else
1642 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1643 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1644 param, NULL);
1645 if (ret)
1646 goto out;
1647 }
1648
1649 out:
1650 return ret;
1651 }
1652
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1653 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1654 enum smu_clk_type clk_type,
1655 uint32_t min,
1656 uint32_t max)
1657 {
1658 int ret = 0, clk_id = 0;
1659 uint32_t param;
1660
1661 if (min <= 0 && max <= 0)
1662 return -EINVAL;
1663
1664 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1665 return 0;
1666
1667 clk_id = smu_cmn_to_asic_specific_index(smu,
1668 CMN2ASIC_MAPPING_CLK,
1669 clk_type);
1670 if (clk_id < 0)
1671 return clk_id;
1672
1673 if (max > 0) {
1674 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1675 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1676 param, NULL);
1677 if (ret)
1678 return ret;
1679 }
1680
1681 if (min > 0) {
1682 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1683 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1684 param, NULL);
1685 if (ret)
1686 return ret;
1687 }
1688
1689 return ret;
1690 }
1691
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1692 int smu_v13_0_set_performance_level(struct smu_context *smu,
1693 enum amd_dpm_forced_level level)
1694 {
1695 struct smu_13_0_dpm_context *dpm_context =
1696 smu->smu_dpm.dpm_context;
1697 struct smu_13_0_dpm_table *gfx_table =
1698 &dpm_context->dpm_tables.gfx_table;
1699 struct smu_13_0_dpm_table *mem_table =
1700 &dpm_context->dpm_tables.uclk_table;
1701 struct smu_13_0_dpm_table *soc_table =
1702 &dpm_context->dpm_tables.soc_table;
1703 struct smu_13_0_dpm_table *vclk_table =
1704 &dpm_context->dpm_tables.vclk_table;
1705 struct smu_13_0_dpm_table *dclk_table =
1706 &dpm_context->dpm_tables.dclk_table;
1707 struct smu_13_0_dpm_table *fclk_table =
1708 &dpm_context->dpm_tables.fclk_table;
1709 struct smu_umd_pstate_table *pstate_table =
1710 &smu->pstate_table;
1711 struct amdgpu_device *adev = smu->adev;
1712 uint32_t sclk_min = 0, sclk_max = 0;
1713 uint32_t mclk_min = 0, mclk_max = 0;
1714 uint32_t socclk_min = 0, socclk_max = 0;
1715 uint32_t vclk_min = 0, vclk_max = 0;
1716 uint32_t dclk_min = 0, dclk_max = 0;
1717 uint32_t fclk_min = 0, fclk_max = 0;
1718 int ret = 0, i;
1719 bool auto_level = false;
1720
1721 switch (level) {
1722 case AMD_DPM_FORCED_LEVEL_HIGH:
1723 sclk_min = sclk_max = gfx_table->max;
1724 mclk_min = mclk_max = mem_table->max;
1725 socclk_min = socclk_max = soc_table->max;
1726 vclk_min = vclk_max = vclk_table->max;
1727 dclk_min = dclk_max = dclk_table->max;
1728 fclk_min = fclk_max = fclk_table->max;
1729 break;
1730 case AMD_DPM_FORCED_LEVEL_LOW:
1731 sclk_min = sclk_max = gfx_table->min;
1732 mclk_min = mclk_max = mem_table->min;
1733 socclk_min = socclk_max = soc_table->min;
1734 vclk_min = vclk_max = vclk_table->min;
1735 dclk_min = dclk_max = dclk_table->min;
1736 fclk_min = fclk_max = fclk_table->min;
1737 break;
1738 case AMD_DPM_FORCED_LEVEL_AUTO:
1739 sclk_min = gfx_table->min;
1740 sclk_max = gfx_table->max;
1741 mclk_min = mem_table->min;
1742 mclk_max = mem_table->max;
1743 socclk_min = soc_table->min;
1744 socclk_max = soc_table->max;
1745 vclk_min = vclk_table->min;
1746 vclk_max = vclk_table->max;
1747 dclk_min = dclk_table->min;
1748 dclk_max = dclk_table->max;
1749 fclk_min = fclk_table->min;
1750 fclk_max = fclk_table->max;
1751 auto_level = true;
1752 break;
1753 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1754 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1755 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1756 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1757 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1758 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1759 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1760 break;
1761 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1762 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1763 break;
1764 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1765 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1766 break;
1767 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1768 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1769 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1770 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1771 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1772 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1773 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1774 break;
1775 case AMD_DPM_FORCED_LEVEL_MANUAL:
1776 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1777 return 0;
1778 default:
1779 dev_err(adev->dev, "Invalid performance level %d\n", level);
1780 return -EINVAL;
1781 }
1782
1783 /*
1784 * Unset those settings for SMU 13.0.2. As soft limits settings
1785 * for those clock domains are not supported.
1786 */
1787 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) {
1788 mclk_min = mclk_max = 0;
1789 socclk_min = socclk_max = 0;
1790 vclk_min = vclk_max = 0;
1791 dclk_min = dclk_max = 0;
1792 fclk_min = fclk_max = 0;
1793 auto_level = false;
1794 }
1795
1796 if (sclk_min && sclk_max) {
1797 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1798 SMU_GFXCLK,
1799 sclk_min,
1800 sclk_max,
1801 auto_level);
1802 if (ret)
1803 return ret;
1804
1805 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1806 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1807 }
1808
1809 if (mclk_min && mclk_max) {
1810 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1811 SMU_MCLK,
1812 mclk_min,
1813 mclk_max,
1814 auto_level);
1815 if (ret)
1816 return ret;
1817
1818 pstate_table->uclk_pstate.curr.min = mclk_min;
1819 pstate_table->uclk_pstate.curr.max = mclk_max;
1820 }
1821
1822 if (socclk_min && socclk_max) {
1823 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1824 SMU_SOCCLK,
1825 socclk_min,
1826 socclk_max,
1827 auto_level);
1828 if (ret)
1829 return ret;
1830
1831 pstate_table->socclk_pstate.curr.min = socclk_min;
1832 pstate_table->socclk_pstate.curr.max = socclk_max;
1833 }
1834
1835 if (vclk_min && vclk_max) {
1836 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1837 if (adev->vcn.harvest_config & (1 << i))
1838 continue;
1839 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1840 i ? SMU_VCLK1 : SMU_VCLK,
1841 vclk_min,
1842 vclk_max,
1843 auto_level);
1844 if (ret)
1845 return ret;
1846 }
1847 pstate_table->vclk_pstate.curr.min = vclk_min;
1848 pstate_table->vclk_pstate.curr.max = vclk_max;
1849 }
1850
1851 if (dclk_min && dclk_max) {
1852 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1853 if (adev->vcn.harvest_config & (1 << i))
1854 continue;
1855 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1856 i ? SMU_DCLK1 : SMU_DCLK,
1857 dclk_min,
1858 dclk_max,
1859 auto_level);
1860 if (ret)
1861 return ret;
1862 }
1863 pstate_table->dclk_pstate.curr.min = dclk_min;
1864 pstate_table->dclk_pstate.curr.max = dclk_max;
1865 }
1866
1867 if (fclk_min && fclk_max) {
1868 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1869 SMU_FCLK,
1870 fclk_min,
1871 fclk_max,
1872 auto_level);
1873 if (ret)
1874 return ret;
1875
1876 pstate_table->fclk_pstate.curr.min = fclk_min;
1877 pstate_table->fclk_pstate.curr.max = fclk_max;
1878 }
1879
1880 return ret;
1881 }
1882
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1883 int smu_v13_0_set_power_source(struct smu_context *smu,
1884 enum smu_power_src_type power_src)
1885 {
1886 int pwr_source;
1887
1888 pwr_source = smu_cmn_to_asic_specific_index(smu,
1889 CMN2ASIC_MAPPING_PWR,
1890 (uint32_t)power_src);
1891 if (pwr_source < 0)
1892 return -EINVAL;
1893
1894 return smu_cmn_send_smc_msg_with_param(smu,
1895 SMU_MSG_NotifyPowerSource,
1896 pwr_source,
1897 NULL);
1898 }
1899
smu_v13_0_get_boot_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1900 int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
1901 enum smu_clk_type clk_type,
1902 uint32_t *value)
1903 {
1904 int ret = 0;
1905
1906 switch (clk_type) {
1907 case SMU_MCLK:
1908 case SMU_UCLK:
1909 *value = smu->smu_table.boot_values.uclk;
1910 break;
1911 case SMU_FCLK:
1912 *value = smu->smu_table.boot_values.fclk;
1913 break;
1914 case SMU_GFXCLK:
1915 case SMU_SCLK:
1916 *value = smu->smu_table.boot_values.gfxclk;
1917 break;
1918 case SMU_SOCCLK:
1919 *value = smu->smu_table.boot_values.socclk;
1920 break;
1921 case SMU_VCLK:
1922 *value = smu->smu_table.boot_values.vclk;
1923 break;
1924 case SMU_DCLK:
1925 *value = smu->smu_table.boot_values.dclk;
1926 break;
1927 default:
1928 ret = -EINVAL;
1929 break;
1930 }
1931 return ret;
1932 }
1933
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1934 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1935 enum smu_clk_type clk_type, uint16_t level,
1936 uint32_t *value)
1937 {
1938 int ret = 0, clk_id = 0;
1939 uint32_t param;
1940
1941 if (!value)
1942 return -EINVAL;
1943
1944 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1945 return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);
1946
1947 clk_id = smu_cmn_to_asic_specific_index(smu,
1948 CMN2ASIC_MAPPING_CLK,
1949 clk_type);
1950 if (clk_id < 0)
1951 return clk_id;
1952
1953 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1954
1955 ret = smu_cmn_send_smc_msg_with_param(smu,
1956 SMU_MSG_GetDpmFreqByIndex,
1957 param,
1958 value);
1959 if (ret)
1960 return ret;
1961
1962 *value = *value & 0x7fffffff;
1963
1964 return ret;
1965 }
1966
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1967 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1968 enum smu_clk_type clk_type,
1969 uint32_t *value)
1970 {
1971 int ret;
1972
1973 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1974 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1975 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) && (!ret && value))
1976 ++(*value);
1977
1978 return ret;
1979 }
1980
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1981 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1982 enum smu_clk_type clk_type,
1983 bool *is_fine_grained_dpm)
1984 {
1985 int ret = 0, clk_id = 0;
1986 uint32_t param;
1987 uint32_t value;
1988
1989 if (!is_fine_grained_dpm)
1990 return -EINVAL;
1991
1992 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1993 return 0;
1994
1995 clk_id = smu_cmn_to_asic_specific_index(smu,
1996 CMN2ASIC_MAPPING_CLK,
1997 clk_type);
1998 if (clk_id < 0)
1999 return clk_id;
2000
2001 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
2002
2003 ret = smu_cmn_send_smc_msg_with_param(smu,
2004 SMU_MSG_GetDpmFreqByIndex,
2005 param,
2006 &value);
2007 if (ret)
2008 return ret;
2009
2010 /*
2011 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
2012 * now, we un-support it
2013 */
2014 *is_fine_grained_dpm = value & 0x80000000;
2015
2016 return 0;
2017 }
2018
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)2019 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2020 enum smu_clk_type clk_type,
2021 struct smu_13_0_dpm_table *single_dpm_table)
2022 {
2023 int ret = 0;
2024 uint32_t clk;
2025 int i;
2026
2027 ret = smu_v13_0_get_dpm_level_count(smu,
2028 clk_type,
2029 &single_dpm_table->count);
2030 if (ret) {
2031 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2032 return ret;
2033 }
2034
2035 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) {
2036 ret = smu_v13_0_get_fine_grained_status(smu,
2037 clk_type,
2038 &single_dpm_table->is_fine_grained);
2039 if (ret) {
2040 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2041 return ret;
2042 }
2043 }
2044
2045 for (i = 0; i < single_dpm_table->count; i++) {
2046 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2047 clk_type,
2048 i,
2049 &clk);
2050 if (ret) {
2051 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2052 return ret;
2053 }
2054
2055 single_dpm_table->dpm_levels[i].value = clk;
2056 single_dpm_table->dpm_levels[i].enabled = true;
2057
2058 if (i == 0)
2059 single_dpm_table->min = clk;
2060 else if (i == single_dpm_table->count - 1)
2061 single_dpm_table->max = clk;
2062 }
2063
2064 return 0;
2065 }
2066
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2067 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2068 {
2069 struct amdgpu_device *adev = smu->adev;
2070
2071 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2072 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2073 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2074 }
2075
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2076 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2077 {
2078 uint32_t width_level;
2079
2080 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2081 if (width_level > LINK_WIDTH_MAX)
2082 width_level = 0;
2083
2084 return link_width[width_level];
2085 }
2086
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2087 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2088 {
2089 struct amdgpu_device *adev = smu->adev;
2090
2091 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2092 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2093 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2094 }
2095
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2096 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2097 {
2098 uint32_t speed_level;
2099
2100 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2101 if (speed_level > LINK_SPEED_MAX)
2102 speed_level = 0;
2103
2104 return link_speed[speed_level];
2105 }
2106
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable,int inst)2107 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2108 bool enable,
2109 int inst)
2110 {
2111 struct amdgpu_device *adev = smu->adev;
2112 int ret = 0;
2113
2114 if (adev->vcn.harvest_config & (1 << inst))
2115 return ret;
2116
2117 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2118 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2119 inst << 16U, NULL);
2120
2121 return ret;
2122 }
2123
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2124 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2125 bool enable)
2126 {
2127 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2128 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2129 0, NULL);
2130 }
2131
smu_v13_0_run_btc(struct smu_context * smu)2132 int smu_v13_0_run_btc(struct smu_context *smu)
2133 {
2134 int res;
2135
2136 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2137 if (res)
2138 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2139
2140 return res;
2141 }
2142
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2143 int smu_v13_0_gpo_control(struct smu_context *smu,
2144 bool enablement)
2145 {
2146 int res;
2147
2148 res = smu_cmn_send_smc_msg_with_param(smu,
2149 SMU_MSG_AllowGpo,
2150 enablement ? 1 : 0,
2151 NULL);
2152 if (res)
2153 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2154
2155 return res;
2156 }
2157
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2158 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2159 bool enablement)
2160 {
2161 struct amdgpu_device *adev = smu->adev;
2162 int ret = 0;
2163
2164 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2165 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2166 if (ret) {
2167 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2168 return ret;
2169 }
2170 }
2171
2172 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2173 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2174 if (ret) {
2175 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2176 return ret;
2177 }
2178 }
2179
2180 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2181 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2182 if (ret) {
2183 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2184 return ret;
2185 }
2186 }
2187
2188 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2189 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2190 if (ret) {
2191 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2192 return ret;
2193 }
2194 }
2195
2196 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2197 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2198 if (ret) {
2199 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2200 return ret;
2201 }
2202 }
2203
2204 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2205 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2206 if (ret) {
2207 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2208 return ret;
2209 }
2210 }
2211
2212 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2213 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2214 if (ret) {
2215 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2216 return ret;
2217 }
2218 }
2219
2220 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2221 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2222 if (ret) {
2223 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2224 return ret;
2225 }
2226 }
2227
2228 return ret;
2229 }
2230
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2231 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2232 bool enablement)
2233 {
2234 int ret = 0;
2235
2236 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2237 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2238
2239 return ret;
2240 }
2241
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2242 static int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2243 enum smu_baco_seq baco_seq)
2244 {
2245 struct smu_baco_context *smu_baco = &smu->smu_baco;
2246 int ret;
2247
2248 ret = smu_cmn_send_smc_msg_with_param(smu,
2249 SMU_MSG_ArmD3,
2250 baco_seq,
2251 NULL);
2252 if (ret)
2253 return ret;
2254
2255 if (baco_seq == BACO_SEQ_BAMACO ||
2256 baco_seq == BACO_SEQ_BACO)
2257 smu_baco->state = SMU_BACO_STATE_ENTER;
2258 else
2259 smu_baco->state = SMU_BACO_STATE_EXIT;
2260
2261 return 0;
2262 }
2263
smu_v13_0_baco_get_state(struct smu_context * smu)2264 static enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2265 {
2266 struct smu_baco_context *smu_baco = &smu->smu_baco;
2267
2268 return smu_baco->state;
2269 }
2270
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2271 static int smu_v13_0_baco_set_state(struct smu_context *smu,
2272 enum smu_baco_state state)
2273 {
2274 struct smu_baco_context *smu_baco = &smu->smu_baco;
2275 struct amdgpu_device *adev = smu->adev;
2276 int ret = 0;
2277
2278 if (smu_v13_0_baco_get_state(smu) == state)
2279 return 0;
2280
2281 if (state == SMU_BACO_STATE_ENTER) {
2282 ret = smu_cmn_send_smc_msg_with_param(smu,
2283 SMU_MSG_EnterBaco,
2284 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2285 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2286 NULL);
2287 } else {
2288 ret = smu_cmn_send_smc_msg(smu,
2289 SMU_MSG_ExitBaco,
2290 NULL);
2291 if (ret)
2292 return ret;
2293
2294 /* clear vbios scratch 6 and 7 for coming asic reinit */
2295 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2296 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2297 }
2298
2299 if (!ret)
2300 smu_baco->state = state;
2301
2302 return ret;
2303 }
2304
smu_v13_0_get_bamaco_support(struct smu_context * smu)2305 int smu_v13_0_get_bamaco_support(struct smu_context *smu)
2306 {
2307 struct smu_baco_context *smu_baco = &smu->smu_baco;
2308 int bamaco_support = 0;
2309
2310 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
2311 return 0;
2312
2313 if (smu_baco->maco_support)
2314 bamaco_support |= MACO_SUPPORT;
2315
2316 /* return true if ASIC is in BACO state already */
2317 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2318 return bamaco_support |= BACO_SUPPORT;
2319
2320 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2321 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2322 return 0;
2323
2324 return (bamaco_support |= BACO_SUPPORT);
2325 }
2326
smu_v13_0_baco_enter(struct smu_context * smu)2327 int smu_v13_0_baco_enter(struct smu_context *smu)
2328 {
2329 struct amdgpu_device *adev = smu->adev;
2330 int ret;
2331
2332 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2333 return smu_v13_0_baco_set_armd3_sequence(smu,
2334 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2335 BACO_SEQ_BAMACO : BACO_SEQ_BACO);
2336 } else {
2337 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
2338 if (!ret)
2339 usleep_range(10000, 11000);
2340
2341 return ret;
2342 }
2343 }
2344
smu_v13_0_baco_exit(struct smu_context * smu)2345 int smu_v13_0_baco_exit(struct smu_context *smu)
2346 {
2347 struct amdgpu_device *adev = smu->adev;
2348 int ret;
2349
2350 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2351 /* Wait for PMFW handling for the Dstate change */
2352 usleep_range(10000, 11000);
2353 ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2354 } else {
2355 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
2356 }
2357
2358 if (!ret)
2359 adev->gfx.is_poweron = false;
2360
2361 return ret;
2362 }
2363
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2364 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2365 {
2366 uint16_t index;
2367 struct amdgpu_device *adev = smu->adev;
2368
2369 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2370 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
2371 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
2372 }
2373
2374 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2375 SMU_MSG_EnableGfxImu);
2376 return smu_cmn_send_msg_without_waiting(smu, index,
2377 ENABLE_IMU_ARG_GFXOFF_ENABLE);
2378 }
2379
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2380 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2381 enum PP_OD_DPM_TABLE_COMMAND type,
2382 long input[], uint32_t size)
2383 {
2384 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2385 int ret = 0;
2386
2387 /* Only allowed in manual mode */
2388 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2389 return -EINVAL;
2390
2391 switch (type) {
2392 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2393 if (size != 2) {
2394 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2395 return -EINVAL;
2396 }
2397
2398 if (input[0] == 0) {
2399 if (input[1] < smu->gfx_default_hard_min_freq) {
2400 dev_warn(smu->adev->dev,
2401 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2402 input[1], smu->gfx_default_hard_min_freq);
2403 return -EINVAL;
2404 }
2405 smu->gfx_actual_hard_min_freq = input[1];
2406 } else if (input[0] == 1) {
2407 if (input[1] > smu->gfx_default_soft_max_freq) {
2408 dev_warn(smu->adev->dev,
2409 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2410 input[1], smu->gfx_default_soft_max_freq);
2411 return -EINVAL;
2412 }
2413 smu->gfx_actual_soft_max_freq = input[1];
2414 } else {
2415 return -EINVAL;
2416 }
2417 break;
2418 case PP_OD_RESTORE_DEFAULT_TABLE:
2419 if (size != 0) {
2420 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2421 return -EINVAL;
2422 }
2423 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2424 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2425 break;
2426 case PP_OD_COMMIT_DPM_TABLE:
2427 if (size != 0) {
2428 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2429 return -EINVAL;
2430 }
2431 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2432 dev_err(smu->adev->dev,
2433 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2434 smu->gfx_actual_hard_min_freq,
2435 smu->gfx_actual_soft_max_freq);
2436 return -EINVAL;
2437 }
2438
2439 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2440 smu->gfx_actual_hard_min_freq,
2441 NULL);
2442 if (ret) {
2443 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2444 return ret;
2445 }
2446
2447 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2448 smu->gfx_actual_soft_max_freq,
2449 NULL);
2450 if (ret) {
2451 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2452 return ret;
2453 }
2454 break;
2455 default:
2456 return -ENOSYS;
2457 }
2458
2459 return ret;
2460 }
2461
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2462 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2463 {
2464 struct smu_table_context *smu_table = &smu->smu_table;
2465
2466 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2467 smu_table->clocks_table, false);
2468 }
2469
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2470 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2471 {
2472 struct amdgpu_device *adev = smu->adev;
2473
2474 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2475 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2476 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2477 }
2478
smu_v13_0_mode1_reset(struct smu_context * smu)2479 int smu_v13_0_mode1_reset(struct smu_context *smu)
2480 {
2481 int ret = 0;
2482
2483 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2484 if (!ret)
2485 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2486
2487 return ret;
2488 }
2489
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2490 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2491 uint8_t pcie_gen_cap,
2492 uint8_t pcie_width_cap)
2493 {
2494 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2495 struct smu_13_0_pcie_table *pcie_table =
2496 &dpm_context->dpm_tables.pcie_table;
2497 int num_of_levels = pcie_table->num_of_link_levels;
2498 uint32_t smu_pcie_arg;
2499 int ret, i;
2500
2501 if (!num_of_levels)
2502 return 0;
2503
2504 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2505 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2506 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2507
2508 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2509 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2510
2511 /* Force all levels to use the same settings */
2512 for (i = 0; i < num_of_levels; i++) {
2513 pcie_table->pcie_gen[i] = pcie_gen_cap;
2514 pcie_table->pcie_lane[i] = pcie_width_cap;
2515 }
2516 } else {
2517 for (i = 0; i < num_of_levels; i++) {
2518 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2519 pcie_table->pcie_gen[i] = pcie_gen_cap;
2520 if (pcie_table->pcie_lane[i] > pcie_width_cap)
2521 pcie_table->pcie_lane[i] = pcie_width_cap;
2522 }
2523 }
2524
2525 for (i = 0; i < num_of_levels; i++) {
2526 smu_pcie_arg = i << 16;
2527 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2528 smu_pcie_arg |= pcie_table->pcie_lane[i];
2529
2530 ret = smu_cmn_send_smc_msg_with_param(smu,
2531 SMU_MSG_OverridePcieParameters,
2532 smu_pcie_arg,
2533 NULL);
2534 if (ret)
2535 return ret;
2536 }
2537
2538 return 0;
2539 }
2540
smu_v13_0_disable_pmfw_state(struct smu_context * smu)2541 int smu_v13_0_disable_pmfw_state(struct smu_context *smu)
2542 {
2543 int ret;
2544 struct amdgpu_device *adev = smu->adev;
2545
2546 WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0);
2547
2548 ret = RREG32_PCIE(MP1_Public |
2549 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
2550
2551 return ret == 0 ? 0 : -EINVAL;
2552 }
2553
smu_v13_0_enable_uclk_shadow(struct smu_context * smu,bool enable)2554 int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)
2555 {
2556 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);
2557 }
2558
smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context * smu,struct freq_band_range * exclusion_ranges)2559 int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
2560 struct freq_band_range *exclusion_ranges)
2561 {
2562 WifiBandEntryTable_t wifi_bands;
2563 int valid_entries = 0;
2564 int ret, i;
2565
2566 memset(&wifi_bands, 0, sizeof(wifi_bands));
2567 for (i = 0; i < ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {
2568 if (!exclusion_ranges[i].start && !exclusion_ranges[i].end)
2569 break;
2570
2571 /* PMFW expects the inputs to be in Mhz unit */
2572 wifi_bands.WifiBandEntry[valid_entries].LowFreq =
2573 DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);
2574 wifi_bands.WifiBandEntry[valid_entries++].HighFreq =
2575 DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);
2576 }
2577 wifi_bands.WifiBandEntryNum = valid_entries;
2578
2579 /*
2580 * Per confirm with PMFW team, WifiBandEntryNum = 0
2581 * is a valid setting.
2582 *
2583 * Considering the scenarios below:
2584 * - At first the wifi device adds an exclusion range e.g. (2400,2500) to
2585 * BIOS and our driver gets notified. We will set WifiBandEntryNum = 1
2586 * and pass the WifiBandEntry (2400, 2500) to PMFW.
2587 *
2588 * - Later the wifi device removes the wifiband list added above and
2589 * our driver gets notified again. At this time, driver will set
2590 * WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.
2591 *
2592 * - PMFW may still need to do some uclk shadow update(e.g. switching
2593 * from shadow clock back to primary clock) on receiving this.
2594 */
2595 ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &wifi_bands, true);
2596 if (ret)
2597 dev_warn(smu->adev->dev, "Failed to set wifiband!");
2598
2599 return ret;
2600 }
2601