1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_0_kicker.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
63 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
64
65 #define mmMP1_SMN_C2PMSG_66 0x0282
66 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
67
68 #define mmMP1_SMN_C2PMSG_82 0x0292
69 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
70
71 #define mmMP1_SMN_C2PMSG_90 0x029a
72 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
73
74 #define SMU13_VOLTAGE_SCALE 4
75
76 #define LINK_WIDTH_MAX 6
77 #define LINK_SPEED_MAX 3
78
79 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
81 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
82 #define smnPCIE_LC_SPEED_CNTL 0x11140290
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
84 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
85
86 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
87
88 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
89
90 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
91 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
92
smu_v13_0_init_microcode(struct smu_context * smu)93 int smu_v13_0_init_microcode(struct smu_context *smu)
94 {
95 struct amdgpu_device *adev = smu->adev;
96 char ucode_prefix[30];
97 int err = 0;
98 const struct smc_firmware_header_v1_0 *hdr;
99 const struct common_firmware_header *header;
100 struct amdgpu_firmware_info *ucode = NULL;
101
102 /* doesn't need to load smu firmware in IOV mode */
103 if (amdgpu_sriov_vf(adev))
104 return 0;
105
106 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
107
108 if (amdgpu_is_kicker_fw(adev))
109 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
110 "amdgpu/%s_kicker.bin", ucode_prefix);
111 else
112 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
113 "amdgpu/%s.bin", ucode_prefix);
114 if (err)
115 goto out;
116
117 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
118 amdgpu_ucode_print_smc_hdr(&hdr->header);
119 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
120
121 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
122 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
123 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
124 ucode->fw = adev->pm.fw;
125 header = (const struct common_firmware_header *)ucode->fw->data;
126 adev->firmware.fw_size +=
127 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
128 }
129
130 out:
131 if (err)
132 amdgpu_ucode_release(&adev->pm.fw);
133 return err;
134 }
135
smu_v13_0_fini_microcode(struct smu_context * smu)136 void smu_v13_0_fini_microcode(struct smu_context *smu)
137 {
138 struct amdgpu_device *adev = smu->adev;
139
140 amdgpu_ucode_release(&adev->pm.fw);
141 adev->pm.fw_version = 0;
142 }
143
smu_v13_0_load_microcode(struct smu_context * smu)144 int smu_v13_0_load_microcode(struct smu_context *smu)
145 {
146 #if 0
147 struct amdgpu_device *adev = smu->adev;
148 const uint32_t *src;
149 const struct smc_firmware_header_v1_0 *hdr;
150 uint32_t addr_start = MP1_SRAM;
151 uint32_t i;
152 uint32_t smc_fw_size;
153 uint32_t mp1_fw_flags;
154
155 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
156 src = (const uint32_t *)(adev->pm.fw->data +
157 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
158 smc_fw_size = hdr->header.ucode_size_bytes;
159
160 for (i = 1; i < smc_fw_size/4 - 1; i++) {
161 WREG32_PCIE(addr_start, src[i]);
162 addr_start += 4;
163 }
164
165 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
166 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
167 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
168 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
169
170 for (i = 0; i < adev->usec_timeout; i++) {
171 mp1_fw_flags = RREG32_PCIE(MP1_Public |
172 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
173 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
174 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
175 break;
176 udelay(1);
177 }
178
179 if (i == adev->usec_timeout)
180 return -ETIME;
181 #endif
182
183 return 0;
184 }
185
smu_v13_0_init_pptable_microcode(struct smu_context * smu)186 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
187 {
188 struct amdgpu_device *adev = smu->adev;
189 struct amdgpu_firmware_info *ucode = NULL;
190 uint32_t size = 0, pptable_id = 0;
191 int ret = 0;
192 void *table;
193
194 /* doesn't need to load smu firmware in IOV mode */
195 if (amdgpu_sriov_vf(adev))
196 return 0;
197
198 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
199 return 0;
200
201 if (!adev->scpm_enabled)
202 return 0;
203
204 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 7)) ||
205 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) ||
206 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)))
207 return 0;
208
209 /* override pptable_id from driver parameter */
210 if (amdgpu_smu_pptable_id >= 0) {
211 pptable_id = amdgpu_smu_pptable_id;
212 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
213 } else {
214 pptable_id = smu->smu_table.boot_values.pp_table_id;
215 }
216
217 /* "pptable_id == 0" means vbios carries the pptable. */
218 if (!pptable_id)
219 return 0;
220
221 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
222 if (ret)
223 return ret;
224
225 smu->pptable_firmware.data = table;
226 smu->pptable_firmware.size = size;
227
228 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
229 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
230 ucode->fw = &smu->pptable_firmware;
231 adev->firmware.fw_size +=
232 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
233
234 return 0;
235 }
236
smu_v13_0_check_fw_status(struct smu_context * smu)237 int smu_v13_0_check_fw_status(struct smu_context *smu)
238 {
239 struct amdgpu_device *adev = smu->adev;
240 uint32_t mp1_fw_flags;
241
242 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
243 case IP_VERSION(13, 0, 4):
244 case IP_VERSION(13, 0, 11):
245 mp1_fw_flags = RREG32_PCIE(MP1_Public |
246 (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
247 break;
248 default:
249 mp1_fw_flags = RREG32_PCIE(MP1_Public |
250 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
251 break;
252 }
253
254 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
255 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
256 return 0;
257
258 return -EIO;
259 }
260
smu_v13_0_check_fw_version(struct smu_context * smu)261 int smu_v13_0_check_fw_version(struct smu_context *smu)
262 {
263 struct amdgpu_device *adev = smu->adev;
264 uint32_t if_version = 0xff, smu_version = 0xff;
265 uint8_t smu_program, smu_major, smu_minor, smu_debug;
266 int ret = 0;
267
268 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
269 if (ret)
270 return ret;
271
272 smu_program = (smu_version >> 24) & 0xff;
273 smu_major = (smu_version >> 16) & 0xff;
274 smu_minor = (smu_version >> 8) & 0xff;
275 smu_debug = (smu_version >> 0) & 0xff;
276 adev->pm.fw_version = smu_version;
277
278 /* only for dGPU w/ SMU13*/
279 if (adev->pm.fw)
280 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
281 smu_program, smu_version, smu_major, smu_minor, smu_debug);
282
283 /*
284 * 1. if_version mismatch is not critical as our fw is designed
285 * to be backward compatible.
286 * 2. New fw usually brings some optimizations. But that's visible
287 * only on the paired driver.
288 * Considering above, we just leave user a verbal message instead
289 * of halt driver loading.
290 */
291 if (if_version != smu->smc_driver_if_version) {
292 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
293 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
294 smu->smc_driver_if_version, if_version,
295 smu_program, smu_version, smu_major, smu_minor, smu_debug);
296 dev_info(adev->dev, "SMU driver if version not matched\n");
297 }
298
299 return ret;
300 }
301
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)302 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
303 {
304 struct amdgpu_device *adev = smu->adev;
305 uint32_t ppt_offset_bytes;
306 const struct smc_firmware_header_v2_0 *v2;
307
308 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
309
310 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
311 *size = le32_to_cpu(v2->ppt_size_bytes);
312 *table = (uint8_t *)v2 + ppt_offset_bytes;
313
314 return 0;
315 }
316
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)317 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
318 uint32_t *size, uint32_t pptable_id)
319 {
320 struct amdgpu_device *adev = smu->adev;
321 const struct smc_firmware_header_v2_1 *v2_1;
322 struct smc_soft_pptable_entry *entries;
323 uint32_t pptable_count = 0;
324 int i = 0;
325
326 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
327 entries = (struct smc_soft_pptable_entry *)
328 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
329 pptable_count = le32_to_cpu(v2_1->pptable_count);
330 for (i = 0; i < pptable_count; i++) {
331 if (le32_to_cpu(entries[i].id) == pptable_id) {
332 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
333 *size = le32_to_cpu(entries[i].ppt_size_bytes);
334 break;
335 }
336 }
337
338 if (i == pptable_count)
339 return -EINVAL;
340
341 return 0;
342 }
343
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)344 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
345 {
346 struct amdgpu_device *adev = smu->adev;
347 uint16_t atom_table_size;
348 uint8_t frev, crev;
349 int ret, index;
350
351 dev_info(adev->dev, "use vbios provided pptable\n");
352 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
353 powerplayinfo);
354
355 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
356 (uint8_t **)table);
357 if (ret)
358 return ret;
359
360 if (size)
361 *size = atom_table_size;
362
363 return 0;
364 }
365
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)366 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
367 void **table,
368 uint32_t *size,
369 uint32_t pptable_id)
370 {
371 const struct smc_firmware_header_v1_0 *hdr;
372 struct amdgpu_device *adev = smu->adev;
373 uint16_t version_major, version_minor;
374 int ret;
375
376 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
377 if (!hdr)
378 return -EINVAL;
379
380 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
381
382 version_major = le16_to_cpu(hdr->header.header_version_major);
383 version_minor = le16_to_cpu(hdr->header.header_version_minor);
384 if (version_major != 2) {
385 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
386 version_major, version_minor);
387 return -EINVAL;
388 }
389
390 switch (version_minor) {
391 case 0:
392 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
393 break;
394 case 1:
395 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
396 break;
397 default:
398 ret = -EINVAL;
399 break;
400 }
401
402 return ret;
403 }
404
smu_v13_0_setup_pptable(struct smu_context * smu)405 int smu_v13_0_setup_pptable(struct smu_context *smu)
406 {
407 struct amdgpu_device *adev = smu->adev;
408 uint32_t size = 0, pptable_id = 0;
409 void *table;
410 int ret = 0;
411
412 /* override pptable_id from driver parameter */
413 if (amdgpu_smu_pptable_id >= 0) {
414 pptable_id = amdgpu_smu_pptable_id;
415 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
416 } else {
417 pptable_id = smu->smu_table.boot_values.pp_table_id;
418 }
419
420 /* force using vbios pptable in sriov mode */
421 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
422 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
423 else
424 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
425
426 if (ret)
427 return ret;
428
429 if (!smu->smu_table.power_play_table)
430 smu->smu_table.power_play_table = table;
431 if (!smu->smu_table.power_play_table_size)
432 smu->smu_table.power_play_table_size = size;
433
434 return 0;
435 }
436
smu_v13_0_init_smc_tables(struct smu_context * smu)437 int smu_v13_0_init_smc_tables(struct smu_context *smu)
438 {
439 struct smu_table_context *smu_table = &smu->smu_table;
440 struct smu_table *tables = smu_table->tables;
441 int ret = 0;
442
443 smu_table->driver_pptable =
444 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
445 if (!smu_table->driver_pptable) {
446 ret = -ENOMEM;
447 goto err0_out;
448 }
449
450 smu_table->max_sustainable_clocks =
451 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
452 if (!smu_table->max_sustainable_clocks) {
453 ret = -ENOMEM;
454 goto err1_out;
455 }
456
457 /* Aldebaran does not support OVERDRIVE */
458 if (tables[SMU_TABLE_OVERDRIVE].size) {
459 smu_table->overdrive_table =
460 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
461 if (!smu_table->overdrive_table) {
462 ret = -ENOMEM;
463 goto err2_out;
464 }
465
466 smu_table->boot_overdrive_table =
467 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
468 if (!smu_table->boot_overdrive_table) {
469 ret = -ENOMEM;
470 goto err3_out;
471 }
472
473 smu_table->user_overdrive_table =
474 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
475 if (!smu_table->user_overdrive_table) {
476 ret = -ENOMEM;
477 goto err4_out;
478 }
479 }
480
481 smu_table->combo_pptable =
482 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
483 if (!smu_table->combo_pptable) {
484 ret = -ENOMEM;
485 goto err5_out;
486 }
487
488 return 0;
489
490 err5_out:
491 kfree(smu_table->user_overdrive_table);
492 err4_out:
493 kfree(smu_table->boot_overdrive_table);
494 err3_out:
495 kfree(smu_table->overdrive_table);
496 err2_out:
497 kfree(smu_table->max_sustainable_clocks);
498 err1_out:
499 kfree(smu_table->driver_pptable);
500 err0_out:
501 return ret;
502 }
503
smu_v13_0_fini_smc_tables(struct smu_context * smu)504 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
505 {
506 struct smu_table_context *smu_table = &smu->smu_table;
507 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
508
509 kfree(smu_table->gpu_metrics_table);
510 kfree(smu_table->combo_pptable);
511 kfree(smu_table->user_overdrive_table);
512 kfree(smu_table->boot_overdrive_table);
513 kfree(smu_table->overdrive_table);
514 kfree(smu_table->max_sustainable_clocks);
515 kfree(smu_table->driver_pptable);
516 smu_table->gpu_metrics_table = NULL;
517 smu_table->combo_pptable = NULL;
518 smu_table->user_overdrive_table = NULL;
519 smu_table->boot_overdrive_table = NULL;
520 smu_table->overdrive_table = NULL;
521 smu_table->max_sustainable_clocks = NULL;
522 smu_table->driver_pptable = NULL;
523 kfree(smu_table->hardcode_pptable);
524 smu_table->hardcode_pptable = NULL;
525
526 kfree(smu_table->ecc_table);
527 kfree(smu_table->metrics_table);
528 kfree(smu_table->watermarks_table);
529 smu_table->ecc_table = NULL;
530 smu_table->metrics_table = NULL;
531 smu_table->watermarks_table = NULL;
532 smu_table->metrics_time = 0;
533
534 kfree(smu_dpm->dpm_policies);
535 kfree(smu_dpm->dpm_context);
536 kfree(smu_dpm->golden_dpm_context);
537 kfree(smu_dpm->dpm_current_power_state);
538 kfree(smu_dpm->dpm_request_power_state);
539 smu_dpm->dpm_policies = NULL;
540 smu_dpm->dpm_context = NULL;
541 smu_dpm->golden_dpm_context = NULL;
542 smu_dpm->dpm_context_size = 0;
543 smu_dpm->dpm_current_power_state = NULL;
544 smu_dpm->dpm_request_power_state = NULL;
545
546 return 0;
547 }
548
smu_v13_0_init_power(struct smu_context * smu)549 int smu_v13_0_init_power(struct smu_context *smu)
550 {
551 struct smu_power_context *smu_power = &smu->smu_power;
552
553 if (smu_power->power_context || smu_power->power_context_size != 0)
554 return -EINVAL;
555
556 smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
557 GFP_KERNEL);
558 if (!smu_power->power_context)
559 return -ENOMEM;
560 smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
561
562 return 0;
563 }
564
smu_v13_0_fini_power(struct smu_context * smu)565 int smu_v13_0_fini_power(struct smu_context *smu)
566 {
567 struct smu_power_context *smu_power = &smu->smu_power;
568
569 if (!smu_power->power_context || smu_power->power_context_size == 0)
570 return -EINVAL;
571
572 kfree(smu_power->power_context);
573 smu_power->power_context = NULL;
574 smu_power->power_context_size = 0;
575
576 return 0;
577 }
578
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)579 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
580 {
581 int ret, index;
582 uint16_t size;
583 uint8_t frev, crev;
584 struct atom_common_table_header *header;
585 struct atom_firmware_info_v3_4 *v_3_4;
586 struct atom_firmware_info_v3_3 *v_3_3;
587 struct atom_firmware_info_v3_1 *v_3_1;
588 struct atom_smu_info_v3_6 *smu_info_v3_6;
589 struct atom_smu_info_v4_0 *smu_info_v4_0;
590
591 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
592 firmwareinfo);
593
594 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
595 (uint8_t **)&header);
596 if (ret)
597 return ret;
598
599 if (header->format_revision != 3) {
600 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
601 return -EINVAL;
602 }
603
604 switch (header->content_revision) {
605 case 0:
606 case 1:
607 case 2:
608 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
609 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
610 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
611 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
612 smu->smu_table.boot_values.socclk = 0;
613 smu->smu_table.boot_values.dcefclk = 0;
614 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
615 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
616 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
617 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
618 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
619 smu->smu_table.boot_values.pp_table_id = 0;
620 break;
621 case 3:
622 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
623 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
624 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
625 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
626 smu->smu_table.boot_values.socclk = 0;
627 smu->smu_table.boot_values.dcefclk = 0;
628 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
629 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
630 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
631 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
632 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
633 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
634 break;
635 case 4:
636 default:
637 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
638 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
639 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
640 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
641 smu->smu_table.boot_values.socclk = 0;
642 smu->smu_table.boot_values.dcefclk = 0;
643 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
644 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
645 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
646 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
647 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
648 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
649 break;
650 }
651
652 smu->smu_table.boot_values.format_revision = header->format_revision;
653 smu->smu_table.boot_values.content_revision = header->content_revision;
654
655 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
656 smu_info);
657 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
658 (uint8_t **)&header)) {
659
660 if ((frev == 3) && (crev == 6)) {
661 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
662
663 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
664 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
665 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
666 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
667 } else if ((frev == 3) && (crev == 1)) {
668 return 0;
669 } else if ((frev == 4) && (crev == 0)) {
670 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
671
672 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
673 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
674 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
675 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
676 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
677 } else {
678 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
679 (uint32_t)frev, (uint32_t)crev);
680 }
681 }
682
683 return 0;
684 }
685
686
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)687 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
688 {
689 struct smu_table_context *smu_table = &smu->smu_table;
690 struct smu_table *memory_pool = &smu_table->memory_pool;
691 int ret = 0;
692 uint64_t address;
693 uint32_t address_low, address_high;
694
695 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
696 return ret;
697
698 address = memory_pool->mc_address;
699 address_high = (uint32_t)upper_32_bits(address);
700 address_low = (uint32_t)lower_32_bits(address);
701
702 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
703 address_high, NULL);
704 if (ret)
705 return ret;
706 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
707 address_low, NULL);
708 if (ret)
709 return ret;
710 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
711 (uint32_t)memory_pool->size, NULL);
712 if (ret)
713 return ret;
714
715 return ret;
716 }
717
smu_v13_0_set_driver_table_location(struct smu_context * smu)718 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
719 {
720 struct smu_table *driver_table = &smu->smu_table.driver_table;
721 int ret = 0;
722
723 if (driver_table->mc_address) {
724 ret = smu_cmn_send_smc_msg_with_param(smu,
725 SMU_MSG_SetDriverDramAddrHigh,
726 upper_32_bits(driver_table->mc_address),
727 NULL);
728 if (!ret)
729 ret = smu_cmn_send_smc_msg_with_param(smu,
730 SMU_MSG_SetDriverDramAddrLow,
731 lower_32_bits(driver_table->mc_address),
732 NULL);
733 }
734
735 return ret;
736 }
737
smu_v13_0_set_tool_table_location(struct smu_context * smu)738 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
739 {
740 int ret = 0;
741 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
742
743 if (tool_table->mc_address) {
744 ret = smu_cmn_send_smc_msg_with_param(smu,
745 SMU_MSG_SetToolsDramAddrHigh,
746 upper_32_bits(tool_table->mc_address),
747 NULL);
748 if (!ret)
749 ret = smu_cmn_send_smc_msg_with_param(smu,
750 SMU_MSG_SetToolsDramAddrLow,
751 lower_32_bits(tool_table->mc_address),
752 NULL);
753 }
754
755 return ret;
756 }
757
smu_v13_0_set_allowed_mask(struct smu_context * smu)758 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
759 {
760 struct smu_feature *feature = &smu->smu_feature;
761 int ret = 0;
762 uint32_t feature_mask[2];
763
764 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
765 feature->feature_num < 64)
766 return -EINVAL;
767
768 bitmap_to_arr32(feature_mask, feature->allowed, 64);
769
770 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
771 feature_mask[1], NULL);
772 if (ret)
773 return ret;
774
775 return smu_cmn_send_smc_msg_with_param(smu,
776 SMU_MSG_SetAllowedFeaturesMaskLow,
777 feature_mask[0],
778 NULL);
779 }
780
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)781 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
782 {
783 int ret = 0;
784 struct amdgpu_device *adev = smu->adev;
785
786 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
787 case IP_VERSION(13, 0, 0):
788 case IP_VERSION(13, 0, 1):
789 case IP_VERSION(13, 0, 3):
790 case IP_VERSION(13, 0, 4):
791 case IP_VERSION(13, 0, 5):
792 case IP_VERSION(13, 0, 7):
793 case IP_VERSION(13, 0, 8):
794 case IP_VERSION(13, 0, 10):
795 case IP_VERSION(13, 0, 11):
796 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
797 return 0;
798 if (enable)
799 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
800 else
801 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
802 break;
803 default:
804 break;
805 }
806
807 return ret;
808 }
809
smu_v13_0_system_features_control(struct smu_context * smu,bool en)810 int smu_v13_0_system_features_control(struct smu_context *smu,
811 bool en)
812 {
813 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
814 SMU_MSG_DisableAllSmuFeatures), NULL);
815 }
816
smu_v13_0_notify_display_change(struct smu_context * smu)817 int smu_v13_0_notify_display_change(struct smu_context *smu)
818 {
819 int ret = 0;
820
821 if (!amdgpu_device_has_dc_support(smu->adev))
822 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL);
823
824 return ret;
825 }
826
827 static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)828 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
829 enum smu_clk_type clock_select)
830 {
831 int ret = 0;
832 int clk_id;
833
834 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
835 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
836 return 0;
837
838 clk_id = smu_cmn_to_asic_specific_index(smu,
839 CMN2ASIC_MAPPING_CLK,
840 clock_select);
841 if (clk_id < 0)
842 return -EINVAL;
843
844 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
845 clk_id << 16, clock);
846 if (ret) {
847 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
848 return ret;
849 }
850
851 if (*clock != 0)
852 return 0;
853
854 /* if DC limit is zero, return AC limit */
855 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
856 clk_id << 16, clock);
857 if (ret) {
858 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
859 return ret;
860 }
861
862 return 0;
863 }
864
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)865 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
866 {
867 struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
868 smu->smu_table.max_sustainable_clocks;
869 int ret = 0;
870
871 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
872 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
873 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
874 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
875 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
876 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
877
878 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
879 ret = smu_v13_0_get_max_sustainable_clock(smu,
880 &(max_sustainable_clocks->uclock),
881 SMU_UCLK);
882 if (ret) {
883 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
884 __func__);
885 return ret;
886 }
887 }
888
889 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
890 ret = smu_v13_0_get_max_sustainable_clock(smu,
891 &(max_sustainable_clocks->soc_clock),
892 SMU_SOCCLK);
893 if (ret) {
894 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
895 __func__);
896 return ret;
897 }
898 }
899
900 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
901 ret = smu_v13_0_get_max_sustainable_clock(smu,
902 &(max_sustainable_clocks->dcef_clock),
903 SMU_DCEFCLK);
904 if (ret) {
905 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
906 __func__);
907 return ret;
908 }
909
910 ret = smu_v13_0_get_max_sustainable_clock(smu,
911 &(max_sustainable_clocks->display_clock),
912 SMU_DISPCLK);
913 if (ret) {
914 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
915 __func__);
916 return ret;
917 }
918 ret = smu_v13_0_get_max_sustainable_clock(smu,
919 &(max_sustainable_clocks->phy_clock),
920 SMU_PHYCLK);
921 if (ret) {
922 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
923 __func__);
924 return ret;
925 }
926 ret = smu_v13_0_get_max_sustainable_clock(smu,
927 &(max_sustainable_clocks->pixel_clock),
928 SMU_PIXCLK);
929 if (ret) {
930 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
931 __func__);
932 return ret;
933 }
934 }
935
936 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
937 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
938
939 return 0;
940 }
941
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)942 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
943 uint32_t *power_limit)
944 {
945 int power_src;
946 int ret = 0;
947
948 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
949 return -EINVAL;
950
951 power_src = smu_cmn_to_asic_specific_index(smu,
952 CMN2ASIC_MAPPING_PWR,
953 smu->adev->pm.ac_power ?
954 SMU_POWER_SOURCE_AC :
955 SMU_POWER_SOURCE_DC);
956 if (power_src < 0)
957 return -EINVAL;
958
959 ret = smu_cmn_send_smc_msg_with_param(smu,
960 SMU_MSG_GetPptLimit,
961 power_src << 16,
962 power_limit);
963 if (ret)
964 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
965
966 return ret;
967 }
968
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)969 int smu_v13_0_set_power_limit(struct smu_context *smu,
970 enum smu_ppt_limit_type limit_type,
971 uint32_t limit)
972 {
973 int ret = 0;
974
975 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
976 return -EINVAL;
977
978 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
979 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
980 return -EOPNOTSUPP;
981 }
982
983 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
984 if (ret) {
985 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
986 return ret;
987 }
988
989 smu->current_power_limit = limit;
990
991 return 0;
992 }
993
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)994 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
995 {
996 return smu_cmn_send_smc_msg(smu,
997 SMU_MSG_AllowIHHostInterrupt,
998 NULL);
999 }
1000
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1001 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1002 {
1003 int ret = 0;
1004
1005 if (smu->dc_controlled_by_gpio &&
1006 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1007 ret = smu_v13_0_allow_ih_interrupt(smu);
1008
1009 return ret;
1010 }
1011
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1012 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1013 {
1014 int ret = 0;
1015
1016 if (!smu->irq_source.num_types)
1017 return 0;
1018
1019 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1020 if (ret)
1021 return ret;
1022
1023 return smu_v13_0_process_pending_interrupt(smu);
1024 }
1025
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1026 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1027 {
1028 if (!smu->irq_source.num_types)
1029 return 0;
1030
1031 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1032 }
1033
convert_to_vddc(uint8_t vid)1034 static uint16_t convert_to_vddc(uint8_t vid)
1035 {
1036 return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1037 }
1038
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1039 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1040 {
1041 struct amdgpu_device *adev = smu->adev;
1042 uint32_t vdd = 0, val_vid = 0;
1043
1044 if (!value)
1045 return -EINVAL;
1046 val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1047 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1048 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1049
1050 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1051
1052 *value = vdd;
1053
1054 return 0;
1055
1056 }
1057
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1058 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1059 {
1060 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1061 return AMD_FAN_CTRL_MANUAL;
1062 else
1063 return AMD_FAN_CTRL_AUTO;
1064 }
1065
1066 static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1067 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1068 {
1069 int ret = 0;
1070
1071 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1072 return 0;
1073
1074 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1075 if (ret)
1076 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1077 __func__, (auto_fan_control ? "Start" : "Stop"));
1078
1079 return ret;
1080 }
1081
1082 static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1083 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1084 {
1085 struct amdgpu_device *adev = smu->adev;
1086
1087 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1088 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1089 CG_FDO_CTRL2, TMIN, 0));
1090 WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1091 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1092 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1093
1094 return 0;
1095 }
1096
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1097 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1098 uint32_t speed)
1099 {
1100 struct amdgpu_device *adev = smu->adev;
1101 uint32_t duty100, duty;
1102 uint64_t tmp64;
1103
1104 speed = min_t(uint32_t, speed, 255);
1105
1106 if (smu_v13_0_auto_fan_control(smu, 0))
1107 return -EINVAL;
1108
1109 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1110 CG_FDO_CTRL1, FMAX_DUTY100);
1111 if (!duty100)
1112 return -EINVAL;
1113
1114 tmp64 = (uint64_t)speed * duty100;
1115 do_div(tmp64, 255);
1116 duty = (uint32_t)tmp64;
1117
1118 WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1119 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1120 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1121
1122 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1123 }
1124
1125 int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1126 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1127 uint32_t mode)
1128 {
1129 int ret = 0;
1130
1131 switch (mode) {
1132 case AMD_FAN_CTRL_NONE:
1133 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1134 break;
1135 case AMD_FAN_CTRL_MANUAL:
1136 ret = smu_v13_0_auto_fan_control(smu, 0);
1137 break;
1138 case AMD_FAN_CTRL_AUTO:
1139 ret = smu_v13_0_auto_fan_control(smu, 1);
1140 break;
1141 default:
1142 break;
1143 }
1144
1145 if (ret) {
1146 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1147 return -EINVAL;
1148 }
1149
1150 return ret;
1151 }
1152
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1153 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1154 uint32_t speed)
1155 {
1156 struct amdgpu_device *adev = smu->adev;
1157 uint32_t crystal_clock_freq = 2500;
1158 uint32_t tach_period;
1159 int ret;
1160
1161 if (!speed || speed > UINT_MAX/8)
1162 return -EINVAL;
1163
1164 ret = smu_v13_0_auto_fan_control(smu, 0);
1165 if (ret)
1166 return ret;
1167
1168 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1169 WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1170 REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1171 CG_TACH_CTRL, TARGET_PERIOD,
1172 tach_period));
1173
1174 return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1175 }
1176
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1177 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1178 uint32_t pstate)
1179 {
1180 int ret = 0;
1181 ret = smu_cmn_send_smc_msg_with_param(smu,
1182 SMU_MSG_SetXgmiMode,
1183 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1184 NULL);
1185 return ret;
1186 }
1187
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1188 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1189 struct amdgpu_irq_src *source,
1190 unsigned tyep,
1191 enum amdgpu_interrupt_state state)
1192 {
1193 struct smu_context *smu = adev->powerplay.pp_handle;
1194 uint32_t low, high;
1195 uint32_t val = 0;
1196
1197 switch (state) {
1198 case AMDGPU_IRQ_STATE_DISABLE:
1199 /* For THM irqs */
1200 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1201 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1202 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1203 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1204
1205 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1206
1207 /* For MP1 SW irqs */
1208 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1209 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1210 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1211
1212 break;
1213 case AMDGPU_IRQ_STATE_ENABLE:
1214 /* For THM irqs */
1215 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1216 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1217 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1218 smu->thermal_range.software_shutdown_temp);
1219
1220 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1221 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1222 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1223 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1224 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1225 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1226 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1227 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1228 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1229
1230 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1231 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1232 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1233 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1234
1235 /* For MP1 SW irqs */
1236 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1237 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1238 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1239 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1240
1241 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1242 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1243 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1244
1245 break;
1246 default:
1247 break;
1248 }
1249
1250 return 0;
1251 }
1252
smu_v13_0_interrupt_work(struct smu_context * smu)1253 void smu_v13_0_interrupt_work(struct smu_context *smu)
1254 {
1255 smu_cmn_send_smc_msg(smu,
1256 SMU_MSG_ReenableAcDcInterrupt,
1257 NULL);
1258 }
1259
1260 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1261 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1262 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1263
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1264 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1265 struct amdgpu_irq_src *source,
1266 struct amdgpu_iv_entry *entry)
1267 {
1268 struct smu_context *smu = adev->powerplay.pp_handle;
1269 uint32_t client_id = entry->client_id;
1270 uint32_t src_id = entry->src_id;
1271 /*
1272 * ctxid is used to distinguish different
1273 * events for SMCToHost interrupt.
1274 */
1275 uint32_t ctxid = entry->src_data[0];
1276 uint32_t data;
1277 uint32_t high;
1278
1279 if (client_id == SOC15_IH_CLIENTID_THM) {
1280 switch (src_id) {
1281 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1282 schedule_delayed_work(&smu->swctf_delayed_work,
1283 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1284 break;
1285 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1286 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1287 break;
1288 default:
1289 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1290 src_id);
1291 break;
1292 }
1293 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1294 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1295 /*
1296 * HW CTF just occurred. Shutdown to prevent further damage.
1297 */
1298 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1299 orderly_poweroff(true);
1300 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1301 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1302 /* ACK SMUToHost interrupt */
1303 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1304 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1305 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1306
1307 switch (ctxid) {
1308 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1309 dev_dbg(adev->dev, "Switched to AC mode!\n");
1310 schedule_work(&smu->interrupt_work);
1311 adev->pm.ac_power = true;
1312 break;
1313 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1314 dev_dbg(adev->dev, "Switched to DC mode!\n");
1315 schedule_work(&smu->interrupt_work);
1316 adev->pm.ac_power = false;
1317 break;
1318 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1319 /*
1320 * Increment the throttle interrupt counter
1321 */
1322 atomic64_inc(&smu->throttle_int_counter);
1323
1324 if (!atomic_read(&adev->throttling_logging_enabled))
1325 return 0;
1326
1327 if (__ratelimit(&adev->throttling_logging_rs))
1328 schedule_work(&smu->throttling_logging_work);
1329
1330 break;
1331 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL:
1332 high = smu->thermal_range.software_shutdown_temp +
1333 smu->thermal_range.software_shutdown_temp_offset;
1334 high = min_t(typeof(high),
1335 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1336 high);
1337 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1338 high,
1339 smu->thermal_range.software_shutdown_temp_offset);
1340
1341 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1342 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1343 DIG_THERM_INTH,
1344 (high & 0xff));
1345 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1346 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1347 break;
1348 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY:
1349 high = min_t(typeof(high),
1350 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1351 smu->thermal_range.software_shutdown_temp);
1352 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1353
1354 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1355 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1356 DIG_THERM_INTH,
1357 (high & 0xff));
1358 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1359 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1360 break;
1361 default:
1362 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1363 ctxid, client_id);
1364 break;
1365 }
1366 }
1367 }
1368
1369 return 0;
1370 }
1371
1372 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1373 .set = smu_v13_0_set_irq_state,
1374 .process = smu_v13_0_irq_process,
1375 };
1376
smu_v13_0_register_irq_handler(struct smu_context * smu)1377 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1378 {
1379 struct amdgpu_device *adev = smu->adev;
1380 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1381 int ret = 0;
1382
1383 if (amdgpu_sriov_vf(adev))
1384 return 0;
1385
1386 irq_src->num_types = 1;
1387 irq_src->funcs = &smu_v13_0_irq_funcs;
1388
1389 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1390 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1391 irq_src);
1392 if (ret)
1393 return ret;
1394
1395 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1396 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1397 irq_src);
1398 if (ret)
1399 return ret;
1400
1401 /* Register CTF(GPIO_19) interrupt */
1402 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1403 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1404 irq_src);
1405 if (ret)
1406 return ret;
1407
1408 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1409 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1410 irq_src);
1411 if (ret)
1412 return ret;
1413
1414 return ret;
1415 }
1416
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1417 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1418 struct pp_smu_nv_clock_table *max_clocks)
1419 {
1420 struct smu_table_context *table_context = &smu->smu_table;
1421 struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1422
1423 if (!max_clocks || !table_context->max_sustainable_clocks)
1424 return -EINVAL;
1425
1426 sustainable_clocks = table_context->max_sustainable_clocks;
1427
1428 max_clocks->dcfClockInKhz =
1429 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1430 max_clocks->displayClockInKhz =
1431 (unsigned int) sustainable_clocks->display_clock * 1000;
1432 max_clocks->phyClockInKhz =
1433 (unsigned int) sustainable_clocks->phy_clock * 1000;
1434 max_clocks->pixelClockInKhz =
1435 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1436 max_clocks->uClockInKhz =
1437 (unsigned int) sustainable_clocks->uclock * 1000;
1438 max_clocks->socClockInKhz =
1439 (unsigned int) sustainable_clocks->soc_clock * 1000;
1440 max_clocks->dscClockInKhz = 0;
1441 max_clocks->dppClockInKhz = 0;
1442 max_clocks->fabricClockInKhz = 0;
1443
1444 return 0;
1445 }
1446
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1447 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1448 {
1449 int ret = 0;
1450
1451 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1452
1453 return ret;
1454 }
1455
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1456 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1457 uint64_t event_arg)
1458 {
1459 int ret = 0;
1460
1461 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1462 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1463
1464 return ret;
1465 }
1466
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1467 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1468 uint64_t event_arg)
1469 {
1470 int ret = -EINVAL;
1471
1472 switch (event) {
1473 case SMU_EVENT_RESET_COMPLETE:
1474 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1475 break;
1476 default:
1477 break;
1478 }
1479
1480 return ret;
1481 }
1482
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1483 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1484 uint32_t *min, uint32_t *max)
1485 {
1486 int ret = 0, clk_id = 0;
1487 uint32_t param = 0;
1488 uint32_t clock_limit;
1489
1490 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1491 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
1492 if (ret)
1493 return ret;
1494
1495 /* clock in Mhz unit */
1496 if (min)
1497 *min = clock_limit / 100;
1498 if (max)
1499 *max = clock_limit / 100;
1500
1501 return 0;
1502 }
1503
1504 clk_id = smu_cmn_to_asic_specific_index(smu,
1505 CMN2ASIC_MAPPING_CLK,
1506 clk_type);
1507 if (clk_id < 0) {
1508 ret = -EINVAL;
1509 goto failed;
1510 }
1511 param = (clk_id & 0xffff) << 16;
1512
1513 if (max) {
1514 if (smu->adev->pm.ac_power)
1515 ret = smu_cmn_send_smc_msg_with_param(smu,
1516 SMU_MSG_GetMaxDpmFreq,
1517 param,
1518 max);
1519 else
1520 ret = smu_cmn_send_smc_msg_with_param(smu,
1521 SMU_MSG_GetDcModeMaxDpmFreq,
1522 param,
1523 max);
1524 if (ret)
1525 goto failed;
1526 }
1527
1528 if (min) {
1529 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1530 if (ret)
1531 goto failed;
1532 }
1533
1534 failed:
1535 return ret;
1536 }
1537
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1538 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1539 enum smu_clk_type clk_type,
1540 uint32_t min,
1541 uint32_t max,
1542 bool automatic)
1543 {
1544 int ret = 0, clk_id = 0;
1545 uint32_t param;
1546
1547 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1548 return 0;
1549
1550 clk_id = smu_cmn_to_asic_specific_index(smu,
1551 CMN2ASIC_MAPPING_CLK,
1552 clk_type);
1553 if (clk_id < 0)
1554 return clk_id;
1555
1556 if (max > 0) {
1557 if (automatic)
1558 param = (uint32_t)((clk_id << 16) | 0xffff);
1559 else
1560 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1561 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1562 param, NULL);
1563 if (ret)
1564 goto out;
1565 }
1566
1567 if (min > 0) {
1568 if (automatic)
1569 param = (uint32_t)((clk_id << 16) | 0);
1570 else
1571 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1572 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1573 param, NULL);
1574 if (ret)
1575 goto out;
1576 }
1577
1578 out:
1579 return ret;
1580 }
1581
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1582 int smu_v13_0_set_performance_level(struct smu_context *smu,
1583 enum amd_dpm_forced_level level)
1584 {
1585 struct smu_13_0_dpm_context *dpm_context =
1586 smu->smu_dpm.dpm_context;
1587 struct smu_13_0_dpm_table *gfx_table =
1588 &dpm_context->dpm_tables.gfx_table;
1589 struct smu_13_0_dpm_table *mem_table =
1590 &dpm_context->dpm_tables.uclk_table;
1591 struct smu_13_0_dpm_table *soc_table =
1592 &dpm_context->dpm_tables.soc_table;
1593 struct smu_13_0_dpm_table *vclk_table =
1594 &dpm_context->dpm_tables.vclk_table;
1595 struct smu_13_0_dpm_table *dclk_table =
1596 &dpm_context->dpm_tables.dclk_table;
1597 struct smu_13_0_dpm_table *fclk_table =
1598 &dpm_context->dpm_tables.fclk_table;
1599 struct smu_umd_pstate_table *pstate_table =
1600 &smu->pstate_table;
1601 struct amdgpu_device *adev = smu->adev;
1602 uint32_t sclk_min = 0, sclk_max = 0;
1603 uint32_t mclk_min = 0, mclk_max = 0;
1604 uint32_t socclk_min = 0, socclk_max = 0;
1605 uint32_t vclk_min = 0, vclk_max = 0;
1606 uint32_t dclk_min = 0, dclk_max = 0;
1607 uint32_t fclk_min = 0, fclk_max = 0;
1608 int ret = 0, i;
1609 bool auto_level = false;
1610
1611 switch (level) {
1612 case AMD_DPM_FORCED_LEVEL_HIGH:
1613 sclk_min = sclk_max = gfx_table->max;
1614 mclk_min = mclk_max = mem_table->max;
1615 socclk_min = socclk_max = soc_table->max;
1616 vclk_min = vclk_max = vclk_table->max;
1617 dclk_min = dclk_max = dclk_table->max;
1618 fclk_min = fclk_max = fclk_table->max;
1619 break;
1620 case AMD_DPM_FORCED_LEVEL_LOW:
1621 sclk_min = sclk_max = gfx_table->min;
1622 mclk_min = mclk_max = mem_table->min;
1623 socclk_min = socclk_max = soc_table->min;
1624 vclk_min = vclk_max = vclk_table->min;
1625 dclk_min = dclk_max = dclk_table->min;
1626 fclk_min = fclk_max = fclk_table->min;
1627 break;
1628 case AMD_DPM_FORCED_LEVEL_AUTO:
1629 sclk_min = gfx_table->min;
1630 sclk_max = gfx_table->max;
1631 mclk_min = mem_table->min;
1632 mclk_max = mem_table->max;
1633 socclk_min = soc_table->min;
1634 socclk_max = soc_table->max;
1635 vclk_min = vclk_table->min;
1636 vclk_max = vclk_table->max;
1637 dclk_min = dclk_table->min;
1638 dclk_max = dclk_table->max;
1639 fclk_min = fclk_table->min;
1640 fclk_max = fclk_table->max;
1641 auto_level = true;
1642 break;
1643 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1644 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1645 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1646 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1647 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1648 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1649 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1650 break;
1651 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1652 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1653 break;
1654 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1655 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1656 break;
1657 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1658 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1659 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1660 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1661 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1662 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1663 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1664 break;
1665 case AMD_DPM_FORCED_LEVEL_MANUAL:
1666 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1667 return 0;
1668 default:
1669 dev_err(adev->dev, "Invalid performance level %d\n", level);
1670 return -EINVAL;
1671 }
1672
1673 /*
1674 * Unset those settings for SMU 13.0.2. As soft limits settings
1675 * for those clock domains are not supported.
1676 */
1677 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) {
1678 mclk_min = mclk_max = 0;
1679 socclk_min = socclk_max = 0;
1680 vclk_min = vclk_max = 0;
1681 dclk_min = dclk_max = 0;
1682 fclk_min = fclk_max = 0;
1683 auto_level = false;
1684 }
1685
1686 if (sclk_min && sclk_max) {
1687 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1688 SMU_GFXCLK,
1689 sclk_min,
1690 sclk_max,
1691 auto_level);
1692 if (ret)
1693 return ret;
1694
1695 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1696 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1697 }
1698
1699 if (mclk_min && mclk_max) {
1700 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1701 SMU_MCLK,
1702 mclk_min,
1703 mclk_max,
1704 auto_level);
1705 if (ret)
1706 return ret;
1707
1708 pstate_table->uclk_pstate.curr.min = mclk_min;
1709 pstate_table->uclk_pstate.curr.max = mclk_max;
1710 }
1711
1712 if (socclk_min && socclk_max) {
1713 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1714 SMU_SOCCLK,
1715 socclk_min,
1716 socclk_max,
1717 auto_level);
1718 if (ret)
1719 return ret;
1720
1721 pstate_table->socclk_pstate.curr.min = socclk_min;
1722 pstate_table->socclk_pstate.curr.max = socclk_max;
1723 }
1724
1725 if (vclk_min && vclk_max) {
1726 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1727 if (adev->vcn.harvest_config & (1 << i))
1728 continue;
1729 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1730 i ? SMU_VCLK1 : SMU_VCLK,
1731 vclk_min,
1732 vclk_max,
1733 auto_level);
1734 if (ret)
1735 return ret;
1736 }
1737 pstate_table->vclk_pstate.curr.min = vclk_min;
1738 pstate_table->vclk_pstate.curr.max = vclk_max;
1739 }
1740
1741 if (dclk_min && dclk_max) {
1742 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1743 if (adev->vcn.harvest_config & (1 << i))
1744 continue;
1745 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1746 i ? SMU_DCLK1 : SMU_DCLK,
1747 dclk_min,
1748 dclk_max,
1749 auto_level);
1750 if (ret)
1751 return ret;
1752 }
1753 pstate_table->dclk_pstate.curr.min = dclk_min;
1754 pstate_table->dclk_pstate.curr.max = dclk_max;
1755 }
1756
1757 if (fclk_min && fclk_max) {
1758 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1759 SMU_FCLK,
1760 fclk_min,
1761 fclk_max,
1762 auto_level);
1763 if (ret)
1764 return ret;
1765
1766 pstate_table->fclk_pstate.curr.min = fclk_min;
1767 pstate_table->fclk_pstate.curr.max = fclk_max;
1768 }
1769
1770 return ret;
1771 }
1772
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1773 int smu_v13_0_set_power_source(struct smu_context *smu,
1774 enum smu_power_src_type power_src)
1775 {
1776 int pwr_source;
1777
1778 pwr_source = smu_cmn_to_asic_specific_index(smu,
1779 CMN2ASIC_MAPPING_PWR,
1780 (uint32_t)power_src);
1781 if (pwr_source < 0)
1782 return -EINVAL;
1783
1784 return smu_cmn_send_smc_msg_with_param(smu,
1785 SMU_MSG_NotifyPowerSource,
1786 pwr_source,
1787 NULL);
1788 }
1789
smu_v13_0_get_boot_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1790 int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
1791 enum smu_clk_type clk_type,
1792 uint32_t *value)
1793 {
1794 int ret = 0;
1795
1796 switch (clk_type) {
1797 case SMU_MCLK:
1798 case SMU_UCLK:
1799 *value = smu->smu_table.boot_values.uclk;
1800 break;
1801 case SMU_FCLK:
1802 *value = smu->smu_table.boot_values.fclk;
1803 break;
1804 case SMU_GFXCLK:
1805 case SMU_SCLK:
1806 *value = smu->smu_table.boot_values.gfxclk;
1807 break;
1808 case SMU_SOCCLK:
1809 *value = smu->smu_table.boot_values.socclk;
1810 break;
1811 case SMU_VCLK:
1812 *value = smu->smu_table.boot_values.vclk;
1813 break;
1814 case SMU_DCLK:
1815 *value = smu->smu_table.boot_values.dclk;
1816 break;
1817 default:
1818 ret = -EINVAL;
1819 break;
1820 }
1821 return ret;
1822 }
1823
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1824 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1825 enum smu_clk_type clk_type, uint16_t level,
1826 uint32_t *value)
1827 {
1828 int ret = 0, clk_id = 0;
1829 uint32_t param;
1830
1831 if (!value)
1832 return -EINVAL;
1833
1834 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1835 return smu_v13_0_get_boot_freq_by_index(smu, clk_type, value);
1836
1837 clk_id = smu_cmn_to_asic_specific_index(smu,
1838 CMN2ASIC_MAPPING_CLK,
1839 clk_type);
1840 if (clk_id < 0)
1841 return clk_id;
1842
1843 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1844
1845 ret = smu_cmn_send_smc_msg_with_param(smu,
1846 SMU_MSG_GetDpmFreqByIndex,
1847 param,
1848 value);
1849 if (ret)
1850 return ret;
1851
1852 *value = *value & 0x7fffffff;
1853
1854 return ret;
1855 }
1856
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1857 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1858 enum smu_clk_type clk_type,
1859 uint32_t *value)
1860 {
1861 int ret;
1862
1863 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1864 /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1865 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) && (!ret && value))
1866 ++(*value);
1867
1868 return ret;
1869 }
1870
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1871 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1872 enum smu_clk_type clk_type,
1873 bool *is_fine_grained_dpm)
1874 {
1875 int ret = 0, clk_id = 0;
1876 uint32_t param;
1877 uint32_t value;
1878
1879 if (!is_fine_grained_dpm)
1880 return -EINVAL;
1881
1882 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1883 return 0;
1884
1885 clk_id = smu_cmn_to_asic_specific_index(smu,
1886 CMN2ASIC_MAPPING_CLK,
1887 clk_type);
1888 if (clk_id < 0)
1889 return clk_id;
1890
1891 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1892
1893 ret = smu_cmn_send_smc_msg_with_param(smu,
1894 SMU_MSG_GetDpmFreqByIndex,
1895 param,
1896 &value);
1897 if (ret)
1898 return ret;
1899
1900 /*
1901 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1902 * now, we un-support it
1903 */
1904 *is_fine_grained_dpm = value & 0x80000000;
1905
1906 return 0;
1907 }
1908
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)1909 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1910 enum smu_clk_type clk_type,
1911 struct smu_13_0_dpm_table *single_dpm_table)
1912 {
1913 int ret = 0;
1914 uint32_t clk;
1915 int i;
1916
1917 ret = smu_v13_0_get_dpm_level_count(smu,
1918 clk_type,
1919 &single_dpm_table->count);
1920 if (ret) {
1921 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1922 return ret;
1923 }
1924
1925 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) {
1926 ret = smu_v13_0_get_fine_grained_status(smu,
1927 clk_type,
1928 &single_dpm_table->is_fine_grained);
1929 if (ret) {
1930 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1931 return ret;
1932 }
1933 }
1934
1935 for (i = 0; i < single_dpm_table->count; i++) {
1936 ret = smu_v13_0_get_dpm_freq_by_index(smu,
1937 clk_type,
1938 i,
1939 &clk);
1940 if (ret) {
1941 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1942 return ret;
1943 }
1944
1945 single_dpm_table->dpm_levels[i].value = clk;
1946 single_dpm_table->dpm_levels[i].enabled = true;
1947
1948 if (i == 0)
1949 single_dpm_table->min = clk;
1950 else if (i == single_dpm_table->count - 1)
1951 single_dpm_table->max = clk;
1952 }
1953
1954 return 0;
1955 }
1956
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)1957 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
1958 {
1959 struct amdgpu_device *adev = smu->adev;
1960
1961 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1962 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1963 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1964 }
1965
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)1966 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
1967 {
1968 uint32_t width_level;
1969
1970 width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
1971 if (width_level > LINK_WIDTH_MAX)
1972 width_level = 0;
1973
1974 return link_width[width_level];
1975 }
1976
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)1977 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1978 {
1979 struct amdgpu_device *adev = smu->adev;
1980
1981 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1982 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1983 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1984 }
1985
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)1986 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
1987 {
1988 uint32_t speed_level;
1989
1990 speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
1991 if (speed_level > LINK_SPEED_MAX)
1992 speed_level = 0;
1993
1994 return link_speed[speed_level];
1995 }
1996
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable,int inst)1997 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
1998 bool enable,
1999 int inst)
2000 {
2001 struct amdgpu_device *adev = smu->adev;
2002 int ret = 0;
2003
2004 if (adev->vcn.harvest_config & (1 << inst))
2005 return ret;
2006
2007 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2008 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2009 inst << 16U, NULL);
2010
2011 return ret;
2012 }
2013
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2014 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2015 bool enable)
2016 {
2017 return smu_cmn_send_smc_msg_with_param(smu, enable ?
2018 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2019 0, NULL);
2020 }
2021
smu_v13_0_run_btc(struct smu_context * smu)2022 int smu_v13_0_run_btc(struct smu_context *smu)
2023 {
2024 int res;
2025
2026 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2027 if (res)
2028 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2029
2030 return res;
2031 }
2032
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2033 int smu_v13_0_gpo_control(struct smu_context *smu,
2034 bool enablement)
2035 {
2036 int res;
2037
2038 res = smu_cmn_send_smc_msg_with_param(smu,
2039 SMU_MSG_AllowGpo,
2040 enablement ? 1 : 0,
2041 NULL);
2042 if (res)
2043 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2044
2045 return res;
2046 }
2047
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2048 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2049 bool enablement)
2050 {
2051 struct amdgpu_device *adev = smu->adev;
2052 int ret = 0;
2053
2054 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2055 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2056 if (ret) {
2057 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2058 return ret;
2059 }
2060 }
2061
2062 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2063 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2064 if (ret) {
2065 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2066 return ret;
2067 }
2068 }
2069
2070 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2071 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2072 if (ret) {
2073 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2074 return ret;
2075 }
2076 }
2077
2078 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2079 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2080 if (ret) {
2081 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2082 return ret;
2083 }
2084 }
2085
2086 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2087 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2088 if (ret) {
2089 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2090 return ret;
2091 }
2092 }
2093
2094 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2095 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2096 if (ret) {
2097 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2098 return ret;
2099 }
2100 }
2101
2102 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2103 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2104 if (ret) {
2105 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2106 return ret;
2107 }
2108 }
2109
2110 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2111 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2112 if (ret) {
2113 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2114 return ret;
2115 }
2116 }
2117
2118 return ret;
2119 }
2120
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2121 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2122 bool enablement)
2123 {
2124 int ret = 0;
2125
2126 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2127 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2128
2129 return ret;
2130 }
2131
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2132 static int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2133 enum smu_baco_seq baco_seq)
2134 {
2135 struct smu_baco_context *smu_baco = &smu->smu_baco;
2136 int ret;
2137
2138 ret = smu_cmn_send_smc_msg_with_param(smu,
2139 SMU_MSG_ArmD3,
2140 baco_seq,
2141 NULL);
2142 if (ret)
2143 return ret;
2144
2145 if (baco_seq == BACO_SEQ_BAMACO ||
2146 baco_seq == BACO_SEQ_BACO)
2147 smu_baco->state = SMU_BACO_STATE_ENTER;
2148 else
2149 smu_baco->state = SMU_BACO_STATE_EXIT;
2150
2151 return 0;
2152 }
2153
smu_v13_0_baco_get_state(struct smu_context * smu)2154 static enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2155 {
2156 struct smu_baco_context *smu_baco = &smu->smu_baco;
2157
2158 return smu_baco->state;
2159 }
2160
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2161 static int smu_v13_0_baco_set_state(struct smu_context *smu,
2162 enum smu_baco_state state)
2163 {
2164 struct smu_baco_context *smu_baco = &smu->smu_baco;
2165 struct amdgpu_device *adev = smu->adev;
2166 int ret = 0;
2167
2168 if (smu_v13_0_baco_get_state(smu) == state)
2169 return 0;
2170
2171 if (state == SMU_BACO_STATE_ENTER) {
2172 ret = smu_cmn_send_smc_msg_with_param(smu,
2173 SMU_MSG_EnterBaco,
2174 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2175 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2176 NULL);
2177 } else {
2178 ret = smu_cmn_send_smc_msg(smu,
2179 SMU_MSG_ExitBaco,
2180 NULL);
2181 if (ret)
2182 return ret;
2183
2184 /* clear vbios scratch 6 and 7 for coming asic reinit */
2185 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2186 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2187 }
2188
2189 if (!ret)
2190 smu_baco->state = state;
2191
2192 return ret;
2193 }
2194
smu_v13_0_get_bamaco_support(struct smu_context * smu)2195 int smu_v13_0_get_bamaco_support(struct smu_context *smu)
2196 {
2197 struct smu_baco_context *smu_baco = &smu->smu_baco;
2198 int bamaco_support = 0;
2199
2200 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
2201 return 0;
2202
2203 if (smu_baco->maco_support)
2204 bamaco_support |= MACO_SUPPORT;
2205
2206 /* return true if ASIC is in BACO state already */
2207 if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2208 return bamaco_support |= BACO_SUPPORT;
2209
2210 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2211 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2212 return 0;
2213
2214 return (bamaco_support |= BACO_SUPPORT);
2215 }
2216
smu_v13_0_baco_enter(struct smu_context * smu)2217 int smu_v13_0_baco_enter(struct smu_context *smu)
2218 {
2219 struct amdgpu_device *adev = smu->adev;
2220 int ret;
2221
2222 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2223 return smu_v13_0_baco_set_armd3_sequence(smu,
2224 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
2225 BACO_SEQ_BAMACO : BACO_SEQ_BACO);
2226 } else {
2227 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
2228 if (!ret)
2229 usleep_range(10000, 11000);
2230
2231 return ret;
2232 }
2233 }
2234
smu_v13_0_baco_exit(struct smu_context * smu)2235 int smu_v13_0_baco_exit(struct smu_context *smu)
2236 {
2237 struct amdgpu_device *adev = smu->adev;
2238 int ret;
2239
2240 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2241 /* Wait for PMFW handling for the Dstate change */
2242 usleep_range(10000, 11000);
2243 ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2244 } else {
2245 ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
2246 }
2247
2248 if (!ret)
2249 adev->gfx.is_poweron = false;
2250
2251 return ret;
2252 }
2253
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2254 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2255 {
2256 uint16_t index;
2257 struct amdgpu_device *adev = smu->adev;
2258
2259 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2260 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
2261 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
2262 }
2263
2264 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2265 SMU_MSG_EnableGfxImu);
2266 return smu_cmn_send_msg_without_waiting(smu, index,
2267 ENABLE_IMU_ARG_GFXOFF_ENABLE);
2268 }
2269
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2270 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2271 enum PP_OD_DPM_TABLE_COMMAND type,
2272 long input[], uint32_t size)
2273 {
2274 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2275 int ret = 0;
2276
2277 /* Only allowed in manual mode */
2278 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2279 return -EINVAL;
2280
2281 switch (type) {
2282 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2283 if (size != 2) {
2284 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2285 return -EINVAL;
2286 }
2287
2288 if (input[0] == 0) {
2289 if (input[1] < smu->gfx_default_hard_min_freq) {
2290 dev_warn(smu->adev->dev,
2291 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2292 input[1], smu->gfx_default_hard_min_freq);
2293 return -EINVAL;
2294 }
2295 smu->gfx_actual_hard_min_freq = input[1];
2296 } else if (input[0] == 1) {
2297 if (input[1] > smu->gfx_default_soft_max_freq) {
2298 dev_warn(smu->adev->dev,
2299 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2300 input[1], smu->gfx_default_soft_max_freq);
2301 return -EINVAL;
2302 }
2303 smu->gfx_actual_soft_max_freq = input[1];
2304 } else {
2305 return -EINVAL;
2306 }
2307 break;
2308 case PP_OD_RESTORE_DEFAULT_TABLE:
2309 if (size != 0) {
2310 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2311 return -EINVAL;
2312 }
2313 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2314 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2315 break;
2316 case PP_OD_COMMIT_DPM_TABLE:
2317 if (size != 0) {
2318 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2319 return -EINVAL;
2320 }
2321 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2322 dev_err(smu->adev->dev,
2323 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2324 smu->gfx_actual_hard_min_freq,
2325 smu->gfx_actual_soft_max_freq);
2326 return -EINVAL;
2327 }
2328
2329 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2330 smu->gfx_actual_hard_min_freq,
2331 NULL);
2332 if (ret) {
2333 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2334 return ret;
2335 }
2336
2337 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2338 smu->gfx_actual_soft_max_freq,
2339 NULL);
2340 if (ret) {
2341 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2342 return ret;
2343 }
2344 break;
2345 default:
2346 return -ENOSYS;
2347 }
2348
2349 return ret;
2350 }
2351
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2352 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2353 {
2354 struct smu_table_context *smu_table = &smu->smu_table;
2355
2356 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2357 smu_table->clocks_table, false);
2358 }
2359
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2360 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2361 {
2362 struct amdgpu_device *adev = smu->adev;
2363
2364 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2365 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2366 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2367 }
2368
smu_v13_0_mode1_reset(struct smu_context * smu)2369 int smu_v13_0_mode1_reset(struct smu_context *smu)
2370 {
2371 int ret = 0;
2372
2373 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2374 if (!ret)
2375 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2376
2377 return ret;
2378 }
2379
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2380 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2381 uint8_t pcie_gen_cap,
2382 uint8_t pcie_width_cap)
2383 {
2384 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2385 struct smu_13_0_pcie_table *pcie_table =
2386 &dpm_context->dpm_tables.pcie_table;
2387 int num_of_levels = pcie_table->num_of_link_levels;
2388 uint32_t smu_pcie_arg;
2389 int ret, i;
2390
2391 if (!num_of_levels)
2392 return 0;
2393
2394 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2395 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2396 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2397
2398 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2399 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2400
2401 /* Force all levels to use the same settings */
2402 for (i = 0; i < num_of_levels; i++) {
2403 pcie_table->pcie_gen[i] = pcie_gen_cap;
2404 pcie_table->pcie_lane[i] = pcie_width_cap;
2405 }
2406 } else {
2407 for (i = 0; i < num_of_levels; i++) {
2408 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2409 pcie_table->pcie_gen[i] = pcie_gen_cap;
2410 if (pcie_table->pcie_lane[i] > pcie_width_cap)
2411 pcie_table->pcie_lane[i] = pcie_width_cap;
2412 }
2413 }
2414
2415 for (i = 0; i < num_of_levels; i++) {
2416 smu_pcie_arg = i << 16;
2417 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2418 smu_pcie_arg |= pcie_table->pcie_lane[i];
2419
2420 ret = smu_cmn_send_smc_msg_with_param(smu,
2421 SMU_MSG_OverridePcieParameters,
2422 smu_pcie_arg,
2423 NULL);
2424 if (ret)
2425 return ret;
2426 }
2427
2428 return 0;
2429 }
2430
smu_v13_0_disable_pmfw_state(struct smu_context * smu)2431 int smu_v13_0_disable_pmfw_state(struct smu_context *smu)
2432 {
2433 int ret;
2434 struct amdgpu_device *adev = smu->adev;
2435
2436 WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0);
2437
2438 ret = RREG32_PCIE(MP1_Public |
2439 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
2440
2441 return ret == 0 ? 0 : -EINVAL;
2442 }
2443
smu_v13_0_enable_uclk_shadow(struct smu_context * smu,bool enable)2444 int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)
2445 {
2446 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);
2447 }
2448
smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context * smu,struct freq_band_range * exclusion_ranges)2449 int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
2450 struct freq_band_range *exclusion_ranges)
2451 {
2452 WifiBandEntryTable_t wifi_bands;
2453 int valid_entries = 0;
2454 int ret, i;
2455
2456 memset(&wifi_bands, 0, sizeof(wifi_bands));
2457 for (i = 0; i < ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {
2458 if (!exclusion_ranges[i].start && !exclusion_ranges[i].end)
2459 break;
2460
2461 /* PMFW expects the inputs to be in Mhz unit */
2462 wifi_bands.WifiBandEntry[valid_entries].LowFreq =
2463 DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);
2464 wifi_bands.WifiBandEntry[valid_entries++].HighFreq =
2465 DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);
2466 }
2467 wifi_bands.WifiBandEntryNum = valid_entries;
2468
2469 /*
2470 * Per confirm with PMFW team, WifiBandEntryNum = 0
2471 * is a valid setting.
2472 *
2473 * Considering the scenarios below:
2474 * - At first the wifi device adds an exclusion range e.g. (2400,2500) to
2475 * BIOS and our driver gets notified. We will set WifiBandEntryNum = 1
2476 * and pass the WifiBandEntry (2400, 2500) to PMFW.
2477 *
2478 * - Later the wifi device removes the wifiband list added above and
2479 * our driver gets notified again. At this time, driver will set
2480 * WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.
2481 *
2482 * - PMFW may still need to do some uclk shadow update(e.g. switching
2483 * from shadow clock back to primary clock) on receiving this.
2484 */
2485 ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &wifi_bands, true);
2486 if (ret)
2487 dev_warn(smu->adev->dev, "Failed to set wifiband!");
2488
2489 return ret;
2490 }
2491
smu_v13_0_reset_custom_level(struct smu_context * smu)2492 void smu_v13_0_reset_custom_level(struct smu_context *smu)
2493 {
2494 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2495
2496 pstate_table->uclk_pstate.custom.min = 0;
2497 pstate_table->uclk_pstate.custom.max = 0;
2498 pstate_table->gfxclk_pstate.custom.min = 0;
2499 pstate_table->gfxclk_pstate.custom.max = 0;
2500 }
2501