1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "smu_v15_0_0_ppt.h" 50 #include "amd_pcie.h" 51 52 /* 53 * DO NOT use these for err/warn/info/debug messages. 54 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 55 * They are more MGPU friendly. 56 */ 57 #undef pr_err 58 #undef pr_warn 59 #undef pr_info 60 #undef pr_debug 61 62 static const struct amd_pm_funcs swsmu_pm_funcs; 63 static int smu_force_smuclk_levels(struct smu_context *smu, 64 enum smu_clk_type clk_type, 65 uint32_t mask); 66 static int smu_handle_task(struct smu_context *smu, 67 enum amd_dpm_forced_level level, 68 enum amd_pp_task task_id); 69 static int smu_reset(struct smu_context *smu); 70 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 71 static int smu_set_fan_control_mode(void *handle, u32 value); 72 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); 73 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 74 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 75 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 76 static void smu_power_profile_mode_get(struct smu_context *smu, 77 enum PP_SMC_POWER_PROFILE profile_mode); 78 static void smu_power_profile_mode_put(struct smu_context *smu, 79 enum PP_SMC_POWER_PROFILE profile_mode); 80 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 81 static int smu_od_edit_dpm_table(void *handle, 82 enum PP_OD_DPM_TABLE_COMMAND type, 83 long *input, uint32_t size); 84 85 static int smu_sys_get_pp_feature_mask(void *handle, 86 char *buf) 87 { 88 struct smu_context *smu = handle; 89 90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 91 return -EOPNOTSUPP; 92 93 return smu_get_pp_feature_mask(smu, buf); 94 } 95 96 static int smu_sys_set_pp_feature_mask(void *handle, 97 uint64_t new_mask) 98 { 99 struct smu_context *smu = handle; 100 101 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 102 return -EOPNOTSUPP; 103 104 return smu_set_pp_feature_mask(smu, new_mask); 105 } 106 107 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 108 { 109 if (!smu->ppt_funcs->set_gfx_off_residency) 110 return -EINVAL; 111 112 return smu_set_gfx_off_residency(smu, value); 113 } 114 115 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 116 { 117 if (!smu->ppt_funcs->get_gfx_off_residency) 118 return -EINVAL; 119 120 return smu_get_gfx_off_residency(smu, value); 121 } 122 123 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 124 { 125 if (!smu->ppt_funcs->get_gfx_off_entrycount) 126 return -EINVAL; 127 128 return smu_get_gfx_off_entrycount(smu, value); 129 } 130 131 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 132 { 133 if (!smu->ppt_funcs->get_gfx_off_status) 134 return -EINVAL; 135 136 *value = smu_get_gfx_off_status(smu); 137 138 return 0; 139 } 140 141 int smu_set_soft_freq_range(struct smu_context *smu, 142 enum pp_clock_type type, 143 uint32_t min, 144 uint32_t max) 145 { 146 enum smu_clk_type clk_type; 147 int ret = 0; 148 149 clk_type = smu_convert_to_smuclk(type); 150 if (clk_type == SMU_CLK_COUNT) 151 return -EINVAL; 152 153 if (smu->ppt_funcs->set_soft_freq_limited_range) 154 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 155 clk_type, 156 min, 157 max, 158 false); 159 160 return ret; 161 } 162 163 int smu_get_dpm_freq_range(struct smu_context *smu, 164 enum smu_clk_type clk_type, 165 uint32_t *min, 166 uint32_t *max) 167 { 168 int ret = -ENOTSUPP; 169 170 if (!min && !max) 171 return -EINVAL; 172 173 if (smu->ppt_funcs->get_dpm_ultimate_freq) 174 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 175 clk_type, 176 min, 177 max); 178 179 return ret; 180 } 181 182 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 183 { 184 int ret = 0; 185 struct amdgpu_device *adev = smu->adev; 186 187 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 188 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 189 if (ret) 190 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 191 } 192 return ret; 193 } 194 195 static u32 smu_get_mclk(void *handle, bool low) 196 { 197 struct smu_context *smu = handle; 198 uint32_t clk_freq; 199 int ret = 0; 200 201 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 202 low ? &clk_freq : NULL, 203 !low ? &clk_freq : NULL); 204 if (ret) 205 return 0; 206 return clk_freq * 100; 207 } 208 209 static u32 smu_get_sclk(void *handle, bool low) 210 { 211 struct smu_context *smu = handle; 212 uint32_t clk_freq; 213 int ret = 0; 214 215 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 216 low ? &clk_freq : NULL, 217 !low ? &clk_freq : NULL); 218 if (ret) 219 return 0; 220 return clk_freq * 100; 221 } 222 223 static int smu_set_gfx_imu_enable(struct smu_context *smu) 224 { 225 struct amdgpu_device *adev = smu->adev; 226 227 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 228 return 0; 229 230 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 231 return 0; 232 233 return smu_set_gfx_power_up_by_imu(smu); 234 } 235 236 static bool is_vcn_enabled(struct amdgpu_device *adev) 237 { 238 int i; 239 240 for (i = 0; i < adev->num_ip_blocks; i++) { 241 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 242 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 243 !adev->ip_blocks[i].status.valid) 244 return false; 245 } 246 247 return true; 248 } 249 250 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 251 bool enable, 252 int inst) 253 { 254 struct smu_power_context *smu_power = &smu->smu_power; 255 struct smu_power_gate *power_gate = &smu_power->power_gate; 256 int ret = 0; 257 258 /* 259 * don't poweron vcn/jpeg when they are skipped. 260 */ 261 if (!is_vcn_enabled(smu->adev)) 262 return 0; 263 264 if (!smu->ppt_funcs->dpm_set_vcn_enable) 265 return 0; 266 267 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 268 return 0; 269 270 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 271 if (!ret) 272 atomic_set(&power_gate->vcn_gated[inst], !enable); 273 274 return ret; 275 } 276 277 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 278 bool enable) 279 { 280 struct smu_power_context *smu_power = &smu->smu_power; 281 struct smu_power_gate *power_gate = &smu_power->power_gate; 282 int ret = 0; 283 284 if (!is_vcn_enabled(smu->adev)) 285 return 0; 286 287 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 288 return 0; 289 290 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 291 return 0; 292 293 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 294 if (!ret) 295 atomic_set(&power_gate->jpeg_gated, !enable); 296 297 return ret; 298 } 299 300 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 301 bool enable) 302 { 303 struct smu_power_context *smu_power = &smu->smu_power; 304 struct smu_power_gate *power_gate = &smu_power->power_gate; 305 int ret = 0; 306 307 if (!smu->ppt_funcs->dpm_set_vpe_enable) 308 return 0; 309 310 if (atomic_read(&power_gate->vpe_gated) ^ enable) 311 return 0; 312 313 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 314 if (!ret) 315 atomic_set(&power_gate->vpe_gated, !enable); 316 317 return ret; 318 } 319 320 static int smu_dpm_set_isp_enable(struct smu_context *smu, 321 bool enable) 322 { 323 struct smu_power_context *smu_power = &smu->smu_power; 324 struct smu_power_gate *power_gate = &smu_power->power_gate; 325 int ret; 326 327 if (!smu->ppt_funcs->dpm_set_isp_enable) 328 return 0; 329 330 if (atomic_read(&power_gate->isp_gated) ^ enable) 331 return 0; 332 333 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 334 if (!ret) 335 atomic_set(&power_gate->isp_gated, !enable); 336 337 return ret; 338 } 339 340 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 341 bool enable) 342 { 343 struct smu_power_context *smu_power = &smu->smu_power; 344 struct smu_power_gate *power_gate = &smu_power->power_gate; 345 int ret = 0; 346 347 if (!smu->adev->enable_umsch_mm) 348 return 0; 349 350 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 351 return 0; 352 353 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 354 return 0; 355 356 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 357 if (!ret) 358 atomic_set(&power_gate->umsch_mm_gated, !enable); 359 360 return ret; 361 } 362 363 static int smu_set_mall_enable(struct smu_context *smu) 364 { 365 int ret = 0; 366 367 if (!smu->ppt_funcs->set_mall_enable) 368 return 0; 369 370 ret = smu->ppt_funcs->set_mall_enable(smu); 371 372 return ret; 373 } 374 375 /** 376 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 377 * 378 * @handle: smu_context pointer 379 * @block_type: the IP block to power gate/ungate 380 * @gate: to power gate if true, ungate otherwise 381 * @inst: the instance of the IP block to power gate/ungate 382 * 383 * This API uses no smu->mutex lock protection due to: 384 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 385 * This is guarded to be race condition free by the caller. 386 * 2. Or get called on user setting request of power_dpm_force_performance_level. 387 * Under this case, the smu->mutex lock protection is already enforced on 388 * the parent API smu_force_performance_level of the call path. 389 */ 390 static int smu_dpm_set_power_gate(void *handle, 391 uint32_t block_type, 392 bool gate, 393 int inst) 394 { 395 struct smu_context *smu = handle; 396 int ret = 0; 397 398 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 399 dev_WARN(smu->adev->dev, 400 "SMU uninitialized but power %s requested for %u!\n", 401 gate ? "gate" : "ungate", block_type); 402 return -EOPNOTSUPP; 403 } 404 405 switch (block_type) { 406 /* 407 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 408 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 409 */ 410 case AMD_IP_BLOCK_TYPE_UVD: 411 case AMD_IP_BLOCK_TYPE_VCN: 412 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 413 if (ret) 414 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 415 gate ? "gate" : "ungate", inst); 416 break; 417 case AMD_IP_BLOCK_TYPE_GFX: 418 ret = smu_gfx_off_control(smu, gate); 419 if (ret) 420 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 421 gate ? "enable" : "disable"); 422 break; 423 case AMD_IP_BLOCK_TYPE_SDMA: 424 ret = smu_powergate_sdma(smu, gate); 425 if (ret) 426 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 427 gate ? "gate" : "ungate"); 428 break; 429 case AMD_IP_BLOCK_TYPE_JPEG: 430 ret = smu_dpm_set_jpeg_enable(smu, !gate); 431 if (ret) 432 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 433 gate ? "gate" : "ungate"); 434 break; 435 case AMD_IP_BLOCK_TYPE_VPE: 436 ret = smu_dpm_set_vpe_enable(smu, !gate); 437 if (ret) 438 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 439 gate ? "gate" : "ungate"); 440 break; 441 case AMD_IP_BLOCK_TYPE_ISP: 442 ret = smu_dpm_set_isp_enable(smu, !gate); 443 if (ret) 444 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 445 gate ? "gate" : "ungate"); 446 break; 447 default: 448 dev_err(smu->adev->dev, "Unsupported block type!\n"); 449 return -EINVAL; 450 } 451 452 return ret; 453 } 454 455 /** 456 * smu_set_user_clk_dependencies - set user profile clock dependencies 457 * 458 * @smu: smu_context pointer 459 * @clk: enum smu_clk_type type 460 * 461 * Enable/Disable the clock dependency for the @clk type. 462 */ 463 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 464 { 465 if (smu->adev->in_suspend) 466 return; 467 468 if (clk == SMU_MCLK) { 469 smu->user_dpm_profile.clk_dependency = 0; 470 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 471 } else if (clk == SMU_FCLK) { 472 /* MCLK takes precedence over FCLK */ 473 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 474 return; 475 476 smu->user_dpm_profile.clk_dependency = 0; 477 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 478 } else if (clk == SMU_SOCCLK) { 479 /* MCLK takes precedence over SOCCLK */ 480 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 481 return; 482 483 smu->user_dpm_profile.clk_dependency = 0; 484 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 485 } else 486 /* Add clk dependencies here, if any */ 487 return; 488 } 489 490 /** 491 * smu_restore_dpm_user_profile - reinstate user dpm profile 492 * 493 * @smu: smu_context pointer 494 * 495 * Restore the saved user power configurations include power limit, 496 * clock frequencies, fan control mode and fan speed. 497 */ 498 static void smu_restore_dpm_user_profile(struct smu_context *smu) 499 { 500 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 501 int ret = 0; 502 503 if (!smu->adev->in_suspend) 504 return; 505 506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 507 return; 508 509 /* Enable restore flag */ 510 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 511 512 /* set the user dpm power limits */ 513 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { 514 if (!smu->user_dpm_profile.power_limits[i]) 515 continue; 516 ret = smu_set_power_limit(smu, i, 517 smu->user_dpm_profile.power_limits[i]); 518 if (ret) 519 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); 520 } 521 522 /* set the user dpm clock configurations */ 523 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 524 enum smu_clk_type clk_type; 525 526 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 527 /* 528 * Iterate over smu clk type and force the saved user clk 529 * configs, skip if clock dependency is enabled 530 */ 531 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 532 smu->user_dpm_profile.clk_mask[clk_type]) { 533 ret = smu_force_smuclk_levels(smu, clk_type, 534 smu->user_dpm_profile.clk_mask[clk_type]); 535 if (ret) 536 dev_err(smu->adev->dev, 537 "Failed to set clock type = %d\n", clk_type); 538 } 539 } 540 } 541 542 /* set the user dpm fan configurations */ 543 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 544 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 545 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 546 if (ret != -EOPNOTSUPP) { 547 smu->user_dpm_profile.fan_speed_pwm = 0; 548 smu->user_dpm_profile.fan_speed_rpm = 0; 549 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 550 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 551 } 552 553 if (smu->user_dpm_profile.fan_speed_pwm) { 554 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 555 if (ret != -EOPNOTSUPP) 556 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 557 } 558 559 if (smu->user_dpm_profile.fan_speed_rpm) { 560 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 561 if (ret != -EOPNOTSUPP) 562 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 563 } 564 } 565 566 /* Restore user customized OD settings */ 567 if (smu->user_dpm_profile.user_od) { 568 if (smu->ppt_funcs->restore_user_od_settings) { 569 ret = smu->ppt_funcs->restore_user_od_settings(smu); 570 if (ret) 571 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 572 } 573 } 574 575 /* Disable restore flag */ 576 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 577 } 578 579 static int smu_get_power_num_states(void *handle, 580 struct pp_states_info *state_info) 581 { 582 if (!state_info) 583 return -EINVAL; 584 585 /* not support power state */ 586 memset(state_info, 0, sizeof(struct pp_states_info)); 587 state_info->nums = 1; 588 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 589 590 return 0; 591 } 592 593 bool is_support_sw_smu(struct amdgpu_device *adev) 594 { 595 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 596 if (adev->asic_type == CHIP_VEGA20) 597 return false; 598 599 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 600 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 601 return true; 602 603 return false; 604 } 605 606 bool is_support_cclk_dpm(struct amdgpu_device *adev) 607 { 608 struct smu_context *smu = adev->powerplay.pp_handle; 609 610 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 611 return false; 612 613 return true; 614 } 615 616 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 617 uint32_t param, uint32_t *read_arg) 618 { 619 struct smu_context *smu = adev->powerplay.pp_handle; 620 int ret = -EOPNOTSUPP; 621 622 if (!smu) 623 return ret; 624 625 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 626 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 627 628 return ret; 629 } 630 631 static int smu_sys_get_pp_table(void *handle, 632 char **table) 633 { 634 struct smu_context *smu = handle; 635 struct smu_table_context *smu_table = &smu->smu_table; 636 637 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 638 return -EOPNOTSUPP; 639 640 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 641 return -EOPNOTSUPP; 642 643 if (smu_table->hardcode_pptable) 644 *table = smu_table->hardcode_pptable; 645 else 646 *table = smu_table->power_play_table; 647 648 return smu_table->power_play_table_size; 649 } 650 651 static int smu_sys_set_pp_table(void *handle, 652 const char *buf, 653 size_t size) 654 { 655 struct smu_context *smu = handle; 656 struct smu_table_context *smu_table = &smu->smu_table; 657 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 658 int ret = 0; 659 660 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 661 return -EOPNOTSUPP; 662 663 if (header->usStructureSize != size) { 664 dev_err(smu->adev->dev, "pp table size not matched !\n"); 665 return -EIO; 666 } 667 668 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 669 kfree(smu_table->hardcode_pptable); 670 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 671 if (!smu_table->hardcode_pptable) 672 return -ENOMEM; 673 } 674 675 memcpy(smu_table->hardcode_pptable, buf, size); 676 smu_table->power_play_table = smu_table->hardcode_pptable; 677 smu_table->power_play_table_size = size; 678 679 /* 680 * Special hw_fini action(for Navi1x, the DPMs disablement will be 681 * skipped) may be needed for custom pptable uploading. 682 */ 683 smu->uploading_custom_pp_table = true; 684 685 ret = smu_reset(smu); 686 if (ret) 687 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 688 689 smu->uploading_custom_pp_table = false; 690 691 return ret; 692 } 693 694 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 695 { 696 /* 697 * With SCPM enabled, the allowed featuremasks setting(via 698 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 699 * That means there is no way to let PMFW knows the settings below. 700 * Thus, we just assume all the features are allowed under 701 * such scenario. 702 */ 703 if (smu->adev->scpm_enabled) { 704 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 705 return 0; 706 } 707 708 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 709 710 return smu_init_allowed_features(smu); 711 } 712 713 static int smu_set_funcs(struct amdgpu_device *adev) 714 { 715 struct smu_context *smu = adev->powerplay.pp_handle; 716 717 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 718 smu->od_enabled = true; 719 720 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 721 case IP_VERSION(11, 0, 0): 722 case IP_VERSION(11, 0, 5): 723 case IP_VERSION(11, 0, 9): 724 navi10_set_ppt_funcs(smu); 725 break; 726 case IP_VERSION(11, 0, 7): 727 case IP_VERSION(11, 0, 11): 728 case IP_VERSION(11, 0, 12): 729 case IP_VERSION(11, 0, 13): 730 sienna_cichlid_set_ppt_funcs(smu); 731 break; 732 case IP_VERSION(12, 0, 0): 733 case IP_VERSION(12, 0, 1): 734 renoir_set_ppt_funcs(smu); 735 break; 736 case IP_VERSION(11, 5, 0): 737 case IP_VERSION(11, 5, 2): 738 vangogh_set_ppt_funcs(smu); 739 break; 740 case IP_VERSION(13, 0, 1): 741 case IP_VERSION(13, 0, 3): 742 case IP_VERSION(13, 0, 8): 743 yellow_carp_set_ppt_funcs(smu); 744 break; 745 case IP_VERSION(13, 0, 4): 746 case IP_VERSION(13, 0, 11): 747 smu_v13_0_4_set_ppt_funcs(smu); 748 break; 749 case IP_VERSION(13, 0, 5): 750 smu_v13_0_5_set_ppt_funcs(smu); 751 break; 752 case IP_VERSION(11, 0, 8): 753 cyan_skillfish_set_ppt_funcs(smu); 754 break; 755 case IP_VERSION(11, 0, 2): 756 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 757 arcturus_set_ppt_funcs(smu); 758 /* OD is not supported on Arcturus */ 759 smu->od_enabled = false; 760 break; 761 case IP_VERSION(13, 0, 2): 762 aldebaran_set_ppt_funcs(smu); 763 /* Enable pp_od_clk_voltage node */ 764 smu->od_enabled = true; 765 break; 766 case IP_VERSION(13, 0, 0): 767 case IP_VERSION(13, 0, 10): 768 smu_v13_0_0_set_ppt_funcs(smu); 769 break; 770 case IP_VERSION(13, 0, 6): 771 case IP_VERSION(13, 0, 14): 772 case IP_VERSION(13, 0, 12): 773 smu_v13_0_6_set_ppt_funcs(smu); 774 /* Enable pp_od_clk_voltage node */ 775 smu->od_enabled = true; 776 break; 777 case IP_VERSION(13, 0, 7): 778 smu_v13_0_7_set_ppt_funcs(smu); 779 break; 780 case IP_VERSION(14, 0, 0): 781 case IP_VERSION(14, 0, 1): 782 case IP_VERSION(14, 0, 4): 783 case IP_VERSION(14, 0, 5): 784 smu_v14_0_0_set_ppt_funcs(smu); 785 break; 786 case IP_VERSION(14, 0, 2): 787 case IP_VERSION(14, 0, 3): 788 smu_v14_0_2_set_ppt_funcs(smu); 789 break; 790 case IP_VERSION(15, 0, 0): 791 smu_v15_0_0_set_ppt_funcs(smu); 792 break; 793 default: 794 return -EINVAL; 795 } 796 797 return 0; 798 } 799 800 static int smu_early_init(struct amdgpu_ip_block *ip_block) 801 { 802 struct amdgpu_device *adev = ip_block->adev; 803 struct smu_context *smu; 804 int r; 805 806 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 807 if (!smu) 808 return -ENOMEM; 809 810 smu->adev = adev; 811 smu->pm_enabled = !!amdgpu_dpm; 812 smu->is_apu = false; 813 smu->smu_baco.state = SMU_BACO_STATE_NONE; 814 smu->smu_baco.platform_support = false; 815 smu->smu_baco.maco_support = false; 816 smu->user_dpm_profile.fan_mode = -1; 817 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 818 819 adev->powerplay.pp_handle = smu; 820 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 821 822 r = smu_set_funcs(adev); 823 if (r) 824 return r; 825 return smu_init_microcode(smu); 826 } 827 828 static int smu_set_default_dpm_table(struct smu_context *smu) 829 { 830 struct amdgpu_device *adev = smu->adev; 831 struct smu_power_context *smu_power = &smu->smu_power; 832 struct smu_power_gate *power_gate = &smu_power->power_gate; 833 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 834 int ret = 0; 835 836 if (!smu->ppt_funcs->set_default_dpm_table) 837 return 0; 838 839 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 840 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 841 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 842 } 843 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 844 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 845 846 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 847 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 848 ret = smu_dpm_set_vcn_enable(smu, true, i); 849 if (ret) 850 return ret; 851 } 852 } 853 854 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 855 ret = smu_dpm_set_jpeg_enable(smu, true); 856 if (ret) 857 goto err_out; 858 } 859 860 ret = smu->ppt_funcs->set_default_dpm_table(smu); 861 if (ret) 862 dev_err(smu->adev->dev, 863 "Failed to setup default dpm clock tables!\n"); 864 865 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 866 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 867 err_out: 868 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 869 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 870 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 871 } 872 873 return ret; 874 } 875 876 static int smu_apply_default_config_table_settings(struct smu_context *smu) 877 { 878 struct amdgpu_device *adev = smu->adev; 879 int ret = 0; 880 881 ret = smu_get_default_config_table_settings(smu, 882 &adev->pm.config_table); 883 if (ret) 884 return ret; 885 886 return smu_set_config_table(smu, &adev->pm.config_table); 887 } 888 889 static int smu_late_init(struct amdgpu_ip_block *ip_block) 890 { 891 struct amdgpu_device *adev = ip_block->adev; 892 struct smu_context *smu = adev->powerplay.pp_handle; 893 int ret = 0; 894 895 smu_set_fine_grain_gfx_freq_parameters(smu); 896 897 if (!smu->pm_enabled) 898 return 0; 899 900 ret = smu_post_init(smu); 901 if (ret) { 902 dev_err(adev->dev, "Failed to post smu init!\n"); 903 return ret; 904 } 905 906 /* 907 * Explicitly notify PMFW the power mode the system in. Since 908 * the PMFW may boot the ASIC with a different mode. 909 * For those supporting ACDC switch via gpio, PMFW will 910 * handle the switch automatically. Driver involvement 911 * is unnecessary. 912 */ 913 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 914 smu_set_ac_dc(smu); 915 916 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 917 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 918 return 0; 919 920 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 921 ret = smu_set_default_od_settings(smu); 922 if (ret) { 923 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 924 return ret; 925 } 926 } 927 928 ret = smu_populate_umd_state_clk(smu); 929 if (ret) { 930 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 931 return ret; 932 } 933 934 ret = smu_get_asic_power_limits(smu, 935 &smu->current_power_limit, 936 &smu->default_power_limit, 937 &smu->max_power_limit, 938 &smu->min_power_limit); 939 if (ret) { 940 dev_err(adev->dev, "Failed to get asic power limits!\n"); 941 return ret; 942 } 943 944 if (!amdgpu_sriov_vf(adev)) 945 smu_get_unique_id(smu); 946 947 smu_get_fan_parameters(smu); 948 949 smu_handle_task(smu, 950 smu->smu_dpm.dpm_level, 951 AMD_PP_TASK_COMPLETE_INIT); 952 953 ret = smu_apply_default_config_table_settings(smu); 954 if (ret && (ret != -EOPNOTSUPP)) { 955 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 956 return ret; 957 } 958 959 smu_restore_dpm_user_profile(smu); 960 961 return 0; 962 } 963 964 static int smu_init_fb_allocations(struct smu_context *smu) 965 { 966 struct amdgpu_device *adev = smu->adev; 967 struct smu_table_context *smu_table = &smu->smu_table; 968 struct smu_table *tables = smu_table->tables; 969 struct smu_table *driver_table = &(smu_table->driver_table); 970 uint32_t max_table_size = 0; 971 int ret, i; 972 973 /* VRAM allocation for tool table */ 974 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 975 ret = amdgpu_bo_create_kernel(adev, 976 tables[SMU_TABLE_PMSTATUSLOG].size, 977 tables[SMU_TABLE_PMSTATUSLOG].align, 978 tables[SMU_TABLE_PMSTATUSLOG].domain, 979 &tables[SMU_TABLE_PMSTATUSLOG].bo, 980 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 981 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 982 if (ret) { 983 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 984 return ret; 985 } 986 } 987 988 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 989 /* VRAM allocation for driver table */ 990 for (i = 0; i < SMU_TABLE_COUNT; i++) { 991 if (tables[i].size == 0) 992 continue; 993 994 /* If one of the tables has VRAM domain restriction, keep it in 995 * VRAM 996 */ 997 if ((tables[i].domain & 998 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 999 AMDGPU_GEM_DOMAIN_VRAM) 1000 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1001 1002 if (i == SMU_TABLE_PMSTATUSLOG) 1003 continue; 1004 1005 if (max_table_size < tables[i].size) 1006 max_table_size = tables[i].size; 1007 } 1008 1009 driver_table->size = max_table_size; 1010 driver_table->align = PAGE_SIZE; 1011 1012 ret = amdgpu_bo_create_kernel(adev, 1013 driver_table->size, 1014 driver_table->align, 1015 driver_table->domain, 1016 &driver_table->bo, 1017 &driver_table->mc_address, 1018 &driver_table->cpu_addr); 1019 if (ret) { 1020 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1021 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1022 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1023 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1024 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1025 } 1026 1027 return ret; 1028 } 1029 1030 static int smu_fini_fb_allocations(struct smu_context *smu) 1031 { 1032 struct smu_table_context *smu_table = &smu->smu_table; 1033 struct smu_table *tables = smu_table->tables; 1034 struct smu_table *driver_table = &(smu_table->driver_table); 1035 1036 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1037 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1038 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1039 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1040 1041 amdgpu_bo_free_kernel(&driver_table->bo, 1042 &driver_table->mc_address, 1043 &driver_table->cpu_addr); 1044 1045 return 0; 1046 } 1047 1048 static void smu_update_gpu_addresses(struct smu_context *smu) 1049 { 1050 struct smu_table_context *smu_table = &smu->smu_table; 1051 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1052 struct smu_table *driver_table = &(smu_table->driver_table); 1053 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1054 1055 if (pm_status_table->bo) 1056 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1057 if (driver_table->bo) 1058 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1059 if (dummy_read_1_table->bo) 1060 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1061 } 1062 1063 /** 1064 * smu_alloc_memory_pool - allocate memory pool in the system memory 1065 * 1066 * @smu: amdgpu_device pointer 1067 * 1068 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1069 * and DramLogSetDramAddr can notify it changed. 1070 * 1071 * Returns 0 on success, error on failure. 1072 */ 1073 static int smu_alloc_memory_pool(struct smu_context *smu) 1074 { 1075 struct amdgpu_device *adev = smu->adev; 1076 struct smu_table_context *smu_table = &smu->smu_table; 1077 struct smu_table *memory_pool = &smu_table->memory_pool; 1078 uint64_t pool_size = smu->pool_size; 1079 int ret = 0; 1080 1081 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1082 return ret; 1083 1084 memory_pool->size = pool_size; 1085 memory_pool->align = PAGE_SIZE; 1086 memory_pool->domain = 1087 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1088 AMDGPU_GEM_DOMAIN_VRAM : 1089 AMDGPU_GEM_DOMAIN_GTT; 1090 1091 switch (pool_size) { 1092 case SMU_MEMORY_POOL_SIZE_256_MB: 1093 case SMU_MEMORY_POOL_SIZE_512_MB: 1094 case SMU_MEMORY_POOL_SIZE_1_GB: 1095 case SMU_MEMORY_POOL_SIZE_2_GB: 1096 ret = amdgpu_bo_create_kernel(adev, 1097 memory_pool->size, 1098 memory_pool->align, 1099 memory_pool->domain, 1100 &memory_pool->bo, 1101 &memory_pool->mc_address, 1102 &memory_pool->cpu_addr); 1103 if (ret) 1104 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1105 break; 1106 default: 1107 break; 1108 } 1109 1110 return ret; 1111 } 1112 1113 static int smu_free_memory_pool(struct smu_context *smu) 1114 { 1115 struct smu_table_context *smu_table = &smu->smu_table; 1116 struct smu_table *memory_pool = &smu_table->memory_pool; 1117 1118 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1119 return 0; 1120 1121 amdgpu_bo_free_kernel(&memory_pool->bo, 1122 &memory_pool->mc_address, 1123 &memory_pool->cpu_addr); 1124 1125 memset(memory_pool, 0, sizeof(struct smu_table)); 1126 1127 return 0; 1128 } 1129 1130 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1131 { 1132 struct smu_table_context *smu_table = &smu->smu_table; 1133 struct smu_table *dummy_read_1_table = 1134 &smu_table->dummy_read_1_table; 1135 struct amdgpu_device *adev = smu->adev; 1136 int ret = 0; 1137 1138 if (!dummy_read_1_table->size) 1139 return 0; 1140 1141 ret = amdgpu_bo_create_kernel(adev, 1142 dummy_read_1_table->size, 1143 dummy_read_1_table->align, 1144 dummy_read_1_table->domain, 1145 &dummy_read_1_table->bo, 1146 &dummy_read_1_table->mc_address, 1147 &dummy_read_1_table->cpu_addr); 1148 if (ret) 1149 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1150 1151 return ret; 1152 } 1153 1154 static void smu_free_dummy_read_table(struct smu_context *smu) 1155 { 1156 struct smu_table_context *smu_table = &smu->smu_table; 1157 struct smu_table *dummy_read_1_table = 1158 &smu_table->dummy_read_1_table; 1159 1160 1161 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1162 &dummy_read_1_table->mc_address, 1163 &dummy_read_1_table->cpu_addr); 1164 1165 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1166 } 1167 1168 static int smu_smc_table_sw_init(struct smu_context *smu) 1169 { 1170 int ret; 1171 1172 /** 1173 * Create smu_table structure, and init smc tables such as 1174 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1175 */ 1176 ret = smu_init_smc_tables(smu); 1177 if (ret) { 1178 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1179 return ret; 1180 } 1181 1182 /** 1183 * Create smu_power_context structure, and allocate smu_dpm_context and 1184 * context size to fill the smu_power_context data. 1185 */ 1186 ret = smu_init_power(smu); 1187 if (ret) { 1188 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1189 return ret; 1190 } 1191 1192 /* 1193 * allocate vram bos to store smc table contents. 1194 */ 1195 ret = smu_init_fb_allocations(smu); 1196 if (ret) 1197 return ret; 1198 1199 ret = smu_alloc_memory_pool(smu); 1200 if (ret) 1201 return ret; 1202 1203 ret = smu_alloc_dummy_read_table(smu); 1204 if (ret) 1205 return ret; 1206 1207 ret = smu_i2c_init(smu); 1208 if (ret) 1209 return ret; 1210 1211 return 0; 1212 } 1213 1214 static int smu_smc_table_sw_fini(struct smu_context *smu) 1215 { 1216 int ret; 1217 1218 smu_i2c_fini(smu); 1219 1220 smu_free_dummy_read_table(smu); 1221 1222 ret = smu_free_memory_pool(smu); 1223 if (ret) 1224 return ret; 1225 1226 ret = smu_fini_fb_allocations(smu); 1227 if (ret) 1228 return ret; 1229 1230 ret = smu_fini_power(smu); 1231 if (ret) { 1232 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1233 return ret; 1234 } 1235 1236 ret = smu_fini_smc_tables(smu); 1237 if (ret) { 1238 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1239 return ret; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static void smu_throttling_logging_work_fn(struct work_struct *work) 1246 { 1247 struct smu_context *smu = container_of(work, struct smu_context, 1248 throttling_logging_work); 1249 1250 smu_log_thermal_throttling(smu); 1251 } 1252 1253 static void smu_interrupt_work_fn(struct work_struct *work) 1254 { 1255 struct smu_context *smu = container_of(work, struct smu_context, 1256 interrupt_work); 1257 1258 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1259 smu->ppt_funcs->interrupt_work(smu); 1260 } 1261 1262 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1263 { 1264 struct smu_context *smu = 1265 container_of(work, struct smu_context, swctf_delayed_work.work); 1266 struct smu_temperature_range *range = 1267 &smu->thermal_range; 1268 struct amdgpu_device *adev = smu->adev; 1269 uint32_t hotspot_tmp, size; 1270 1271 /* 1272 * If the hotspot temperature is confirmed as below SW CTF setting point 1273 * after the delay enforced, nothing will be done. 1274 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1275 */ 1276 if (range->software_shutdown_temp && 1277 smu->ppt_funcs->read_sensor && 1278 !smu->ppt_funcs->read_sensor(smu, 1279 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1280 &hotspot_tmp, 1281 &size) && 1282 hotspot_tmp / 1000 < range->software_shutdown_temp) 1283 return; 1284 1285 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1286 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1287 orderly_poweroff(true); 1288 } 1289 1290 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1291 { 1292 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1293 struct smu_dpm_policy_ctxt *policy_ctxt; 1294 struct smu_dpm_policy *policy; 1295 1296 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1297 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1298 if (policy) 1299 policy->current_level = XGMI_PLPD_DEFAULT; 1300 return; 1301 } 1302 1303 /* PMFW put PLPD into default policy after enabling the feature */ 1304 if (smu_feature_is_enabled(smu, 1305 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1306 if (policy) 1307 policy->current_level = XGMI_PLPD_DEFAULT; 1308 } else { 1309 policy_ctxt = dpm_ctxt->dpm_policies; 1310 if (policy_ctxt) 1311 policy_ctxt->policy_mask &= 1312 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1313 } 1314 } 1315 1316 static void smu_init_power_profile(struct smu_context *smu) 1317 { 1318 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1319 smu->power_profile_mode = 1320 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1321 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1322 } 1323 1324 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1325 { 1326 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1327 1328 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1329 return; 1330 1331 set_bit(fea_id, fea_cap->cap_map); 1332 } 1333 1334 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1335 { 1336 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1337 1338 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1339 return false; 1340 1341 return test_bit(fea_id, fea_cap->cap_map); 1342 } 1343 1344 static void smu_feature_cap_init(struct smu_context *smu) 1345 { 1346 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1347 1348 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1349 } 1350 1351 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1352 { 1353 struct amdgpu_device *adev = ip_block->adev; 1354 struct smu_context *smu = adev->powerplay.pp_handle; 1355 int i, ret; 1356 1357 smu->pool_size = adev->pm.smu_prv_buffer_size; 1358 smu_feature_init(smu, SMU_FEATURE_MAX); 1359 1360 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1361 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1362 atomic64_set(&smu->throttle_int_counter, 0); 1363 smu->watermarks_bitmap = 0; 1364 1365 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1366 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1367 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1368 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1369 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1370 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1371 1372 smu_init_power_profile(smu); 1373 smu->display_config = &adev->pm.pm_display_cfg; 1374 1375 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1376 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1377 1378 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1379 smu_swctf_delayed_work_handler); 1380 1381 smu_feature_cap_init(smu); 1382 1383 ret = smu_smc_table_sw_init(smu); 1384 if (ret) { 1385 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1386 return ret; 1387 } 1388 1389 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1390 ret = smu_get_vbios_bootup_values(smu); 1391 if (ret) { 1392 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1393 return ret; 1394 } 1395 1396 ret = smu_init_pptable_microcode(smu); 1397 if (ret) { 1398 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1399 return ret; 1400 } 1401 1402 ret = smu_register_irq_handler(smu); 1403 if (ret) { 1404 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1405 return ret; 1406 } 1407 1408 /* If there is no way to query fan control mode, fan control is not supported */ 1409 if (!smu->ppt_funcs->get_fan_control_mode) 1410 smu->adev->pm.no_fan = true; 1411 1412 return 0; 1413 } 1414 1415 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1416 { 1417 struct amdgpu_device *adev = ip_block->adev; 1418 struct smu_context *smu = adev->powerplay.pp_handle; 1419 int ret; 1420 1421 ret = smu_smc_table_sw_fini(smu); 1422 if (ret) { 1423 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1424 return ret; 1425 } 1426 1427 if (smu->custom_profile_params) { 1428 kfree(smu->custom_profile_params); 1429 smu->custom_profile_params = NULL; 1430 } 1431 1432 smu_fini_microcode(smu); 1433 1434 return 0; 1435 } 1436 1437 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1438 { 1439 struct amdgpu_device *adev = smu->adev; 1440 struct smu_temperature_range *range = 1441 &smu->thermal_range; 1442 int ret = 0; 1443 1444 if (!smu->ppt_funcs->get_thermal_temperature_range) 1445 return 0; 1446 1447 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1448 if (ret) 1449 return ret; 1450 1451 adev->pm.dpm.thermal.min_temp = range->min; 1452 adev->pm.dpm.thermal.max_temp = range->max; 1453 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1454 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1455 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1456 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1457 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1458 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1459 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1460 1461 return ret; 1462 } 1463 1464 /** 1465 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1466 * 1467 * @smu: smu_context pointer 1468 * 1469 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1470 * Returns 0 on success, error on failure. 1471 */ 1472 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1473 { 1474 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1475 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1476 struct amdgpu_device *adev = smu->adev; 1477 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1478 uint64_t start, end; 1479 int ret, i, j; 1480 1481 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1482 if (ret) { 1483 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1484 return ret; 1485 } 1486 1487 /* 1488 * The exclusion ranges array we got might be filled with holes and duplicate 1489 * entries. For example: 1490 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1491 * We need to do some sortups to eliminate those holes and duplicate entries. 1492 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1493 */ 1494 for (i = 0; i < num_of_wbrf_ranges; i++) { 1495 start = wifi_bands[i].start; 1496 end = wifi_bands[i].end; 1497 1498 /* get the last valid entry to fill the intermediate hole */ 1499 if (!start && !end) { 1500 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1501 if (wifi_bands[j].start && wifi_bands[j].end) 1502 break; 1503 1504 /* no valid entry left */ 1505 if (j <= i) 1506 break; 1507 1508 start = wifi_bands[i].start = wifi_bands[j].start; 1509 end = wifi_bands[i].end = wifi_bands[j].end; 1510 wifi_bands[j].start = 0; 1511 wifi_bands[j].end = 0; 1512 num_of_wbrf_ranges = j; 1513 } 1514 1515 /* eliminate duplicate entries */ 1516 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1517 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1518 wifi_bands[j].start = 0; 1519 wifi_bands[j].end = 0; 1520 } 1521 } 1522 } 1523 1524 /* Send the sorted wifi_bands to PMFW */ 1525 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1526 /* Try to set the wifi_bands again */ 1527 if (unlikely(ret == -EBUSY)) { 1528 mdelay(5); 1529 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1530 } 1531 1532 return ret; 1533 } 1534 1535 /** 1536 * smu_wbrf_event_handler - handle notify events 1537 * 1538 * @nb: notifier block 1539 * @action: event type 1540 * @_arg: event data 1541 * 1542 * Calls relevant amdgpu function in response to wbrf event 1543 * notification from kernel. 1544 */ 1545 static int smu_wbrf_event_handler(struct notifier_block *nb, 1546 unsigned long action, void *_arg) 1547 { 1548 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1549 1550 switch (action) { 1551 case WBRF_CHANGED: 1552 schedule_delayed_work(&smu->wbrf_delayed_work, 1553 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1554 break; 1555 default: 1556 return NOTIFY_DONE; 1557 } 1558 1559 return NOTIFY_OK; 1560 } 1561 1562 /** 1563 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1564 * 1565 * @work: struct work_struct pointer 1566 * 1567 * Flood is over and driver will consume the latest exclusion ranges. 1568 */ 1569 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1570 { 1571 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1572 1573 smu_wbrf_handle_exclusion_ranges(smu); 1574 } 1575 1576 /** 1577 * smu_wbrf_support_check - check wbrf support 1578 * 1579 * @smu: smu_context pointer 1580 * 1581 * Verifies the ACPI interface whether wbrf is supported. 1582 */ 1583 static void smu_wbrf_support_check(struct smu_context *smu) 1584 { 1585 struct amdgpu_device *adev = smu->adev; 1586 1587 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1588 acpi_amd_wbrf_supported_consumer(adev->dev); 1589 1590 if (smu->wbrf_supported) 1591 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1592 } 1593 1594 /** 1595 * smu_wbrf_init - init driver wbrf support 1596 * 1597 * @smu: smu_context pointer 1598 * 1599 * Verifies the AMD ACPI interfaces and registers with the wbrf 1600 * notifier chain if wbrf feature is supported. 1601 * Returns 0 on success, error on failure. 1602 */ 1603 static int smu_wbrf_init(struct smu_context *smu) 1604 { 1605 int ret; 1606 1607 if (!smu->wbrf_supported) 1608 return 0; 1609 1610 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1611 1612 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1613 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1614 if (ret) 1615 return ret; 1616 1617 /* 1618 * Some wifiband exclusion ranges may be already there 1619 * before our driver loaded. To make sure our driver 1620 * is awared of those exclusion ranges. 1621 */ 1622 schedule_delayed_work(&smu->wbrf_delayed_work, 1623 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1624 1625 return 0; 1626 } 1627 1628 /** 1629 * smu_wbrf_fini - tear down driver wbrf support 1630 * 1631 * @smu: smu_context pointer 1632 * 1633 * Unregisters with the wbrf notifier chain. 1634 */ 1635 static void smu_wbrf_fini(struct smu_context *smu) 1636 { 1637 if (!smu->wbrf_supported) 1638 return; 1639 1640 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1641 1642 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1643 } 1644 1645 static int smu_smc_hw_setup(struct smu_context *smu) 1646 { 1647 struct amdgpu_device *adev = smu->adev; 1648 uint8_t pcie_gen = 0, pcie_width = 0; 1649 uint64_t features_supported; 1650 int ret = 0; 1651 1652 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1653 case IP_VERSION(11, 0, 7): 1654 case IP_VERSION(11, 0, 11): 1655 case IP_VERSION(11, 5, 0): 1656 case IP_VERSION(11, 5, 2): 1657 case IP_VERSION(11, 0, 12): 1658 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1659 dev_info(adev->dev, "dpm has been enabled\n"); 1660 ret = smu_system_features_control(smu, true); 1661 if (ret) { 1662 dev_err(adev->dev, "Failed system features control!\n"); 1663 return ret; 1664 } 1665 1666 return smu_enable_thermal_alert(smu); 1667 } 1668 break; 1669 default: 1670 break; 1671 } 1672 1673 ret = smu_init_display_count(smu, 0); 1674 if (ret) { 1675 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1676 return ret; 1677 } 1678 1679 ret = smu_set_driver_table_location(smu); 1680 if (ret) { 1681 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1682 return ret; 1683 } 1684 1685 /* 1686 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1687 */ 1688 ret = smu_set_tool_table_location(smu); 1689 if (ret) { 1690 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1691 return ret; 1692 } 1693 1694 /* 1695 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1696 * pool location. 1697 */ 1698 ret = smu_notify_memory_pool_location(smu); 1699 if (ret) { 1700 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1701 return ret; 1702 } 1703 1704 /* 1705 * It is assumed the pptable used before runpm is same as 1706 * the one used afterwards. Thus, we can reuse the stored 1707 * copy and do not need to resetup the pptable again. 1708 */ 1709 if (!adev->in_runpm) { 1710 ret = smu_setup_pptable(smu); 1711 if (ret) { 1712 dev_err(adev->dev, "Failed to setup pptable!\n"); 1713 return ret; 1714 } 1715 } 1716 1717 /* smu_dump_pptable(smu); */ 1718 1719 /* 1720 * With SCPM enabled, PSP is responsible for the PPTable transferring 1721 * (to SMU). Driver involvement is not needed and permitted. 1722 */ 1723 if (!adev->scpm_enabled) { 1724 /* 1725 * Copy pptable bo in the vram to smc with SMU MSGs such as 1726 * SetDriverDramAddr and TransferTableDram2Smu. 1727 */ 1728 ret = smu_write_pptable(smu); 1729 if (ret) { 1730 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1731 return ret; 1732 } 1733 } 1734 1735 /* issue Run*Btc msg */ 1736 ret = smu_run_btc(smu); 1737 if (ret) 1738 return ret; 1739 1740 /* Enable UclkShadow on wbrf supported */ 1741 if (smu->wbrf_supported) { 1742 ret = smu_enable_uclk_shadow(smu, true); 1743 if (ret) { 1744 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1745 return ret; 1746 } 1747 } 1748 1749 /* 1750 * With SCPM enabled, these actions(and relevant messages) are 1751 * not needed and permitted. 1752 */ 1753 if (!adev->scpm_enabled) { 1754 ret = smu_feature_set_allowed_mask(smu); 1755 if (ret) { 1756 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1757 return ret; 1758 } 1759 } 1760 1761 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1762 pcie_gen = 4; 1763 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1764 pcie_gen = 3; 1765 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1766 pcie_gen = 2; 1767 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1768 pcie_gen = 1; 1769 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1770 pcie_gen = 0; 1771 1772 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1773 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1774 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1775 */ 1776 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1777 pcie_width = 7; 1778 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1779 pcie_width = 6; 1780 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1781 pcie_width = 5; 1782 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1783 pcie_width = 4; 1784 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1785 pcie_width = 3; 1786 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1787 pcie_width = 2; 1788 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1789 pcie_width = 1; 1790 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1791 if (ret) { 1792 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1793 return ret; 1794 } 1795 1796 ret = smu_system_features_control(smu, true); 1797 if (ret) { 1798 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1799 return ret; 1800 } 1801 1802 smu_init_xgmi_plpd_mode(smu); 1803 1804 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1805 if (ret) { 1806 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1807 return ret; 1808 } 1809 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1810 (unsigned long *)&features_supported); 1811 1812 if (!smu_is_dpm_running(smu)) 1813 dev_info(adev->dev, "dpm has been disabled\n"); 1814 1815 /* 1816 * Set initialized values (get from vbios) to dpm tables context such as 1817 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1818 * type of clks. 1819 */ 1820 ret = smu_set_default_dpm_table(smu); 1821 if (ret) { 1822 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1823 return ret; 1824 } 1825 1826 ret = smu_get_thermal_temperature_range(smu); 1827 if (ret) { 1828 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1829 return ret; 1830 } 1831 1832 ret = smu_enable_thermal_alert(smu); 1833 if (ret) { 1834 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1835 return ret; 1836 } 1837 1838 ret = smu_notify_display_change(smu); 1839 if (ret) { 1840 dev_err(adev->dev, "Failed to notify display change!\n"); 1841 return ret; 1842 } 1843 1844 /* 1845 * Set min deep sleep dce fclk with bootup value from vbios via 1846 * SetMinDeepSleepDcefclk MSG. 1847 */ 1848 ret = smu_set_min_dcef_deep_sleep(smu, 1849 smu->smu_table.boot_values.dcefclk / 100); 1850 if (ret) { 1851 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1852 return ret; 1853 } 1854 1855 /* Init wbrf support. Properly setup the notifier */ 1856 ret = smu_wbrf_init(smu); 1857 if (ret) 1858 dev_err(adev->dev, "Error during wbrf init call\n"); 1859 1860 return ret; 1861 } 1862 1863 static int smu_start_smc_engine(struct smu_context *smu) 1864 { 1865 struct amdgpu_device *adev = smu->adev; 1866 int ret = 0; 1867 1868 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1869 smu_update_gpu_addresses(smu); 1870 1871 smu->smc_fw_state = SMU_FW_INIT; 1872 1873 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1874 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1875 if (smu->ppt_funcs->load_microcode) { 1876 ret = smu->ppt_funcs->load_microcode(smu); 1877 if (ret) 1878 return ret; 1879 } 1880 } 1881 } 1882 1883 if (smu->ppt_funcs->check_fw_status) { 1884 ret = smu->ppt_funcs->check_fw_status(smu); 1885 if (ret) { 1886 dev_err(adev->dev, "SMC is not ready\n"); 1887 return ret; 1888 } 1889 } 1890 1891 /* 1892 * Send msg GetDriverIfVersion to check if the return value is equal 1893 * with DRIVER_IF_VERSION of smc header. 1894 */ 1895 ret = smu_check_fw_version(smu); 1896 if (ret) 1897 return ret; 1898 1899 return ret; 1900 } 1901 1902 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1903 { 1904 int i, ret; 1905 struct amdgpu_device *adev = ip_block->adev; 1906 struct smu_context *smu = adev->powerplay.pp_handle; 1907 1908 if (amdgpu_sriov_multi_vf_mode(adev)) { 1909 smu->pm_enabled = false; 1910 return 0; 1911 } 1912 1913 ret = smu_start_smc_engine(smu); 1914 if (ret) { 1915 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1916 return ret; 1917 } 1918 1919 /* 1920 * Check whether wbrf is supported. This needs to be done 1921 * before SMU setup starts since part of SMU configuration 1922 * relies on this. 1923 */ 1924 smu_wbrf_support_check(smu); 1925 1926 if (smu->is_apu) { 1927 ret = smu_set_gfx_imu_enable(smu); 1928 if (ret) 1929 return ret; 1930 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1931 smu_dpm_set_vcn_enable(smu, true, i); 1932 smu_dpm_set_jpeg_enable(smu, true); 1933 smu_dpm_set_umsch_mm_enable(smu, true); 1934 smu_set_mall_enable(smu); 1935 smu_set_gfx_cgpg(smu, true); 1936 } 1937 1938 if (!smu->pm_enabled) 1939 return 0; 1940 1941 ret = smu_init_driver_allowed_feature_mask(smu); 1942 if (ret) 1943 return ret; 1944 1945 ret = smu_smc_hw_setup(smu); 1946 if (ret) { 1947 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1948 return ret; 1949 } 1950 1951 /* 1952 * Move maximum sustainable clock retrieving here considering 1953 * 1. It is not needed on resume(from S3). 1954 * 2. DAL settings come between .hw_init and .late_init of SMU. 1955 * And DAL needs to know the maximum sustainable clocks. Thus 1956 * it cannot be put in .late_init(). 1957 */ 1958 ret = smu_init_max_sustainable_clocks(smu); 1959 if (ret) { 1960 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1961 return ret; 1962 } 1963 1964 adev->pm.dpm_enabled = true; 1965 1966 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1967 1968 return 0; 1969 } 1970 1971 static int smu_disable_dpms(struct smu_context *smu) 1972 { 1973 struct amdgpu_device *adev = smu->adev; 1974 int ret = 0; 1975 bool use_baco = !smu->is_apu && 1976 ((amdgpu_in_reset(adev) && 1977 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1978 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1979 1980 /* 1981 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1982 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1983 */ 1984 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1985 case IP_VERSION(13, 0, 0): 1986 case IP_VERSION(13, 0, 7): 1987 case IP_VERSION(13, 0, 10): 1988 case IP_VERSION(14, 0, 2): 1989 case IP_VERSION(14, 0, 3): 1990 return 0; 1991 default: 1992 break; 1993 } 1994 1995 /* 1996 * For custom pptable uploading, skip the DPM features 1997 * disable process on Navi1x ASICs. 1998 * - As the gfx related features are under control of 1999 * RLC on those ASICs. RLC reinitialization will be 2000 * needed to reenable them. That will cost much more 2001 * efforts. 2002 * 2003 * - SMU firmware can handle the DPM reenablement 2004 * properly. 2005 */ 2006 if (smu->uploading_custom_pp_table) { 2007 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2008 case IP_VERSION(11, 0, 0): 2009 case IP_VERSION(11, 0, 5): 2010 case IP_VERSION(11, 0, 9): 2011 case IP_VERSION(11, 0, 7): 2012 case IP_VERSION(11, 0, 11): 2013 case IP_VERSION(11, 5, 0): 2014 case IP_VERSION(11, 5, 2): 2015 case IP_VERSION(11, 0, 12): 2016 case IP_VERSION(11, 0, 13): 2017 return 0; 2018 default: 2019 break; 2020 } 2021 } 2022 2023 /* 2024 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2025 * on BACO in. Driver involvement is unnecessary. 2026 */ 2027 if (use_baco) { 2028 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2029 case IP_VERSION(11, 0, 7): 2030 case IP_VERSION(11, 0, 0): 2031 case IP_VERSION(11, 0, 5): 2032 case IP_VERSION(11, 0, 9): 2033 case IP_VERSION(13, 0, 7): 2034 return 0; 2035 default: 2036 break; 2037 } 2038 } 2039 2040 /* 2041 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2042 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2043 */ 2044 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2045 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2046 return 0; 2047 2048 /* vangogh s0ix */ 2049 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2050 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2051 adev->in_s0ix) 2052 return 0; 2053 2054 /* 2055 * For gpu reset, runpm and hibernation through BACO, 2056 * BACO feature has to be kept enabled. 2057 */ 2058 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2059 ret = smu_disable_all_features_with_exception(smu, 2060 SMU_FEATURE_BACO_BIT); 2061 if (ret) 2062 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2063 } else { 2064 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2065 if (!adev->scpm_enabled) { 2066 ret = smu_system_features_control(smu, false); 2067 if (ret) 2068 dev_err(adev->dev, "Failed to disable smu features.\n"); 2069 } 2070 } 2071 2072 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2073 * otherwise SMU will hang while interacting with RLC if RLC is halted 2074 * this is a WA for Vangogh asic which fix the SMU hang issue. 2075 */ 2076 ret = smu_notify_rlc_state(smu, false); 2077 if (ret) { 2078 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2079 return ret; 2080 } 2081 2082 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2083 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2084 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2085 adev->gfx.rlc.funcs->stop(adev); 2086 2087 return ret; 2088 } 2089 2090 static int smu_smc_hw_cleanup(struct smu_context *smu) 2091 { 2092 struct amdgpu_device *adev = smu->adev; 2093 int ret = 0; 2094 2095 smu_wbrf_fini(smu); 2096 2097 cancel_work_sync(&smu->throttling_logging_work); 2098 cancel_work_sync(&smu->interrupt_work); 2099 2100 ret = smu_disable_thermal_alert(smu); 2101 if (ret) { 2102 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2103 return ret; 2104 } 2105 2106 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2107 2108 ret = smu_disable_dpms(smu); 2109 if (ret) { 2110 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2111 return ret; 2112 } 2113 2114 return 0; 2115 } 2116 2117 static int smu_reset_mp1_state(struct smu_context *smu) 2118 { 2119 struct amdgpu_device *adev = smu->adev; 2120 int ret = 0; 2121 2122 if ((!adev->in_runpm) && (!adev->in_suspend) && 2123 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2124 IP_VERSION(13, 0, 10) && 2125 !amdgpu_device_has_display_hardware(adev)) 2126 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2127 2128 return ret; 2129 } 2130 2131 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2132 { 2133 struct amdgpu_device *adev = ip_block->adev; 2134 struct smu_context *smu = adev->powerplay.pp_handle; 2135 int i, ret; 2136 2137 if (amdgpu_sriov_multi_vf_mode(adev)) 2138 return 0; 2139 2140 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2141 smu_dpm_set_vcn_enable(smu, false, i); 2142 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2143 } 2144 smu_dpm_set_jpeg_enable(smu, false); 2145 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2146 smu_dpm_set_umsch_mm_enable(smu, false); 2147 2148 if (!smu->pm_enabled) 2149 return 0; 2150 2151 adev->pm.dpm_enabled = false; 2152 2153 ret = smu_smc_hw_cleanup(smu); 2154 if (ret) 2155 return ret; 2156 2157 ret = smu_reset_mp1_state(smu); 2158 if (ret) 2159 return ret; 2160 2161 return 0; 2162 } 2163 2164 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2165 { 2166 struct amdgpu_device *adev = ip_block->adev; 2167 struct smu_context *smu = adev->powerplay.pp_handle; 2168 2169 kfree(smu); 2170 } 2171 2172 static int smu_reset(struct smu_context *smu) 2173 { 2174 struct amdgpu_device *adev = smu->adev; 2175 struct amdgpu_ip_block *ip_block; 2176 int ret; 2177 2178 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2179 if (!ip_block) 2180 return -EINVAL; 2181 2182 ret = smu_hw_fini(ip_block); 2183 if (ret) 2184 return ret; 2185 2186 ret = smu_hw_init(ip_block); 2187 if (ret) 2188 return ret; 2189 2190 ret = smu_late_init(ip_block); 2191 if (ret) 2192 return ret; 2193 2194 return 0; 2195 } 2196 2197 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2198 { 2199 struct amdgpu_device *adev = ip_block->adev; 2200 struct smu_context *smu = adev->powerplay.pp_handle; 2201 int ret; 2202 uint64_t count; 2203 2204 if (amdgpu_sriov_multi_vf_mode(adev)) 2205 return 0; 2206 2207 if (!smu->pm_enabled) 2208 return 0; 2209 2210 adev->pm.dpm_enabled = false; 2211 2212 ret = smu_smc_hw_cleanup(smu); 2213 if (ret) 2214 return ret; 2215 2216 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2217 2218 smu_set_gfx_cgpg(smu, false); 2219 2220 /* 2221 * pwfw resets entrycount when device is suspended, so we save the 2222 * last value to be used when we resume to keep it consistent 2223 */ 2224 ret = smu_get_entrycount_gfxoff(smu, &count); 2225 if (!ret) 2226 adev->gfx.gfx_off_entrycount = count; 2227 2228 /* clear this on suspend so it will get reprogrammed on resume */ 2229 smu->workload_mask = 0; 2230 2231 return 0; 2232 } 2233 2234 static int smu_resume(struct amdgpu_ip_block *ip_block) 2235 { 2236 int ret; 2237 struct amdgpu_device *adev = ip_block->adev; 2238 struct smu_context *smu = adev->powerplay.pp_handle; 2239 2240 if (amdgpu_sriov_multi_vf_mode(adev)) 2241 return 0; 2242 2243 if (!smu->pm_enabled) 2244 return 0; 2245 2246 dev_info(adev->dev, "SMU is resuming...\n"); 2247 2248 ret = smu_start_smc_engine(smu); 2249 if (ret) { 2250 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2251 return ret; 2252 } 2253 2254 ret = smu_smc_hw_setup(smu); 2255 if (ret) { 2256 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2257 return ret; 2258 } 2259 2260 ret = smu_set_gfx_imu_enable(smu); 2261 if (ret) 2262 return ret; 2263 2264 smu_set_gfx_cgpg(smu, true); 2265 2266 smu->disable_uclk_switch = 0; 2267 2268 adev->pm.dpm_enabled = true; 2269 2270 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2271 2272 return 0; 2273 } 2274 2275 static int smu_display_configuration_change(void *handle, 2276 const struct amd_pp_display_configuration *display_config) 2277 { 2278 struct smu_context *smu = handle; 2279 2280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2281 return -EOPNOTSUPP; 2282 2283 if (!display_config) 2284 return -EINVAL; 2285 2286 smu_set_min_dcef_deep_sleep(smu, 2287 display_config->min_dcef_deep_sleep_set_clk / 100); 2288 2289 return 0; 2290 } 2291 2292 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2293 enum amd_clockgating_state state) 2294 { 2295 return 0; 2296 } 2297 2298 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2299 enum amd_powergating_state state) 2300 { 2301 return 0; 2302 } 2303 2304 static int smu_enable_umd_pstate(void *handle, 2305 enum amd_dpm_forced_level *level) 2306 { 2307 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2308 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2309 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2310 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2311 2312 struct smu_context *smu = (struct smu_context*)(handle); 2313 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2314 2315 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2316 return -EINVAL; 2317 2318 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2319 /* enter umd pstate, save current level, disable gfx cg*/ 2320 if (*level & profile_mode_mask) { 2321 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2322 smu_gpo_control(smu, false); 2323 smu_gfx_ulv_control(smu, false); 2324 smu_deep_sleep_control(smu, false); 2325 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2326 } 2327 } else { 2328 /* exit umd pstate, restore level, enable gfx cg*/ 2329 if (!(*level & profile_mode_mask)) { 2330 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2331 *level = smu_dpm_ctx->saved_dpm_level; 2332 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2333 smu_deep_sleep_control(smu, true); 2334 smu_gfx_ulv_control(smu, true); 2335 smu_gpo_control(smu, true); 2336 } 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int smu_bump_power_profile_mode(struct smu_context *smu, 2343 long *custom_params, 2344 u32 custom_params_max_idx) 2345 { 2346 u32 workload_mask = 0; 2347 int i, ret = 0; 2348 2349 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2350 if (smu->workload_refcount[i]) 2351 workload_mask |= 1 << i; 2352 } 2353 2354 if (smu->workload_mask == workload_mask) 2355 return 0; 2356 2357 if (smu->ppt_funcs->set_power_profile_mode) 2358 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2359 custom_params, 2360 custom_params_max_idx); 2361 2362 if (!ret) 2363 smu->workload_mask = workload_mask; 2364 2365 return ret; 2366 } 2367 2368 static void smu_power_profile_mode_get(struct smu_context *smu, 2369 enum PP_SMC_POWER_PROFILE profile_mode) 2370 { 2371 smu->workload_refcount[profile_mode]++; 2372 } 2373 2374 static void smu_power_profile_mode_put(struct smu_context *smu, 2375 enum PP_SMC_POWER_PROFILE profile_mode) 2376 { 2377 if (smu->workload_refcount[profile_mode]) 2378 smu->workload_refcount[profile_mode]--; 2379 } 2380 2381 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2382 enum amd_dpm_forced_level level, 2383 bool skip_display_settings) 2384 { 2385 int ret = 0; 2386 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2387 2388 if (!skip_display_settings) { 2389 ret = smu_display_config_changed(smu); 2390 if (ret) { 2391 dev_err(smu->adev->dev, "Failed to change display config!"); 2392 return ret; 2393 } 2394 } 2395 2396 ret = smu_apply_clocks_adjust_rules(smu); 2397 if (ret) { 2398 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2399 return ret; 2400 } 2401 2402 if (!skip_display_settings) { 2403 ret = smu_notify_smc_display_config(smu); 2404 if (ret) { 2405 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2406 return ret; 2407 } 2408 } 2409 2410 if (smu_dpm_ctx->dpm_level != level) { 2411 ret = smu_asic_set_performance_level(smu, level); 2412 if (ret) { 2413 if (ret == -EOPNOTSUPP) 2414 dev_info(smu->adev->dev, "set performance level %d not supported", 2415 level); 2416 else 2417 dev_err(smu->adev->dev, "Failed to set performance level %d", 2418 level); 2419 return ret; 2420 } 2421 2422 /* update the saved copy */ 2423 smu_dpm_ctx->dpm_level = level; 2424 } 2425 2426 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2427 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2428 smu_bump_power_profile_mode(smu, NULL, 0); 2429 2430 return ret; 2431 } 2432 2433 static int smu_handle_task(struct smu_context *smu, 2434 enum amd_dpm_forced_level level, 2435 enum amd_pp_task task_id) 2436 { 2437 int ret = 0; 2438 2439 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2440 return -EOPNOTSUPP; 2441 2442 switch (task_id) { 2443 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2444 ret = smu_pre_display_config_changed(smu); 2445 if (ret) 2446 return ret; 2447 ret = smu_adjust_power_state_dynamic(smu, level, false); 2448 break; 2449 case AMD_PP_TASK_COMPLETE_INIT: 2450 ret = smu_adjust_power_state_dynamic(smu, level, true); 2451 break; 2452 case AMD_PP_TASK_READJUST_POWER_STATE: 2453 ret = smu_adjust_power_state_dynamic(smu, level, true); 2454 break; 2455 default: 2456 break; 2457 } 2458 2459 return ret; 2460 } 2461 2462 static int smu_handle_dpm_task(void *handle, 2463 enum amd_pp_task task_id, 2464 enum amd_pm_state_type *user_state) 2465 { 2466 struct smu_context *smu = handle; 2467 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2468 2469 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2470 2471 } 2472 2473 static int smu_switch_power_profile(void *handle, 2474 enum PP_SMC_POWER_PROFILE type, 2475 bool enable) 2476 { 2477 struct smu_context *smu = handle; 2478 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2479 int ret; 2480 2481 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2482 return -EOPNOTSUPP; 2483 2484 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2485 return -EINVAL; 2486 2487 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2488 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2489 if (enable) 2490 smu_power_profile_mode_get(smu, type); 2491 else 2492 smu_power_profile_mode_put(smu, type); 2493 /* don't switch the active workload when paused */ 2494 if (smu->pause_workload) 2495 ret = 0; 2496 else 2497 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2498 if (ret) { 2499 if (enable) 2500 smu_power_profile_mode_put(smu, type); 2501 else 2502 smu_power_profile_mode_get(smu, type); 2503 return ret; 2504 } 2505 } 2506 2507 return 0; 2508 } 2509 2510 static int smu_pause_power_profile(void *handle, 2511 bool pause) 2512 { 2513 struct smu_context *smu = handle; 2514 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2515 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2516 int ret; 2517 2518 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2519 return -EOPNOTSUPP; 2520 2521 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2522 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2523 smu->pause_workload = pause; 2524 2525 /* force to bootup default profile */ 2526 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2527 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2528 workload_mask, 2529 NULL, 2530 0); 2531 else 2532 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2533 return ret; 2534 } 2535 2536 return 0; 2537 } 2538 2539 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2540 { 2541 struct smu_context *smu = handle; 2542 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2543 2544 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2545 return -EOPNOTSUPP; 2546 2547 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2548 return -EINVAL; 2549 2550 return smu_dpm_ctx->dpm_level; 2551 } 2552 2553 static int smu_force_performance_level(void *handle, 2554 enum amd_dpm_forced_level level) 2555 { 2556 struct smu_context *smu = handle; 2557 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2558 int ret = 0; 2559 2560 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2561 return -EOPNOTSUPP; 2562 2563 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2564 return -EINVAL; 2565 2566 ret = smu_enable_umd_pstate(smu, &level); 2567 if (ret) 2568 return ret; 2569 2570 ret = smu_handle_task(smu, level, 2571 AMD_PP_TASK_READJUST_POWER_STATE); 2572 2573 /* reset user dpm clock state */ 2574 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2575 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2576 smu->user_dpm_profile.clk_dependency = 0; 2577 } 2578 2579 return ret; 2580 } 2581 2582 static int smu_set_display_count(void *handle, uint32_t count) 2583 { 2584 struct smu_context *smu = handle; 2585 2586 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2587 return -EOPNOTSUPP; 2588 2589 return smu_init_display_count(smu, count); 2590 } 2591 2592 static int smu_force_smuclk_levels(struct smu_context *smu, 2593 enum smu_clk_type clk_type, 2594 uint32_t mask) 2595 { 2596 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2597 int ret = 0; 2598 2599 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2600 return -EOPNOTSUPP; 2601 2602 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2603 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2604 return -EINVAL; 2605 } 2606 2607 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2608 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2609 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2610 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2611 smu_set_user_clk_dependencies(smu, clk_type); 2612 } 2613 } 2614 2615 return ret; 2616 } 2617 2618 static int smu_force_ppclk_levels(void *handle, 2619 enum pp_clock_type type, 2620 uint32_t mask) 2621 { 2622 struct smu_context *smu = handle; 2623 enum smu_clk_type clk_type; 2624 2625 switch (type) { 2626 case PP_SCLK: 2627 clk_type = SMU_SCLK; break; 2628 case PP_MCLK: 2629 clk_type = SMU_MCLK; break; 2630 case PP_PCIE: 2631 clk_type = SMU_PCIE; break; 2632 case PP_SOCCLK: 2633 clk_type = SMU_SOCCLK; break; 2634 case PP_FCLK: 2635 clk_type = SMU_FCLK; break; 2636 case PP_DCEFCLK: 2637 clk_type = SMU_DCEFCLK; break; 2638 case PP_VCLK: 2639 clk_type = SMU_VCLK; break; 2640 case PP_VCLK1: 2641 clk_type = SMU_VCLK1; break; 2642 case PP_DCLK: 2643 clk_type = SMU_DCLK; break; 2644 case PP_DCLK1: 2645 clk_type = SMU_DCLK1; break; 2646 case OD_SCLK: 2647 clk_type = SMU_OD_SCLK; break; 2648 case OD_MCLK: 2649 clk_type = SMU_OD_MCLK; break; 2650 case OD_VDDC_CURVE: 2651 clk_type = SMU_OD_VDDC_CURVE; break; 2652 case OD_RANGE: 2653 clk_type = SMU_OD_RANGE; break; 2654 default: 2655 return -EINVAL; 2656 } 2657 2658 return smu_force_smuclk_levels(smu, clk_type, mask); 2659 } 2660 2661 /* 2662 * On system suspending or resetting, the dpm_enabled 2663 * flag will be cleared. So that those SMU services which 2664 * are not supported will be gated. 2665 * However, the mp1 state setting should still be granted 2666 * even if the dpm_enabled cleared. 2667 */ 2668 static int smu_set_mp1_state(void *handle, 2669 enum pp_mp1_state mp1_state) 2670 { 2671 struct smu_context *smu = handle; 2672 int ret = 0; 2673 2674 if (!smu->pm_enabled) 2675 return -EOPNOTSUPP; 2676 2677 if (smu->ppt_funcs && 2678 smu->ppt_funcs->set_mp1_state) 2679 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2680 2681 return ret; 2682 } 2683 2684 static int smu_set_df_cstate(void *handle, 2685 enum pp_df_cstate state) 2686 { 2687 struct smu_context *smu = handle; 2688 int ret = 0; 2689 2690 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2691 return -EOPNOTSUPP; 2692 2693 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2694 return 0; 2695 2696 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2697 if (ret) 2698 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2699 2700 return ret; 2701 } 2702 2703 int smu_write_watermarks_table(struct smu_context *smu) 2704 { 2705 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2706 return -EOPNOTSUPP; 2707 2708 return smu_set_watermarks_table(smu, NULL); 2709 } 2710 2711 static int smu_set_watermarks_for_clock_ranges(void *handle, 2712 struct pp_smu_wm_range_sets *clock_ranges) 2713 { 2714 struct smu_context *smu = handle; 2715 2716 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2717 return -EOPNOTSUPP; 2718 2719 if (smu->disable_watermark) 2720 return 0; 2721 2722 return smu_set_watermarks_table(smu, clock_ranges); 2723 } 2724 2725 int smu_set_ac_dc(struct smu_context *smu) 2726 { 2727 int ret = 0; 2728 2729 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2730 return -EOPNOTSUPP; 2731 2732 /* controlled by firmware */ 2733 if (smu->dc_controlled_by_gpio) 2734 return 0; 2735 2736 ret = smu_set_power_source(smu, 2737 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2738 SMU_POWER_SOURCE_DC); 2739 if (ret) 2740 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2741 smu->adev->pm.ac_power ? "AC" : "DC"); 2742 2743 return ret; 2744 } 2745 2746 const struct amd_ip_funcs smu_ip_funcs = { 2747 .name = "smu", 2748 .early_init = smu_early_init, 2749 .late_init = smu_late_init, 2750 .sw_init = smu_sw_init, 2751 .sw_fini = smu_sw_fini, 2752 .hw_init = smu_hw_init, 2753 .hw_fini = smu_hw_fini, 2754 .late_fini = smu_late_fini, 2755 .suspend = smu_suspend, 2756 .resume = smu_resume, 2757 .is_idle = NULL, 2758 .check_soft_reset = NULL, 2759 .wait_for_idle = NULL, 2760 .soft_reset = NULL, 2761 .set_clockgating_state = smu_set_clockgating_state, 2762 .set_powergating_state = smu_set_powergating_state, 2763 }; 2764 2765 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2766 .type = AMD_IP_BLOCK_TYPE_SMC, 2767 .major = 11, 2768 .minor = 0, 2769 .rev = 0, 2770 .funcs = &smu_ip_funcs, 2771 }; 2772 2773 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2774 .type = AMD_IP_BLOCK_TYPE_SMC, 2775 .major = 12, 2776 .minor = 0, 2777 .rev = 0, 2778 .funcs = &smu_ip_funcs, 2779 }; 2780 2781 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2782 .type = AMD_IP_BLOCK_TYPE_SMC, 2783 .major = 13, 2784 .minor = 0, 2785 .rev = 0, 2786 .funcs = &smu_ip_funcs, 2787 }; 2788 2789 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2790 .type = AMD_IP_BLOCK_TYPE_SMC, 2791 .major = 14, 2792 .minor = 0, 2793 .rev = 0, 2794 .funcs = &smu_ip_funcs, 2795 }; 2796 2797 const struct amdgpu_ip_block_version smu_v15_0_ip_block = { 2798 .type = AMD_IP_BLOCK_TYPE_SMC, 2799 .major = 15, 2800 .minor = 0, 2801 .rev = 0, 2802 .funcs = &smu_ip_funcs, 2803 }; 2804 2805 const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2806 { 2807 struct smu_context *smu = (struct smu_context *)handle; 2808 const struct ras_smu_drv *tmp = NULL; 2809 int ret; 2810 2811 ret = smu_get_ras_smu_drv(smu, &tmp); 2812 2813 return ret ? NULL : tmp; 2814 } 2815 2816 static int smu_load_microcode(void *handle) 2817 { 2818 struct smu_context *smu = handle; 2819 struct amdgpu_device *adev = smu->adev; 2820 int ret = 0; 2821 2822 if (!smu->pm_enabled) 2823 return -EOPNOTSUPP; 2824 2825 /* This should be used for non PSP loading */ 2826 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2827 return 0; 2828 2829 if (smu->ppt_funcs->load_microcode) { 2830 ret = smu->ppt_funcs->load_microcode(smu); 2831 if (ret) { 2832 dev_err(adev->dev, "Load microcode failed\n"); 2833 return ret; 2834 } 2835 } 2836 2837 if (smu->ppt_funcs->check_fw_status) { 2838 ret = smu->ppt_funcs->check_fw_status(smu); 2839 if (ret) { 2840 dev_err(adev->dev, "SMC is not ready\n"); 2841 return ret; 2842 } 2843 } 2844 2845 return ret; 2846 } 2847 2848 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2849 { 2850 int ret = 0; 2851 2852 if (smu->ppt_funcs->set_gfx_cgpg) 2853 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2854 2855 return ret; 2856 } 2857 2858 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2859 { 2860 struct smu_context *smu = handle; 2861 int ret = 0; 2862 2863 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2864 return -EOPNOTSUPP; 2865 2866 if (!smu->ppt_funcs->set_fan_speed_rpm) 2867 return -EOPNOTSUPP; 2868 2869 if (speed == U32_MAX) 2870 return -EINVAL; 2871 2872 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2873 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2874 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2875 smu->user_dpm_profile.fan_speed_rpm = speed; 2876 2877 /* Override custom PWM setting as they cannot co-exist */ 2878 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2879 smu->user_dpm_profile.fan_speed_pwm = 0; 2880 } 2881 2882 return ret; 2883 } 2884 2885 /** 2886 * smu_get_power_limit - Request one of the SMU Power Limits 2887 * 2888 * @handle: pointer to smu context 2889 * @limit: requested limit is written back to this variable 2890 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2891 * @pp_power_type: &pp_power_type type of power 2892 * Return: 0 on success, <0 on error 2893 * 2894 */ 2895 int smu_get_power_limit(void *handle, 2896 uint32_t *limit, 2897 enum pp_power_limit_level pp_limit_level, 2898 enum pp_power_type pp_power_type) 2899 { 2900 struct smu_context *smu = handle; 2901 struct amdgpu_device *adev = smu->adev; 2902 enum smu_ppt_limit_level limit_level; 2903 uint32_t limit_type; 2904 int ret = 0; 2905 2906 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2907 return -EOPNOTSUPP; 2908 2909 if (!limit) 2910 return -EINVAL; 2911 2912 switch (pp_power_type) { 2913 case PP_PWR_TYPE_SUSTAINED: 2914 limit_type = SMU_DEFAULT_PPT_LIMIT; 2915 break; 2916 case PP_PWR_TYPE_FAST: 2917 limit_type = SMU_FAST_PPT_LIMIT; 2918 break; 2919 default: 2920 return -EOPNOTSUPP; 2921 } 2922 2923 switch (pp_limit_level) { 2924 case PP_PWR_LIMIT_CURRENT: 2925 limit_level = SMU_PPT_LIMIT_CURRENT; 2926 break; 2927 case PP_PWR_LIMIT_DEFAULT: 2928 limit_level = SMU_PPT_LIMIT_DEFAULT; 2929 break; 2930 case PP_PWR_LIMIT_MAX: 2931 limit_level = SMU_PPT_LIMIT_MAX; 2932 break; 2933 case PP_PWR_LIMIT_MIN: 2934 limit_level = SMU_PPT_LIMIT_MIN; 2935 break; 2936 default: 2937 return -EOPNOTSUPP; 2938 } 2939 2940 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2941 if (smu->ppt_funcs->get_ppt_limit) 2942 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2943 else 2944 return -EOPNOTSUPP; 2945 } else { 2946 switch (limit_level) { 2947 case SMU_PPT_LIMIT_CURRENT: 2948 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2949 case IP_VERSION(13, 0, 2): 2950 case IP_VERSION(13, 0, 6): 2951 case IP_VERSION(13, 0, 12): 2952 case IP_VERSION(13, 0, 14): 2953 case IP_VERSION(11, 0, 7): 2954 case IP_VERSION(11, 0, 11): 2955 case IP_VERSION(11, 0, 12): 2956 case IP_VERSION(11, 0, 13): 2957 ret = smu_get_asic_power_limits(smu, 2958 &smu->current_power_limit, 2959 NULL, NULL, NULL); 2960 break; 2961 default: 2962 break; 2963 } 2964 *limit = smu->current_power_limit; 2965 break; 2966 case SMU_PPT_LIMIT_DEFAULT: 2967 *limit = smu->default_power_limit; 2968 break; 2969 case SMU_PPT_LIMIT_MAX: 2970 *limit = smu->max_power_limit; 2971 break; 2972 case SMU_PPT_LIMIT_MIN: 2973 *limit = smu->min_power_limit; 2974 break; 2975 default: 2976 return -EINVAL; 2977 } 2978 } 2979 2980 return ret; 2981 } 2982 2983 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 2984 { 2985 struct smu_context *smu = handle; 2986 int ret = 0; 2987 2988 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2989 return -EOPNOTSUPP; 2990 2991 if (limit_type == SMU_DEFAULT_PPT_LIMIT) { 2992 if (!limit) 2993 limit = smu->current_power_limit; 2994 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 2995 dev_err(smu->adev->dev, 2996 "New power limit (%d) is out of range [%d,%d]\n", 2997 limit, smu->min_power_limit, smu->max_power_limit); 2998 return -EINVAL; 2999 } 3000 } 3001 3002 if (smu->ppt_funcs->set_power_limit) { 3003 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 3004 if (ret) 3005 return ret; 3006 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 3007 smu->user_dpm_profile.power_limits[limit_type] = limit; 3008 } 3009 3010 return 0; 3011 } 3012 3013 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3014 { 3015 enum smu_clk_type clk_type; 3016 3017 switch (type) { 3018 case PP_SCLK: 3019 clk_type = SMU_SCLK; break; 3020 case PP_MCLK: 3021 clk_type = SMU_MCLK; break; 3022 case PP_PCIE: 3023 clk_type = SMU_PCIE; break; 3024 case PP_SOCCLK: 3025 clk_type = SMU_SOCCLK; break; 3026 case PP_FCLK: 3027 clk_type = SMU_FCLK; break; 3028 case PP_DCEFCLK: 3029 clk_type = SMU_DCEFCLK; break; 3030 case PP_VCLK: 3031 clk_type = SMU_VCLK; break; 3032 case PP_VCLK1: 3033 clk_type = SMU_VCLK1; break; 3034 case PP_DCLK: 3035 clk_type = SMU_DCLK; break; 3036 case PP_DCLK1: 3037 clk_type = SMU_DCLK1; break; 3038 case PP_ISPICLK: 3039 clk_type = SMU_ISPICLK; 3040 break; 3041 case PP_ISPXCLK: 3042 clk_type = SMU_ISPXCLK; 3043 break; 3044 case OD_SCLK: 3045 clk_type = SMU_OD_SCLK; break; 3046 case OD_MCLK: 3047 clk_type = SMU_OD_MCLK; break; 3048 case OD_VDDC_CURVE: 3049 clk_type = SMU_OD_VDDC_CURVE; break; 3050 case OD_RANGE: 3051 clk_type = SMU_OD_RANGE; break; 3052 case OD_VDDGFX_OFFSET: 3053 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3054 case OD_CCLK: 3055 clk_type = SMU_OD_CCLK; break; 3056 case OD_FAN_CURVE: 3057 clk_type = SMU_OD_FAN_CURVE; break; 3058 case OD_ACOUSTIC_LIMIT: 3059 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3060 case OD_ACOUSTIC_TARGET: 3061 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3062 case OD_FAN_TARGET_TEMPERATURE: 3063 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3064 case OD_FAN_MINIMUM_PWM: 3065 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3066 case OD_FAN_ZERO_RPM_ENABLE: 3067 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3068 case OD_FAN_ZERO_RPM_STOP_TEMP: 3069 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3070 default: 3071 clk_type = SMU_CLK_COUNT; break; 3072 } 3073 3074 return clk_type; 3075 } 3076 3077 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3078 { 3079 struct smu_context *smu = handle; 3080 enum smu_clk_type clk_type; 3081 3082 clk_type = smu_convert_to_smuclk(type); 3083 if (clk_type == SMU_CLK_COUNT) 3084 return -EINVAL; 3085 3086 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3087 return -EOPNOTSUPP; 3088 3089 if (!smu->ppt_funcs->emit_clk_levels) 3090 return -ENOENT; 3091 3092 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3093 3094 } 3095 3096 static int smu_od_edit_dpm_table(void *handle, 3097 enum PP_OD_DPM_TABLE_COMMAND type, 3098 long *input, uint32_t size) 3099 { 3100 struct smu_context *smu = handle; 3101 int ret = 0; 3102 3103 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3104 return -EOPNOTSUPP; 3105 3106 if (smu->ppt_funcs->od_edit_dpm_table) { 3107 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3108 } 3109 3110 return ret; 3111 } 3112 3113 static int smu_read_sensor(void *handle, 3114 int sensor, 3115 void *data, 3116 int *size_arg) 3117 { 3118 struct smu_context *smu = handle; 3119 struct amdgpu_device *adev = smu->adev; 3120 struct smu_umd_pstate_table *pstate_table = 3121 &smu->pstate_table; 3122 int i, ret = 0; 3123 uint32_t *size, size_val; 3124 3125 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3126 return -EOPNOTSUPP; 3127 3128 if (!data || !size_arg) 3129 return -EINVAL; 3130 3131 size_val = *size_arg; 3132 size = &size_val; 3133 3134 if (smu->ppt_funcs->read_sensor) 3135 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3136 goto unlock; 3137 3138 switch (sensor) { 3139 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3140 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3141 *size = 4; 3142 break; 3143 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3144 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3145 *size = 4; 3146 break; 3147 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3148 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3149 *size = 4; 3150 break; 3151 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3152 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3153 *size = 4; 3154 break; 3155 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3156 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3157 *size = 8; 3158 break; 3159 case AMDGPU_PP_SENSOR_UVD_POWER: 3160 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3161 *size = 4; 3162 break; 3163 case AMDGPU_PP_SENSOR_VCE_POWER: 3164 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3165 *size = 4; 3166 break; 3167 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3168 *(uint32_t *)data = 0; 3169 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3170 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3171 *(uint32_t *)data = 1; 3172 break; 3173 } 3174 } 3175 *size = 4; 3176 break; 3177 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3178 *(uint32_t *)data = 0; 3179 *size = 4; 3180 break; 3181 default: 3182 *size = 0; 3183 ret = -EOPNOTSUPP; 3184 break; 3185 } 3186 3187 unlock: 3188 // assign uint32_t to int 3189 *size_arg = size_val; 3190 3191 return ret; 3192 } 3193 3194 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3195 { 3196 int ret = -EOPNOTSUPP; 3197 struct smu_context *smu = handle; 3198 3199 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3200 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3201 3202 return ret; 3203 } 3204 3205 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3206 { 3207 int ret = -EOPNOTSUPP; 3208 struct smu_context *smu = handle; 3209 3210 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3211 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3212 3213 return ret; 3214 } 3215 3216 static int smu_get_power_profile_mode(void *handle, char *buf) 3217 { 3218 struct smu_context *smu = handle; 3219 3220 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3221 !smu->ppt_funcs->get_power_profile_mode) 3222 return -EOPNOTSUPP; 3223 if (!buf) 3224 return -EINVAL; 3225 3226 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3227 } 3228 3229 static int smu_set_power_profile_mode(void *handle, 3230 long *param, 3231 uint32_t param_size) 3232 { 3233 struct smu_context *smu = handle; 3234 bool custom = false; 3235 int ret = 0; 3236 3237 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3238 !smu->ppt_funcs->set_power_profile_mode) 3239 return -EOPNOTSUPP; 3240 3241 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3242 custom = true; 3243 /* clear frontend mask so custom changes propogate */ 3244 smu->workload_mask = 0; 3245 } 3246 3247 if ((param[param_size] != smu->power_profile_mode) || custom) { 3248 /* clear the old user preference */ 3249 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3250 /* set the new user preference */ 3251 smu_power_profile_mode_get(smu, param[param_size]); 3252 ret = smu_bump_power_profile_mode(smu, 3253 custom ? param : NULL, 3254 custom ? param_size : 0); 3255 if (ret) 3256 smu_power_profile_mode_put(smu, param[param_size]); 3257 else 3258 /* store the user's preference */ 3259 smu->power_profile_mode = param[param_size]; 3260 } 3261 3262 return ret; 3263 } 3264 3265 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3266 { 3267 struct smu_context *smu = handle; 3268 3269 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3270 return -EOPNOTSUPP; 3271 3272 if (!smu->ppt_funcs->get_fan_control_mode) 3273 return -EOPNOTSUPP; 3274 3275 if (!fan_mode) 3276 return -EINVAL; 3277 3278 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3279 3280 return 0; 3281 } 3282 3283 static int smu_set_fan_control_mode(void *handle, u32 value) 3284 { 3285 struct smu_context *smu = handle; 3286 int ret = 0; 3287 3288 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3289 return -EOPNOTSUPP; 3290 3291 if (!smu->ppt_funcs->set_fan_control_mode) 3292 return -EOPNOTSUPP; 3293 3294 if (value == U32_MAX) 3295 return -EINVAL; 3296 3297 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3298 if (ret) 3299 goto out; 3300 3301 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3302 smu->user_dpm_profile.fan_mode = value; 3303 3304 /* reset user dpm fan speed */ 3305 if (value != AMD_FAN_CTRL_MANUAL) { 3306 smu->user_dpm_profile.fan_speed_pwm = 0; 3307 smu->user_dpm_profile.fan_speed_rpm = 0; 3308 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3309 } 3310 } 3311 3312 out: 3313 return ret; 3314 } 3315 3316 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3317 { 3318 struct smu_context *smu = handle; 3319 int ret = 0; 3320 3321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3322 return -EOPNOTSUPP; 3323 3324 if (!smu->ppt_funcs->get_fan_speed_pwm) 3325 return -EOPNOTSUPP; 3326 3327 if (!speed) 3328 return -EINVAL; 3329 3330 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3331 3332 return ret; 3333 } 3334 3335 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3336 { 3337 struct smu_context *smu = handle; 3338 int ret = 0; 3339 3340 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3341 return -EOPNOTSUPP; 3342 3343 if (!smu->ppt_funcs->set_fan_speed_pwm) 3344 return -EOPNOTSUPP; 3345 3346 if (speed == U32_MAX) 3347 return -EINVAL; 3348 3349 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3350 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3351 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3352 smu->user_dpm_profile.fan_speed_pwm = speed; 3353 3354 /* Override custom RPM setting as they cannot co-exist */ 3355 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3356 smu->user_dpm_profile.fan_speed_rpm = 0; 3357 } 3358 3359 return ret; 3360 } 3361 3362 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3363 { 3364 struct smu_context *smu = handle; 3365 int ret = 0; 3366 3367 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3368 return -EOPNOTSUPP; 3369 3370 if (!smu->ppt_funcs->get_fan_speed_rpm) 3371 return -EOPNOTSUPP; 3372 3373 if (!speed) 3374 return -EINVAL; 3375 3376 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3377 3378 return ret; 3379 } 3380 3381 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3382 { 3383 struct smu_context *smu = handle; 3384 3385 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3386 return -EOPNOTSUPP; 3387 3388 return smu_set_min_dcef_deep_sleep(smu, clk); 3389 } 3390 3391 static int smu_get_clock_by_type_with_latency(void *handle, 3392 enum amd_pp_clock_type type, 3393 struct pp_clock_levels_with_latency *clocks) 3394 { 3395 struct smu_context *smu = handle; 3396 enum smu_clk_type clk_type; 3397 int ret = 0; 3398 3399 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3400 return -EOPNOTSUPP; 3401 3402 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3403 switch (type) { 3404 case amd_pp_sys_clock: 3405 clk_type = SMU_GFXCLK; 3406 break; 3407 case amd_pp_mem_clock: 3408 clk_type = SMU_MCLK; 3409 break; 3410 case amd_pp_dcef_clock: 3411 clk_type = SMU_DCEFCLK; 3412 break; 3413 case amd_pp_disp_clock: 3414 clk_type = SMU_DISPCLK; 3415 break; 3416 default: 3417 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3418 return -EINVAL; 3419 } 3420 3421 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3422 } 3423 3424 return ret; 3425 } 3426 3427 static int smu_display_clock_voltage_request(void *handle, 3428 struct pp_display_clock_request *clock_req) 3429 { 3430 struct smu_context *smu = handle; 3431 int ret = 0; 3432 3433 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3434 return -EOPNOTSUPP; 3435 3436 if (smu->ppt_funcs->display_clock_voltage_request) 3437 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3438 3439 return ret; 3440 } 3441 3442 3443 static int smu_display_disable_memory_clock_switch(void *handle, 3444 bool disable_memory_clock_switch) 3445 { 3446 struct smu_context *smu = handle; 3447 int ret = -EINVAL; 3448 3449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3450 return -EOPNOTSUPP; 3451 3452 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3453 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3454 3455 return ret; 3456 } 3457 3458 static int smu_set_xgmi_pstate(void *handle, 3459 uint32_t pstate) 3460 { 3461 struct smu_context *smu = handle; 3462 int ret = 0; 3463 3464 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3465 return -EOPNOTSUPP; 3466 3467 if (smu->ppt_funcs->set_xgmi_pstate) 3468 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3469 3470 if (ret) 3471 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3472 3473 return ret; 3474 } 3475 3476 static int smu_get_baco_capability(void *handle) 3477 { 3478 struct smu_context *smu = handle; 3479 3480 if (!smu->pm_enabled) 3481 return false; 3482 3483 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3484 return false; 3485 3486 return smu->ppt_funcs->get_bamaco_support(smu); 3487 } 3488 3489 static int smu_baco_set_state(void *handle, int state) 3490 { 3491 struct smu_context *smu = handle; 3492 int ret = 0; 3493 3494 if (!smu->pm_enabled) 3495 return -EOPNOTSUPP; 3496 3497 if (state == 0) { 3498 if (smu->ppt_funcs->baco_exit) 3499 ret = smu->ppt_funcs->baco_exit(smu); 3500 } else if (state == 1) { 3501 if (smu->ppt_funcs->baco_enter) 3502 ret = smu->ppt_funcs->baco_enter(smu); 3503 } else { 3504 return -EINVAL; 3505 } 3506 3507 if (ret) 3508 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3509 (state)?"enter":"exit"); 3510 3511 return ret; 3512 } 3513 3514 bool smu_mode1_reset_is_support(struct smu_context *smu) 3515 { 3516 bool ret = false; 3517 3518 if (!smu->pm_enabled) 3519 return false; 3520 3521 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3522 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3523 3524 return ret; 3525 } 3526 3527 bool smu_link_reset_is_support(struct smu_context *smu) 3528 { 3529 if (!smu->pm_enabled) 3530 return false; 3531 3532 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3533 } 3534 3535 int smu_mode1_reset(struct smu_context *smu) 3536 { 3537 int ret = 0; 3538 3539 if (!smu->pm_enabled) 3540 return -EOPNOTSUPP; 3541 3542 if (smu->ppt_funcs->mode1_reset) 3543 ret = smu->ppt_funcs->mode1_reset(smu); 3544 3545 return ret; 3546 } 3547 3548 static int smu_mode2_reset(void *handle) 3549 { 3550 struct smu_context *smu = handle; 3551 int ret = 0; 3552 3553 if (!smu->pm_enabled) 3554 return -EOPNOTSUPP; 3555 3556 if (smu->ppt_funcs->mode2_reset) 3557 ret = smu->ppt_funcs->mode2_reset(smu); 3558 3559 if (ret) 3560 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3561 3562 return ret; 3563 } 3564 3565 int smu_link_reset(struct smu_context *smu) 3566 { 3567 int ret = 0; 3568 3569 if (!smu->pm_enabled) 3570 return -EOPNOTSUPP; 3571 3572 if (smu->ppt_funcs->link_reset) 3573 ret = smu->ppt_funcs->link_reset(smu); 3574 3575 return ret; 3576 } 3577 3578 static int smu_enable_gfx_features(void *handle) 3579 { 3580 struct smu_context *smu = handle; 3581 int ret = 0; 3582 3583 if (!smu->pm_enabled) 3584 return -EOPNOTSUPP; 3585 3586 if (smu->ppt_funcs->enable_gfx_features) 3587 ret = smu->ppt_funcs->enable_gfx_features(smu); 3588 3589 if (ret) 3590 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3591 3592 return ret; 3593 } 3594 3595 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3596 struct pp_smu_nv_clock_table *max_clocks) 3597 { 3598 struct smu_context *smu = handle; 3599 int ret = 0; 3600 3601 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3602 return -EOPNOTSUPP; 3603 3604 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3605 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3606 3607 return ret; 3608 } 3609 3610 static int smu_get_uclk_dpm_states(void *handle, 3611 unsigned int *clock_values_in_khz, 3612 unsigned int *num_states) 3613 { 3614 struct smu_context *smu = handle; 3615 int ret = 0; 3616 3617 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3618 return -EOPNOTSUPP; 3619 3620 if (smu->ppt_funcs->get_uclk_dpm_states) 3621 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3622 3623 return ret; 3624 } 3625 3626 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3627 { 3628 struct smu_context *smu = handle; 3629 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3630 3631 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3632 return -EOPNOTSUPP; 3633 3634 if (smu->ppt_funcs->get_current_power_state) 3635 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3636 3637 return pm_state; 3638 } 3639 3640 static int smu_get_dpm_clock_table(void *handle, 3641 struct dpm_clocks *clock_table) 3642 { 3643 struct smu_context *smu = handle; 3644 int ret = 0; 3645 3646 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3647 return -EOPNOTSUPP; 3648 3649 if (smu->ppt_funcs->get_dpm_clock_table) 3650 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3651 3652 return ret; 3653 } 3654 3655 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3656 { 3657 struct smu_context *smu = handle; 3658 struct smu_table_context *smu_table = &smu->smu_table; 3659 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3660 struct smu_driver_table *gpu_metrics_table; 3661 3662 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3663 return -EOPNOTSUPP; 3664 3665 if (!smu->ppt_funcs->get_gpu_metrics) 3666 return -EOPNOTSUPP; 3667 3668 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; 3669 3670 /* If cached table is valid, return it */ 3671 if (smu_driver_table_is_valid(gpu_metrics_table)) { 3672 *table = gpu_metrics_table->cache.buffer; 3673 return gpu_metrics_table->cache.size; 3674 } 3675 3676 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3677 } 3678 3679 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3680 size_t size) 3681 { 3682 struct smu_context *smu = handle; 3683 3684 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3685 return -EOPNOTSUPP; 3686 3687 if (!smu->ppt_funcs->get_pm_metrics) 3688 return -EOPNOTSUPP; 3689 3690 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3691 } 3692 3693 static int smu_enable_mgpu_fan_boost(void *handle) 3694 { 3695 struct smu_context *smu = handle; 3696 int ret = 0; 3697 3698 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3699 return -EOPNOTSUPP; 3700 3701 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3702 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3703 3704 return ret; 3705 } 3706 3707 static int smu_gfx_state_change_set(void *handle, 3708 uint32_t state) 3709 { 3710 struct smu_context *smu = handle; 3711 int ret = 0; 3712 3713 if (smu->ppt_funcs->gfx_state_change_set) 3714 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3715 3716 return ret; 3717 } 3718 3719 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3720 { 3721 int ret = 0; 3722 3723 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3724 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3725 3726 return ret; 3727 } 3728 3729 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3730 { 3731 int ret = -EOPNOTSUPP; 3732 3733 if (smu->ppt_funcs && 3734 smu->ppt_funcs->get_ecc_info) 3735 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3736 3737 return ret; 3738 3739 } 3740 3741 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3742 { 3743 struct smu_context *smu = handle; 3744 struct smu_table_context *smu_table = &smu->smu_table; 3745 struct smu_table *memory_pool = &smu_table->memory_pool; 3746 3747 if (!addr || !size) 3748 return -EINVAL; 3749 3750 *addr = NULL; 3751 *size = 0; 3752 if (memory_pool->bo) { 3753 *addr = memory_pool->cpu_addr; 3754 *size = memory_pool->size; 3755 } 3756 3757 return 0; 3758 } 3759 3760 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3761 size_t *size) 3762 { 3763 size_t offset = *size; 3764 int level; 3765 3766 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3767 if (level == policy->current_level) 3768 offset += sysfs_emit_at(sysbuf, offset, 3769 "%d : %s*\n", level, 3770 policy->desc->get_desc(policy, level)); 3771 else 3772 offset += sysfs_emit_at(sysbuf, offset, 3773 "%d : %s\n", level, 3774 policy->desc->get_desc(policy, level)); 3775 } 3776 3777 *size = offset; 3778 } 3779 3780 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3781 enum pp_pm_policy p_type, char *sysbuf) 3782 { 3783 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3784 struct smu_dpm_policy_ctxt *policy_ctxt; 3785 struct smu_dpm_policy *dpm_policy; 3786 size_t offset = 0; 3787 3788 policy_ctxt = dpm_ctxt->dpm_policies; 3789 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3790 !policy_ctxt->policy_mask) 3791 return -EOPNOTSUPP; 3792 3793 if (p_type == PP_PM_POLICY_NONE) 3794 return -EINVAL; 3795 3796 dpm_policy = smu_get_pm_policy(smu, p_type); 3797 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3798 return -ENOENT; 3799 3800 if (!sysbuf) 3801 return -EINVAL; 3802 3803 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3804 3805 return offset; 3806 } 3807 3808 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3809 enum pp_pm_policy p_type) 3810 { 3811 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3812 struct smu_dpm_policy_ctxt *policy_ctxt; 3813 int i; 3814 3815 policy_ctxt = dpm_ctxt->dpm_policies; 3816 if (!policy_ctxt) 3817 return NULL; 3818 3819 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3820 if (policy_ctxt->policies[i].policy_type == p_type) 3821 return &policy_ctxt->policies[i]; 3822 } 3823 3824 return NULL; 3825 } 3826 3827 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3828 int level) 3829 { 3830 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3831 struct smu_dpm_policy *dpm_policy = NULL; 3832 struct smu_dpm_policy_ctxt *policy_ctxt; 3833 int ret = -EOPNOTSUPP; 3834 3835 policy_ctxt = dpm_ctxt->dpm_policies; 3836 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3837 !policy_ctxt->policy_mask) 3838 return ret; 3839 3840 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3841 return -EINVAL; 3842 3843 dpm_policy = smu_get_pm_policy(smu, p_type); 3844 3845 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3846 return ret; 3847 3848 if (dpm_policy->current_level == level) 3849 return 0; 3850 3851 ret = dpm_policy->set_policy(smu, level); 3852 3853 if (!ret) 3854 dpm_policy->current_level = level; 3855 3856 return ret; 3857 } 3858 3859 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3860 { 3861 struct smu_context *smu = handle; 3862 struct smu_table_context *smu_table = &smu->smu_table; 3863 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3864 enum smu_driver_table_id table_id; 3865 struct smu_driver_table *temp_table; 3866 3867 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3868 return -EOPNOTSUPP; 3869 3870 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3871 return -EOPNOTSUPP; 3872 3873 table_id = smu_metrics_get_temp_table_id(type); 3874 3875 if (table_id == SMU_DRIVER_TABLE_COUNT) 3876 return -EINVAL; 3877 3878 temp_table = &driver_tables[table_id]; 3879 3880 /* If the request is to get size alone, return the cached table size */ 3881 if (!table && temp_table->cache.size) 3882 return temp_table->cache.size; 3883 3884 if (smu_driver_table_is_valid(temp_table)) { 3885 memcpy(table, temp_table->cache.buffer, temp_table->cache.size); 3886 return temp_table->cache.size; 3887 } 3888 3889 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3890 } 3891 3892 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3893 { 3894 struct smu_context *smu = handle; 3895 bool ret = false; 3896 3897 if (!smu->pm_enabled) 3898 return false; 3899 3900 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3901 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3902 3903 return ret; 3904 } 3905 3906 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3907 { 3908 struct smu_context *smu = handle; 3909 3910 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3911 return -EOPNOTSUPP; 3912 3913 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3914 return -EOPNOTSUPP; 3915 3916 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3917 } 3918 3919 static const struct amd_pm_funcs swsmu_pm_funcs = { 3920 /* export for sysfs */ 3921 .set_fan_control_mode = smu_set_fan_control_mode, 3922 .get_fan_control_mode = smu_get_fan_control_mode, 3923 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3924 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3925 .force_clock_level = smu_force_ppclk_levels, 3926 .emit_clock_levels = smu_emit_ppclk_levels, 3927 .force_performance_level = smu_force_performance_level, 3928 .read_sensor = smu_read_sensor, 3929 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3930 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3931 .get_performance_level = smu_get_performance_level, 3932 .get_current_power_state = smu_get_current_power_state, 3933 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3934 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3935 .get_pp_num_states = smu_get_power_num_states, 3936 .get_pp_table = smu_sys_get_pp_table, 3937 .set_pp_table = smu_sys_set_pp_table, 3938 .switch_power_profile = smu_switch_power_profile, 3939 .pause_power_profile = smu_pause_power_profile, 3940 /* export to amdgpu */ 3941 .dispatch_tasks = smu_handle_dpm_task, 3942 .load_firmware = smu_load_microcode, 3943 .set_powergating_by_smu = smu_dpm_set_power_gate, 3944 .set_power_limit = smu_set_power_limit, 3945 .get_power_limit = smu_get_power_limit, 3946 .get_power_profile_mode = smu_get_power_profile_mode, 3947 .set_power_profile_mode = smu_set_power_profile_mode, 3948 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3949 .set_mp1_state = smu_set_mp1_state, 3950 .gfx_state_change_set = smu_gfx_state_change_set, 3951 /* export to DC */ 3952 .get_sclk = smu_get_sclk, 3953 .get_mclk = smu_get_mclk, 3954 .display_configuration_change = smu_display_configuration_change, 3955 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3956 .display_clock_voltage_request = smu_display_clock_voltage_request, 3957 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3958 .set_active_display_count = smu_set_display_count, 3959 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3960 .get_asic_baco_capability = smu_get_baco_capability, 3961 .set_asic_baco_state = smu_baco_set_state, 3962 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3963 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3964 .asic_reset_mode_2 = smu_mode2_reset, 3965 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3966 .set_df_cstate = smu_set_df_cstate, 3967 .set_xgmi_pstate = smu_set_xgmi_pstate, 3968 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3969 .get_pm_metrics = smu_sys_get_pm_metrics, 3970 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3971 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3972 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3973 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3974 .get_dpm_clock_table = smu_get_dpm_clock_table, 3975 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3976 .get_xcp_metrics = smu_sys_get_xcp_metrics, 3977 .get_temp_metrics = smu_sys_get_temp_metrics, 3978 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 3979 }; 3980 3981 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3982 uint64_t event_arg) 3983 { 3984 int ret = -EINVAL; 3985 3986 if (smu->ppt_funcs->wait_for_event) 3987 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3988 3989 return ret; 3990 } 3991 3992 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3993 { 3994 3995 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3996 return -EOPNOTSUPP; 3997 3998 /* Confirm the buffer allocated is of correct size */ 3999 if (size != smu->stb_context.stb_buf_size) 4000 return -EINVAL; 4001 4002 /* 4003 * No need to lock smu mutex as we access STB directly through MMIO 4004 * and not going through SMU messaging route (for now at least). 4005 * For registers access rely on implementation internal locking. 4006 */ 4007 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4008 } 4009 4010 #if defined(CONFIG_DEBUG_FS) 4011 4012 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4013 { 4014 struct amdgpu_device *adev = filp->f_inode->i_private; 4015 struct smu_context *smu = adev->powerplay.pp_handle; 4016 unsigned char *buf; 4017 int r; 4018 4019 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4020 if (!buf) 4021 return -ENOMEM; 4022 4023 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4024 if (r) 4025 goto out; 4026 4027 filp->private_data = buf; 4028 4029 return 0; 4030 4031 out: 4032 kvfree(buf); 4033 return r; 4034 } 4035 4036 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4037 loff_t *pos) 4038 { 4039 struct amdgpu_device *adev = filp->f_inode->i_private; 4040 struct smu_context *smu = adev->powerplay.pp_handle; 4041 4042 4043 if (!filp->private_data) 4044 return -EINVAL; 4045 4046 return simple_read_from_buffer(buf, 4047 size, 4048 pos, filp->private_data, 4049 smu->stb_context.stb_buf_size); 4050 } 4051 4052 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4053 { 4054 kvfree(filp->private_data); 4055 filp->private_data = NULL; 4056 4057 return 0; 4058 } 4059 4060 /* 4061 * We have to define not only read method but also 4062 * open and release because .read takes up to PAGE_SIZE 4063 * data each time so and so is invoked multiple times. 4064 * We allocate the STB buffer in .open and release it 4065 * in .release 4066 */ 4067 static const struct file_operations smu_stb_debugfs_fops = { 4068 .owner = THIS_MODULE, 4069 .open = smu_stb_debugfs_open, 4070 .read = smu_stb_debugfs_read, 4071 .release = smu_stb_debugfs_release, 4072 .llseek = default_llseek, 4073 }; 4074 4075 #endif 4076 4077 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4078 { 4079 #if defined(CONFIG_DEBUG_FS) 4080 4081 struct smu_context *smu = adev->powerplay.pp_handle; 4082 4083 if (!smu || (!smu->stb_context.stb_buf_size)) 4084 return; 4085 4086 debugfs_create_file_size("amdgpu_smu_stb_dump", 4087 S_IRUSR, 4088 adev_to_drm(adev)->primary->debugfs_root, 4089 adev, 4090 &smu_stb_debugfs_fops, 4091 smu->stb_context.stb_buf_size); 4092 #endif 4093 } 4094 4095 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4096 { 4097 int ret = 0; 4098 4099 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4100 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4101 4102 return ret; 4103 } 4104 4105 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4106 { 4107 int ret = 0; 4108 4109 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4110 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4111 4112 return ret; 4113 } 4114 4115 int smu_send_rma_reason(struct smu_context *smu) 4116 { 4117 int ret = 0; 4118 4119 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4120 ret = smu->ppt_funcs->send_rma_reason(smu); 4121 4122 return ret; 4123 } 4124 4125 /** 4126 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4127 * @smu: smu_context pointer 4128 * 4129 * This function checks if the SMU supports resetting the SDMA engine. 4130 * It returns true if supported, false otherwise. 4131 */ 4132 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4133 { 4134 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4135 } 4136 4137 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4138 { 4139 int ret = 0; 4140 4141 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4142 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4143 4144 return ret; 4145 } 4146 4147 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4148 { 4149 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4150 } 4151 4152 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4153 { 4154 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4155 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4156 4157 return 0; 4158 } 4159