1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27 #include <linux/power_supply.h>
28 #include <linux/reboot.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
33 #include "atom.h"
34 #include "arcturus_ppt.h"
35 #include "navi10_ppt.h"
36 #include "sienna_cichlid_ppt.h"
37 #include "renoir_ppt.h"
38 #include "vangogh_ppt.h"
39 #include "aldebaran_ppt.h"
40 #include "yellow_carp_ppt.h"
41 #include "cyan_skillfish_ppt.h"
42 #include "smu_v13_0_0_ppt.h"
43 #include "smu_v13_0_4_ppt.h"
44 #include "smu_v13_0_5_ppt.h"
45 #include "smu_v13_0_6_ppt.h"
46 #include "smu_v13_0_7_ppt.h"
47 #include "smu_v14_0_0_ppt.h"
48 #include "smu_v14_0_2_ppt.h"
49 #include "amd_pcie.h"
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 static const struct amd_pm_funcs swsmu_pm_funcs;
62 static int smu_force_smuclk_levels(struct smu_context *smu,
63 enum smu_clk_type clk_type,
64 uint32_t mask);
65 static int smu_handle_task(struct smu_context *smu,
66 enum amd_dpm_forced_level level,
67 enum amd_pp_task task_id);
68 static int smu_reset(struct smu_context *smu);
69 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
70 static int smu_set_fan_control_mode(void *handle, u32 value);
71 static int smu_set_power_limit(void *handle, uint32_t limit);
72 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
73 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
74 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
75 static void smu_power_profile_mode_get(struct smu_context *smu,
76 enum PP_SMC_POWER_PROFILE profile_mode);
77 static void smu_power_profile_mode_put(struct smu_context *smu,
78 enum PP_SMC_POWER_PROFILE profile_mode);
79
smu_sys_get_pp_feature_mask(void * handle,char * buf)80 static int smu_sys_get_pp_feature_mask(void *handle,
81 char *buf)
82 {
83 struct smu_context *smu = handle;
84
85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
86 return -EOPNOTSUPP;
87
88 return smu_get_pp_feature_mask(smu, buf);
89 }
90
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)91 static int smu_sys_set_pp_feature_mask(void *handle,
92 uint64_t new_mask)
93 {
94 struct smu_context *smu = handle;
95
96 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
97 return -EOPNOTSUPP;
98
99 return smu_set_pp_feature_mask(smu, new_mask);
100 }
101
smu_set_residency_gfxoff(struct smu_context * smu,bool value)102 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
103 {
104 if (!smu->ppt_funcs->set_gfx_off_residency)
105 return -EINVAL;
106
107 return smu_set_gfx_off_residency(smu, value);
108 }
109
smu_get_residency_gfxoff(struct smu_context * smu,u32 * value)110 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
111 {
112 if (!smu->ppt_funcs->get_gfx_off_residency)
113 return -EINVAL;
114
115 return smu_get_gfx_off_residency(smu, value);
116 }
117
smu_get_entrycount_gfxoff(struct smu_context * smu,u64 * value)118 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
119 {
120 if (!smu->ppt_funcs->get_gfx_off_entrycount)
121 return -EINVAL;
122
123 return smu_get_gfx_off_entrycount(smu, value);
124 }
125
smu_get_status_gfxoff(struct smu_context * smu,uint32_t * value)126 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
127 {
128 if (!smu->ppt_funcs->get_gfx_off_status)
129 return -EINVAL;
130
131 *value = smu_get_gfx_off_status(smu);
132
133 return 0;
134 }
135
smu_set_soft_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)136 int smu_set_soft_freq_range(struct smu_context *smu,
137 enum smu_clk_type clk_type,
138 uint32_t min,
139 uint32_t max)
140 {
141 int ret = 0;
142
143 if (smu->ppt_funcs->set_soft_freq_limited_range)
144 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
145 clk_type,
146 min,
147 max,
148 false);
149
150 return ret;
151 }
152
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)153 int smu_get_dpm_freq_range(struct smu_context *smu,
154 enum smu_clk_type clk_type,
155 uint32_t *min,
156 uint32_t *max)
157 {
158 int ret = -ENOTSUPP;
159
160 if (!min && !max)
161 return -EINVAL;
162
163 if (smu->ppt_funcs->get_dpm_ultimate_freq)
164 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
165 clk_type,
166 min,
167 max);
168
169 return ret;
170 }
171
smu_set_gfx_power_up_by_imu(struct smu_context * smu)172 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
173 {
174 int ret = 0;
175 struct amdgpu_device *adev = smu->adev;
176
177 if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
178 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
179 if (ret)
180 dev_err(adev->dev, "Failed to enable gfx imu!\n");
181 }
182 return ret;
183 }
184
smu_get_mclk(void * handle,bool low)185 static u32 smu_get_mclk(void *handle, bool low)
186 {
187 struct smu_context *smu = handle;
188 uint32_t clk_freq;
189 int ret = 0;
190
191 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
192 low ? &clk_freq : NULL,
193 !low ? &clk_freq : NULL);
194 if (ret)
195 return 0;
196 return clk_freq * 100;
197 }
198
smu_get_sclk(void * handle,bool low)199 static u32 smu_get_sclk(void *handle, bool low)
200 {
201 struct smu_context *smu = handle;
202 uint32_t clk_freq;
203 int ret = 0;
204
205 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
206 low ? &clk_freq : NULL,
207 !low ? &clk_freq : NULL);
208 if (ret)
209 return 0;
210 return clk_freq * 100;
211 }
212
smu_set_gfx_imu_enable(struct smu_context * smu)213 static int smu_set_gfx_imu_enable(struct smu_context *smu)
214 {
215 struct amdgpu_device *adev = smu->adev;
216
217 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
218 return 0;
219
220 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
221 return 0;
222
223 return smu_set_gfx_power_up_by_imu(smu);
224 }
225
is_vcn_enabled(struct amdgpu_device * adev)226 static bool is_vcn_enabled(struct amdgpu_device *adev)
227 {
228 int i;
229
230 for (i = 0; i < adev->num_ip_blocks; i++) {
231 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
232 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) &&
233 !adev->ip_blocks[i].status.valid)
234 return false;
235 }
236
237 return true;
238 }
239
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)240 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
241 bool enable,
242 int inst)
243 {
244 struct smu_power_context *smu_power = &smu->smu_power;
245 struct smu_power_gate *power_gate = &smu_power->power_gate;
246 int ret = 0;
247
248 /*
249 * don't poweron vcn/jpeg when they are skipped.
250 */
251 if (!is_vcn_enabled(smu->adev))
252 return 0;
253
254 if (!smu->ppt_funcs->dpm_set_vcn_enable)
255 return 0;
256
257 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
258 return 0;
259
260 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
261 if (!ret)
262 atomic_set(&power_gate->vcn_gated[inst], !enable);
263
264 return ret;
265 }
266
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)267 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
268 bool enable)
269 {
270 struct smu_power_context *smu_power = &smu->smu_power;
271 struct smu_power_gate *power_gate = &smu_power->power_gate;
272 int ret = 0;
273
274 if (!is_vcn_enabled(smu->adev))
275 return 0;
276
277 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
278 return 0;
279
280 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
281 return 0;
282
283 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
284 if (!ret)
285 atomic_set(&power_gate->jpeg_gated, !enable);
286
287 return ret;
288 }
289
smu_dpm_set_vpe_enable(struct smu_context * smu,bool enable)290 static int smu_dpm_set_vpe_enable(struct smu_context *smu,
291 bool enable)
292 {
293 struct smu_power_context *smu_power = &smu->smu_power;
294 struct smu_power_gate *power_gate = &smu_power->power_gate;
295 int ret = 0;
296
297 if (!smu->ppt_funcs->dpm_set_vpe_enable)
298 return 0;
299
300 if (atomic_read(&power_gate->vpe_gated) ^ enable)
301 return 0;
302
303 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable);
304 if (!ret)
305 atomic_set(&power_gate->vpe_gated, !enable);
306
307 return ret;
308 }
309
smu_dpm_set_umsch_mm_enable(struct smu_context * smu,bool enable)310 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu,
311 bool enable)
312 {
313 struct smu_power_context *smu_power = &smu->smu_power;
314 struct smu_power_gate *power_gate = &smu_power->power_gate;
315 int ret = 0;
316
317 if (!smu->adev->enable_umsch_mm)
318 return 0;
319
320 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable)
321 return 0;
322
323 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable)
324 return 0;
325
326 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable);
327 if (!ret)
328 atomic_set(&power_gate->umsch_mm_gated, !enable);
329
330 return ret;
331 }
332
smu_set_mall_enable(struct smu_context * smu)333 static int smu_set_mall_enable(struct smu_context *smu)
334 {
335 int ret = 0;
336
337 if (!smu->ppt_funcs->set_mall_enable)
338 return 0;
339
340 ret = smu->ppt_funcs->set_mall_enable(smu);
341
342 return ret;
343 }
344
345 /**
346 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
347 *
348 * @handle: smu_context pointer
349 * @block_type: the IP block to power gate/ungate
350 * @gate: to power gate if true, ungate otherwise
351 * @inst: the instance of the IP block to power gate/ungate
352 *
353 * This API uses no smu->mutex lock protection due to:
354 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
355 * This is guarded to be race condition free by the caller.
356 * 2. Or get called on user setting request of power_dpm_force_performance_level.
357 * Under this case, the smu->mutex lock protection is already enforced on
358 * the parent API smu_force_performance_level of the call path.
359 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate,int inst)360 static int smu_dpm_set_power_gate(void *handle,
361 uint32_t block_type,
362 bool gate,
363 int inst)
364 {
365 struct smu_context *smu = handle;
366 int ret = 0;
367
368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
369 dev_WARN(smu->adev->dev,
370 "SMU uninitialized but power %s requested for %u!\n",
371 gate ? "gate" : "ungate", block_type);
372 return -EOPNOTSUPP;
373 }
374
375 switch (block_type) {
376 /*
377 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
378 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
379 */
380 case AMD_IP_BLOCK_TYPE_UVD:
381 case AMD_IP_BLOCK_TYPE_VCN:
382 ret = smu_dpm_set_vcn_enable(smu, !gate, inst);
383 if (ret)
384 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
385 gate ? "gate" : "ungate", inst);
386 break;
387 case AMD_IP_BLOCK_TYPE_GFX:
388 ret = smu_gfx_off_control(smu, gate);
389 if (ret)
390 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
391 gate ? "enable" : "disable");
392 break;
393 case AMD_IP_BLOCK_TYPE_SDMA:
394 ret = smu_powergate_sdma(smu, gate);
395 if (ret)
396 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
397 gate ? "gate" : "ungate");
398 break;
399 case AMD_IP_BLOCK_TYPE_JPEG:
400 ret = smu_dpm_set_jpeg_enable(smu, !gate);
401 if (ret)
402 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
403 gate ? "gate" : "ungate");
404 break;
405 case AMD_IP_BLOCK_TYPE_VPE:
406 ret = smu_dpm_set_vpe_enable(smu, !gate);
407 if (ret)
408 dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
409 gate ? "gate" : "ungate");
410 break;
411 default:
412 dev_err(smu->adev->dev, "Unsupported block type!\n");
413 return -EINVAL;
414 }
415
416 return ret;
417 }
418
419 /**
420 * smu_set_user_clk_dependencies - set user profile clock dependencies
421 *
422 * @smu: smu_context pointer
423 * @clk: enum smu_clk_type type
424 *
425 * Enable/Disable the clock dependency for the @clk type.
426 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)427 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
428 {
429 if (smu->adev->in_suspend)
430 return;
431
432 if (clk == SMU_MCLK) {
433 smu->user_dpm_profile.clk_dependency = 0;
434 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
435 } else if (clk == SMU_FCLK) {
436 /* MCLK takes precedence over FCLK */
437 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
438 return;
439
440 smu->user_dpm_profile.clk_dependency = 0;
441 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
442 } else if (clk == SMU_SOCCLK) {
443 /* MCLK takes precedence over SOCCLK */
444 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
445 return;
446
447 smu->user_dpm_profile.clk_dependency = 0;
448 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
449 } else
450 /* Add clk dependencies here, if any */
451 return;
452 }
453
454 /**
455 * smu_restore_dpm_user_profile - reinstate user dpm profile
456 *
457 * @smu: smu_context pointer
458 *
459 * Restore the saved user power configurations include power limit,
460 * clock frequencies, fan control mode and fan speed.
461 */
smu_restore_dpm_user_profile(struct smu_context * smu)462 static void smu_restore_dpm_user_profile(struct smu_context *smu)
463 {
464 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
465 int ret = 0;
466
467 if (!smu->adev->in_suspend)
468 return;
469
470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
471 return;
472
473 /* Enable restore flag */
474 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
475
476 /* set the user dpm power limit */
477 if (smu->user_dpm_profile.power_limit) {
478 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
479 if (ret)
480 dev_err(smu->adev->dev, "Failed to set power limit value\n");
481 }
482
483 /* set the user dpm clock configurations */
484 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
485 enum smu_clk_type clk_type;
486
487 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
488 /*
489 * Iterate over smu clk type and force the saved user clk
490 * configs, skip if clock dependency is enabled
491 */
492 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
493 smu->user_dpm_profile.clk_mask[clk_type]) {
494 ret = smu_force_smuclk_levels(smu, clk_type,
495 smu->user_dpm_profile.clk_mask[clk_type]);
496 if (ret)
497 dev_err(smu->adev->dev,
498 "Failed to set clock type = %d\n", clk_type);
499 }
500 }
501 }
502
503 /* set the user dpm fan configurations */
504 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
505 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
506 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
507 if (ret != -EOPNOTSUPP) {
508 smu->user_dpm_profile.fan_speed_pwm = 0;
509 smu->user_dpm_profile.fan_speed_rpm = 0;
510 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
511 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
512 }
513
514 if (smu->user_dpm_profile.fan_speed_pwm) {
515 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
516 if (ret != -EOPNOTSUPP)
517 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
518 }
519
520 if (smu->user_dpm_profile.fan_speed_rpm) {
521 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
522 if (ret != -EOPNOTSUPP)
523 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
524 }
525 }
526
527 /* Restore user customized OD settings */
528 if (smu->user_dpm_profile.user_od) {
529 if (smu->ppt_funcs->restore_user_od_settings) {
530 ret = smu->ppt_funcs->restore_user_od_settings(smu);
531 if (ret)
532 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
533 }
534 }
535
536 /* Disable restore flag */
537 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
538 }
539
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)540 static int smu_get_power_num_states(void *handle,
541 struct pp_states_info *state_info)
542 {
543 if (!state_info)
544 return -EINVAL;
545
546 /* not support power state */
547 memset(state_info, 0, sizeof(struct pp_states_info));
548 state_info->nums = 1;
549 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
550
551 return 0;
552 }
553
is_support_sw_smu(struct amdgpu_device * adev)554 bool is_support_sw_smu(struct amdgpu_device *adev)
555 {
556 /* vega20 is 11.0.2, but it's supported via the powerplay code */
557 if (adev->asic_type == CHIP_VEGA20)
558 return false;
559
560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) &&
561 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC))
562 return true;
563
564 return false;
565 }
566
is_support_cclk_dpm(struct amdgpu_device * adev)567 bool is_support_cclk_dpm(struct amdgpu_device *adev)
568 {
569 struct smu_context *smu = adev->powerplay.pp_handle;
570
571 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
572 return false;
573
574 return true;
575 }
576
577
smu_sys_get_pp_table(void * handle,char ** table)578 static int smu_sys_get_pp_table(void *handle,
579 char **table)
580 {
581 struct smu_context *smu = handle;
582 struct smu_table_context *smu_table = &smu->smu_table;
583
584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
585 return -EOPNOTSUPP;
586
587 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
588 return -EINVAL;
589
590 if (smu_table->hardcode_pptable)
591 *table = smu_table->hardcode_pptable;
592 else
593 *table = smu_table->power_play_table;
594
595 return smu_table->power_play_table_size;
596 }
597
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)598 static int smu_sys_set_pp_table(void *handle,
599 const char *buf,
600 size_t size)
601 {
602 struct smu_context *smu = handle;
603 struct smu_table_context *smu_table = &smu->smu_table;
604 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
605 int ret = 0;
606
607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
608 return -EOPNOTSUPP;
609
610 if (header->usStructureSize != size) {
611 dev_err(smu->adev->dev, "pp table size not matched !\n");
612 return -EIO;
613 }
614
615 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) {
616 kfree(smu_table->hardcode_pptable);
617 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
618 if (!smu_table->hardcode_pptable)
619 return -ENOMEM;
620 }
621
622 memcpy(smu_table->hardcode_pptable, buf, size);
623 smu_table->power_play_table = smu_table->hardcode_pptable;
624 smu_table->power_play_table_size = size;
625
626 /*
627 * Special hw_fini action(for Navi1x, the DPMs disablement will be
628 * skipped) may be needed for custom pptable uploading.
629 */
630 smu->uploading_custom_pp_table = true;
631
632 ret = smu_reset(smu);
633 if (ret)
634 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
635
636 smu->uploading_custom_pp_table = false;
637
638 return ret;
639 }
640
smu_get_driver_allowed_feature_mask(struct smu_context * smu)641 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
642 {
643 struct smu_feature *feature = &smu->smu_feature;
644 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
645 int ret = 0;
646
647 /*
648 * With SCPM enabled, the allowed featuremasks setting(via
649 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
650 * That means there is no way to let PMFW knows the settings below.
651 * Thus, we just assume all the features are allowed under
652 * such scenario.
653 */
654 if (smu->adev->scpm_enabled) {
655 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
656 return 0;
657 }
658
659 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
660
661 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
662 SMU_FEATURE_MAX/32);
663 if (ret)
664 return ret;
665
666 bitmap_or(feature->allowed, feature->allowed,
667 (unsigned long *)allowed_feature_mask,
668 feature->feature_num);
669
670 return ret;
671 }
672
smu_set_funcs(struct amdgpu_device * adev)673 static int smu_set_funcs(struct amdgpu_device *adev)
674 {
675 struct smu_context *smu = adev->powerplay.pp_handle;
676
677 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
678 smu->od_enabled = true;
679
680 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
681 case IP_VERSION(11, 0, 0):
682 case IP_VERSION(11, 0, 5):
683 case IP_VERSION(11, 0, 9):
684 navi10_set_ppt_funcs(smu);
685 break;
686 case IP_VERSION(11, 0, 7):
687 case IP_VERSION(11, 0, 11):
688 case IP_VERSION(11, 0, 12):
689 case IP_VERSION(11, 0, 13):
690 sienna_cichlid_set_ppt_funcs(smu);
691 break;
692 case IP_VERSION(12, 0, 0):
693 case IP_VERSION(12, 0, 1):
694 renoir_set_ppt_funcs(smu);
695 break;
696 case IP_VERSION(11, 5, 0):
697 vangogh_set_ppt_funcs(smu);
698 break;
699 case IP_VERSION(13, 0, 1):
700 case IP_VERSION(13, 0, 3):
701 case IP_VERSION(13, 0, 8):
702 yellow_carp_set_ppt_funcs(smu);
703 break;
704 case IP_VERSION(13, 0, 4):
705 case IP_VERSION(13, 0, 11):
706 smu_v13_0_4_set_ppt_funcs(smu);
707 break;
708 case IP_VERSION(13, 0, 5):
709 smu_v13_0_5_set_ppt_funcs(smu);
710 break;
711 case IP_VERSION(11, 0, 8):
712 cyan_skillfish_set_ppt_funcs(smu);
713 break;
714 case IP_VERSION(11, 0, 2):
715 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
716 arcturus_set_ppt_funcs(smu);
717 /* OD is not supported on Arcturus */
718 smu->od_enabled = false;
719 break;
720 case IP_VERSION(13, 0, 2):
721 aldebaran_set_ppt_funcs(smu);
722 /* Enable pp_od_clk_voltage node */
723 smu->od_enabled = true;
724 break;
725 case IP_VERSION(13, 0, 0):
726 case IP_VERSION(13, 0, 10):
727 smu_v13_0_0_set_ppt_funcs(smu);
728 break;
729 case IP_VERSION(13, 0, 6):
730 case IP_VERSION(13, 0, 14):
731 case IP_VERSION(13, 0, 12):
732 smu_v13_0_6_set_ppt_funcs(smu);
733 /* Enable pp_od_clk_voltage node */
734 smu->od_enabled = true;
735 break;
736 case IP_VERSION(13, 0, 7):
737 smu_v13_0_7_set_ppt_funcs(smu);
738 break;
739 case IP_VERSION(14, 0, 0):
740 case IP_VERSION(14, 0, 1):
741 case IP_VERSION(14, 0, 4):
742 smu_v14_0_0_set_ppt_funcs(smu);
743 break;
744 case IP_VERSION(14, 0, 2):
745 case IP_VERSION(14, 0, 3):
746 smu_v14_0_2_set_ppt_funcs(smu);
747 break;
748 default:
749 return -EINVAL;
750 }
751
752 return 0;
753 }
754
smu_early_init(struct amdgpu_ip_block * ip_block)755 static int smu_early_init(struct amdgpu_ip_block *ip_block)
756 {
757 struct amdgpu_device *adev = ip_block->adev;
758 struct smu_context *smu;
759 int r;
760
761 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
762 if (!smu)
763 return -ENOMEM;
764
765 smu->adev = adev;
766 smu->pm_enabled = !!amdgpu_dpm;
767 smu->is_apu = false;
768 smu->smu_baco.state = SMU_BACO_STATE_NONE;
769 smu->smu_baco.platform_support = false;
770 smu->smu_baco.maco_support = false;
771 smu->user_dpm_profile.fan_mode = -1;
772 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN;
773
774 mutex_init(&smu->message_lock);
775
776 adev->powerplay.pp_handle = smu;
777 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
778
779 r = smu_set_funcs(adev);
780 if (r)
781 return r;
782 return smu_init_microcode(smu);
783 }
784
smu_set_default_dpm_table(struct smu_context * smu)785 static int smu_set_default_dpm_table(struct smu_context *smu)
786 {
787 struct amdgpu_device *adev = smu->adev;
788 struct smu_power_context *smu_power = &smu->smu_power;
789 struct smu_power_gate *power_gate = &smu_power->power_gate;
790 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i;
791 int ret = 0;
792
793 if (!smu->ppt_funcs->set_default_dpm_table)
794 return 0;
795
796 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
797 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
798 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]);
799 }
800 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
801 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
802
803 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
804 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
805 ret = smu_dpm_set_vcn_enable(smu, true, i);
806 if (ret)
807 return ret;
808 }
809 }
810
811 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
812 ret = smu_dpm_set_jpeg_enable(smu, true);
813 if (ret)
814 goto err_out;
815 }
816
817 ret = smu->ppt_funcs->set_default_dpm_table(smu);
818 if (ret)
819 dev_err(smu->adev->dev,
820 "Failed to setup default dpm clock tables!\n");
821
822 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
823 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
824 err_out:
825 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
826 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
827 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i);
828 }
829
830 return ret;
831 }
832
smu_apply_default_config_table_settings(struct smu_context * smu)833 static int smu_apply_default_config_table_settings(struct smu_context *smu)
834 {
835 struct amdgpu_device *adev = smu->adev;
836 int ret = 0;
837
838 ret = smu_get_default_config_table_settings(smu,
839 &adev->pm.config_table);
840 if (ret)
841 return ret;
842
843 return smu_set_config_table(smu, &adev->pm.config_table);
844 }
845
smu_late_init(struct amdgpu_ip_block * ip_block)846 static int smu_late_init(struct amdgpu_ip_block *ip_block)
847 {
848 struct amdgpu_device *adev = ip_block->adev;
849 struct smu_context *smu = adev->powerplay.pp_handle;
850 int ret = 0;
851
852 smu_set_fine_grain_gfx_freq_parameters(smu);
853
854 if (!smu->pm_enabled)
855 return 0;
856
857 ret = smu_post_init(smu);
858 if (ret) {
859 dev_err(adev->dev, "Failed to post smu init!\n");
860 return ret;
861 }
862
863 /*
864 * Explicitly notify PMFW the power mode the system in. Since
865 * the PMFW may boot the ASIC with a different mode.
866 * For those supporting ACDC switch via gpio, PMFW will
867 * handle the switch automatically. Driver involvement
868 * is unnecessary.
869 */
870 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
871 smu_set_ac_dc(smu);
872
873 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) ||
874 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3)))
875 return 0;
876
877 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
878 ret = smu_set_default_od_settings(smu);
879 if (ret) {
880 dev_err(adev->dev, "Failed to setup default OD settings!\n");
881 return ret;
882 }
883 }
884
885 ret = smu_populate_umd_state_clk(smu);
886 if (ret) {
887 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
888 return ret;
889 }
890
891 ret = smu_get_asic_power_limits(smu,
892 &smu->current_power_limit,
893 &smu->default_power_limit,
894 &smu->max_power_limit,
895 &smu->min_power_limit);
896 if (ret) {
897 dev_err(adev->dev, "Failed to get asic power limits!\n");
898 return ret;
899 }
900
901 if (!amdgpu_sriov_vf(adev))
902 smu_get_unique_id(smu);
903
904 smu_get_fan_parameters(smu);
905
906 smu_handle_task(smu,
907 smu->smu_dpm.dpm_level,
908 AMD_PP_TASK_COMPLETE_INIT);
909
910 ret = smu_apply_default_config_table_settings(smu);
911 if (ret && (ret != -EOPNOTSUPP)) {
912 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
913 return ret;
914 }
915
916 smu_restore_dpm_user_profile(smu);
917
918 return 0;
919 }
920
smu_init_fb_allocations(struct smu_context * smu)921 static int smu_init_fb_allocations(struct smu_context *smu)
922 {
923 struct amdgpu_device *adev = smu->adev;
924 struct smu_table_context *smu_table = &smu->smu_table;
925 struct smu_table *tables = smu_table->tables;
926 struct smu_table *driver_table = &(smu_table->driver_table);
927 uint32_t max_table_size = 0;
928 int ret, i;
929
930 /* VRAM allocation for tool table */
931 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
932 ret = amdgpu_bo_create_kernel(adev,
933 tables[SMU_TABLE_PMSTATUSLOG].size,
934 tables[SMU_TABLE_PMSTATUSLOG].align,
935 tables[SMU_TABLE_PMSTATUSLOG].domain,
936 &tables[SMU_TABLE_PMSTATUSLOG].bo,
937 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
938 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
939 if (ret) {
940 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
941 return ret;
942 }
943 }
944
945 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT;
946 /* VRAM allocation for driver table */
947 for (i = 0; i < SMU_TABLE_COUNT; i++) {
948 if (tables[i].size == 0)
949 continue;
950
951 /* If one of the tables has VRAM domain restriction, keep it in
952 * VRAM
953 */
954 if ((tables[i].domain &
955 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) ==
956 AMDGPU_GEM_DOMAIN_VRAM)
957 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
958
959 if (i == SMU_TABLE_PMSTATUSLOG)
960 continue;
961
962 if (max_table_size < tables[i].size)
963 max_table_size = tables[i].size;
964 }
965
966 driver_table->size = max_table_size;
967 driver_table->align = PAGE_SIZE;
968
969 ret = amdgpu_bo_create_kernel(adev,
970 driver_table->size,
971 driver_table->align,
972 driver_table->domain,
973 &driver_table->bo,
974 &driver_table->mc_address,
975 &driver_table->cpu_addr);
976 if (ret) {
977 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
978 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
979 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
980 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
981 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
982 }
983
984 return ret;
985 }
986
smu_fini_fb_allocations(struct smu_context * smu)987 static int smu_fini_fb_allocations(struct smu_context *smu)
988 {
989 struct smu_table_context *smu_table = &smu->smu_table;
990 struct smu_table *tables = smu_table->tables;
991 struct smu_table *driver_table = &(smu_table->driver_table);
992
993 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
994 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
995 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
996 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
997
998 amdgpu_bo_free_kernel(&driver_table->bo,
999 &driver_table->mc_address,
1000 &driver_table->cpu_addr);
1001
1002 return 0;
1003 }
1004
1005 /**
1006 * smu_alloc_memory_pool - allocate memory pool in the system memory
1007 *
1008 * @smu: amdgpu_device pointer
1009 *
1010 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1011 * and DramLogSetDramAddr can notify it changed.
1012 *
1013 * Returns 0 on success, error on failure.
1014 */
smu_alloc_memory_pool(struct smu_context * smu)1015 static int smu_alloc_memory_pool(struct smu_context *smu)
1016 {
1017 struct amdgpu_device *adev = smu->adev;
1018 struct smu_table_context *smu_table = &smu->smu_table;
1019 struct smu_table *memory_pool = &smu_table->memory_pool;
1020 uint64_t pool_size = smu->pool_size;
1021 int ret = 0;
1022
1023 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1024 return ret;
1025
1026 memory_pool->size = pool_size;
1027 memory_pool->align = PAGE_SIZE;
1028 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
1029
1030 switch (pool_size) {
1031 case SMU_MEMORY_POOL_SIZE_256_MB:
1032 case SMU_MEMORY_POOL_SIZE_512_MB:
1033 case SMU_MEMORY_POOL_SIZE_1_GB:
1034 case SMU_MEMORY_POOL_SIZE_2_GB:
1035 ret = amdgpu_bo_create_kernel(adev,
1036 memory_pool->size,
1037 memory_pool->align,
1038 memory_pool->domain,
1039 &memory_pool->bo,
1040 &memory_pool->mc_address,
1041 &memory_pool->cpu_addr);
1042 if (ret)
1043 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
1044 break;
1045 default:
1046 break;
1047 }
1048
1049 return ret;
1050 }
1051
smu_free_memory_pool(struct smu_context * smu)1052 static int smu_free_memory_pool(struct smu_context *smu)
1053 {
1054 struct smu_table_context *smu_table = &smu->smu_table;
1055 struct smu_table *memory_pool = &smu_table->memory_pool;
1056
1057 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1058 return 0;
1059
1060 amdgpu_bo_free_kernel(&memory_pool->bo,
1061 &memory_pool->mc_address,
1062 &memory_pool->cpu_addr);
1063
1064 memset(memory_pool, 0, sizeof(struct smu_table));
1065
1066 return 0;
1067 }
1068
smu_alloc_dummy_read_table(struct smu_context * smu)1069 static int smu_alloc_dummy_read_table(struct smu_context *smu)
1070 {
1071 struct smu_table_context *smu_table = &smu->smu_table;
1072 struct smu_table *dummy_read_1_table =
1073 &smu_table->dummy_read_1_table;
1074 struct amdgpu_device *adev = smu->adev;
1075 int ret = 0;
1076
1077 if (!dummy_read_1_table->size)
1078 return 0;
1079
1080 ret = amdgpu_bo_create_kernel(adev,
1081 dummy_read_1_table->size,
1082 dummy_read_1_table->align,
1083 dummy_read_1_table->domain,
1084 &dummy_read_1_table->bo,
1085 &dummy_read_1_table->mc_address,
1086 &dummy_read_1_table->cpu_addr);
1087 if (ret)
1088 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
1089
1090 return ret;
1091 }
1092
smu_free_dummy_read_table(struct smu_context * smu)1093 static void smu_free_dummy_read_table(struct smu_context *smu)
1094 {
1095 struct smu_table_context *smu_table = &smu->smu_table;
1096 struct smu_table *dummy_read_1_table =
1097 &smu_table->dummy_read_1_table;
1098
1099
1100 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
1101 &dummy_read_1_table->mc_address,
1102 &dummy_read_1_table->cpu_addr);
1103
1104 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
1105 }
1106
smu_smc_table_sw_init(struct smu_context * smu)1107 static int smu_smc_table_sw_init(struct smu_context *smu)
1108 {
1109 int ret;
1110
1111 /**
1112 * Create smu_table structure, and init smc tables such as
1113 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
1114 */
1115 ret = smu_init_smc_tables(smu);
1116 if (ret) {
1117 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
1118 return ret;
1119 }
1120
1121 /**
1122 * Create smu_power_context structure, and allocate smu_dpm_context and
1123 * context size to fill the smu_power_context data.
1124 */
1125 ret = smu_init_power(smu);
1126 if (ret) {
1127 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1128 return ret;
1129 }
1130
1131 /*
1132 * allocate vram bos to store smc table contents.
1133 */
1134 ret = smu_init_fb_allocations(smu);
1135 if (ret)
1136 return ret;
1137
1138 ret = smu_alloc_memory_pool(smu);
1139 if (ret)
1140 return ret;
1141
1142 ret = smu_alloc_dummy_read_table(smu);
1143 if (ret)
1144 return ret;
1145
1146 ret = smu_i2c_init(smu);
1147 if (ret)
1148 return ret;
1149
1150 return 0;
1151 }
1152
smu_smc_table_sw_fini(struct smu_context * smu)1153 static int smu_smc_table_sw_fini(struct smu_context *smu)
1154 {
1155 int ret;
1156
1157 smu_i2c_fini(smu);
1158
1159 smu_free_dummy_read_table(smu);
1160
1161 ret = smu_free_memory_pool(smu);
1162 if (ret)
1163 return ret;
1164
1165 ret = smu_fini_fb_allocations(smu);
1166 if (ret)
1167 return ret;
1168
1169 ret = smu_fini_power(smu);
1170 if (ret) {
1171 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1172 return ret;
1173 }
1174
1175 ret = smu_fini_smc_tables(smu);
1176 if (ret) {
1177 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1178 return ret;
1179 }
1180
1181 return 0;
1182 }
1183
smu_throttling_logging_work_fn(struct work_struct * work)1184 static void smu_throttling_logging_work_fn(struct work_struct *work)
1185 {
1186 struct smu_context *smu = container_of(work, struct smu_context,
1187 throttling_logging_work);
1188
1189 smu_log_thermal_throttling(smu);
1190 }
1191
smu_interrupt_work_fn(struct work_struct * work)1192 static void smu_interrupt_work_fn(struct work_struct *work)
1193 {
1194 struct smu_context *smu = container_of(work, struct smu_context,
1195 interrupt_work);
1196
1197 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1198 smu->ppt_funcs->interrupt_work(smu);
1199 }
1200
smu_swctf_delayed_work_handler(struct work_struct * work)1201 static void smu_swctf_delayed_work_handler(struct work_struct *work)
1202 {
1203 struct smu_context *smu =
1204 container_of(work, struct smu_context, swctf_delayed_work.work);
1205 struct smu_temperature_range *range =
1206 &smu->thermal_range;
1207 struct amdgpu_device *adev = smu->adev;
1208 uint32_t hotspot_tmp, size;
1209
1210 /*
1211 * If the hotspot temperature is confirmed as below SW CTF setting point
1212 * after the delay enforced, nothing will be done.
1213 * Otherwise, a graceful shutdown will be performed to prevent further damage.
1214 */
1215 if (range->software_shutdown_temp &&
1216 smu->ppt_funcs->read_sensor &&
1217 !smu->ppt_funcs->read_sensor(smu,
1218 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1219 &hotspot_tmp,
1220 &size) &&
1221 hotspot_tmp / 1000 < range->software_shutdown_temp)
1222 return;
1223
1224 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1225 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1226 orderly_poweroff(true);
1227 }
1228
smu_init_xgmi_plpd_mode(struct smu_context * smu)1229 static void smu_init_xgmi_plpd_mode(struct smu_context *smu)
1230 {
1231 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm);
1232 struct smu_dpm_policy_ctxt *policy_ctxt;
1233 struct smu_dpm_policy *policy;
1234
1235 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD);
1236 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1237 if (policy)
1238 policy->current_level = XGMI_PLPD_DEFAULT;
1239 return;
1240 }
1241
1242 /* PMFW put PLPD into default policy after enabling the feature */
1243 if (smu_feature_is_enabled(smu,
1244 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) {
1245 if (policy)
1246 policy->current_level = XGMI_PLPD_DEFAULT;
1247 } else {
1248 policy_ctxt = dpm_ctxt->dpm_policies;
1249 if (policy_ctxt)
1250 policy_ctxt->policy_mask &=
1251 ~BIT(PP_PM_POLICY_XGMI_PLPD);
1252 }
1253 }
1254
smu_is_workload_profile_available(struct smu_context * smu,u32 profile)1255 static bool smu_is_workload_profile_available(struct smu_context *smu,
1256 u32 profile)
1257 {
1258 if (profile >= PP_SMC_POWER_PROFILE_COUNT)
1259 return false;
1260 return smu->workload_map && smu->workload_map[profile].valid_mapping;
1261 }
1262
smu_init_power_profile(struct smu_context * smu)1263 static void smu_init_power_profile(struct smu_context *smu)
1264 {
1265 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) {
1266 if (smu->is_apu ||
1267 !smu_is_workload_profile_available(
1268 smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D))
1269 smu->power_profile_mode =
1270 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1271 else
1272 smu->power_profile_mode =
1273 PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1274 }
1275 smu_power_profile_mode_get(smu, smu->power_profile_mode);
1276 }
1277
smu_sw_init(struct amdgpu_ip_block * ip_block)1278 static int smu_sw_init(struct amdgpu_ip_block *ip_block)
1279 {
1280 struct amdgpu_device *adev = ip_block->adev;
1281 struct smu_context *smu = adev->powerplay.pp_handle;
1282 int i, ret;
1283
1284 smu->pool_size = adev->pm.smu_prv_buffer_size;
1285 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1286 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1287 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1288
1289 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1290 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1291 atomic64_set(&smu->throttle_int_counter, 0);
1292 smu->watermarks_bitmap = 0;
1293
1294 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1295 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
1296 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1297 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
1298 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
1299
1300 smu_init_power_profile(smu);
1301 smu->display_config = &adev->pm.pm_display_cfg;
1302
1303 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1304 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1305
1306 INIT_DELAYED_WORK(&smu->swctf_delayed_work,
1307 smu_swctf_delayed_work_handler);
1308
1309 ret = smu_smc_table_sw_init(smu);
1310 if (ret) {
1311 dev_err(adev->dev, "Failed to sw init smc table!\n");
1312 return ret;
1313 }
1314
1315 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1316 ret = smu_get_vbios_bootup_values(smu);
1317 if (ret) {
1318 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1319 return ret;
1320 }
1321
1322 ret = smu_init_pptable_microcode(smu);
1323 if (ret) {
1324 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1325 return ret;
1326 }
1327
1328 ret = smu_register_irq_handler(smu);
1329 if (ret) {
1330 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1331 return ret;
1332 }
1333
1334 /* If there is no way to query fan control mode, fan control is not supported */
1335 if (!smu->ppt_funcs->get_fan_control_mode)
1336 smu->adev->pm.no_fan = true;
1337
1338 return 0;
1339 }
1340
smu_sw_fini(struct amdgpu_ip_block * ip_block)1341 static int smu_sw_fini(struct amdgpu_ip_block *ip_block)
1342 {
1343 struct amdgpu_device *adev = ip_block->adev;
1344 struct smu_context *smu = adev->powerplay.pp_handle;
1345 int ret;
1346
1347 ret = smu_smc_table_sw_fini(smu);
1348 if (ret) {
1349 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1350 return ret;
1351 }
1352
1353 if (smu->custom_profile_params) {
1354 kfree(smu->custom_profile_params);
1355 smu->custom_profile_params = NULL;
1356 }
1357
1358 smu_fini_microcode(smu);
1359
1360 return 0;
1361 }
1362
smu_get_thermal_temperature_range(struct smu_context * smu)1363 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1364 {
1365 struct amdgpu_device *adev = smu->adev;
1366 struct smu_temperature_range *range =
1367 &smu->thermal_range;
1368 int ret = 0;
1369
1370 if (!smu->ppt_funcs->get_thermal_temperature_range)
1371 return 0;
1372
1373 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1374 if (ret)
1375 return ret;
1376
1377 adev->pm.dpm.thermal.min_temp = range->min;
1378 adev->pm.dpm.thermal.max_temp = range->max;
1379 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1380 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1381 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1382 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1383 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1384 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1385 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1386
1387 return ret;
1388 }
1389
1390 /**
1391 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges
1392 *
1393 * @smu: smu_context pointer
1394 *
1395 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling.
1396 * Returns 0 on success, error on failure.
1397 */
smu_wbrf_handle_exclusion_ranges(struct smu_context * smu)1398 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
1399 {
1400 struct wbrf_ranges_in_out wbrf_exclusion = {0};
1401 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list;
1402 struct amdgpu_device *adev = smu->adev;
1403 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;
1404 uint64_t start, end;
1405 int ret, i, j;
1406
1407 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion);
1408 if (ret) {
1409 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n");
1410 return ret;
1411 }
1412
1413 /*
1414 * The exclusion ranges array we got might be filled with holes and duplicate
1415 * entries. For example:
1416 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...}
1417 * We need to do some sortups to eliminate those holes and duplicate entries.
1418 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...}
1419 */
1420 for (i = 0; i < num_of_wbrf_ranges; i++) {
1421 start = wifi_bands[i].start;
1422 end = wifi_bands[i].end;
1423
1424 /* get the last valid entry to fill the intermediate hole */
1425 if (!start && !end) {
1426 for (j = num_of_wbrf_ranges - 1; j > i; j--)
1427 if (wifi_bands[j].start && wifi_bands[j].end)
1428 break;
1429
1430 /* no valid entry left */
1431 if (j <= i)
1432 break;
1433
1434 start = wifi_bands[i].start = wifi_bands[j].start;
1435 end = wifi_bands[i].end = wifi_bands[j].end;
1436 wifi_bands[j].start = 0;
1437 wifi_bands[j].end = 0;
1438 num_of_wbrf_ranges = j;
1439 }
1440
1441 /* eliminate duplicate entries */
1442 for (j = i + 1; j < num_of_wbrf_ranges; j++) {
1443 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) {
1444 wifi_bands[j].start = 0;
1445 wifi_bands[j].end = 0;
1446 }
1447 }
1448 }
1449
1450 /* Send the sorted wifi_bands to PMFW */
1451 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1452 /* Try to set the wifi_bands again */
1453 if (unlikely(ret == -EBUSY)) {
1454 mdelay(5);
1455 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1456 }
1457
1458 return ret;
1459 }
1460
1461 /**
1462 * smu_wbrf_event_handler - handle notify events
1463 *
1464 * @nb: notifier block
1465 * @action: event type
1466 * @_arg: event data
1467 *
1468 * Calls relevant amdgpu function in response to wbrf event
1469 * notification from kernel.
1470 */
smu_wbrf_event_handler(struct notifier_block * nb,unsigned long action,void * _arg)1471 static int smu_wbrf_event_handler(struct notifier_block *nb,
1472 unsigned long action, void *_arg)
1473 {
1474 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier);
1475
1476 switch (action) {
1477 case WBRF_CHANGED:
1478 schedule_delayed_work(&smu->wbrf_delayed_work,
1479 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1480 break;
1481 default:
1482 return NOTIFY_DONE;
1483 }
1484
1485 return NOTIFY_OK;
1486 }
1487
1488 /**
1489 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired
1490 *
1491 * @work: struct work_struct pointer
1492 *
1493 * Flood is over and driver will consume the latest exclusion ranges.
1494 */
smu_wbrf_delayed_work_handler(struct work_struct * work)1495 static void smu_wbrf_delayed_work_handler(struct work_struct *work)
1496 {
1497 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work);
1498
1499 smu_wbrf_handle_exclusion_ranges(smu);
1500 }
1501
1502 /**
1503 * smu_wbrf_support_check - check wbrf support
1504 *
1505 * @smu: smu_context pointer
1506 *
1507 * Verifies the ACPI interface whether wbrf is supported.
1508 */
smu_wbrf_support_check(struct smu_context * smu)1509 static void smu_wbrf_support_check(struct smu_context *smu)
1510 {
1511 struct amdgpu_device *adev = smu->adev;
1512
1513 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf &&
1514 acpi_amd_wbrf_supported_consumer(adev->dev);
1515
1516 if (smu->wbrf_supported)
1517 dev_info(adev->dev, "RF interference mitigation is supported\n");
1518 }
1519
1520 /**
1521 * smu_wbrf_init - init driver wbrf support
1522 *
1523 * @smu: smu_context pointer
1524 *
1525 * Verifies the AMD ACPI interfaces and registers with the wbrf
1526 * notifier chain if wbrf feature is supported.
1527 * Returns 0 on success, error on failure.
1528 */
smu_wbrf_init(struct smu_context * smu)1529 static int smu_wbrf_init(struct smu_context *smu)
1530 {
1531 int ret;
1532
1533 if (!smu->wbrf_supported)
1534 return 0;
1535
1536 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler);
1537
1538 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler;
1539 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier);
1540 if (ret)
1541 return ret;
1542
1543 /*
1544 * Some wifiband exclusion ranges may be already there
1545 * before our driver loaded. To make sure our driver
1546 * is awared of those exclusion ranges.
1547 */
1548 schedule_delayed_work(&smu->wbrf_delayed_work,
1549 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1550
1551 return 0;
1552 }
1553
1554 /**
1555 * smu_wbrf_fini - tear down driver wbrf support
1556 *
1557 * @smu: smu_context pointer
1558 *
1559 * Unregisters with the wbrf notifier chain.
1560 */
smu_wbrf_fini(struct smu_context * smu)1561 static void smu_wbrf_fini(struct smu_context *smu)
1562 {
1563 if (!smu->wbrf_supported)
1564 return;
1565
1566 amd_wbrf_unregister_notifier(&smu->wbrf_notifier);
1567
1568 cancel_delayed_work_sync(&smu->wbrf_delayed_work);
1569 }
1570
smu_smc_hw_setup(struct smu_context * smu)1571 static int smu_smc_hw_setup(struct smu_context *smu)
1572 {
1573 struct smu_feature *feature = &smu->smu_feature;
1574 struct amdgpu_device *adev = smu->adev;
1575 uint8_t pcie_gen = 0, pcie_width = 0;
1576 uint64_t features_supported;
1577 int ret = 0;
1578
1579 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1580 case IP_VERSION(11, 0, 7):
1581 case IP_VERSION(11, 0, 11):
1582 case IP_VERSION(11, 5, 0):
1583 case IP_VERSION(11, 0, 12):
1584 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1585 dev_info(adev->dev, "dpm has been enabled\n");
1586 ret = smu_system_features_control(smu, true);
1587 if (ret)
1588 dev_err(adev->dev, "Failed system features control!\n");
1589 return ret;
1590 }
1591 break;
1592 default:
1593 break;
1594 }
1595
1596 ret = smu_init_display_count(smu, 0);
1597 if (ret) {
1598 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1599 return ret;
1600 }
1601
1602 ret = smu_set_driver_table_location(smu);
1603 if (ret) {
1604 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1605 return ret;
1606 }
1607
1608 /*
1609 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1610 */
1611 ret = smu_set_tool_table_location(smu);
1612 if (ret) {
1613 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1614 return ret;
1615 }
1616
1617 /*
1618 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1619 * pool location.
1620 */
1621 ret = smu_notify_memory_pool_location(smu);
1622 if (ret) {
1623 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1624 return ret;
1625 }
1626
1627 /*
1628 * It is assumed the pptable used before runpm is same as
1629 * the one used afterwards. Thus, we can reuse the stored
1630 * copy and do not need to resetup the pptable again.
1631 */
1632 if (!adev->in_runpm) {
1633 ret = smu_setup_pptable(smu);
1634 if (ret) {
1635 dev_err(adev->dev, "Failed to setup pptable!\n");
1636 return ret;
1637 }
1638 }
1639
1640 /* smu_dump_pptable(smu); */
1641
1642 /*
1643 * With SCPM enabled, PSP is responsible for the PPTable transferring
1644 * (to SMU). Driver involvement is not needed and permitted.
1645 */
1646 if (!adev->scpm_enabled) {
1647 /*
1648 * Copy pptable bo in the vram to smc with SMU MSGs such as
1649 * SetDriverDramAddr and TransferTableDram2Smu.
1650 */
1651 ret = smu_write_pptable(smu);
1652 if (ret) {
1653 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1654 return ret;
1655 }
1656 }
1657
1658 /* issue Run*Btc msg */
1659 ret = smu_run_btc(smu);
1660 if (ret)
1661 return ret;
1662
1663 /* Enable UclkShadow on wbrf supported */
1664 if (smu->wbrf_supported) {
1665 ret = smu_enable_uclk_shadow(smu, true);
1666 if (ret) {
1667 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n");
1668 return ret;
1669 }
1670 }
1671
1672 /*
1673 * With SCPM enabled, these actions(and relevant messages) are
1674 * not needed and permitted.
1675 */
1676 if (!adev->scpm_enabled) {
1677 ret = smu_feature_set_allowed_mask(smu);
1678 if (ret) {
1679 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1680 return ret;
1681 }
1682 }
1683
1684 ret = smu_system_features_control(smu, true);
1685 if (ret) {
1686 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1687 return ret;
1688 }
1689
1690 smu_init_xgmi_plpd_mode(smu);
1691
1692 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1693 if (ret) {
1694 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1695 return ret;
1696 }
1697 bitmap_copy(feature->supported,
1698 (unsigned long *)&features_supported,
1699 feature->feature_num);
1700
1701 if (!smu_is_dpm_running(smu))
1702 dev_info(adev->dev, "dpm has been disabled\n");
1703
1704 /*
1705 * Set initialized values (get from vbios) to dpm tables context such as
1706 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1707 * type of clks.
1708 */
1709 ret = smu_set_default_dpm_table(smu);
1710 if (ret) {
1711 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1712 return ret;
1713 }
1714
1715 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5)
1716 pcie_gen = 4;
1717 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1718 pcie_gen = 3;
1719 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1720 pcie_gen = 2;
1721 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1722 pcie_gen = 1;
1723 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1724 pcie_gen = 0;
1725
1726 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1727 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1728 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1729 */
1730 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
1731 pcie_width = 7;
1732 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1733 pcie_width = 6;
1734 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1735 pcie_width = 5;
1736 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1737 pcie_width = 4;
1738 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1739 pcie_width = 3;
1740 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1741 pcie_width = 2;
1742 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1743 pcie_width = 1;
1744 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1745 if (ret) {
1746 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1747 return ret;
1748 }
1749
1750 ret = smu_get_thermal_temperature_range(smu);
1751 if (ret) {
1752 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1753 return ret;
1754 }
1755
1756 ret = smu_enable_thermal_alert(smu);
1757 if (ret) {
1758 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1759 return ret;
1760 }
1761
1762 ret = smu_notify_display_change(smu);
1763 if (ret) {
1764 dev_err(adev->dev, "Failed to notify display change!\n");
1765 return ret;
1766 }
1767
1768 /*
1769 * Set min deep sleep dce fclk with bootup value from vbios via
1770 * SetMinDeepSleepDcefclk MSG.
1771 */
1772 ret = smu_set_min_dcef_deep_sleep(smu,
1773 smu->smu_table.boot_values.dcefclk / 100);
1774 if (ret) {
1775 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n");
1776 return ret;
1777 }
1778
1779 /* Init wbrf support. Properly setup the notifier */
1780 ret = smu_wbrf_init(smu);
1781 if (ret)
1782 dev_err(adev->dev, "Error during wbrf init call\n");
1783
1784 return ret;
1785 }
1786
smu_start_smc_engine(struct smu_context * smu)1787 static int smu_start_smc_engine(struct smu_context *smu)
1788 {
1789 struct amdgpu_device *adev = smu->adev;
1790 int ret = 0;
1791
1792 smu->smc_fw_state = SMU_FW_INIT;
1793
1794 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1795 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) {
1796 if (smu->ppt_funcs->load_microcode) {
1797 ret = smu->ppt_funcs->load_microcode(smu);
1798 if (ret)
1799 return ret;
1800 }
1801 }
1802 }
1803
1804 if (smu->ppt_funcs->check_fw_status) {
1805 ret = smu->ppt_funcs->check_fw_status(smu);
1806 if (ret) {
1807 dev_err(adev->dev, "SMC is not ready\n");
1808 return ret;
1809 }
1810 }
1811
1812 /*
1813 * Send msg GetDriverIfVersion to check if the return value is equal
1814 * with DRIVER_IF_VERSION of smc header.
1815 */
1816 ret = smu_check_fw_version(smu);
1817 if (ret)
1818 return ret;
1819
1820 return ret;
1821 }
1822
smu_hw_init(struct amdgpu_ip_block * ip_block)1823 static int smu_hw_init(struct amdgpu_ip_block *ip_block)
1824 {
1825 int i, ret;
1826 struct amdgpu_device *adev = ip_block->adev;
1827 struct smu_context *smu = adev->powerplay.pp_handle;
1828
1829 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1830 smu->pm_enabled = false;
1831 return 0;
1832 }
1833
1834 ret = smu_start_smc_engine(smu);
1835 if (ret) {
1836 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1837 return ret;
1838 }
1839
1840 /*
1841 * Check whether wbrf is supported. This needs to be done
1842 * before SMU setup starts since part of SMU configuration
1843 * relies on this.
1844 */
1845 smu_wbrf_support_check(smu);
1846
1847 if (smu->is_apu) {
1848 ret = smu_set_gfx_imu_enable(smu);
1849 if (ret)
1850 return ret;
1851 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1852 smu_dpm_set_vcn_enable(smu, true, i);
1853 smu_dpm_set_jpeg_enable(smu, true);
1854 smu_dpm_set_vpe_enable(smu, true);
1855 smu_dpm_set_umsch_mm_enable(smu, true);
1856 smu_set_mall_enable(smu);
1857 smu_set_gfx_cgpg(smu, true);
1858 }
1859
1860 if (!smu->pm_enabled)
1861 return 0;
1862
1863 ret = smu_get_driver_allowed_feature_mask(smu);
1864 if (ret)
1865 return ret;
1866
1867 ret = smu_smc_hw_setup(smu);
1868 if (ret) {
1869 dev_err(adev->dev, "Failed to setup smc hw!\n");
1870 return ret;
1871 }
1872
1873 /*
1874 * Move maximum sustainable clock retrieving here considering
1875 * 1. It is not needed on resume(from S3).
1876 * 2. DAL settings come between .hw_init and .late_init of SMU.
1877 * And DAL needs to know the maximum sustainable clocks. Thus
1878 * it cannot be put in .late_init().
1879 */
1880 ret = smu_init_max_sustainable_clocks(smu);
1881 if (ret) {
1882 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1883 return ret;
1884 }
1885
1886 adev->pm.dpm_enabled = true;
1887
1888 dev_info(adev->dev, "SMU is initialized successfully!\n");
1889
1890 return 0;
1891 }
1892
smu_disable_dpms(struct smu_context * smu)1893 static int smu_disable_dpms(struct smu_context *smu)
1894 {
1895 struct amdgpu_device *adev = smu->adev;
1896 int ret = 0;
1897 bool use_baco = !smu->is_apu &&
1898 ((amdgpu_in_reset(adev) &&
1899 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1900 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1901
1902 /*
1903 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1904 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1905 */
1906 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1907 case IP_VERSION(13, 0, 0):
1908 case IP_VERSION(13, 0, 7):
1909 case IP_VERSION(13, 0, 10):
1910 case IP_VERSION(14, 0, 2):
1911 case IP_VERSION(14, 0, 3):
1912 return 0;
1913 default:
1914 break;
1915 }
1916
1917 /*
1918 * For custom pptable uploading, skip the DPM features
1919 * disable process on Navi1x ASICs.
1920 * - As the gfx related features are under control of
1921 * RLC on those ASICs. RLC reinitialization will be
1922 * needed to reenable them. That will cost much more
1923 * efforts.
1924 *
1925 * - SMU firmware can handle the DPM reenablement
1926 * properly.
1927 */
1928 if (smu->uploading_custom_pp_table) {
1929 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1930 case IP_VERSION(11, 0, 0):
1931 case IP_VERSION(11, 0, 5):
1932 case IP_VERSION(11, 0, 9):
1933 case IP_VERSION(11, 0, 7):
1934 case IP_VERSION(11, 0, 11):
1935 case IP_VERSION(11, 5, 0):
1936 case IP_VERSION(11, 0, 12):
1937 case IP_VERSION(11, 0, 13):
1938 return 0;
1939 default:
1940 break;
1941 }
1942 }
1943
1944 /*
1945 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1946 * on BACO in. Driver involvement is unnecessary.
1947 */
1948 if (use_baco) {
1949 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1950 case IP_VERSION(11, 0, 7):
1951 case IP_VERSION(11, 0, 0):
1952 case IP_VERSION(11, 0, 5):
1953 case IP_VERSION(11, 0, 9):
1954 case IP_VERSION(13, 0, 7):
1955 return 0;
1956 default:
1957 break;
1958 }
1959 }
1960
1961 /*
1962 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly
1963 * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
1964 */
1965 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 &&
1966 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
1967 return 0;
1968
1969 /*
1970 * For gpu reset, runpm and hibernation through BACO,
1971 * BACO feature has to be kept enabled.
1972 */
1973 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1974 ret = smu_disable_all_features_with_exception(smu,
1975 SMU_FEATURE_BACO_BIT);
1976 if (ret)
1977 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1978 } else {
1979 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1980 if (!adev->scpm_enabled) {
1981 ret = smu_system_features_control(smu, false);
1982 if (ret)
1983 dev_err(adev->dev, "Failed to disable smu features.\n");
1984 }
1985 }
1986
1987 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction.
1988 * otherwise SMU will hang while interacting with RLC if RLC is halted
1989 * this is a WA for Vangogh asic which fix the SMU hang issue.
1990 */
1991 ret = smu_notify_rlc_state(smu, false);
1992 if (ret) {
1993 dev_err(adev->dev, "Fail to notify rlc status!\n");
1994 return ret;
1995 }
1996
1997 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&
1998 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&
1999 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
2000 adev->gfx.rlc.funcs->stop(adev);
2001
2002 return ret;
2003 }
2004
smu_smc_hw_cleanup(struct smu_context * smu)2005 static int smu_smc_hw_cleanup(struct smu_context *smu)
2006 {
2007 struct amdgpu_device *adev = smu->adev;
2008 int ret = 0;
2009
2010 smu_wbrf_fini(smu);
2011
2012 cancel_work_sync(&smu->throttling_logging_work);
2013 cancel_work_sync(&smu->interrupt_work);
2014
2015 ret = smu_disable_thermal_alert(smu);
2016 if (ret) {
2017 dev_err(adev->dev, "Fail to disable thermal alert!\n");
2018 return ret;
2019 }
2020
2021 cancel_delayed_work_sync(&smu->swctf_delayed_work);
2022
2023 ret = smu_disable_dpms(smu);
2024 if (ret) {
2025 dev_err(adev->dev, "Fail to disable dpm features!\n");
2026 return ret;
2027 }
2028
2029 return 0;
2030 }
2031
smu_reset_mp1_state(struct smu_context * smu)2032 static int smu_reset_mp1_state(struct smu_context *smu)
2033 {
2034 struct amdgpu_device *adev = smu->adev;
2035 int ret = 0;
2036
2037 if ((!adev->in_runpm) && (!adev->in_suspend) &&
2038 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2039 IP_VERSION(13, 0, 10) &&
2040 !amdgpu_device_has_display_hardware(adev))
2041 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
2042
2043 return ret;
2044 }
2045
smu_hw_fini(struct amdgpu_ip_block * ip_block)2046 static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
2047 {
2048 struct amdgpu_device *adev = ip_block->adev;
2049 struct smu_context *smu = adev->powerplay.pp_handle;
2050 int i, ret;
2051
2052 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2053 return 0;
2054
2055 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
2056 smu_dpm_set_vcn_enable(smu, false, i);
2057 smu_dpm_set_jpeg_enable(smu, false);
2058 smu_dpm_set_vpe_enable(smu, false);
2059 smu_dpm_set_umsch_mm_enable(smu, false);
2060
2061 adev->vcn.cur_state = AMD_PG_STATE_GATE;
2062 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
2063
2064 if (!smu->pm_enabled)
2065 return 0;
2066
2067 adev->pm.dpm_enabled = false;
2068
2069 ret = smu_smc_hw_cleanup(smu);
2070 if (ret)
2071 return ret;
2072
2073 ret = smu_reset_mp1_state(smu);
2074 if (ret)
2075 return ret;
2076
2077 return 0;
2078 }
2079
smu_late_fini(struct amdgpu_ip_block * ip_block)2080 static void smu_late_fini(struct amdgpu_ip_block *ip_block)
2081 {
2082 struct amdgpu_device *adev = ip_block->adev;
2083 struct smu_context *smu = adev->powerplay.pp_handle;
2084
2085 kfree(smu);
2086 }
2087
smu_reset(struct smu_context * smu)2088 static int smu_reset(struct smu_context *smu)
2089 {
2090 struct amdgpu_device *adev = smu->adev;
2091 struct amdgpu_ip_block *ip_block;
2092 int ret;
2093
2094 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC);
2095 if (!ip_block)
2096 return -EINVAL;
2097
2098 ret = smu_hw_fini(ip_block);
2099 if (ret)
2100 return ret;
2101
2102 ret = smu_hw_init(ip_block);
2103 if (ret)
2104 return ret;
2105
2106 ret = smu_late_init(ip_block);
2107 if (ret)
2108 return ret;
2109
2110 return 0;
2111 }
2112
smu_suspend(struct amdgpu_ip_block * ip_block)2113 static int smu_suspend(struct amdgpu_ip_block *ip_block)
2114 {
2115 struct amdgpu_device *adev = ip_block->adev;
2116 struct smu_context *smu = adev->powerplay.pp_handle;
2117 int ret;
2118 uint64_t count;
2119
2120 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
2121 return 0;
2122
2123 if (!smu->pm_enabled)
2124 return 0;
2125
2126 adev->pm.dpm_enabled = false;
2127
2128 ret = smu_smc_hw_cleanup(smu);
2129 if (ret)
2130 return ret;
2131
2132 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
2133
2134 smu_set_gfx_cgpg(smu, false);
2135
2136 /*
2137 * pwfw resets entrycount when device is suspended, so we save the
2138 * last value to be used when we resume to keep it consistent
2139 */
2140 ret = smu_get_entrycount_gfxoff(smu, &count);
2141 if (!ret)
2142 adev->gfx.gfx_off_entrycount = count;
2143
2144 /* clear this on suspend so it will get reprogrammed on resume */
2145 smu->workload_mask = 0;
2146
2147 return 0;
2148 }
2149
smu_resume(struct amdgpu_ip_block * ip_block)2150 static int smu_resume(struct amdgpu_ip_block *ip_block)
2151 {
2152 int ret;
2153 struct amdgpu_device *adev = ip_block->adev;
2154 struct smu_context *smu = adev->powerplay.pp_handle;
2155
2156 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
2157 return 0;
2158
2159 if (!smu->pm_enabled)
2160 return 0;
2161
2162 dev_info(adev->dev, "SMU is resuming...\n");
2163
2164 ret = smu_start_smc_engine(smu);
2165 if (ret) {
2166 dev_err(adev->dev, "SMC engine is not correctly up!\n");
2167 return ret;
2168 }
2169
2170 ret = smu_smc_hw_setup(smu);
2171 if (ret) {
2172 dev_err(adev->dev, "Failed to setup smc hw!\n");
2173 return ret;
2174 }
2175
2176 ret = smu_set_gfx_imu_enable(smu);
2177 if (ret)
2178 return ret;
2179
2180 smu_set_gfx_cgpg(smu, true);
2181
2182 smu->disable_uclk_switch = 0;
2183
2184 adev->pm.dpm_enabled = true;
2185
2186 dev_info(adev->dev, "SMU is resumed successfully!\n");
2187
2188 return 0;
2189 }
2190
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)2191 static int smu_display_configuration_change(void *handle,
2192 const struct amd_pp_display_configuration *display_config)
2193 {
2194 struct smu_context *smu = handle;
2195
2196 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2197 return -EOPNOTSUPP;
2198
2199 if (!display_config)
2200 return -EINVAL;
2201
2202 smu_set_min_dcef_deep_sleep(smu,
2203 display_config->min_dcef_deep_sleep_set_clk / 100);
2204
2205 return 0;
2206 }
2207
smu_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2208 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2209 enum amd_clockgating_state state)
2210 {
2211 return 0;
2212 }
2213
smu_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2214 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
2215 enum amd_powergating_state state)
2216 {
2217 return 0;
2218 }
2219
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)2220 static int smu_enable_umd_pstate(void *handle,
2221 enum amd_dpm_forced_level *level)
2222 {
2223 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
2224 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
2225 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
2226 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
2227
2228 struct smu_context *smu = (struct smu_context*)(handle);
2229 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2230
2231 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2232 return -EINVAL;
2233
2234 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
2235 /* enter umd pstate, save current level, disable gfx cg*/
2236 if (*level & profile_mode_mask) {
2237 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
2238 smu_gpo_control(smu, false);
2239 smu_gfx_ulv_control(smu, false);
2240 smu_deep_sleep_control(smu, false);
2241 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
2242 }
2243 } else {
2244 /* exit umd pstate, restore level, enable gfx cg*/
2245 if (!(*level & profile_mode_mask)) {
2246 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
2247 *level = smu_dpm_ctx->saved_dpm_level;
2248 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
2249 smu_deep_sleep_control(smu, true);
2250 smu_gfx_ulv_control(smu, true);
2251 smu_gpo_control(smu, true);
2252 }
2253 }
2254
2255 return 0;
2256 }
2257
smu_bump_power_profile_mode(struct smu_context * smu,long * custom_params,u32 custom_params_max_idx)2258 static int smu_bump_power_profile_mode(struct smu_context *smu,
2259 long *custom_params,
2260 u32 custom_params_max_idx)
2261 {
2262 u32 workload_mask = 0;
2263 int i, ret = 0;
2264
2265 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2266 if (smu->workload_refcount[i])
2267 workload_mask |= 1 << i;
2268 }
2269
2270 if (smu->workload_mask == workload_mask)
2271 return 0;
2272
2273 if (smu->ppt_funcs->set_power_profile_mode)
2274 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask,
2275 custom_params,
2276 custom_params_max_idx);
2277
2278 if (!ret)
2279 smu->workload_mask = workload_mask;
2280
2281 return ret;
2282 }
2283
smu_power_profile_mode_get(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile_mode)2284 static void smu_power_profile_mode_get(struct smu_context *smu,
2285 enum PP_SMC_POWER_PROFILE profile_mode)
2286 {
2287 smu->workload_refcount[profile_mode]++;
2288 }
2289
smu_power_profile_mode_put(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile_mode)2290 static void smu_power_profile_mode_put(struct smu_context *smu,
2291 enum PP_SMC_POWER_PROFILE profile_mode)
2292 {
2293 if (smu->workload_refcount[profile_mode])
2294 smu->workload_refcount[profile_mode]--;
2295 }
2296
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings)2297 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
2298 enum amd_dpm_forced_level level,
2299 bool skip_display_settings)
2300 {
2301 int ret = 0;
2302 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2303
2304 if (!skip_display_settings) {
2305 ret = smu_display_config_changed(smu);
2306 if (ret) {
2307 dev_err(smu->adev->dev, "Failed to change display config!");
2308 return ret;
2309 }
2310 }
2311
2312 ret = smu_apply_clocks_adjust_rules(smu);
2313 if (ret) {
2314 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
2315 return ret;
2316 }
2317
2318 if (!skip_display_settings) {
2319 ret = smu_notify_smc_display_config(smu);
2320 if (ret) {
2321 dev_err(smu->adev->dev, "Failed to notify smc display config!");
2322 return ret;
2323 }
2324 }
2325
2326 if (smu_dpm_ctx->dpm_level != level) {
2327 ret = smu_asic_set_performance_level(smu, level);
2328 if (ret) {
2329 dev_err(smu->adev->dev, "Failed to set performance level!");
2330 return ret;
2331 }
2332
2333 /* update the saved copy */
2334 smu_dpm_ctx->dpm_level = level;
2335 }
2336
2337 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2338 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2339 smu_bump_power_profile_mode(smu, NULL, 0);
2340
2341 return ret;
2342 }
2343
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id)2344 static int smu_handle_task(struct smu_context *smu,
2345 enum amd_dpm_forced_level level,
2346 enum amd_pp_task task_id)
2347 {
2348 int ret = 0;
2349
2350 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2351 return -EOPNOTSUPP;
2352
2353 switch (task_id) {
2354 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
2355 ret = smu_pre_display_config_changed(smu);
2356 if (ret)
2357 return ret;
2358 ret = smu_adjust_power_state_dynamic(smu, level, false);
2359 break;
2360 case AMD_PP_TASK_COMPLETE_INIT:
2361 ret = smu_adjust_power_state_dynamic(smu, level, true);
2362 break;
2363 case AMD_PP_TASK_READJUST_POWER_STATE:
2364 ret = smu_adjust_power_state_dynamic(smu, level, true);
2365 break;
2366 default:
2367 break;
2368 }
2369
2370 return ret;
2371 }
2372
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)2373 static int smu_handle_dpm_task(void *handle,
2374 enum amd_pp_task task_id,
2375 enum amd_pm_state_type *user_state)
2376 {
2377 struct smu_context *smu = handle;
2378 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2379
2380 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
2381
2382 }
2383
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool enable)2384 static int smu_switch_power_profile(void *handle,
2385 enum PP_SMC_POWER_PROFILE type,
2386 bool enable)
2387 {
2388 struct smu_context *smu = handle;
2389 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2390 int ret;
2391
2392 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2393 return -EOPNOTSUPP;
2394
2395 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
2396 return -EINVAL;
2397
2398 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2399 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2400 if (enable)
2401 smu_power_profile_mode_get(smu, type);
2402 else
2403 smu_power_profile_mode_put(smu, type);
2404 ret = smu_bump_power_profile_mode(smu, NULL, 0);
2405 if (ret) {
2406 if (enable)
2407 smu_power_profile_mode_put(smu, type);
2408 else
2409 smu_power_profile_mode_get(smu, type);
2410 return ret;
2411 }
2412 }
2413
2414 return 0;
2415 }
2416
smu_get_performance_level(void * handle)2417 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
2418 {
2419 struct smu_context *smu = handle;
2420 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2421
2422 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2423 return -EOPNOTSUPP;
2424
2425 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2426 return -EINVAL;
2427
2428 return smu_dpm_ctx->dpm_level;
2429 }
2430
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)2431 static int smu_force_performance_level(void *handle,
2432 enum amd_dpm_forced_level level)
2433 {
2434 struct smu_context *smu = handle;
2435 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2436 int ret = 0;
2437
2438 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2439 return -EOPNOTSUPP;
2440
2441 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2442 return -EINVAL;
2443
2444 ret = smu_enable_umd_pstate(smu, &level);
2445 if (ret)
2446 return ret;
2447
2448 ret = smu_handle_task(smu, level,
2449 AMD_PP_TASK_READJUST_POWER_STATE);
2450
2451 /* reset user dpm clock state */
2452 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2453 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
2454 smu->user_dpm_profile.clk_dependency = 0;
2455 }
2456
2457 return ret;
2458 }
2459
smu_set_display_count(void * handle,uint32_t count)2460 static int smu_set_display_count(void *handle, uint32_t count)
2461 {
2462 struct smu_context *smu = handle;
2463
2464 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2465 return -EOPNOTSUPP;
2466
2467 return smu_init_display_count(smu, count);
2468 }
2469
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)2470 static int smu_force_smuclk_levels(struct smu_context *smu,
2471 enum smu_clk_type clk_type,
2472 uint32_t mask)
2473 {
2474 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2475 int ret = 0;
2476
2477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2478 return -EOPNOTSUPP;
2479
2480 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2481 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
2482 return -EINVAL;
2483 }
2484
2485 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
2486 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
2487 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2488 smu->user_dpm_profile.clk_mask[clk_type] = mask;
2489 smu_set_user_clk_dependencies(smu, clk_type);
2490 }
2491 }
2492
2493 return ret;
2494 }
2495
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)2496 static int smu_force_ppclk_levels(void *handle,
2497 enum pp_clock_type type,
2498 uint32_t mask)
2499 {
2500 struct smu_context *smu = handle;
2501 enum smu_clk_type clk_type;
2502
2503 switch (type) {
2504 case PP_SCLK:
2505 clk_type = SMU_SCLK; break;
2506 case PP_MCLK:
2507 clk_type = SMU_MCLK; break;
2508 case PP_PCIE:
2509 clk_type = SMU_PCIE; break;
2510 case PP_SOCCLK:
2511 clk_type = SMU_SOCCLK; break;
2512 case PP_FCLK:
2513 clk_type = SMU_FCLK; break;
2514 case PP_DCEFCLK:
2515 clk_type = SMU_DCEFCLK; break;
2516 case PP_VCLK:
2517 clk_type = SMU_VCLK; break;
2518 case PP_VCLK1:
2519 clk_type = SMU_VCLK1; break;
2520 case PP_DCLK:
2521 clk_type = SMU_DCLK; break;
2522 case PP_DCLK1:
2523 clk_type = SMU_DCLK1; break;
2524 case OD_SCLK:
2525 clk_type = SMU_OD_SCLK; break;
2526 case OD_MCLK:
2527 clk_type = SMU_OD_MCLK; break;
2528 case OD_VDDC_CURVE:
2529 clk_type = SMU_OD_VDDC_CURVE; break;
2530 case OD_RANGE:
2531 clk_type = SMU_OD_RANGE; break;
2532 default:
2533 return -EINVAL;
2534 }
2535
2536 return smu_force_smuclk_levels(smu, clk_type, mask);
2537 }
2538
2539 /*
2540 * On system suspending or resetting, the dpm_enabled
2541 * flag will be cleared. So that those SMU services which
2542 * are not supported will be gated.
2543 * However, the mp1 state setting should still be granted
2544 * even if the dpm_enabled cleared.
2545 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2546 static int smu_set_mp1_state(void *handle,
2547 enum pp_mp1_state mp1_state)
2548 {
2549 struct smu_context *smu = handle;
2550 int ret = 0;
2551
2552 if (!smu->pm_enabled)
2553 return -EOPNOTSUPP;
2554
2555 if (smu->ppt_funcs &&
2556 smu->ppt_funcs->set_mp1_state)
2557 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2558
2559 return ret;
2560 }
2561
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2562 static int smu_set_df_cstate(void *handle,
2563 enum pp_df_cstate state)
2564 {
2565 struct smu_context *smu = handle;
2566 int ret = 0;
2567
2568 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2569 return -EOPNOTSUPP;
2570
2571 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2572 return 0;
2573
2574 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2575 if (ret)
2576 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2577
2578 return ret;
2579 }
2580
smu_write_watermarks_table(struct smu_context * smu)2581 int smu_write_watermarks_table(struct smu_context *smu)
2582 {
2583 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2584 return -EOPNOTSUPP;
2585
2586 return smu_set_watermarks_table(smu, NULL);
2587 }
2588
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2589 static int smu_set_watermarks_for_clock_ranges(void *handle,
2590 struct pp_smu_wm_range_sets *clock_ranges)
2591 {
2592 struct smu_context *smu = handle;
2593
2594 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2595 return -EOPNOTSUPP;
2596
2597 if (smu->disable_watermark)
2598 return 0;
2599
2600 return smu_set_watermarks_table(smu, clock_ranges);
2601 }
2602
smu_set_ac_dc(struct smu_context * smu)2603 int smu_set_ac_dc(struct smu_context *smu)
2604 {
2605 int ret = 0;
2606
2607 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2608 return -EOPNOTSUPP;
2609
2610 /* controlled by firmware */
2611 if (smu->dc_controlled_by_gpio)
2612 return 0;
2613
2614 ret = smu_set_power_source(smu,
2615 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2616 SMU_POWER_SOURCE_DC);
2617 if (ret)
2618 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2619 smu->adev->pm.ac_power ? "AC" : "DC");
2620
2621 return ret;
2622 }
2623
2624 const struct amd_ip_funcs smu_ip_funcs = {
2625 .name = "smu",
2626 .early_init = smu_early_init,
2627 .late_init = smu_late_init,
2628 .sw_init = smu_sw_init,
2629 .sw_fini = smu_sw_fini,
2630 .hw_init = smu_hw_init,
2631 .hw_fini = smu_hw_fini,
2632 .late_fini = smu_late_fini,
2633 .suspend = smu_suspend,
2634 .resume = smu_resume,
2635 .is_idle = NULL,
2636 .check_soft_reset = NULL,
2637 .wait_for_idle = NULL,
2638 .soft_reset = NULL,
2639 .set_clockgating_state = smu_set_clockgating_state,
2640 .set_powergating_state = smu_set_powergating_state,
2641 };
2642
2643 const struct amdgpu_ip_block_version smu_v11_0_ip_block = {
2644 .type = AMD_IP_BLOCK_TYPE_SMC,
2645 .major = 11,
2646 .minor = 0,
2647 .rev = 0,
2648 .funcs = &smu_ip_funcs,
2649 };
2650
2651 const struct amdgpu_ip_block_version smu_v12_0_ip_block = {
2652 .type = AMD_IP_BLOCK_TYPE_SMC,
2653 .major = 12,
2654 .minor = 0,
2655 .rev = 0,
2656 .funcs = &smu_ip_funcs,
2657 };
2658
2659 const struct amdgpu_ip_block_version smu_v13_0_ip_block = {
2660 .type = AMD_IP_BLOCK_TYPE_SMC,
2661 .major = 13,
2662 .minor = 0,
2663 .rev = 0,
2664 .funcs = &smu_ip_funcs,
2665 };
2666
2667 const struct amdgpu_ip_block_version smu_v14_0_ip_block = {
2668 .type = AMD_IP_BLOCK_TYPE_SMC,
2669 .major = 14,
2670 .minor = 0,
2671 .rev = 0,
2672 .funcs = &smu_ip_funcs,
2673 };
2674
smu_load_microcode(void * handle)2675 static int smu_load_microcode(void *handle)
2676 {
2677 struct smu_context *smu = handle;
2678 struct amdgpu_device *adev = smu->adev;
2679 int ret = 0;
2680
2681 if (!smu->pm_enabled)
2682 return -EOPNOTSUPP;
2683
2684 /* This should be used for non PSP loading */
2685 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2686 return 0;
2687
2688 if (smu->ppt_funcs->load_microcode) {
2689 ret = smu->ppt_funcs->load_microcode(smu);
2690 if (ret) {
2691 dev_err(adev->dev, "Load microcode failed\n");
2692 return ret;
2693 }
2694 }
2695
2696 if (smu->ppt_funcs->check_fw_status) {
2697 ret = smu->ppt_funcs->check_fw_status(smu);
2698 if (ret) {
2699 dev_err(adev->dev, "SMC is not ready\n");
2700 return ret;
2701 }
2702 }
2703
2704 return ret;
2705 }
2706
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2707 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2708 {
2709 int ret = 0;
2710
2711 if (smu->ppt_funcs->set_gfx_cgpg)
2712 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2713
2714 return ret;
2715 }
2716
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2717 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2718 {
2719 struct smu_context *smu = handle;
2720 int ret = 0;
2721
2722 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2723 return -EOPNOTSUPP;
2724
2725 if (!smu->ppt_funcs->set_fan_speed_rpm)
2726 return -EOPNOTSUPP;
2727
2728 if (speed == U32_MAX)
2729 return -EINVAL;
2730
2731 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2732 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2733 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2734 smu->user_dpm_profile.fan_speed_rpm = speed;
2735
2736 /* Override custom PWM setting as they cannot co-exist */
2737 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2738 smu->user_dpm_profile.fan_speed_pwm = 0;
2739 }
2740
2741 return ret;
2742 }
2743
2744 /**
2745 * smu_get_power_limit - Request one of the SMU Power Limits
2746 *
2747 * @handle: pointer to smu context
2748 * @limit: requested limit is written back to this variable
2749 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2750 * @pp_power_type: &pp_power_type type of power
2751 * Return: 0 on success, <0 on error
2752 *
2753 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2754 int smu_get_power_limit(void *handle,
2755 uint32_t *limit,
2756 enum pp_power_limit_level pp_limit_level,
2757 enum pp_power_type pp_power_type)
2758 {
2759 struct smu_context *smu = handle;
2760 struct amdgpu_device *adev = smu->adev;
2761 enum smu_ppt_limit_level limit_level;
2762 uint32_t limit_type;
2763 int ret = 0;
2764
2765 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2766 return -EOPNOTSUPP;
2767
2768 switch (pp_power_type) {
2769 case PP_PWR_TYPE_SUSTAINED:
2770 limit_type = SMU_DEFAULT_PPT_LIMIT;
2771 break;
2772 case PP_PWR_TYPE_FAST:
2773 limit_type = SMU_FAST_PPT_LIMIT;
2774 break;
2775 default:
2776 return -EOPNOTSUPP;
2777 }
2778
2779 switch (pp_limit_level) {
2780 case PP_PWR_LIMIT_CURRENT:
2781 limit_level = SMU_PPT_LIMIT_CURRENT;
2782 break;
2783 case PP_PWR_LIMIT_DEFAULT:
2784 limit_level = SMU_PPT_LIMIT_DEFAULT;
2785 break;
2786 case PP_PWR_LIMIT_MAX:
2787 limit_level = SMU_PPT_LIMIT_MAX;
2788 break;
2789 case PP_PWR_LIMIT_MIN:
2790 limit_level = SMU_PPT_LIMIT_MIN;
2791 break;
2792 default:
2793 return -EOPNOTSUPP;
2794 }
2795
2796 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2797 if (smu->ppt_funcs->get_ppt_limit)
2798 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2799 } else {
2800 switch (limit_level) {
2801 case SMU_PPT_LIMIT_CURRENT:
2802 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2803 case IP_VERSION(13, 0, 2):
2804 case IP_VERSION(13, 0, 6):
2805 case IP_VERSION(13, 0, 14):
2806 case IP_VERSION(11, 0, 7):
2807 case IP_VERSION(11, 0, 11):
2808 case IP_VERSION(11, 0, 12):
2809 case IP_VERSION(11, 0, 13):
2810 ret = smu_get_asic_power_limits(smu,
2811 &smu->current_power_limit,
2812 NULL, NULL, NULL);
2813 break;
2814 default:
2815 break;
2816 }
2817 *limit = smu->current_power_limit;
2818 break;
2819 case SMU_PPT_LIMIT_DEFAULT:
2820 *limit = smu->default_power_limit;
2821 break;
2822 case SMU_PPT_LIMIT_MAX:
2823 *limit = smu->max_power_limit;
2824 break;
2825 case SMU_PPT_LIMIT_MIN:
2826 *limit = smu->min_power_limit;
2827 break;
2828 default:
2829 return -EINVAL;
2830 }
2831 }
2832
2833 return ret;
2834 }
2835
smu_set_power_limit(void * handle,uint32_t limit)2836 static int smu_set_power_limit(void *handle, uint32_t limit)
2837 {
2838 struct smu_context *smu = handle;
2839 uint32_t limit_type = limit >> 24;
2840 int ret = 0;
2841
2842 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2843 return -EOPNOTSUPP;
2844
2845 limit &= (1<<24)-1;
2846 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2847 if (smu->ppt_funcs->set_power_limit)
2848 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2849
2850 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) {
2851 dev_err(smu->adev->dev,
2852 "New power limit (%d) is out of range [%d,%d]\n",
2853 limit, smu->min_power_limit, smu->max_power_limit);
2854 return -EINVAL;
2855 }
2856
2857 if (!limit)
2858 limit = smu->current_power_limit;
2859
2860 if (smu->ppt_funcs->set_power_limit) {
2861 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2862 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2863 smu->user_dpm_profile.power_limit = limit;
2864 }
2865
2866 return ret;
2867 }
2868
smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)2869 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2870 {
2871 int ret = 0;
2872
2873 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2874 return -EOPNOTSUPP;
2875
2876 if (smu->ppt_funcs->print_clk_levels)
2877 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2878
2879 return ret;
2880 }
2881
smu_convert_to_smuclk(enum pp_clock_type type)2882 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2883 {
2884 enum smu_clk_type clk_type;
2885
2886 switch (type) {
2887 case PP_SCLK:
2888 clk_type = SMU_SCLK; break;
2889 case PP_MCLK:
2890 clk_type = SMU_MCLK; break;
2891 case PP_PCIE:
2892 clk_type = SMU_PCIE; break;
2893 case PP_SOCCLK:
2894 clk_type = SMU_SOCCLK; break;
2895 case PP_FCLK:
2896 clk_type = SMU_FCLK; break;
2897 case PP_DCEFCLK:
2898 clk_type = SMU_DCEFCLK; break;
2899 case PP_VCLK:
2900 clk_type = SMU_VCLK; break;
2901 case PP_VCLK1:
2902 clk_type = SMU_VCLK1; break;
2903 case PP_DCLK:
2904 clk_type = SMU_DCLK; break;
2905 case PP_DCLK1:
2906 clk_type = SMU_DCLK1; break;
2907 case OD_SCLK:
2908 clk_type = SMU_OD_SCLK; break;
2909 case OD_MCLK:
2910 clk_type = SMU_OD_MCLK; break;
2911 case OD_VDDC_CURVE:
2912 clk_type = SMU_OD_VDDC_CURVE; break;
2913 case OD_RANGE:
2914 clk_type = SMU_OD_RANGE; break;
2915 case OD_VDDGFX_OFFSET:
2916 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2917 case OD_CCLK:
2918 clk_type = SMU_OD_CCLK; break;
2919 case OD_FAN_CURVE:
2920 clk_type = SMU_OD_FAN_CURVE; break;
2921 case OD_ACOUSTIC_LIMIT:
2922 clk_type = SMU_OD_ACOUSTIC_LIMIT; break;
2923 case OD_ACOUSTIC_TARGET:
2924 clk_type = SMU_OD_ACOUSTIC_TARGET; break;
2925 case OD_FAN_TARGET_TEMPERATURE:
2926 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break;
2927 case OD_FAN_MINIMUM_PWM:
2928 clk_type = SMU_OD_FAN_MINIMUM_PWM; break;
2929 case OD_FAN_ZERO_RPM_ENABLE:
2930 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break;
2931 case OD_FAN_ZERO_RPM_STOP_TEMP:
2932 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break;
2933 default:
2934 clk_type = SMU_CLK_COUNT; break;
2935 }
2936
2937 return clk_type;
2938 }
2939
smu_print_ppclk_levels(void * handle,enum pp_clock_type type,char * buf)2940 static int smu_print_ppclk_levels(void *handle,
2941 enum pp_clock_type type,
2942 char *buf)
2943 {
2944 struct smu_context *smu = handle;
2945 enum smu_clk_type clk_type;
2946
2947 clk_type = smu_convert_to_smuclk(type);
2948 if (clk_type == SMU_CLK_COUNT)
2949 return -EINVAL;
2950
2951 return smu_print_smuclk_levels(smu, clk_type, buf);
2952 }
2953
smu_emit_ppclk_levels(void * handle,enum pp_clock_type type,char * buf,int * offset)2954 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2955 {
2956 struct smu_context *smu = handle;
2957 enum smu_clk_type clk_type;
2958
2959 clk_type = smu_convert_to_smuclk(type);
2960 if (clk_type == SMU_CLK_COUNT)
2961 return -EINVAL;
2962
2963 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2964 return -EOPNOTSUPP;
2965
2966 if (!smu->ppt_funcs->emit_clk_levels)
2967 return -ENOENT;
2968
2969 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2970
2971 }
2972
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2973 static int smu_od_edit_dpm_table(void *handle,
2974 enum PP_OD_DPM_TABLE_COMMAND type,
2975 long *input, uint32_t size)
2976 {
2977 struct smu_context *smu = handle;
2978 int ret = 0;
2979
2980 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2981 return -EOPNOTSUPP;
2982
2983 if (smu->ppt_funcs->od_edit_dpm_table) {
2984 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2985 }
2986
2987 return ret;
2988 }
2989
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)2990 static int smu_read_sensor(void *handle,
2991 int sensor,
2992 void *data,
2993 int *size_arg)
2994 {
2995 struct smu_context *smu = handle;
2996 struct amdgpu_device *adev = smu->adev;
2997 struct smu_umd_pstate_table *pstate_table =
2998 &smu->pstate_table;
2999 int i, ret = 0;
3000 uint32_t *size, size_val;
3001
3002 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3003 return -EOPNOTSUPP;
3004
3005 if (!data || !size_arg)
3006 return -EINVAL;
3007
3008 size_val = *size_arg;
3009 size = &size_val;
3010
3011 if (smu->ppt_funcs->read_sensor)
3012 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
3013 goto unlock;
3014
3015 switch (sensor) {
3016 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
3017 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
3018 *size = 4;
3019 break;
3020 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
3021 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
3022 *size = 4;
3023 break;
3024 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
3025 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
3026 *size = 4;
3027 break;
3028 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
3029 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
3030 *size = 4;
3031 break;
3032 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3033 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
3034 *size = 8;
3035 break;
3036 case AMDGPU_PP_SENSOR_UVD_POWER:
3037 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
3038 *size = 4;
3039 break;
3040 case AMDGPU_PP_SENSOR_VCE_POWER:
3041 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
3042 *size = 4;
3043 break;
3044 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
3045 *(uint32_t *)data = 0;
3046 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
3047 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
3048 *(uint32_t *)data = 1;
3049 break;
3050 }
3051 }
3052 *size = 4;
3053 break;
3054 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
3055 *(uint32_t *)data = 0;
3056 *size = 4;
3057 break;
3058 default:
3059 *size = 0;
3060 ret = -EOPNOTSUPP;
3061 break;
3062 }
3063
3064 unlock:
3065 // assign uint32_t to int
3066 *size_arg = size_val;
3067
3068 return ret;
3069 }
3070
smu_get_apu_thermal_limit(void * handle,uint32_t * limit)3071 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)
3072 {
3073 int ret = -EOPNOTSUPP;
3074 struct smu_context *smu = handle;
3075
3076 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit)
3077 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit);
3078
3079 return ret;
3080 }
3081
smu_set_apu_thermal_limit(void * handle,uint32_t limit)3082 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)
3083 {
3084 int ret = -EOPNOTSUPP;
3085 struct smu_context *smu = handle;
3086
3087 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)
3088 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit);
3089
3090 return ret;
3091 }
3092
smu_get_power_profile_mode(void * handle,char * buf)3093 static int smu_get_power_profile_mode(void *handle, char *buf)
3094 {
3095 struct smu_context *smu = handle;
3096
3097 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3098 !smu->ppt_funcs->get_power_profile_mode)
3099 return -EOPNOTSUPP;
3100 if (!buf)
3101 return -EINVAL;
3102
3103 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
3104 }
3105
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)3106 static int smu_set_power_profile_mode(void *handle,
3107 long *param,
3108 uint32_t param_size)
3109 {
3110 struct smu_context *smu = handle;
3111 bool custom = false;
3112 int ret = 0;
3113
3114 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3115 !smu->ppt_funcs->set_power_profile_mode)
3116 return -EOPNOTSUPP;
3117
3118 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) {
3119 custom = true;
3120 /* clear frontend mask so custom changes propogate */
3121 smu->workload_mask = 0;
3122 }
3123
3124 if ((param[param_size] != smu->power_profile_mode) || custom) {
3125 /* clear the old user preference */
3126 smu_power_profile_mode_put(smu, smu->power_profile_mode);
3127 /* set the new user preference */
3128 smu_power_profile_mode_get(smu, param[param_size]);
3129 ret = smu_bump_power_profile_mode(smu,
3130 custom ? param : NULL,
3131 custom ? param_size : 0);
3132 if (ret)
3133 smu_power_profile_mode_put(smu, param[param_size]);
3134 else
3135 /* store the user's preference */
3136 smu->power_profile_mode = param[param_size];
3137 }
3138
3139 return ret;
3140 }
3141
smu_get_fan_control_mode(void * handle,u32 * fan_mode)3142 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
3143 {
3144 struct smu_context *smu = handle;
3145
3146 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3147 return -EOPNOTSUPP;
3148
3149 if (!smu->ppt_funcs->get_fan_control_mode)
3150 return -EOPNOTSUPP;
3151
3152 if (!fan_mode)
3153 return -EINVAL;
3154
3155 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
3156
3157 return 0;
3158 }
3159
smu_set_fan_control_mode(void * handle,u32 value)3160 static int smu_set_fan_control_mode(void *handle, u32 value)
3161 {
3162 struct smu_context *smu = handle;
3163 int ret = 0;
3164
3165 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3166 return -EOPNOTSUPP;
3167
3168 if (!smu->ppt_funcs->set_fan_control_mode)
3169 return -EOPNOTSUPP;
3170
3171 if (value == U32_MAX)
3172 return -EINVAL;
3173
3174 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
3175 if (ret)
3176 goto out;
3177
3178 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3179 smu->user_dpm_profile.fan_mode = value;
3180
3181 /* reset user dpm fan speed */
3182 if (value != AMD_FAN_CTRL_MANUAL) {
3183 smu->user_dpm_profile.fan_speed_pwm = 0;
3184 smu->user_dpm_profile.fan_speed_rpm = 0;
3185 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
3186 }
3187 }
3188
3189 out:
3190 return ret;
3191 }
3192
smu_get_fan_speed_pwm(void * handle,u32 * speed)3193 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
3194 {
3195 struct smu_context *smu = handle;
3196 int ret = 0;
3197
3198 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3199 return -EOPNOTSUPP;
3200
3201 if (!smu->ppt_funcs->get_fan_speed_pwm)
3202 return -EOPNOTSUPP;
3203
3204 if (!speed)
3205 return -EINVAL;
3206
3207 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
3208
3209 return ret;
3210 }
3211
smu_set_fan_speed_pwm(void * handle,u32 speed)3212 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
3213 {
3214 struct smu_context *smu = handle;
3215 int ret = 0;
3216
3217 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3218 return -EOPNOTSUPP;
3219
3220 if (!smu->ppt_funcs->set_fan_speed_pwm)
3221 return -EOPNOTSUPP;
3222
3223 if (speed == U32_MAX)
3224 return -EINVAL;
3225
3226 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
3227 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3228 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
3229 smu->user_dpm_profile.fan_speed_pwm = speed;
3230
3231 /* Override custom RPM setting as they cannot co-exist */
3232 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
3233 smu->user_dpm_profile.fan_speed_rpm = 0;
3234 }
3235
3236 return ret;
3237 }
3238
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)3239 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
3240 {
3241 struct smu_context *smu = handle;
3242 int ret = 0;
3243
3244 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3245 return -EOPNOTSUPP;
3246
3247 if (!smu->ppt_funcs->get_fan_speed_rpm)
3248 return -EOPNOTSUPP;
3249
3250 if (!speed)
3251 return -EINVAL;
3252
3253 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
3254
3255 return ret;
3256 }
3257
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)3258 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
3259 {
3260 struct smu_context *smu = handle;
3261
3262 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3263 return -EOPNOTSUPP;
3264
3265 return smu_set_min_dcef_deep_sleep(smu, clk);
3266 }
3267
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)3268 static int smu_get_clock_by_type_with_latency(void *handle,
3269 enum amd_pp_clock_type type,
3270 struct pp_clock_levels_with_latency *clocks)
3271 {
3272 struct smu_context *smu = handle;
3273 enum smu_clk_type clk_type;
3274 int ret = 0;
3275
3276 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3277 return -EOPNOTSUPP;
3278
3279 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
3280 switch (type) {
3281 case amd_pp_sys_clock:
3282 clk_type = SMU_GFXCLK;
3283 break;
3284 case amd_pp_mem_clock:
3285 clk_type = SMU_MCLK;
3286 break;
3287 case amd_pp_dcef_clock:
3288 clk_type = SMU_DCEFCLK;
3289 break;
3290 case amd_pp_disp_clock:
3291 clk_type = SMU_DISPCLK;
3292 break;
3293 default:
3294 dev_err(smu->adev->dev, "Invalid clock type!\n");
3295 return -EINVAL;
3296 }
3297
3298 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
3299 }
3300
3301 return ret;
3302 }
3303
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)3304 static int smu_display_clock_voltage_request(void *handle,
3305 struct pp_display_clock_request *clock_req)
3306 {
3307 struct smu_context *smu = handle;
3308 int ret = 0;
3309
3310 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3311 return -EOPNOTSUPP;
3312
3313 if (smu->ppt_funcs->display_clock_voltage_request)
3314 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
3315
3316 return ret;
3317 }
3318
3319
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)3320 static int smu_display_disable_memory_clock_switch(void *handle,
3321 bool disable_memory_clock_switch)
3322 {
3323 struct smu_context *smu = handle;
3324 int ret = -EINVAL;
3325
3326 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3327 return -EOPNOTSUPP;
3328
3329 if (smu->ppt_funcs->display_disable_memory_clock_switch)
3330 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
3331
3332 return ret;
3333 }
3334
smu_set_xgmi_pstate(void * handle,uint32_t pstate)3335 static int smu_set_xgmi_pstate(void *handle,
3336 uint32_t pstate)
3337 {
3338 struct smu_context *smu = handle;
3339 int ret = 0;
3340
3341 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3342 return -EOPNOTSUPP;
3343
3344 if (smu->ppt_funcs->set_xgmi_pstate)
3345 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
3346
3347 if (ret)
3348 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
3349
3350 return ret;
3351 }
3352
smu_get_baco_capability(void * handle)3353 static int smu_get_baco_capability(void *handle)
3354 {
3355 struct smu_context *smu = handle;
3356
3357 if (!smu->pm_enabled)
3358 return false;
3359
3360 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support)
3361 return false;
3362
3363 return smu->ppt_funcs->get_bamaco_support(smu);
3364 }
3365
smu_baco_set_state(void * handle,int state)3366 static int smu_baco_set_state(void *handle, int state)
3367 {
3368 struct smu_context *smu = handle;
3369 int ret = 0;
3370
3371 if (!smu->pm_enabled)
3372 return -EOPNOTSUPP;
3373
3374 if (state == 0) {
3375 if (smu->ppt_funcs->baco_exit)
3376 ret = smu->ppt_funcs->baco_exit(smu);
3377 } else if (state == 1) {
3378 if (smu->ppt_funcs->baco_enter)
3379 ret = smu->ppt_funcs->baco_enter(smu);
3380 } else {
3381 return -EINVAL;
3382 }
3383
3384 if (ret)
3385 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
3386 (state)?"enter":"exit");
3387
3388 return ret;
3389 }
3390
smu_mode1_reset_is_support(struct smu_context * smu)3391 bool smu_mode1_reset_is_support(struct smu_context *smu)
3392 {
3393 bool ret = false;
3394
3395 if (!smu->pm_enabled)
3396 return false;
3397
3398 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
3399 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
3400
3401 return ret;
3402 }
3403
smu_mode2_reset_is_support(struct smu_context * smu)3404 bool smu_mode2_reset_is_support(struct smu_context *smu)
3405 {
3406 bool ret = false;
3407
3408 if (!smu->pm_enabled)
3409 return false;
3410
3411 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
3412 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
3413
3414 return ret;
3415 }
3416
smu_mode1_reset(struct smu_context * smu)3417 int smu_mode1_reset(struct smu_context *smu)
3418 {
3419 int ret = 0;
3420
3421 if (!smu->pm_enabled)
3422 return -EOPNOTSUPP;
3423
3424 if (smu->ppt_funcs->mode1_reset)
3425 ret = smu->ppt_funcs->mode1_reset(smu);
3426
3427 return ret;
3428 }
3429
smu_mode2_reset(void * handle)3430 static int smu_mode2_reset(void *handle)
3431 {
3432 struct smu_context *smu = handle;
3433 int ret = 0;
3434
3435 if (!smu->pm_enabled)
3436 return -EOPNOTSUPP;
3437
3438 if (smu->ppt_funcs->mode2_reset)
3439 ret = smu->ppt_funcs->mode2_reset(smu);
3440
3441 if (ret)
3442 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
3443
3444 return ret;
3445 }
3446
smu_enable_gfx_features(void * handle)3447 static int smu_enable_gfx_features(void *handle)
3448 {
3449 struct smu_context *smu = handle;
3450 int ret = 0;
3451
3452 if (!smu->pm_enabled)
3453 return -EOPNOTSUPP;
3454
3455 if (smu->ppt_funcs->enable_gfx_features)
3456 ret = smu->ppt_funcs->enable_gfx_features(smu);
3457
3458 if (ret)
3459 dev_err(smu->adev->dev, "enable gfx features failed!\n");
3460
3461 return ret;
3462 }
3463
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)3464 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
3465 struct pp_smu_nv_clock_table *max_clocks)
3466 {
3467 struct smu_context *smu = handle;
3468 int ret = 0;
3469
3470 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3471 return -EOPNOTSUPP;
3472
3473 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
3474 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
3475
3476 return ret;
3477 }
3478
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)3479 static int smu_get_uclk_dpm_states(void *handle,
3480 unsigned int *clock_values_in_khz,
3481 unsigned int *num_states)
3482 {
3483 struct smu_context *smu = handle;
3484 int ret = 0;
3485
3486 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3487 return -EOPNOTSUPP;
3488
3489 if (smu->ppt_funcs->get_uclk_dpm_states)
3490 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
3491
3492 return ret;
3493 }
3494
smu_get_current_power_state(void * handle)3495 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
3496 {
3497 struct smu_context *smu = handle;
3498 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
3499
3500 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3501 return -EOPNOTSUPP;
3502
3503 if (smu->ppt_funcs->get_current_power_state)
3504 pm_state = smu->ppt_funcs->get_current_power_state(smu);
3505
3506 return pm_state;
3507 }
3508
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)3509 static int smu_get_dpm_clock_table(void *handle,
3510 struct dpm_clocks *clock_table)
3511 {
3512 struct smu_context *smu = handle;
3513 int ret = 0;
3514
3515 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3516 return -EOPNOTSUPP;
3517
3518 if (smu->ppt_funcs->get_dpm_clock_table)
3519 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3520
3521 return ret;
3522 }
3523
smu_sys_get_gpu_metrics(void * handle,void ** table)3524 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3525 {
3526 struct smu_context *smu = handle;
3527
3528 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3529 return -EOPNOTSUPP;
3530
3531 if (!smu->ppt_funcs->get_gpu_metrics)
3532 return -EOPNOTSUPP;
3533
3534 return smu->ppt_funcs->get_gpu_metrics(smu, table);
3535 }
3536
smu_sys_get_pm_metrics(void * handle,void * pm_metrics,size_t size)3537 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics,
3538 size_t size)
3539 {
3540 struct smu_context *smu = handle;
3541
3542 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3543 return -EOPNOTSUPP;
3544
3545 if (!smu->ppt_funcs->get_pm_metrics)
3546 return -EOPNOTSUPP;
3547
3548 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size);
3549 }
3550
smu_enable_mgpu_fan_boost(void * handle)3551 static int smu_enable_mgpu_fan_boost(void *handle)
3552 {
3553 struct smu_context *smu = handle;
3554 int ret = 0;
3555
3556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3557 return -EOPNOTSUPP;
3558
3559 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3560 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3561
3562 return ret;
3563 }
3564
smu_gfx_state_change_set(void * handle,uint32_t state)3565 static int smu_gfx_state_change_set(void *handle,
3566 uint32_t state)
3567 {
3568 struct smu_context *smu = handle;
3569 int ret = 0;
3570
3571 if (smu->ppt_funcs->gfx_state_change_set)
3572 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3573
3574 return ret;
3575 }
3576
smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)3577 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
3578 {
3579 int ret = 0;
3580
3581 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3582 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
3583
3584 return ret;
3585 }
3586
smu_get_ecc_info(struct smu_context * smu,void * umc_ecc)3587 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
3588 {
3589 int ret = -EOPNOTSUPP;
3590
3591 if (smu->ppt_funcs &&
3592 smu->ppt_funcs->get_ecc_info)
3593 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3594
3595 return ret;
3596
3597 }
3598
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3599 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3600 {
3601 struct smu_context *smu = handle;
3602 struct smu_table_context *smu_table = &smu->smu_table;
3603 struct smu_table *memory_pool = &smu_table->memory_pool;
3604
3605 if (!addr || !size)
3606 return -EINVAL;
3607
3608 *addr = NULL;
3609 *size = 0;
3610 if (memory_pool->bo) {
3611 *addr = memory_pool->cpu_addr;
3612 *size = memory_pool->size;
3613 }
3614
3615 return 0;
3616 }
3617
smu_print_dpm_policy(struct smu_dpm_policy * policy,char * sysbuf,size_t * size)3618 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf,
3619 size_t *size)
3620 {
3621 size_t offset = *size;
3622 int level;
3623
3624 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) {
3625 if (level == policy->current_level)
3626 offset += sysfs_emit_at(sysbuf, offset,
3627 "%d : %s*\n", level,
3628 policy->desc->get_desc(policy, level));
3629 else
3630 offset += sysfs_emit_at(sysbuf, offset,
3631 "%d : %s\n", level,
3632 policy->desc->get_desc(policy, level));
3633 }
3634
3635 *size = offset;
3636 }
3637
smu_get_pm_policy_info(struct smu_context * smu,enum pp_pm_policy p_type,char * sysbuf)3638 ssize_t smu_get_pm_policy_info(struct smu_context *smu,
3639 enum pp_pm_policy p_type, char *sysbuf)
3640 {
3641 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3642 struct smu_dpm_policy_ctxt *policy_ctxt;
3643 struct smu_dpm_policy *dpm_policy;
3644 size_t offset = 0;
3645
3646 policy_ctxt = dpm_ctxt->dpm_policies;
3647 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt ||
3648 !policy_ctxt->policy_mask)
3649 return -EOPNOTSUPP;
3650
3651 if (p_type == PP_PM_POLICY_NONE)
3652 return -EINVAL;
3653
3654 dpm_policy = smu_get_pm_policy(smu, p_type);
3655 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc)
3656 return -ENOENT;
3657
3658 if (!sysbuf)
3659 return -EINVAL;
3660
3661 smu_print_dpm_policy(dpm_policy, sysbuf, &offset);
3662
3663 return offset;
3664 }
3665
smu_get_pm_policy(struct smu_context * smu,enum pp_pm_policy p_type)3666 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu,
3667 enum pp_pm_policy p_type)
3668 {
3669 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3670 struct smu_dpm_policy_ctxt *policy_ctxt;
3671 int i;
3672
3673 policy_ctxt = dpm_ctxt->dpm_policies;
3674 if (!policy_ctxt)
3675 return NULL;
3676
3677 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) {
3678 if (policy_ctxt->policies[i].policy_type == p_type)
3679 return &policy_ctxt->policies[i];
3680 }
3681
3682 return NULL;
3683 }
3684
smu_set_pm_policy(struct smu_context * smu,enum pp_pm_policy p_type,int level)3685 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
3686 int level)
3687 {
3688 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3689 struct smu_dpm_policy *dpm_policy = NULL;
3690 struct smu_dpm_policy_ctxt *policy_ctxt;
3691 int ret = -EOPNOTSUPP;
3692
3693 policy_ctxt = dpm_ctxt->dpm_policies;
3694 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt ||
3695 !policy_ctxt->policy_mask)
3696 return ret;
3697
3698 if (level < 0 || level >= PP_POLICY_MAX_LEVELS)
3699 return -EINVAL;
3700
3701 dpm_policy = smu_get_pm_policy(smu, p_type);
3702
3703 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy)
3704 return ret;
3705
3706 if (dpm_policy->current_level == level)
3707 return 0;
3708
3709 ret = dpm_policy->set_policy(smu, level);
3710
3711 if (!ret)
3712 dpm_policy->current_level = level;
3713
3714 return ret;
3715 }
3716
3717 static const struct amd_pm_funcs swsmu_pm_funcs = {
3718 /* export for sysfs */
3719 .set_fan_control_mode = smu_set_fan_control_mode,
3720 .get_fan_control_mode = smu_get_fan_control_mode,
3721 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3722 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3723 .force_clock_level = smu_force_ppclk_levels,
3724 .print_clock_levels = smu_print_ppclk_levels,
3725 .emit_clock_levels = smu_emit_ppclk_levels,
3726 .force_performance_level = smu_force_performance_level,
3727 .read_sensor = smu_read_sensor,
3728 .get_apu_thermal_limit = smu_get_apu_thermal_limit,
3729 .set_apu_thermal_limit = smu_set_apu_thermal_limit,
3730 .get_performance_level = smu_get_performance_level,
3731 .get_current_power_state = smu_get_current_power_state,
3732 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3733 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3734 .get_pp_num_states = smu_get_power_num_states,
3735 .get_pp_table = smu_sys_get_pp_table,
3736 .set_pp_table = smu_sys_set_pp_table,
3737 .switch_power_profile = smu_switch_power_profile,
3738 /* export to amdgpu */
3739 .dispatch_tasks = smu_handle_dpm_task,
3740 .load_firmware = smu_load_microcode,
3741 .set_powergating_by_smu = smu_dpm_set_power_gate,
3742 .set_power_limit = smu_set_power_limit,
3743 .get_power_limit = smu_get_power_limit,
3744 .get_power_profile_mode = smu_get_power_profile_mode,
3745 .set_power_profile_mode = smu_set_power_profile_mode,
3746 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3747 .set_mp1_state = smu_set_mp1_state,
3748 .gfx_state_change_set = smu_gfx_state_change_set,
3749 /* export to DC */
3750 .get_sclk = smu_get_sclk,
3751 .get_mclk = smu_get_mclk,
3752 .display_configuration_change = smu_display_configuration_change,
3753 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3754 .display_clock_voltage_request = smu_display_clock_voltage_request,
3755 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3756 .set_active_display_count = smu_set_display_count,
3757 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3758 .get_asic_baco_capability = smu_get_baco_capability,
3759 .set_asic_baco_state = smu_baco_set_state,
3760 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3761 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3762 .asic_reset_mode_2 = smu_mode2_reset,
3763 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3764 .set_df_cstate = smu_set_df_cstate,
3765 .set_xgmi_pstate = smu_set_xgmi_pstate,
3766 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3767 .get_pm_metrics = smu_sys_get_pm_metrics,
3768 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3769 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3770 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3771 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3772 .get_dpm_clock_table = smu_get_dpm_clock_table,
3773 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3774 };
3775
smu_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)3776 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3777 uint64_t event_arg)
3778 {
3779 int ret = -EINVAL;
3780
3781 if (smu->ppt_funcs->wait_for_event)
3782 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3783
3784 return ret;
3785 }
3786
smu_stb_collect_info(struct smu_context * smu,void * buf,uint32_t size)3787 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3788 {
3789
3790 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3791 return -EOPNOTSUPP;
3792
3793 /* Confirm the buffer allocated is of correct size */
3794 if (size != smu->stb_context.stb_buf_size)
3795 return -EINVAL;
3796
3797 /*
3798 * No need to lock smu mutex as we access STB directly through MMIO
3799 * and not going through SMU messaging route (for now at least).
3800 * For registers access rely on implementation internal locking.
3801 */
3802 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3803 }
3804
3805 #if defined(CONFIG_DEBUG_FS)
3806
smu_stb_debugfs_open(struct inode * inode,struct file * filp)3807 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3808 {
3809 struct amdgpu_device *adev = filp->f_inode->i_private;
3810 struct smu_context *smu = adev->powerplay.pp_handle;
3811 unsigned char *buf;
3812 int r;
3813
3814 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3815 if (!buf)
3816 return -ENOMEM;
3817
3818 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3819 if (r)
3820 goto out;
3821
3822 filp->private_data = buf;
3823
3824 return 0;
3825
3826 out:
3827 kvfree(buf);
3828 return r;
3829 }
3830
smu_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)3831 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3832 loff_t *pos)
3833 {
3834 struct amdgpu_device *adev = filp->f_inode->i_private;
3835 struct smu_context *smu = adev->powerplay.pp_handle;
3836
3837
3838 if (!filp->private_data)
3839 return -EINVAL;
3840
3841 return simple_read_from_buffer(buf,
3842 size,
3843 pos, filp->private_data,
3844 smu->stb_context.stb_buf_size);
3845 }
3846
smu_stb_debugfs_release(struct inode * inode,struct file * filp)3847 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3848 {
3849 kvfree(filp->private_data);
3850 filp->private_data = NULL;
3851
3852 return 0;
3853 }
3854
3855 /*
3856 * We have to define not only read method but also
3857 * open and release because .read takes up to PAGE_SIZE
3858 * data each time so and so is invoked multiple times.
3859 * We allocate the STB buffer in .open and release it
3860 * in .release
3861 */
3862 static const struct file_operations smu_stb_debugfs_fops = {
3863 .owner = THIS_MODULE,
3864 .open = smu_stb_debugfs_open,
3865 .read = smu_stb_debugfs_read,
3866 .release = smu_stb_debugfs_release,
3867 .llseek = default_llseek,
3868 };
3869
3870 #endif
3871
amdgpu_smu_stb_debug_fs_init(struct amdgpu_device * adev)3872 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3873 {
3874 #if defined(CONFIG_DEBUG_FS)
3875
3876 struct smu_context *smu = adev->powerplay.pp_handle;
3877
3878 if (!smu || (!smu->stb_context.stb_buf_size))
3879 return;
3880
3881 debugfs_create_file_size("amdgpu_smu_stb_dump",
3882 S_IRUSR,
3883 adev_to_drm(adev)->primary->debugfs_root,
3884 adev,
3885 &smu_stb_debugfs_fops,
3886 smu->stb_context.stb_buf_size);
3887 #endif
3888 }
3889
smu_send_hbm_bad_pages_num(struct smu_context * smu,uint32_t size)3890 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3891 {
3892 int ret = 0;
3893
3894 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3895 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3896
3897 return ret;
3898 }
3899
smu_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)3900 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3901 {
3902 int ret = 0;
3903
3904 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3905 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3906
3907 return ret;
3908 }
3909
smu_send_rma_reason(struct smu_context * smu)3910 int smu_send_rma_reason(struct smu_context *smu)
3911 {
3912 int ret = 0;
3913
3914 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
3915 ret = smu->ppt_funcs->send_rma_reason(smu);
3916
3917 return ret;
3918 }
3919
smu_reset_sdma(struct smu_context * smu,uint32_t inst_mask)3920 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
3921 {
3922 int ret = 0;
3923
3924 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma)
3925 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask);
3926
3927 return ret;
3928 }
3929