1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27 #include <linux/power_supply.h>
28 #include <linux/reboot.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
33 #include "atom.h"
34 #include "arcturus_ppt.h"
35 #include "navi10_ppt.h"
36 #include "sienna_cichlid_ppt.h"
37 #include "renoir_ppt.h"
38 #include "vangogh_ppt.h"
39 #include "aldebaran_ppt.h"
40 #include "yellow_carp_ppt.h"
41 #include "cyan_skillfish_ppt.h"
42 #include "smu_v13_0_0_ppt.h"
43 #include "smu_v13_0_4_ppt.h"
44 #include "smu_v13_0_5_ppt.h"
45 #include "smu_v13_0_6_ppt.h"
46 #include "smu_v13_0_7_ppt.h"
47 #include "smu_v14_0_0_ppt.h"
48 #include "smu_v14_0_2_ppt.h"
49 #include "smu_v15_0_0_ppt.h"
50 #include "amd_pcie.h"
51
52 /*
53 * DO NOT use these for err/warn/info/debug messages.
54 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
55 * They are more MGPU friendly.
56 */
57 #undef pr_err
58 #undef pr_warn
59 #undef pr_info
60 #undef pr_debug
61
62 static const struct amd_pm_funcs swsmu_pm_funcs;
63 static int smu_force_smuclk_levels(struct smu_context *smu,
64 enum smu_clk_type clk_type,
65 uint32_t mask);
66 static int smu_handle_task(struct smu_context *smu,
67 enum amd_dpm_forced_level level,
68 enum amd_pp_task task_id);
69 static int smu_reset(struct smu_context *smu);
70 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
71 static int smu_set_fan_control_mode(void *handle, u32 value);
72 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit);
73 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
74 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
75 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
76 static void smu_power_profile_mode_get(struct smu_context *smu,
77 enum PP_SMC_POWER_PROFILE profile_mode);
78 static void smu_power_profile_mode_put(struct smu_context *smu,
79 enum PP_SMC_POWER_PROFILE profile_mode);
80 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type);
81 static int smu_od_edit_dpm_table(void *handle,
82 enum PP_OD_DPM_TABLE_COMMAND type,
83 long *input, uint32_t size);
84
smu_sys_get_pp_feature_mask(void * handle,char * buf)85 static int smu_sys_get_pp_feature_mask(void *handle,
86 char *buf)
87 {
88 struct smu_context *smu = handle;
89
90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
91 return -EOPNOTSUPP;
92
93 return smu_get_pp_feature_mask(smu, buf);
94 }
95
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)96 static int smu_sys_set_pp_feature_mask(void *handle,
97 uint64_t new_mask)
98 {
99 struct smu_context *smu = handle;
100
101 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
102 return -EOPNOTSUPP;
103
104 return smu_set_pp_feature_mask(smu, new_mask);
105 }
106
smu_set_residency_gfxoff(struct smu_context * smu,bool value)107 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
108 {
109 if (!smu->ppt_funcs->set_gfx_off_residency)
110 return -EINVAL;
111
112 return smu_set_gfx_off_residency(smu, value);
113 }
114
smu_get_residency_gfxoff(struct smu_context * smu,u32 * value)115 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
116 {
117 if (!smu->ppt_funcs->get_gfx_off_residency)
118 return -EINVAL;
119
120 return smu_get_gfx_off_residency(smu, value);
121 }
122
smu_get_entrycount_gfxoff(struct smu_context * smu,u64 * value)123 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
124 {
125 if (!smu->ppt_funcs->get_gfx_off_entrycount)
126 return -EINVAL;
127
128 return smu_get_gfx_off_entrycount(smu, value);
129 }
130
smu_get_status_gfxoff(struct smu_context * smu,uint32_t * value)131 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
132 {
133 if (!smu->ppt_funcs->get_gfx_off_status)
134 return -EINVAL;
135
136 *value = smu_get_gfx_off_status(smu);
137
138 return 0;
139 }
140
smu_set_soft_freq_range(struct smu_context * smu,enum pp_clock_type type,uint32_t min,uint32_t max)141 int smu_set_soft_freq_range(struct smu_context *smu,
142 enum pp_clock_type type,
143 uint32_t min,
144 uint32_t max)
145 {
146 enum smu_clk_type clk_type;
147 int ret = 0;
148
149 clk_type = smu_convert_to_smuclk(type);
150 if (clk_type == SMU_CLK_COUNT)
151 return -EINVAL;
152
153 if (smu->ppt_funcs->set_soft_freq_limited_range)
154 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
155 clk_type,
156 min,
157 max,
158 false);
159
160 return ret;
161 }
162
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)163 int smu_get_dpm_freq_range(struct smu_context *smu,
164 enum smu_clk_type clk_type,
165 uint32_t *min,
166 uint32_t *max)
167 {
168 int ret = -ENOTSUPP;
169
170 if (!min && !max)
171 return -EINVAL;
172
173 if (smu->ppt_funcs->get_dpm_ultimate_freq)
174 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
175 clk_type,
176 min,
177 max);
178
179 return ret;
180 }
181
smu_set_gfx_power_up_by_imu(struct smu_context * smu)182 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
183 {
184 int ret = 0;
185 struct amdgpu_device *adev = smu->adev;
186
187 if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
188 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
189 if (ret)
190 dev_err(adev->dev, "Failed to enable gfx imu!\n");
191 }
192 return ret;
193 }
194
smu_get_mclk(void * handle,bool low)195 static u32 smu_get_mclk(void *handle, bool low)
196 {
197 struct smu_context *smu = handle;
198 uint32_t clk_freq;
199 int ret = 0;
200
201 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
202 low ? &clk_freq : NULL,
203 !low ? &clk_freq : NULL);
204 if (ret)
205 return 0;
206 return clk_freq * 100;
207 }
208
smu_get_sclk(void * handle,bool low)209 static u32 smu_get_sclk(void *handle, bool low)
210 {
211 struct smu_context *smu = handle;
212 uint32_t clk_freq;
213 int ret = 0;
214
215 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
216 low ? &clk_freq : NULL,
217 !low ? &clk_freq : NULL);
218 if (ret)
219 return 0;
220 return clk_freq * 100;
221 }
222
smu_set_gfx_imu_enable(struct smu_context * smu)223 static int smu_set_gfx_imu_enable(struct smu_context *smu)
224 {
225 struct amdgpu_device *adev = smu->adev;
226
227 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
228 return 0;
229
230 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
231 return 0;
232
233 return smu_set_gfx_power_up_by_imu(smu);
234 }
235
is_vcn_enabled(struct amdgpu_device * adev)236 static bool is_vcn_enabled(struct amdgpu_device *adev)
237 {
238 int i;
239
240 for (i = 0; i < adev->num_ip_blocks; i++) {
241 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN ||
242 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) &&
243 !adev->ip_blocks[i].status.valid)
244 return false;
245 }
246
247 return true;
248 }
249
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)250 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
251 bool enable,
252 int inst)
253 {
254 struct smu_power_context *smu_power = &smu->smu_power;
255 struct smu_power_gate *power_gate = &smu_power->power_gate;
256 int ret = 0;
257
258 /*
259 * don't poweron vcn/jpeg when they are skipped.
260 */
261 if (!is_vcn_enabled(smu->adev))
262 return 0;
263
264 if (!smu->ppt_funcs->dpm_set_vcn_enable)
265 return 0;
266
267 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
268 return 0;
269
270 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
271 if (!ret)
272 atomic_set(&power_gate->vcn_gated[inst], !enable);
273
274 return ret;
275 }
276
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)277 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
278 bool enable)
279 {
280 struct smu_power_context *smu_power = &smu->smu_power;
281 struct smu_power_gate *power_gate = &smu_power->power_gate;
282 int ret = 0;
283
284 if (!is_vcn_enabled(smu->adev))
285 return 0;
286
287 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
288 return 0;
289
290 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
291 return 0;
292
293 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
294 if (!ret)
295 atomic_set(&power_gate->jpeg_gated, !enable);
296
297 return ret;
298 }
299
smu_dpm_set_vpe_enable(struct smu_context * smu,bool enable)300 static int smu_dpm_set_vpe_enable(struct smu_context *smu,
301 bool enable)
302 {
303 struct smu_power_context *smu_power = &smu->smu_power;
304 struct smu_power_gate *power_gate = &smu_power->power_gate;
305 int ret = 0;
306
307 if (!smu->ppt_funcs->dpm_set_vpe_enable)
308 return 0;
309
310 if (atomic_read(&power_gate->vpe_gated) ^ enable)
311 return 0;
312
313 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable);
314 if (!ret)
315 atomic_set(&power_gate->vpe_gated, !enable);
316
317 return ret;
318 }
319
smu_dpm_set_isp_enable(struct smu_context * smu,bool enable)320 static int smu_dpm_set_isp_enable(struct smu_context *smu,
321 bool enable)
322 {
323 struct smu_power_context *smu_power = &smu->smu_power;
324 struct smu_power_gate *power_gate = &smu_power->power_gate;
325 int ret;
326
327 if (!smu->ppt_funcs->dpm_set_isp_enable)
328 return 0;
329
330 if (atomic_read(&power_gate->isp_gated) ^ enable)
331 return 0;
332
333 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable);
334 if (!ret)
335 atomic_set(&power_gate->isp_gated, !enable);
336
337 return ret;
338 }
339
smu_dpm_set_umsch_mm_enable(struct smu_context * smu,bool enable)340 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu,
341 bool enable)
342 {
343 struct smu_power_context *smu_power = &smu->smu_power;
344 struct smu_power_gate *power_gate = &smu_power->power_gate;
345 int ret = 0;
346
347 if (!smu->adev->enable_umsch_mm)
348 return 0;
349
350 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable)
351 return 0;
352
353 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable)
354 return 0;
355
356 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable);
357 if (!ret)
358 atomic_set(&power_gate->umsch_mm_gated, !enable);
359
360 return ret;
361 }
362
smu_set_mall_enable(struct smu_context * smu)363 static int smu_set_mall_enable(struct smu_context *smu)
364 {
365 int ret = 0;
366
367 if (!smu->ppt_funcs->set_mall_enable)
368 return 0;
369
370 ret = smu->ppt_funcs->set_mall_enable(smu);
371
372 return ret;
373 }
374
375 /**
376 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
377 *
378 * @handle: smu_context pointer
379 * @block_type: the IP block to power gate/ungate
380 * @gate: to power gate if true, ungate otherwise
381 * @inst: the instance of the IP block to power gate/ungate
382 *
383 * This API uses no smu->mutex lock protection due to:
384 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
385 * This is guarded to be race condition free by the caller.
386 * 2. Or get called on user setting request of power_dpm_force_performance_level.
387 * Under this case, the smu->mutex lock protection is already enforced on
388 * the parent API smu_force_performance_level of the call path.
389 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate,int inst)390 static int smu_dpm_set_power_gate(void *handle,
391 uint32_t block_type,
392 bool gate,
393 int inst)
394 {
395 struct smu_context *smu = handle;
396 int ret = 0;
397
398 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
399 dev_WARN(smu->adev->dev,
400 "SMU uninitialized but power %s requested for %u!\n",
401 gate ? "gate" : "ungate", block_type);
402 return -EOPNOTSUPP;
403 }
404
405 switch (block_type) {
406 /*
407 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
408 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
409 */
410 case AMD_IP_BLOCK_TYPE_UVD:
411 case AMD_IP_BLOCK_TYPE_VCN:
412 ret = smu_dpm_set_vcn_enable(smu, !gate, inst);
413 if (ret)
414 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
415 gate ? "gate" : "ungate", inst);
416 break;
417 case AMD_IP_BLOCK_TYPE_GFX:
418 ret = smu_gfx_off_control(smu, gate);
419 if (ret)
420 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
421 gate ? "enable" : "disable");
422 break;
423 case AMD_IP_BLOCK_TYPE_SDMA:
424 ret = smu_powergate_sdma(smu, gate);
425 if (ret)
426 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
427 gate ? "gate" : "ungate");
428 break;
429 case AMD_IP_BLOCK_TYPE_JPEG:
430 ret = smu_dpm_set_jpeg_enable(smu, !gate);
431 if (ret)
432 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
433 gate ? "gate" : "ungate");
434 break;
435 case AMD_IP_BLOCK_TYPE_VPE:
436 ret = smu_dpm_set_vpe_enable(smu, !gate);
437 if (ret)
438 dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
439 gate ? "gate" : "ungate");
440 break;
441 case AMD_IP_BLOCK_TYPE_ISP:
442 ret = smu_dpm_set_isp_enable(smu, !gate);
443 if (ret)
444 dev_err(smu->adev->dev, "Failed to power %s ISP!\n",
445 gate ? "gate" : "ungate");
446 break;
447 default:
448 dev_err(smu->adev->dev, "Unsupported block type!\n");
449 return -EINVAL;
450 }
451
452 return ret;
453 }
454
455 /**
456 * smu_set_user_clk_dependencies - set user profile clock dependencies
457 *
458 * @smu: smu_context pointer
459 * @clk: enum smu_clk_type type
460 *
461 * Enable/Disable the clock dependency for the @clk type.
462 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)463 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
464 {
465 if (smu->adev->in_suspend)
466 return;
467
468 if (clk == SMU_MCLK) {
469 smu->user_dpm_profile.clk_dependency = 0;
470 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
471 } else if (clk == SMU_FCLK) {
472 /* MCLK takes precedence over FCLK */
473 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
474 return;
475
476 smu->user_dpm_profile.clk_dependency = 0;
477 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
478 } else if (clk == SMU_SOCCLK) {
479 /* MCLK takes precedence over SOCCLK */
480 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
481 return;
482
483 smu->user_dpm_profile.clk_dependency = 0;
484 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
485 } else
486 /* Add clk dependencies here, if any */
487 return;
488 }
489
490 /**
491 * smu_restore_dpm_user_profile - reinstate user dpm profile
492 *
493 * @smu: smu_context pointer
494 *
495 * Restore the saved user power configurations include power limit,
496 * clock frequencies, fan control mode and fan speed.
497 */
smu_restore_dpm_user_profile(struct smu_context * smu)498 static void smu_restore_dpm_user_profile(struct smu_context *smu)
499 {
500 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
501 int ret = 0;
502
503 if (!smu->adev->in_suspend)
504 return;
505
506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
507 return;
508
509 /* Enable restore flag */
510 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
511
512 /* set the user dpm power limits */
513 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) {
514 if (!smu->user_dpm_profile.power_limits[i])
515 continue;
516 ret = smu_set_power_limit(smu, i,
517 smu->user_dpm_profile.power_limits[i]);
518 if (ret)
519 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i);
520 }
521
522 /* set the user dpm clock configurations */
523 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
524 enum smu_clk_type clk_type;
525
526 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
527 /*
528 * Iterate over smu clk type and force the saved user clk
529 * configs, skip if clock dependency is enabled
530 */
531 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
532 smu->user_dpm_profile.clk_mask[clk_type]) {
533 ret = smu_force_smuclk_levels(smu, clk_type,
534 smu->user_dpm_profile.clk_mask[clk_type]);
535 if (ret)
536 dev_err(smu->adev->dev,
537 "Failed to set clock type = %d\n", clk_type);
538 }
539 }
540 }
541
542 /* set the user dpm fan configurations */
543 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
544 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
545 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
546 if (ret != -EOPNOTSUPP) {
547 smu->user_dpm_profile.fan_speed_pwm = 0;
548 smu->user_dpm_profile.fan_speed_rpm = 0;
549 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
550 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
551 }
552
553 if (smu->user_dpm_profile.fan_speed_pwm) {
554 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
555 if (ret != -EOPNOTSUPP)
556 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
557 }
558
559 if (smu->user_dpm_profile.fan_speed_rpm) {
560 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
561 if (ret != -EOPNOTSUPP)
562 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
563 }
564 }
565
566 /* Restore user customized OD settings */
567 if (smu->user_dpm_profile.user_od) {
568 if (smu->ppt_funcs->restore_user_od_settings) {
569 ret = smu->ppt_funcs->restore_user_od_settings(smu);
570 if (ret)
571 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
572 }
573 }
574
575 /* Disable restore flag */
576 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
577 }
578
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)579 static int smu_get_power_num_states(void *handle,
580 struct pp_states_info *state_info)
581 {
582 if (!state_info)
583 return -EINVAL;
584
585 /* not support power state */
586 memset(state_info, 0, sizeof(struct pp_states_info));
587 state_info->nums = 1;
588 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
589
590 return 0;
591 }
592
is_support_sw_smu(struct amdgpu_device * adev)593 bool is_support_sw_smu(struct amdgpu_device *adev)
594 {
595 /* vega20 is 11.0.2, but it's supported via the powerplay code */
596 if (adev->asic_type == CHIP_VEGA20)
597 return false;
598
599 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) &&
600 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC))
601 return true;
602
603 return false;
604 }
605
is_support_cclk_dpm(struct amdgpu_device * adev)606 bool is_support_cclk_dpm(struct amdgpu_device *adev)
607 {
608 struct smu_context *smu = adev->powerplay.pp_handle;
609
610 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
611 return false;
612
613 return true;
614 }
615
amdgpu_smu_ras_send_msg(struct amdgpu_device * adev,enum smu_message_type msg,uint32_t param,uint32_t * read_arg)616 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg,
617 uint32_t param, uint32_t *read_arg)
618 {
619 struct smu_context *smu = adev->powerplay.pp_handle;
620 int ret = -EOPNOTSUPP;
621
622 if (!smu)
623 return ret;
624
625 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg)
626 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg);
627
628 return ret;
629 }
630
smu_sys_get_pp_table(void * handle,char ** table)631 static int smu_sys_get_pp_table(void *handle,
632 char **table)
633 {
634 struct smu_context *smu = handle;
635 struct smu_table_context *smu_table = &smu->smu_table;
636
637 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
638 return -EOPNOTSUPP;
639
640 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
641 return -EOPNOTSUPP;
642
643 if (smu_table->hardcode_pptable)
644 *table = smu_table->hardcode_pptable;
645 else
646 *table = smu_table->power_play_table;
647
648 return smu_table->power_play_table_size;
649 }
650
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)651 static int smu_sys_set_pp_table(void *handle,
652 const char *buf,
653 size_t size)
654 {
655 struct smu_context *smu = handle;
656 struct smu_table_context *smu_table = &smu->smu_table;
657 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
658 int ret = 0;
659
660 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
661 return -EOPNOTSUPP;
662
663 if (header->usStructureSize != size) {
664 dev_err(smu->adev->dev, "pp table size not matched !\n");
665 return -EIO;
666 }
667
668 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) {
669 kfree(smu_table->hardcode_pptable);
670 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
671 if (!smu_table->hardcode_pptable)
672 return -ENOMEM;
673 }
674
675 memcpy(smu_table->hardcode_pptable, buf, size);
676 smu_table->power_play_table = smu_table->hardcode_pptable;
677 smu_table->power_play_table_size = size;
678
679 /*
680 * Special hw_fini action(for Navi1x, the DPMs disablement will be
681 * skipped) may be needed for custom pptable uploading.
682 */
683 smu->uploading_custom_pp_table = true;
684
685 ret = smu_reset(smu);
686 if (ret)
687 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
688
689 smu->uploading_custom_pp_table = false;
690
691 return ret;
692 }
693
smu_init_driver_allowed_feature_mask(struct smu_context * smu)694 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu)
695 {
696 /*
697 * With SCPM enabled, the allowed featuremasks setting(via
698 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
699 * That means there is no way to let PMFW knows the settings below.
700 * Thus, we just assume all the features are allowed under
701 * such scenario.
702 */
703 if (smu->adev->scpm_enabled) {
704 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
705 return 0;
706 }
707
708 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
709
710 return smu_init_allowed_features(smu);
711 }
712
smu_set_funcs(struct amdgpu_device * adev)713 static int smu_set_funcs(struct amdgpu_device *adev)
714 {
715 struct smu_context *smu = adev->powerplay.pp_handle;
716
717 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
718 smu->od_enabled = true;
719
720 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
721 case IP_VERSION(11, 0, 0):
722 case IP_VERSION(11, 0, 5):
723 case IP_VERSION(11, 0, 9):
724 navi10_set_ppt_funcs(smu);
725 break;
726 case IP_VERSION(11, 0, 7):
727 case IP_VERSION(11, 0, 11):
728 case IP_VERSION(11, 0, 12):
729 case IP_VERSION(11, 0, 13):
730 sienna_cichlid_set_ppt_funcs(smu);
731 break;
732 case IP_VERSION(12, 0, 0):
733 case IP_VERSION(12, 0, 1):
734 renoir_set_ppt_funcs(smu);
735 break;
736 case IP_VERSION(11, 5, 0):
737 case IP_VERSION(11, 5, 2):
738 vangogh_set_ppt_funcs(smu);
739 break;
740 case IP_VERSION(13, 0, 1):
741 case IP_VERSION(13, 0, 3):
742 case IP_VERSION(13, 0, 8):
743 yellow_carp_set_ppt_funcs(smu);
744 break;
745 case IP_VERSION(13, 0, 4):
746 case IP_VERSION(13, 0, 11):
747 smu_v13_0_4_set_ppt_funcs(smu);
748 break;
749 case IP_VERSION(13, 0, 5):
750 smu_v13_0_5_set_ppt_funcs(smu);
751 break;
752 case IP_VERSION(11, 0, 8):
753 cyan_skillfish_set_ppt_funcs(smu);
754 break;
755 case IP_VERSION(11, 0, 2):
756 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
757 arcturus_set_ppt_funcs(smu);
758 /* OD is not supported on Arcturus */
759 smu->od_enabled = false;
760 break;
761 case IP_VERSION(13, 0, 2):
762 aldebaran_set_ppt_funcs(smu);
763 /* Enable pp_od_clk_voltage node */
764 smu->od_enabled = true;
765 break;
766 case IP_VERSION(13, 0, 0):
767 case IP_VERSION(13, 0, 10):
768 smu_v13_0_0_set_ppt_funcs(smu);
769 break;
770 case IP_VERSION(13, 0, 6):
771 case IP_VERSION(13, 0, 14):
772 case IP_VERSION(13, 0, 12):
773 smu_v13_0_6_set_ppt_funcs(smu);
774 /* Enable pp_od_clk_voltage node */
775 smu->od_enabled = true;
776 break;
777 case IP_VERSION(13, 0, 7):
778 smu_v13_0_7_set_ppt_funcs(smu);
779 break;
780 case IP_VERSION(14, 0, 0):
781 case IP_VERSION(14, 0, 1):
782 case IP_VERSION(14, 0, 4):
783 case IP_VERSION(14, 0, 5):
784 smu_v14_0_0_set_ppt_funcs(smu);
785 break;
786 case IP_VERSION(14, 0, 2):
787 case IP_VERSION(14, 0, 3):
788 smu_v14_0_2_set_ppt_funcs(smu);
789 break;
790 case IP_VERSION(15, 0, 0):
791 smu_v15_0_0_set_ppt_funcs(smu);
792 break;
793 default:
794 return -EINVAL;
795 }
796
797 return 0;
798 }
799
smu_early_init(struct amdgpu_ip_block * ip_block)800 static int smu_early_init(struct amdgpu_ip_block *ip_block)
801 {
802 struct amdgpu_device *adev = ip_block->adev;
803 struct smu_context *smu;
804 int r;
805
806 smu = kzalloc_obj(struct smu_context);
807 if (!smu)
808 return -ENOMEM;
809
810 smu->adev = adev;
811 smu->pm_enabled = !!amdgpu_dpm;
812 smu->is_apu = false;
813 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
814 smu->smu_baco.platform_support = false;
815 smu->smu_baco.maco_support = false;
816 smu->user_dpm_profile.fan_mode = -1;
817 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN;
818
819 adev->powerplay.pp_handle = smu;
820 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
821
822 r = smu_set_funcs(adev);
823 if (r)
824 return r;
825 return smu_init_microcode(smu);
826 }
827
smu_set_default_dpm_table(struct smu_context * smu)828 static int smu_set_default_dpm_table(struct smu_context *smu)
829 {
830 struct amdgpu_device *adev = smu->adev;
831 struct smu_power_context *smu_power = &smu->smu_power;
832 struct smu_power_gate *power_gate = &smu_power->power_gate;
833 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i;
834 int ret = 0;
835
836 if (!smu->ppt_funcs->set_default_dpm_table)
837 return 0;
838
839 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
840 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
841 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]);
842 }
843 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
844 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
845
846 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
847 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
848 ret = smu_dpm_set_vcn_enable(smu, true, i);
849 if (ret)
850 return ret;
851 }
852 }
853
854 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
855 ret = smu_dpm_set_jpeg_enable(smu, true);
856 if (ret)
857 goto err_out;
858 }
859
860 ret = smu->ppt_funcs->set_default_dpm_table(smu);
861 if (ret)
862 dev_err(smu->adev->dev,
863 "Failed to setup default dpm clock tables!\n");
864
865 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
866 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
867 err_out:
868 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
869 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
870 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i);
871 }
872
873 return ret;
874 }
875
smu_apply_default_config_table_settings(struct smu_context * smu)876 static int smu_apply_default_config_table_settings(struct smu_context *smu)
877 {
878 struct amdgpu_device *adev = smu->adev;
879 int ret = 0;
880
881 ret = smu_get_default_config_table_settings(smu,
882 &adev->pm.config_table);
883 if (ret)
884 return ret;
885
886 return smu_set_config_table(smu, &adev->pm.config_table);
887 }
888
smu_late_init(struct amdgpu_ip_block * ip_block)889 static int smu_late_init(struct amdgpu_ip_block *ip_block)
890 {
891 struct amdgpu_device *adev = ip_block->adev;
892 struct smu_context *smu = adev->powerplay.pp_handle;
893 int ret = 0;
894
895 smu_set_fine_grain_gfx_freq_parameters(smu);
896
897 if (!smu->pm_enabled)
898 return 0;
899
900 ret = smu_post_init(smu);
901 if (ret) {
902 dev_err(adev->dev, "Failed to post smu init!\n");
903 return ret;
904 }
905
906 /*
907 * Explicitly notify PMFW the power mode the system in. Since
908 * the PMFW may boot the ASIC with a different mode.
909 * For those supporting ACDC switch via gpio, PMFW will
910 * handle the switch automatically. Driver involvement
911 * is unnecessary.
912 */
913 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
914 smu_set_ac_dc(smu);
915
916 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) ||
917 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3)))
918 return 0;
919
920 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
921 ret = smu_set_default_od_settings(smu);
922 if (ret) {
923 dev_err(adev->dev, "Failed to setup default OD settings!\n");
924 return ret;
925 }
926 }
927
928 ret = smu_populate_umd_state_clk(smu);
929 if (ret) {
930 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
931 return ret;
932 }
933
934 ret = smu_get_asic_power_limits(smu,
935 &smu->current_power_limit,
936 &smu->default_power_limit,
937 &smu->max_power_limit,
938 &smu->min_power_limit);
939 if (ret) {
940 dev_err(adev->dev, "Failed to get asic power limits!\n");
941 return ret;
942 }
943
944 if (!amdgpu_sriov_vf(adev))
945 smu_get_unique_id(smu);
946
947 smu_get_fan_parameters(smu);
948
949 smu_handle_task(smu,
950 smu->smu_dpm.dpm_level,
951 AMD_PP_TASK_COMPLETE_INIT);
952
953 ret = smu_apply_default_config_table_settings(smu);
954 if (ret && (ret != -EOPNOTSUPP)) {
955 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
956 return ret;
957 }
958
959 smu_restore_dpm_user_profile(smu);
960
961 return 0;
962 }
963
smu_init_fb_allocations(struct smu_context * smu)964 static int smu_init_fb_allocations(struct smu_context *smu)
965 {
966 struct amdgpu_device *adev = smu->adev;
967 struct smu_table_context *smu_table = &smu->smu_table;
968 struct smu_table *tables = smu_table->tables;
969 struct smu_table *driver_table = &(smu_table->driver_table);
970 uint32_t max_table_size = 0;
971 int ret, i;
972
973 /* VRAM allocation for tool table */
974 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
975 ret = amdgpu_bo_create_kernel(adev,
976 tables[SMU_TABLE_PMSTATUSLOG].size,
977 tables[SMU_TABLE_PMSTATUSLOG].align,
978 tables[SMU_TABLE_PMSTATUSLOG].domain,
979 &tables[SMU_TABLE_PMSTATUSLOG].bo,
980 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
981 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
982 if (ret) {
983 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
984 return ret;
985 }
986 }
987
988 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT;
989 /* VRAM allocation for driver table */
990 for (i = 0; i < SMU_TABLE_COUNT; i++) {
991 if (tables[i].size == 0)
992 continue;
993
994 /* If one of the tables has VRAM domain restriction, keep it in
995 * VRAM
996 */
997 if ((tables[i].domain &
998 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) ==
999 AMDGPU_GEM_DOMAIN_VRAM)
1000 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
1001
1002 if (i == SMU_TABLE_PMSTATUSLOG)
1003 continue;
1004
1005 if (max_table_size < tables[i].size)
1006 max_table_size = tables[i].size;
1007 }
1008
1009 driver_table->size = max_table_size;
1010 driver_table->align = PAGE_SIZE;
1011
1012 ret = amdgpu_bo_create_kernel(adev,
1013 driver_table->size,
1014 driver_table->align,
1015 driver_table->domain,
1016 &driver_table->bo,
1017 &driver_table->mc_address,
1018 &driver_table->cpu_addr);
1019 if (ret) {
1020 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
1021 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1022 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1023 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1024 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1025 }
1026
1027 return ret;
1028 }
1029
smu_fini_fb_allocations(struct smu_context * smu)1030 static int smu_fini_fb_allocations(struct smu_context *smu)
1031 {
1032 struct smu_table_context *smu_table = &smu->smu_table;
1033 struct smu_table *tables = smu_table->tables;
1034 struct smu_table *driver_table = &(smu_table->driver_table);
1035
1036 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
1037 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
1038 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
1039 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
1040
1041 amdgpu_bo_free_kernel(&driver_table->bo,
1042 &driver_table->mc_address,
1043 &driver_table->cpu_addr);
1044
1045 return 0;
1046 }
1047
smu_update_gpu_addresses(struct smu_context * smu)1048 static void smu_update_gpu_addresses(struct smu_context *smu)
1049 {
1050 struct smu_table_context *smu_table = &smu->smu_table;
1051 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG;
1052 struct smu_table *driver_table = &(smu_table->driver_table);
1053 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table;
1054
1055 if (pm_status_table->bo)
1056 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo);
1057 if (driver_table->bo)
1058 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo);
1059 if (dummy_read_1_table->bo)
1060 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo);
1061 }
1062
1063 /**
1064 * smu_alloc_memory_pool - allocate memory pool in the system memory
1065 *
1066 * @smu: amdgpu_device pointer
1067 *
1068 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
1069 * and DramLogSetDramAddr can notify it changed.
1070 *
1071 * Returns 0 on success, error on failure.
1072 */
smu_alloc_memory_pool(struct smu_context * smu)1073 static int smu_alloc_memory_pool(struct smu_context *smu)
1074 {
1075 struct amdgpu_device *adev = smu->adev;
1076 struct smu_table_context *smu_table = &smu->smu_table;
1077 struct smu_table *memory_pool = &smu_table->memory_pool;
1078 uint64_t pool_size = smu->pool_size;
1079 int ret = 0;
1080
1081 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
1082 return ret;
1083
1084 memory_pool->size = pool_size;
1085 memory_pool->align = PAGE_SIZE;
1086 memory_pool->domain =
1087 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ?
1088 AMDGPU_GEM_DOMAIN_VRAM :
1089 AMDGPU_GEM_DOMAIN_GTT;
1090
1091 switch (pool_size) {
1092 case SMU_MEMORY_POOL_SIZE_256_MB:
1093 case SMU_MEMORY_POOL_SIZE_512_MB:
1094 case SMU_MEMORY_POOL_SIZE_1_GB:
1095 case SMU_MEMORY_POOL_SIZE_2_GB:
1096 ret = amdgpu_bo_create_kernel(adev,
1097 memory_pool->size,
1098 memory_pool->align,
1099 memory_pool->domain,
1100 &memory_pool->bo,
1101 &memory_pool->mc_address,
1102 &memory_pool->cpu_addr);
1103 if (ret)
1104 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
1105 break;
1106 default:
1107 break;
1108 }
1109
1110 return ret;
1111 }
1112
smu_free_memory_pool(struct smu_context * smu)1113 static int smu_free_memory_pool(struct smu_context *smu)
1114 {
1115 struct smu_table_context *smu_table = &smu->smu_table;
1116 struct smu_table *memory_pool = &smu_table->memory_pool;
1117
1118 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
1119 return 0;
1120
1121 amdgpu_bo_free_kernel(&memory_pool->bo,
1122 &memory_pool->mc_address,
1123 &memory_pool->cpu_addr);
1124
1125 memset(memory_pool, 0, sizeof(struct smu_table));
1126
1127 return 0;
1128 }
1129
smu_alloc_dummy_read_table(struct smu_context * smu)1130 static int smu_alloc_dummy_read_table(struct smu_context *smu)
1131 {
1132 struct smu_table_context *smu_table = &smu->smu_table;
1133 struct smu_table *dummy_read_1_table =
1134 &smu_table->dummy_read_1_table;
1135 struct amdgpu_device *adev = smu->adev;
1136 int ret = 0;
1137
1138 if (!dummy_read_1_table->size)
1139 return 0;
1140
1141 ret = amdgpu_bo_create_kernel(adev,
1142 dummy_read_1_table->size,
1143 dummy_read_1_table->align,
1144 dummy_read_1_table->domain,
1145 &dummy_read_1_table->bo,
1146 &dummy_read_1_table->mc_address,
1147 &dummy_read_1_table->cpu_addr);
1148 if (ret)
1149 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
1150
1151 return ret;
1152 }
1153
smu_free_dummy_read_table(struct smu_context * smu)1154 static void smu_free_dummy_read_table(struct smu_context *smu)
1155 {
1156 struct smu_table_context *smu_table = &smu->smu_table;
1157 struct smu_table *dummy_read_1_table =
1158 &smu_table->dummy_read_1_table;
1159
1160
1161 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
1162 &dummy_read_1_table->mc_address,
1163 &dummy_read_1_table->cpu_addr);
1164
1165 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
1166 }
1167
smu_smc_table_sw_init(struct smu_context * smu)1168 static int smu_smc_table_sw_init(struct smu_context *smu)
1169 {
1170 int ret;
1171
1172 /**
1173 * Create smu_table structure, and init smc tables such as
1174 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
1175 */
1176 ret = smu_init_smc_tables(smu);
1177 if (ret) {
1178 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
1179 return ret;
1180 }
1181
1182 /**
1183 * Create smu_power_context structure, and allocate smu_dpm_context and
1184 * context size to fill the smu_power_context data.
1185 */
1186 ret = smu_init_power(smu);
1187 if (ret) {
1188 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1189 return ret;
1190 }
1191
1192 /*
1193 * allocate vram bos to store smc table contents.
1194 */
1195 ret = smu_init_fb_allocations(smu);
1196 if (ret)
1197 return ret;
1198
1199 ret = smu_alloc_memory_pool(smu);
1200 if (ret)
1201 return ret;
1202
1203 ret = smu_alloc_dummy_read_table(smu);
1204 if (ret)
1205 return ret;
1206
1207 ret = smu_i2c_init(smu);
1208 if (ret)
1209 return ret;
1210
1211 return 0;
1212 }
1213
smu_smc_table_sw_fini(struct smu_context * smu)1214 static int smu_smc_table_sw_fini(struct smu_context *smu)
1215 {
1216 int ret;
1217
1218 smu_i2c_fini(smu);
1219
1220 smu_free_dummy_read_table(smu);
1221
1222 ret = smu_free_memory_pool(smu);
1223 if (ret)
1224 return ret;
1225
1226 ret = smu_fini_fb_allocations(smu);
1227 if (ret)
1228 return ret;
1229
1230 ret = smu_fini_power(smu);
1231 if (ret) {
1232 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1233 return ret;
1234 }
1235
1236 ret = smu_fini_smc_tables(smu);
1237 if (ret) {
1238 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1239 return ret;
1240 }
1241
1242 return 0;
1243 }
1244
smu_throttling_logging_work_fn(struct work_struct * work)1245 static void smu_throttling_logging_work_fn(struct work_struct *work)
1246 {
1247 struct smu_context *smu = container_of(work, struct smu_context,
1248 throttling_logging_work);
1249
1250 smu_log_thermal_throttling(smu);
1251 }
1252
smu_interrupt_work_fn(struct work_struct * work)1253 static void smu_interrupt_work_fn(struct work_struct *work)
1254 {
1255 struct smu_context *smu = container_of(work, struct smu_context,
1256 interrupt_work);
1257
1258 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1259 smu->ppt_funcs->interrupt_work(smu);
1260 }
1261
smu_swctf_delayed_work_handler(struct work_struct * work)1262 static void smu_swctf_delayed_work_handler(struct work_struct *work)
1263 {
1264 struct smu_context *smu =
1265 container_of(work, struct smu_context, swctf_delayed_work.work);
1266 struct smu_temperature_range *range =
1267 &smu->thermal_range;
1268 struct amdgpu_device *adev = smu->adev;
1269 uint32_t hotspot_tmp, size;
1270
1271 /*
1272 * If the hotspot temperature is confirmed as below SW CTF setting point
1273 * after the delay enforced, nothing will be done.
1274 * Otherwise, a graceful shutdown will be performed to prevent further damage.
1275 */
1276 if (range->software_shutdown_temp &&
1277 smu->ppt_funcs->read_sensor &&
1278 !smu->ppt_funcs->read_sensor(smu,
1279 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1280 &hotspot_tmp,
1281 &size) &&
1282 hotspot_tmp / 1000 < range->software_shutdown_temp)
1283 return;
1284
1285 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1286 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1287 orderly_poweroff(true);
1288 }
1289
smu_init_xgmi_plpd_mode(struct smu_context * smu)1290 static void smu_init_xgmi_plpd_mode(struct smu_context *smu)
1291 {
1292 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm);
1293 struct smu_dpm_policy_ctxt *policy_ctxt;
1294 struct smu_dpm_policy *policy;
1295
1296 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD);
1297 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1298 if (policy)
1299 policy->current_level = XGMI_PLPD_DEFAULT;
1300 return;
1301 }
1302
1303 /* PMFW put PLPD into default policy after enabling the feature */
1304 if (smu_feature_is_enabled(smu,
1305 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) {
1306 if (policy)
1307 policy->current_level = XGMI_PLPD_DEFAULT;
1308 } else {
1309 policy_ctxt = dpm_ctxt->dpm_policies;
1310 if (policy_ctxt)
1311 policy_ctxt->policy_mask &=
1312 ~BIT(PP_PM_POLICY_XGMI_PLPD);
1313 }
1314 }
1315
smu_init_power_profile(struct smu_context * smu)1316 static void smu_init_power_profile(struct smu_context *smu)
1317 {
1318 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN)
1319 smu->power_profile_mode =
1320 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1321 smu_power_profile_mode_get(smu, smu->power_profile_mode);
1322 }
1323
smu_feature_cap_set(struct smu_context * smu,enum smu_feature_cap_id fea_id)1324 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id)
1325 {
1326 struct smu_feature_cap *fea_cap = &smu->fea_cap;
1327
1328 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT)
1329 return;
1330
1331 set_bit(fea_id, fea_cap->cap_map);
1332 }
1333
smu_feature_cap_test(struct smu_context * smu,enum smu_feature_cap_id fea_id)1334 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id)
1335 {
1336 struct smu_feature_cap *fea_cap = &smu->fea_cap;
1337
1338 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT)
1339 return false;
1340
1341 return test_bit(fea_id, fea_cap->cap_map);
1342 }
1343
smu_feature_cap_init(struct smu_context * smu)1344 static void smu_feature_cap_init(struct smu_context *smu)
1345 {
1346 struct smu_feature_cap *fea_cap = &smu->fea_cap;
1347
1348 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT);
1349 }
1350
smu_sw_init(struct amdgpu_ip_block * ip_block)1351 static int smu_sw_init(struct amdgpu_ip_block *ip_block)
1352 {
1353 struct amdgpu_device *adev = ip_block->adev;
1354 struct smu_context *smu = adev->powerplay.pp_handle;
1355 int i, ret;
1356
1357 smu->pool_size = adev->pm.smu_prv_buffer_size;
1358 smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT);
1359
1360 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1361 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1362 atomic64_set(&smu->throttle_int_counter, 0);
1363 smu->watermarks_bitmap = 0;
1364
1365 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1366 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
1367 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1368 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
1369 atomic_set(&smu->smu_power.power_gate.isp_gated, 1);
1370 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
1371
1372 smu_init_power_profile(smu);
1373 smu->display_config = &adev->pm.pm_display_cfg;
1374
1375 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1376 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1377
1378 INIT_DELAYED_WORK(&smu->swctf_delayed_work,
1379 smu_swctf_delayed_work_handler);
1380
1381 smu_feature_cap_init(smu);
1382
1383 ret = smu_smc_table_sw_init(smu);
1384 if (ret) {
1385 dev_err(adev->dev, "Failed to sw init smc table!\n");
1386 return ret;
1387 }
1388
1389 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1390 ret = smu_get_vbios_bootup_values(smu);
1391 if (ret) {
1392 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1393 return ret;
1394 }
1395
1396 ret = smu_init_pptable_microcode(smu);
1397 if (ret) {
1398 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1399 return ret;
1400 }
1401
1402 ret = smu_register_irq_handler(smu);
1403 if (ret) {
1404 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1405 return ret;
1406 }
1407
1408 /* If there is no way to query fan control mode, fan control is not supported */
1409 if (!smu->ppt_funcs->get_fan_control_mode)
1410 smu->adev->pm.no_fan = true;
1411
1412 return 0;
1413 }
1414
smu_sw_fini(struct amdgpu_ip_block * ip_block)1415 static int smu_sw_fini(struct amdgpu_ip_block *ip_block)
1416 {
1417 struct amdgpu_device *adev = ip_block->adev;
1418 struct smu_context *smu = adev->powerplay.pp_handle;
1419 int ret;
1420
1421 ret = smu_smc_table_sw_fini(smu);
1422 if (ret) {
1423 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1424 return ret;
1425 }
1426
1427 if (smu->custom_profile_params) {
1428 kfree(smu->custom_profile_params);
1429 smu->custom_profile_params = NULL;
1430 }
1431
1432 smu_fini_microcode(smu);
1433
1434 return 0;
1435 }
1436
smu_get_thermal_temperature_range(struct smu_context * smu)1437 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1438 {
1439 struct amdgpu_device *adev = smu->adev;
1440 struct smu_temperature_range *range =
1441 &smu->thermal_range;
1442 int ret = 0;
1443
1444 if (!smu->ppt_funcs->get_thermal_temperature_range)
1445 return 0;
1446
1447 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1448 if (ret)
1449 return ret;
1450
1451 adev->pm.dpm.thermal.min_temp = range->min;
1452 adev->pm.dpm.thermal.max_temp = range->max;
1453 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1454 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1455 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1456 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1457 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1458 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1459 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1460
1461 return ret;
1462 }
1463
1464 /**
1465 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges
1466 *
1467 * @smu: smu_context pointer
1468 *
1469 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling.
1470 * Returns 0 on success, error on failure.
1471 */
smu_wbrf_handle_exclusion_ranges(struct smu_context * smu)1472 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
1473 {
1474 struct wbrf_ranges_in_out wbrf_exclusion = {0};
1475 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list;
1476 struct amdgpu_device *adev = smu->adev;
1477 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;
1478 uint64_t start, end;
1479 int ret, i, j;
1480
1481 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion);
1482 if (ret) {
1483 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n");
1484 return ret;
1485 }
1486
1487 /*
1488 * The exclusion ranges array we got might be filled with holes and duplicate
1489 * entries. For example:
1490 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...}
1491 * We need to do some sortups to eliminate those holes and duplicate entries.
1492 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...}
1493 */
1494 for (i = 0; i < num_of_wbrf_ranges; i++) {
1495 start = wifi_bands[i].start;
1496 end = wifi_bands[i].end;
1497
1498 /* get the last valid entry to fill the intermediate hole */
1499 if (!start && !end) {
1500 for (j = num_of_wbrf_ranges - 1; j > i; j--)
1501 if (wifi_bands[j].start && wifi_bands[j].end)
1502 break;
1503
1504 /* no valid entry left */
1505 if (j <= i)
1506 break;
1507
1508 start = wifi_bands[i].start = wifi_bands[j].start;
1509 end = wifi_bands[i].end = wifi_bands[j].end;
1510 wifi_bands[j].start = 0;
1511 wifi_bands[j].end = 0;
1512 num_of_wbrf_ranges = j;
1513 }
1514
1515 /* eliminate duplicate entries */
1516 for (j = i + 1; j < num_of_wbrf_ranges; j++) {
1517 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) {
1518 wifi_bands[j].start = 0;
1519 wifi_bands[j].end = 0;
1520 }
1521 }
1522 }
1523
1524 /* Send the sorted wifi_bands to PMFW */
1525 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1526 /* Try to set the wifi_bands again */
1527 if (unlikely(ret == -EBUSY)) {
1528 mdelay(5);
1529 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);
1530 }
1531
1532 return ret;
1533 }
1534
1535 /**
1536 * smu_wbrf_event_handler - handle notify events
1537 *
1538 * @nb: notifier block
1539 * @action: event type
1540 * @_arg: event data
1541 *
1542 * Calls relevant amdgpu function in response to wbrf event
1543 * notification from kernel.
1544 */
smu_wbrf_event_handler(struct notifier_block * nb,unsigned long action,void * _arg)1545 static int smu_wbrf_event_handler(struct notifier_block *nb,
1546 unsigned long action, void *_arg)
1547 {
1548 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier);
1549
1550 switch (action) {
1551 case WBRF_CHANGED:
1552 schedule_delayed_work(&smu->wbrf_delayed_work,
1553 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1554 break;
1555 default:
1556 return NOTIFY_DONE;
1557 }
1558
1559 return NOTIFY_OK;
1560 }
1561
1562 /**
1563 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired
1564 *
1565 * @work: struct work_struct pointer
1566 *
1567 * Flood is over and driver will consume the latest exclusion ranges.
1568 */
smu_wbrf_delayed_work_handler(struct work_struct * work)1569 static void smu_wbrf_delayed_work_handler(struct work_struct *work)
1570 {
1571 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work);
1572
1573 smu_wbrf_handle_exclusion_ranges(smu);
1574 }
1575
1576 /**
1577 * smu_wbrf_support_check - check wbrf support
1578 *
1579 * @smu: smu_context pointer
1580 *
1581 * Verifies the ACPI interface whether wbrf is supported.
1582 */
smu_wbrf_support_check(struct smu_context * smu)1583 static void smu_wbrf_support_check(struct smu_context *smu)
1584 {
1585 struct amdgpu_device *adev = smu->adev;
1586
1587 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf &&
1588 acpi_amd_wbrf_supported_consumer(adev->dev);
1589
1590 if (smu->wbrf_supported)
1591 dev_info(adev->dev, "RF interference mitigation is supported\n");
1592 }
1593
1594 /**
1595 * smu_wbrf_init - init driver wbrf support
1596 *
1597 * @smu: smu_context pointer
1598 *
1599 * Verifies the AMD ACPI interfaces and registers with the wbrf
1600 * notifier chain if wbrf feature is supported.
1601 * Returns 0 on success, error on failure.
1602 */
smu_wbrf_init(struct smu_context * smu)1603 static int smu_wbrf_init(struct smu_context *smu)
1604 {
1605 int ret;
1606
1607 if (!smu->wbrf_supported)
1608 return 0;
1609
1610 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler);
1611
1612 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler;
1613 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier);
1614 if (ret)
1615 return ret;
1616
1617 /*
1618 * Some wifiband exclusion ranges may be already there
1619 * before our driver loaded. To make sure our driver
1620 * is awared of those exclusion ranges.
1621 */
1622 schedule_delayed_work(&smu->wbrf_delayed_work,
1623 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
1624
1625 return 0;
1626 }
1627
1628 /**
1629 * smu_wbrf_fini - tear down driver wbrf support
1630 *
1631 * @smu: smu_context pointer
1632 *
1633 * Unregisters with the wbrf notifier chain.
1634 */
smu_wbrf_fini(struct smu_context * smu)1635 static void smu_wbrf_fini(struct smu_context *smu)
1636 {
1637 if (!smu->wbrf_supported)
1638 return;
1639
1640 amd_wbrf_unregister_notifier(&smu->wbrf_notifier);
1641
1642 cancel_delayed_work_sync(&smu->wbrf_delayed_work);
1643 }
1644
smu_smc_hw_setup(struct smu_context * smu)1645 static int smu_smc_hw_setup(struct smu_context *smu)
1646 {
1647 struct amdgpu_device *adev = smu->adev;
1648 uint8_t pcie_gen = 0, pcie_width = 0;
1649 struct smu_feature_bits features_supported;
1650 int ret = 0;
1651
1652 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1653 case IP_VERSION(11, 0, 7):
1654 case IP_VERSION(11, 0, 11):
1655 case IP_VERSION(11, 5, 0):
1656 case IP_VERSION(11, 5, 2):
1657 case IP_VERSION(11, 0, 12):
1658 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1659 dev_info(adev->dev, "dpm has been enabled\n");
1660 ret = smu_system_features_control(smu, true);
1661 if (ret) {
1662 dev_err(adev->dev, "Failed system features control!\n");
1663 return ret;
1664 }
1665
1666 return smu_enable_thermal_alert(smu);
1667 }
1668 break;
1669 default:
1670 break;
1671 }
1672
1673 ret = smu_init_display_count(smu, 0);
1674 if (ret) {
1675 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1676 return ret;
1677 }
1678
1679 ret = smu_set_driver_table_location(smu);
1680 if (ret) {
1681 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1682 return ret;
1683 }
1684
1685 /*
1686 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1687 */
1688 ret = smu_set_tool_table_location(smu);
1689 if (ret) {
1690 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1691 return ret;
1692 }
1693
1694 /*
1695 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1696 * pool location.
1697 */
1698 ret = smu_notify_memory_pool_location(smu);
1699 if (ret) {
1700 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1701 return ret;
1702 }
1703
1704 /*
1705 * It is assumed the pptable used before runpm is same as
1706 * the one used afterwards. Thus, we can reuse the stored
1707 * copy and do not need to resetup the pptable again.
1708 */
1709 if (!adev->in_runpm) {
1710 ret = smu_setup_pptable(smu);
1711 if (ret) {
1712 dev_err(adev->dev, "Failed to setup pptable!\n");
1713 return ret;
1714 }
1715 }
1716
1717 /* smu_dump_pptable(smu); */
1718
1719 /*
1720 * With SCPM enabled, PSP is responsible for the PPTable transferring
1721 * (to SMU). Driver involvement is not needed and permitted.
1722 */
1723 if (!adev->scpm_enabled) {
1724 /*
1725 * Copy pptable bo in the vram to smc with SMU MSGs such as
1726 * SetDriverDramAddr and TransferTableDram2Smu.
1727 */
1728 ret = smu_write_pptable(smu);
1729 if (ret) {
1730 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1731 return ret;
1732 }
1733 }
1734
1735 /* issue Run*Btc msg */
1736 ret = smu_run_btc(smu);
1737 if (ret)
1738 return ret;
1739
1740 /* Enable UclkShadow on wbrf supported */
1741 if (smu->wbrf_supported) {
1742 ret = smu_enable_uclk_shadow(smu, true);
1743 if (ret) {
1744 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n");
1745 return ret;
1746 }
1747 }
1748
1749 /*
1750 * With SCPM enabled, these actions(and relevant messages) are
1751 * not needed and permitted.
1752 */
1753 if (!adev->scpm_enabled) {
1754 ret = smu_feature_set_allowed_mask(smu);
1755 if (ret) {
1756 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1757 return ret;
1758 }
1759 }
1760
1761 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5)
1762 pcie_gen = 4;
1763 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1764 pcie_gen = 3;
1765 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1766 pcie_gen = 2;
1767 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1768 pcie_gen = 1;
1769 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1770 pcie_gen = 0;
1771
1772 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1773 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1774 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1775 */
1776 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)
1777 pcie_width = 7;
1778 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1779 pcie_width = 6;
1780 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1781 pcie_width = 5;
1782 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1783 pcie_width = 4;
1784 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1785 pcie_width = 3;
1786 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1787 pcie_width = 2;
1788 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1789 pcie_width = 1;
1790 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1791 if (ret) {
1792 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1793 return ret;
1794 }
1795
1796 ret = smu_system_features_control(smu, true);
1797 if (ret) {
1798 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1799 return ret;
1800 }
1801
1802 smu_init_xgmi_plpd_mode(smu);
1803
1804 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1805 if (ret) {
1806 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1807 return ret;
1808 }
1809 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED,
1810 features_supported.bits);
1811
1812 if (!smu_is_dpm_running(smu))
1813 dev_info(adev->dev, "dpm has been disabled\n");
1814
1815 /*
1816 * Set initialized values (get from vbios) to dpm tables context such as
1817 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1818 * type of clks.
1819 */
1820 ret = smu_set_default_dpm_table(smu);
1821 if (ret) {
1822 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1823 return ret;
1824 }
1825
1826 ret = smu_get_thermal_temperature_range(smu);
1827 if (ret) {
1828 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1829 return ret;
1830 }
1831
1832 ret = smu_enable_thermal_alert(smu);
1833 if (ret) {
1834 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1835 return ret;
1836 }
1837
1838 ret = smu_notify_display_change(smu);
1839 if (ret) {
1840 dev_err(adev->dev, "Failed to notify display change!\n");
1841 return ret;
1842 }
1843
1844 /*
1845 * Set min deep sleep dce fclk with bootup value from vbios via
1846 * SetMinDeepSleepDcefclk MSG.
1847 */
1848 ret = smu_set_min_dcef_deep_sleep(smu,
1849 smu->smu_table.boot_values.dcefclk / 100);
1850 if (ret) {
1851 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n");
1852 return ret;
1853 }
1854
1855 /* Init wbrf support. Properly setup the notifier */
1856 ret = smu_wbrf_init(smu);
1857 if (ret)
1858 dev_err(adev->dev, "Error during wbrf init call\n");
1859
1860 return ret;
1861 }
1862
smu_start_smc_engine(struct smu_context * smu)1863 static int smu_start_smc_engine(struct smu_context *smu)
1864 {
1865 struct amdgpu_device *adev = smu->adev;
1866 int ret = 0;
1867
1868 if (amdgpu_virt_xgmi_migrate_enabled(adev))
1869 smu_update_gpu_addresses(smu);
1870
1871 smu->smc_fw_state = SMU_FW_INIT;
1872
1873 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1874 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) {
1875 if (smu->ppt_funcs->load_microcode) {
1876 ret = smu->ppt_funcs->load_microcode(smu);
1877 if (ret)
1878 return ret;
1879 }
1880 }
1881 }
1882
1883 if (smu->ppt_funcs->check_fw_status) {
1884 ret = smu->ppt_funcs->check_fw_status(smu);
1885 if (ret) {
1886 dev_err(adev->dev, "SMC is not ready\n");
1887 return ret;
1888 }
1889 }
1890
1891 /*
1892 * Send msg GetDriverIfVersion to check if the return value is equal
1893 * with DRIVER_IF_VERSION of smc header.
1894 */
1895 ret = smu_check_fw_version(smu);
1896 if (ret)
1897 return ret;
1898
1899 return ret;
1900 }
1901
smu_hw_init(struct amdgpu_ip_block * ip_block)1902 static int smu_hw_init(struct amdgpu_ip_block *ip_block)
1903 {
1904 int i, ret;
1905 struct amdgpu_device *adev = ip_block->adev;
1906 struct smu_context *smu = adev->powerplay.pp_handle;
1907
1908 if (amdgpu_sriov_multi_vf_mode(adev)) {
1909 smu->pm_enabled = false;
1910 return 0;
1911 }
1912
1913 ret = smu_start_smc_engine(smu);
1914 if (ret) {
1915 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1916 return ret;
1917 }
1918
1919 /*
1920 * Check whether wbrf is supported. This needs to be done
1921 * before SMU setup starts since part of SMU configuration
1922 * relies on this.
1923 */
1924 smu_wbrf_support_check(smu);
1925
1926 if (smu->is_apu) {
1927 ret = smu_set_gfx_imu_enable(smu);
1928 if (ret)
1929 return ret;
1930 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1931 smu_dpm_set_vcn_enable(smu, true, i);
1932 smu_dpm_set_jpeg_enable(smu, true);
1933 smu_dpm_set_umsch_mm_enable(smu, true);
1934 smu_set_mall_enable(smu);
1935 smu_set_gfx_cgpg(smu, true);
1936 }
1937
1938 if (!smu->pm_enabled)
1939 return 0;
1940
1941 ret = smu_init_driver_allowed_feature_mask(smu);
1942 if (ret)
1943 return ret;
1944
1945 ret = smu_smc_hw_setup(smu);
1946 if (ret) {
1947 dev_err(adev->dev, "Failed to setup smc hw!\n");
1948 return ret;
1949 }
1950
1951 /*
1952 * Move maximum sustainable clock retrieving here considering
1953 * 1. It is not needed on resume(from S3).
1954 * 2. DAL settings come between .hw_init and .late_init of SMU.
1955 * And DAL needs to know the maximum sustainable clocks. Thus
1956 * it cannot be put in .late_init().
1957 */
1958 ret = smu_init_max_sustainable_clocks(smu);
1959 if (ret) {
1960 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1961 return ret;
1962 }
1963
1964 adev->pm.dpm_enabled = true;
1965
1966 dev_info(adev->dev, "SMU is initialized successfully!\n");
1967
1968 return 0;
1969 }
1970
smu_disable_dpms(struct smu_context * smu)1971 static int smu_disable_dpms(struct smu_context *smu)
1972 {
1973 struct amdgpu_device *adev = smu->adev;
1974 int ret = 0;
1975 bool use_baco = !smu->is_apu &&
1976 ((amdgpu_in_reset(adev) &&
1977 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1978 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1979
1980 /*
1981 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1982 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1983 */
1984 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1985 case IP_VERSION(13, 0, 0):
1986 case IP_VERSION(13, 0, 7):
1987 case IP_VERSION(13, 0, 10):
1988 case IP_VERSION(14, 0, 2):
1989 case IP_VERSION(14, 0, 3):
1990 return 0;
1991 default:
1992 break;
1993 }
1994
1995 /*
1996 * For custom pptable uploading, skip the DPM features
1997 * disable process on Navi1x ASICs.
1998 * - As the gfx related features are under control of
1999 * RLC on those ASICs. RLC reinitialization will be
2000 * needed to reenable them. That will cost much more
2001 * efforts.
2002 *
2003 * - SMU firmware can handle the DPM reenablement
2004 * properly.
2005 */
2006 if (smu->uploading_custom_pp_table) {
2007 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2008 case IP_VERSION(11, 0, 0):
2009 case IP_VERSION(11, 0, 5):
2010 case IP_VERSION(11, 0, 9):
2011 case IP_VERSION(11, 0, 7):
2012 case IP_VERSION(11, 0, 11):
2013 case IP_VERSION(11, 5, 0):
2014 case IP_VERSION(11, 5, 2):
2015 case IP_VERSION(11, 0, 12):
2016 case IP_VERSION(11, 0, 13):
2017 return 0;
2018 default:
2019 break;
2020 }
2021 }
2022
2023 /*
2024 * For Sienna_Cichlid, PMFW will handle the features disablement properly
2025 * on BACO in. Driver involvement is unnecessary.
2026 */
2027 if (use_baco) {
2028 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2029 case IP_VERSION(11, 0, 7):
2030 case IP_VERSION(11, 0, 0):
2031 case IP_VERSION(11, 0, 5):
2032 case IP_VERSION(11, 0, 9):
2033 case IP_VERSION(13, 0, 7):
2034 return 0;
2035 default:
2036 break;
2037 }
2038 }
2039
2040 /*
2041 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly
2042 * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
2043 */
2044 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 &&
2045 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix))
2046 return 0;
2047
2048 /* vangogh s0ix */
2049 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
2050 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) &&
2051 adev->in_s0ix)
2052 return 0;
2053
2054 /*
2055 * For gpu reset, runpm and hibernation through BACO,
2056 * BACO feature has to be kept enabled.
2057 */
2058 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
2059 ret = smu_disable_all_features_with_exception(smu,
2060 SMU_FEATURE_BACO_BIT);
2061 if (ret)
2062 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
2063 } else {
2064 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
2065 if (!adev->scpm_enabled) {
2066 ret = smu_system_features_control(smu, false);
2067 if (ret)
2068 dev_err(adev->dev, "Failed to disable smu features.\n");
2069 }
2070 }
2071
2072 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction.
2073 * otherwise SMU will hang while interacting with RLC if RLC is halted
2074 * this is a WA for Vangogh asic which fix the SMU hang issue.
2075 */
2076 ret = smu_notify_rlc_state(smu, false);
2077 if (ret) {
2078 dev_err(adev->dev, "Fail to notify rlc status!\n");
2079 return ret;
2080 }
2081
2082 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) &&
2083 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) &&
2084 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
2085 adev->gfx.rlc.funcs->stop(adev);
2086
2087 return ret;
2088 }
2089
smu_smc_hw_cleanup(struct smu_context * smu)2090 static int smu_smc_hw_cleanup(struct smu_context *smu)
2091 {
2092 struct amdgpu_device *adev = smu->adev;
2093 int ret = 0;
2094
2095 smu_wbrf_fini(smu);
2096
2097 cancel_work_sync(&smu->throttling_logging_work);
2098 cancel_work_sync(&smu->interrupt_work);
2099
2100 ret = smu_disable_thermal_alert(smu);
2101 if (ret) {
2102 dev_err(adev->dev, "Fail to disable thermal alert!\n");
2103 return ret;
2104 }
2105
2106 cancel_delayed_work_sync(&smu->swctf_delayed_work);
2107
2108 ret = smu_disable_dpms(smu);
2109 if (ret) {
2110 dev_err(adev->dev, "Fail to disable dpm features!\n");
2111 return ret;
2112 }
2113
2114 return 0;
2115 }
2116
smu_reset_mp1_state(struct smu_context * smu)2117 static int smu_reset_mp1_state(struct smu_context *smu)
2118 {
2119 struct amdgpu_device *adev = smu->adev;
2120 int ret = 0;
2121
2122 if ((!adev->in_runpm) && (!adev->in_suspend) &&
2123 (!amdgpu_in_reset(adev)) && !smu->is_apu &&
2124 amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0))
2125 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
2126
2127 return ret;
2128 }
2129
smu_hw_fini(struct amdgpu_ip_block * ip_block)2130 static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
2131 {
2132 struct amdgpu_device *adev = ip_block->adev;
2133 struct smu_context *smu = adev->powerplay.pp_handle;
2134 int i, ret;
2135
2136 if (amdgpu_sriov_multi_vf_mode(adev))
2137 return 0;
2138
2139 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2140 smu_dpm_set_vcn_enable(smu, false, i);
2141 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE;
2142 }
2143 smu_dpm_set_jpeg_enable(smu, false);
2144 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
2145 smu_dpm_set_umsch_mm_enable(smu, false);
2146
2147 if (!smu->pm_enabled)
2148 return 0;
2149
2150 adev->pm.dpm_enabled = false;
2151
2152 ret = smu_smc_hw_cleanup(smu);
2153 if (ret)
2154 return ret;
2155
2156 ret = smu_reset_mp1_state(smu);
2157 if (ret)
2158 return ret;
2159
2160 return 0;
2161 }
2162
smu_late_fini(struct amdgpu_ip_block * ip_block)2163 static void smu_late_fini(struct amdgpu_ip_block *ip_block)
2164 {
2165 struct amdgpu_device *adev = ip_block->adev;
2166 struct smu_context *smu = adev->powerplay.pp_handle;
2167
2168 kfree(smu);
2169 }
2170
smu_reset(struct smu_context * smu)2171 static int smu_reset(struct smu_context *smu)
2172 {
2173 struct amdgpu_device *adev = smu->adev;
2174 struct amdgpu_ip_block *ip_block;
2175 int ret;
2176
2177 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC);
2178 if (!ip_block)
2179 return -EINVAL;
2180
2181 ret = smu_hw_fini(ip_block);
2182 if (ret)
2183 return ret;
2184
2185 ret = smu_hw_init(ip_block);
2186 if (ret)
2187 return ret;
2188
2189 ret = smu_late_init(ip_block);
2190 if (ret)
2191 return ret;
2192
2193 return 0;
2194 }
2195
smu_suspend(struct amdgpu_ip_block * ip_block)2196 static int smu_suspend(struct amdgpu_ip_block *ip_block)
2197 {
2198 struct amdgpu_device *adev = ip_block->adev;
2199 struct smu_context *smu = adev->powerplay.pp_handle;
2200 int ret;
2201 uint64_t count;
2202
2203 if (amdgpu_sriov_multi_vf_mode(adev))
2204 return 0;
2205
2206 if (!smu->pm_enabled)
2207 return 0;
2208
2209 adev->pm.dpm_enabled = false;
2210
2211 ret = smu_smc_hw_cleanup(smu);
2212 if (ret)
2213 return ret;
2214
2215 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
2216
2217 smu_set_gfx_cgpg(smu, false);
2218
2219 /*
2220 * pwfw resets entrycount when device is suspended, so we save the
2221 * last value to be used when we resume to keep it consistent
2222 */
2223 ret = smu_get_entrycount_gfxoff(smu, &count);
2224 if (!ret)
2225 adev->gfx.gfx_off_entrycount = count;
2226
2227 /* clear this on suspend so it will get reprogrammed on resume */
2228 smu->workload_mask = 0;
2229
2230 return 0;
2231 }
2232
smu_resume(struct amdgpu_ip_block * ip_block)2233 static int smu_resume(struct amdgpu_ip_block *ip_block)
2234 {
2235 int ret;
2236 struct amdgpu_device *adev = ip_block->adev;
2237 struct smu_context *smu = adev->powerplay.pp_handle;
2238
2239 if (amdgpu_sriov_multi_vf_mode(adev))
2240 return 0;
2241
2242 if (!smu->pm_enabled)
2243 return 0;
2244
2245 dev_info(adev->dev, "SMU is resuming...\n");
2246
2247 ret = smu_start_smc_engine(smu);
2248 if (ret) {
2249 dev_err(adev->dev, "SMC engine is not correctly up!\n");
2250 return ret;
2251 }
2252
2253 ret = smu_smc_hw_setup(smu);
2254 if (ret) {
2255 dev_err(adev->dev, "Failed to setup smc hw!\n");
2256 return ret;
2257 }
2258
2259 ret = smu_set_gfx_imu_enable(smu);
2260 if (ret)
2261 return ret;
2262
2263 smu_set_gfx_cgpg(smu, true);
2264
2265 smu->disable_uclk_switch = 0;
2266
2267 adev->pm.dpm_enabled = true;
2268
2269 dev_info(adev->dev, "SMU is resumed successfully!\n");
2270
2271 return 0;
2272 }
2273
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)2274 static int smu_display_configuration_change(void *handle,
2275 const struct amd_pp_display_configuration *display_config)
2276 {
2277 struct smu_context *smu = handle;
2278
2279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2280 return -EOPNOTSUPP;
2281
2282 if (!display_config)
2283 return -EINVAL;
2284
2285 smu_set_min_dcef_deep_sleep(smu,
2286 display_config->min_dcef_deep_sleep_set_clk / 100);
2287
2288 return 0;
2289 }
2290
smu_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2291 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2292 enum amd_clockgating_state state)
2293 {
2294 return 0;
2295 }
2296
smu_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2297 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
2298 enum amd_powergating_state state)
2299 {
2300 return 0;
2301 }
2302
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)2303 static int smu_enable_umd_pstate(void *handle,
2304 enum amd_dpm_forced_level *level)
2305 {
2306 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
2307 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
2308 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
2309 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
2310
2311 struct smu_context *smu = (struct smu_context*)(handle);
2312 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2313
2314 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2315 return -EINVAL;
2316
2317 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
2318 /* enter umd pstate, save current level, disable gfx cg*/
2319 if (*level & profile_mode_mask) {
2320 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
2321 smu_gpo_control(smu, false);
2322 smu_gfx_ulv_control(smu, false);
2323 smu_deep_sleep_control(smu, false);
2324 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
2325 }
2326 } else {
2327 /* exit umd pstate, restore level, enable gfx cg*/
2328 if (!(*level & profile_mode_mask)) {
2329 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
2330 *level = smu_dpm_ctx->saved_dpm_level;
2331 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
2332 smu_deep_sleep_control(smu, true);
2333 smu_gfx_ulv_control(smu, true);
2334 smu_gpo_control(smu, true);
2335 }
2336 }
2337
2338 return 0;
2339 }
2340
smu_bump_power_profile_mode(struct smu_context * smu,long * custom_params,u32 custom_params_max_idx)2341 static int smu_bump_power_profile_mode(struct smu_context *smu,
2342 long *custom_params,
2343 u32 custom_params_max_idx)
2344 {
2345 u32 workload_mask = 0;
2346 int i, ret = 0;
2347
2348 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2349 if (smu->workload_refcount[i])
2350 workload_mask |= 1 << i;
2351 }
2352
2353 if (smu->workload_mask == workload_mask)
2354 return 0;
2355
2356 if (smu->ppt_funcs->set_power_profile_mode)
2357 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask,
2358 custom_params,
2359 custom_params_max_idx);
2360
2361 if (!ret)
2362 smu->workload_mask = workload_mask;
2363
2364 return ret;
2365 }
2366
smu_power_profile_mode_get(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile_mode)2367 static void smu_power_profile_mode_get(struct smu_context *smu,
2368 enum PP_SMC_POWER_PROFILE profile_mode)
2369 {
2370 smu->workload_refcount[profile_mode]++;
2371 }
2372
smu_power_profile_mode_put(struct smu_context * smu,enum PP_SMC_POWER_PROFILE profile_mode)2373 static void smu_power_profile_mode_put(struct smu_context *smu,
2374 enum PP_SMC_POWER_PROFILE profile_mode)
2375 {
2376 if (smu->workload_refcount[profile_mode])
2377 smu->workload_refcount[profile_mode]--;
2378 }
2379
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings)2380 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
2381 enum amd_dpm_forced_level level,
2382 bool skip_display_settings)
2383 {
2384 int ret = 0;
2385 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2386
2387 if (!skip_display_settings) {
2388 ret = smu_display_config_changed(smu);
2389 if (ret) {
2390 dev_err(smu->adev->dev, "Failed to change display config!");
2391 return ret;
2392 }
2393 }
2394
2395 ret = smu_apply_clocks_adjust_rules(smu);
2396 if (ret) {
2397 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
2398 return ret;
2399 }
2400
2401 if (!skip_display_settings) {
2402 ret = smu_notify_smc_display_config(smu);
2403 if (ret) {
2404 dev_err(smu->adev->dev, "Failed to notify smc display config!");
2405 return ret;
2406 }
2407 }
2408
2409 if (smu_dpm_ctx->dpm_level != level) {
2410 ret = smu_asic_set_performance_level(smu, level);
2411 if (ret) {
2412 if (ret == -EOPNOTSUPP)
2413 dev_info(smu->adev->dev, "set performance level %d not supported",
2414 level);
2415 else
2416 dev_err(smu->adev->dev, "Failed to set performance level %d",
2417 level);
2418 return ret;
2419 }
2420
2421 /* update the saved copy */
2422 smu_dpm_ctx->dpm_level = level;
2423 }
2424
2425 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2426 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2427 smu_bump_power_profile_mode(smu, NULL, 0);
2428
2429 return ret;
2430 }
2431
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id)2432 static int smu_handle_task(struct smu_context *smu,
2433 enum amd_dpm_forced_level level,
2434 enum amd_pp_task task_id)
2435 {
2436 int ret = 0;
2437
2438 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2439 return -EOPNOTSUPP;
2440
2441 switch (task_id) {
2442 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
2443 ret = smu_pre_display_config_changed(smu);
2444 if (ret)
2445 return ret;
2446 ret = smu_adjust_power_state_dynamic(smu, level, false);
2447 break;
2448 case AMD_PP_TASK_COMPLETE_INIT:
2449 ret = smu_adjust_power_state_dynamic(smu, level, true);
2450 break;
2451 case AMD_PP_TASK_READJUST_POWER_STATE:
2452 ret = smu_adjust_power_state_dynamic(smu, level, true);
2453 break;
2454 default:
2455 break;
2456 }
2457
2458 return ret;
2459 }
2460
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)2461 static int smu_handle_dpm_task(void *handle,
2462 enum amd_pp_task task_id,
2463 enum amd_pm_state_type *user_state)
2464 {
2465 struct smu_context *smu = handle;
2466 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2467
2468 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
2469
2470 }
2471
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool enable)2472 static int smu_switch_power_profile(void *handle,
2473 enum PP_SMC_POWER_PROFILE type,
2474 bool enable)
2475 {
2476 struct smu_context *smu = handle;
2477 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2478 int ret;
2479
2480 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2481 return -EOPNOTSUPP;
2482
2483 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
2484 return -EINVAL;
2485
2486 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2487 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2488 if (enable)
2489 smu_power_profile_mode_get(smu, type);
2490 else
2491 smu_power_profile_mode_put(smu, type);
2492 /* don't switch the active workload when paused */
2493 if (smu->pause_workload)
2494 ret = 0;
2495 else
2496 ret = smu_bump_power_profile_mode(smu, NULL, 0);
2497 if (ret) {
2498 if (enable)
2499 smu_power_profile_mode_put(smu, type);
2500 else
2501 smu_power_profile_mode_get(smu, type);
2502 return ret;
2503 }
2504 }
2505
2506 return 0;
2507 }
2508
smu_pause_power_profile(void * handle,bool pause)2509 static int smu_pause_power_profile(void *handle,
2510 bool pause)
2511 {
2512 struct smu_context *smu = handle;
2513 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2514 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
2515 int ret;
2516
2517 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2518 return -EOPNOTSUPP;
2519
2520 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2521 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2522 smu->pause_workload = pause;
2523
2524 /* force to bootup default profile */
2525 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode)
2526 ret = smu->ppt_funcs->set_power_profile_mode(smu,
2527 workload_mask,
2528 NULL,
2529 0);
2530 else
2531 ret = smu_bump_power_profile_mode(smu, NULL, 0);
2532 return ret;
2533 }
2534
2535 return 0;
2536 }
2537
smu_get_performance_level(void * handle)2538 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
2539 {
2540 struct smu_context *smu = handle;
2541 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2542
2543 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2544 return -EOPNOTSUPP;
2545
2546 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2547 return -EINVAL;
2548
2549 return smu_dpm_ctx->dpm_level;
2550 }
2551
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)2552 static int smu_force_performance_level(void *handle,
2553 enum amd_dpm_forced_level level)
2554 {
2555 struct smu_context *smu = handle;
2556 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2557 int ret = 0;
2558
2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2560 return -EOPNOTSUPP;
2561
2562 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2563 return -EINVAL;
2564
2565 ret = smu_enable_umd_pstate(smu, &level);
2566 if (ret)
2567 return ret;
2568
2569 ret = smu_handle_task(smu, level,
2570 AMD_PP_TASK_READJUST_POWER_STATE);
2571
2572 /* reset user dpm clock state */
2573 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2574 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
2575 smu->user_dpm_profile.clk_dependency = 0;
2576 }
2577
2578 return ret;
2579 }
2580
smu_set_display_count(void * handle,uint32_t count)2581 static int smu_set_display_count(void *handle, uint32_t count)
2582 {
2583 struct smu_context *smu = handle;
2584
2585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2586 return -EOPNOTSUPP;
2587
2588 return smu_init_display_count(smu, count);
2589 }
2590
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)2591 static int smu_force_smuclk_levels(struct smu_context *smu,
2592 enum smu_clk_type clk_type,
2593 uint32_t mask)
2594 {
2595 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2596 int ret = 0;
2597
2598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2599 return -EOPNOTSUPP;
2600
2601 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2602 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
2603 return -EINVAL;
2604 }
2605
2606 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
2607 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
2608 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2609 smu->user_dpm_profile.clk_mask[clk_type] = mask;
2610 smu_set_user_clk_dependencies(smu, clk_type);
2611 }
2612 }
2613
2614 return ret;
2615 }
2616
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)2617 static int smu_force_ppclk_levels(void *handle,
2618 enum pp_clock_type type,
2619 uint32_t mask)
2620 {
2621 struct smu_context *smu = handle;
2622 enum smu_clk_type clk_type;
2623
2624 switch (type) {
2625 case PP_SCLK:
2626 clk_type = SMU_SCLK; break;
2627 case PP_MCLK:
2628 clk_type = SMU_MCLK; break;
2629 case PP_PCIE:
2630 clk_type = SMU_PCIE; break;
2631 case PP_SOCCLK:
2632 clk_type = SMU_SOCCLK; break;
2633 case PP_FCLK:
2634 clk_type = SMU_FCLK; break;
2635 case PP_DCEFCLK:
2636 clk_type = SMU_DCEFCLK; break;
2637 case PP_VCLK:
2638 clk_type = SMU_VCLK; break;
2639 case PP_VCLK1:
2640 clk_type = SMU_VCLK1; break;
2641 case PP_DCLK:
2642 clk_type = SMU_DCLK; break;
2643 case PP_DCLK1:
2644 clk_type = SMU_DCLK1; break;
2645 case OD_SCLK:
2646 clk_type = SMU_OD_SCLK; break;
2647 case OD_MCLK:
2648 clk_type = SMU_OD_MCLK; break;
2649 case OD_VDDC_CURVE:
2650 clk_type = SMU_OD_VDDC_CURVE; break;
2651 case OD_RANGE:
2652 clk_type = SMU_OD_RANGE; break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 return smu_force_smuclk_levels(smu, clk_type, mask);
2658 }
2659
2660 /*
2661 * On system suspending or resetting, the dpm_enabled
2662 * flag will be cleared. So that those SMU services which
2663 * are not supported will be gated.
2664 * However, the mp1 state setting should still be granted
2665 * even if the dpm_enabled cleared.
2666 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2667 static int smu_set_mp1_state(void *handle,
2668 enum pp_mp1_state mp1_state)
2669 {
2670 struct smu_context *smu = handle;
2671 int ret = 0;
2672
2673 if (!smu->pm_enabled)
2674 return -EOPNOTSUPP;
2675
2676 if (smu->ppt_funcs &&
2677 smu->ppt_funcs->set_mp1_state)
2678 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2679
2680 return ret;
2681 }
2682
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2683 static int smu_set_df_cstate(void *handle,
2684 enum pp_df_cstate state)
2685 {
2686 struct smu_context *smu = handle;
2687 int ret = 0;
2688
2689 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2690 return -EOPNOTSUPP;
2691
2692 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2693 return 0;
2694
2695 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2696 if (ret)
2697 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2698
2699 return ret;
2700 }
2701
smu_write_watermarks_table(struct smu_context * smu)2702 int smu_write_watermarks_table(struct smu_context *smu)
2703 {
2704 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2705 return -EOPNOTSUPP;
2706
2707 return smu_set_watermarks_table(smu, NULL);
2708 }
2709
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2710 static int smu_set_watermarks_for_clock_ranges(void *handle,
2711 struct pp_smu_wm_range_sets *clock_ranges)
2712 {
2713 struct smu_context *smu = handle;
2714
2715 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2716 return -EOPNOTSUPP;
2717
2718 if (smu->disable_watermark)
2719 return 0;
2720
2721 return smu_set_watermarks_table(smu, clock_ranges);
2722 }
2723
smu_set_ac_dc(struct smu_context * smu)2724 int smu_set_ac_dc(struct smu_context *smu)
2725 {
2726 int ret = 0;
2727
2728 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2729 return -EOPNOTSUPP;
2730
2731 /* controlled by firmware */
2732 if (smu->dc_controlled_by_gpio)
2733 return 0;
2734
2735 ret = smu_set_power_source(smu,
2736 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2737 SMU_POWER_SOURCE_DC);
2738 if (ret)
2739 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2740 smu->adev->pm.ac_power ? "AC" : "DC");
2741
2742 return ret;
2743 }
2744
2745 const struct amd_ip_funcs smu_ip_funcs = {
2746 .name = "smu",
2747 .early_init = smu_early_init,
2748 .late_init = smu_late_init,
2749 .sw_init = smu_sw_init,
2750 .sw_fini = smu_sw_fini,
2751 .hw_init = smu_hw_init,
2752 .hw_fini = smu_hw_fini,
2753 .late_fini = smu_late_fini,
2754 .suspend = smu_suspend,
2755 .resume = smu_resume,
2756 .is_idle = NULL,
2757 .check_soft_reset = NULL,
2758 .wait_for_idle = NULL,
2759 .soft_reset = NULL,
2760 .set_clockgating_state = smu_set_clockgating_state,
2761 .set_powergating_state = smu_set_powergating_state,
2762 };
2763
2764 const struct amdgpu_ip_block_version smu_v11_0_ip_block = {
2765 .type = AMD_IP_BLOCK_TYPE_SMC,
2766 .major = 11,
2767 .minor = 0,
2768 .rev = 0,
2769 .funcs = &smu_ip_funcs,
2770 };
2771
2772 const struct amdgpu_ip_block_version smu_v12_0_ip_block = {
2773 .type = AMD_IP_BLOCK_TYPE_SMC,
2774 .major = 12,
2775 .minor = 0,
2776 .rev = 0,
2777 .funcs = &smu_ip_funcs,
2778 };
2779
2780 const struct amdgpu_ip_block_version smu_v13_0_ip_block = {
2781 .type = AMD_IP_BLOCK_TYPE_SMC,
2782 .major = 13,
2783 .minor = 0,
2784 .rev = 0,
2785 .funcs = &smu_ip_funcs,
2786 };
2787
2788 const struct amdgpu_ip_block_version smu_v14_0_ip_block = {
2789 .type = AMD_IP_BLOCK_TYPE_SMC,
2790 .major = 14,
2791 .minor = 0,
2792 .rev = 0,
2793 .funcs = &smu_ip_funcs,
2794 };
2795
2796 const struct amdgpu_ip_block_version smu_v15_0_ip_block = {
2797 .type = AMD_IP_BLOCK_TYPE_SMC,
2798 .major = 15,
2799 .minor = 0,
2800 .rev = 0,
2801 .funcs = &smu_ip_funcs,
2802 };
2803
smu_get_ras_smu_driver(void * handle)2804 const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle)
2805 {
2806 struct smu_context *smu = (struct smu_context *)handle;
2807 const struct ras_smu_drv *tmp = NULL;
2808 int ret;
2809
2810 ret = smu_get_ras_smu_drv(smu, &tmp);
2811
2812 return ret ? NULL : tmp;
2813 }
2814
smu_load_microcode(void * handle)2815 static int smu_load_microcode(void *handle)
2816 {
2817 struct smu_context *smu = handle;
2818 struct amdgpu_device *adev = smu->adev;
2819 int ret = 0;
2820
2821 if (!smu->pm_enabled)
2822 return -EOPNOTSUPP;
2823
2824 /* This should be used for non PSP loading */
2825 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2826 return 0;
2827
2828 if (smu->ppt_funcs->load_microcode) {
2829 ret = smu->ppt_funcs->load_microcode(smu);
2830 if (ret) {
2831 dev_err(adev->dev, "Load microcode failed\n");
2832 return ret;
2833 }
2834 }
2835
2836 if (smu->ppt_funcs->check_fw_status) {
2837 ret = smu->ppt_funcs->check_fw_status(smu);
2838 if (ret) {
2839 dev_err(adev->dev, "SMC is not ready\n");
2840 return ret;
2841 }
2842 }
2843
2844 return ret;
2845 }
2846
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2847 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2848 {
2849 int ret = 0;
2850
2851 if (smu->ppt_funcs->set_gfx_cgpg)
2852 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2853
2854 return ret;
2855 }
2856
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2857 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2858 {
2859 struct smu_context *smu = handle;
2860 int ret = 0;
2861
2862 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2863 return -EOPNOTSUPP;
2864
2865 if (!smu->ppt_funcs->set_fan_speed_rpm)
2866 return -EOPNOTSUPP;
2867
2868 if (speed == U32_MAX)
2869 return -EINVAL;
2870
2871 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2872 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2873 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2874 smu->user_dpm_profile.fan_speed_rpm = speed;
2875
2876 /* Override custom PWM setting as they cannot co-exist */
2877 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2878 smu->user_dpm_profile.fan_speed_pwm = 0;
2879 }
2880
2881 return ret;
2882 }
2883
2884 /**
2885 * smu_get_power_limit - Request one of the SMU Power Limits
2886 *
2887 * @handle: pointer to smu context
2888 * @limit: requested limit is written back to this variable
2889 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2890 * @pp_power_type: &pp_power_type type of power
2891 * Return: 0 on success, <0 on error
2892 *
2893 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2894 int smu_get_power_limit(void *handle,
2895 uint32_t *limit,
2896 enum pp_power_limit_level pp_limit_level,
2897 enum pp_power_type pp_power_type)
2898 {
2899 struct smu_context *smu = handle;
2900 struct amdgpu_device *adev = smu->adev;
2901 enum smu_ppt_limit_level limit_level;
2902 uint32_t limit_type;
2903 int ret = 0;
2904
2905 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2906 return -EOPNOTSUPP;
2907
2908 if (!limit)
2909 return -EINVAL;
2910
2911 switch (pp_power_type) {
2912 case PP_PWR_TYPE_SUSTAINED:
2913 limit_type = SMU_DEFAULT_PPT_LIMIT;
2914 break;
2915 case PP_PWR_TYPE_FAST:
2916 limit_type = SMU_FAST_PPT_LIMIT;
2917 break;
2918 default:
2919 return -EOPNOTSUPP;
2920 }
2921
2922 switch (pp_limit_level) {
2923 case PP_PWR_LIMIT_CURRENT:
2924 limit_level = SMU_PPT_LIMIT_CURRENT;
2925 break;
2926 case PP_PWR_LIMIT_DEFAULT:
2927 limit_level = SMU_PPT_LIMIT_DEFAULT;
2928 break;
2929 case PP_PWR_LIMIT_MAX:
2930 limit_level = SMU_PPT_LIMIT_MAX;
2931 break;
2932 case PP_PWR_LIMIT_MIN:
2933 limit_level = SMU_PPT_LIMIT_MIN;
2934 break;
2935 default:
2936 return -EOPNOTSUPP;
2937 }
2938
2939 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2940 if (smu->ppt_funcs->get_ppt_limit)
2941 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2942 else
2943 return -EOPNOTSUPP;
2944 } else {
2945 switch (limit_level) {
2946 case SMU_PPT_LIMIT_CURRENT:
2947 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2948 case IP_VERSION(13, 0, 2):
2949 case IP_VERSION(13, 0, 6):
2950 case IP_VERSION(13, 0, 12):
2951 case IP_VERSION(13, 0, 14):
2952 case IP_VERSION(11, 0, 7):
2953 case IP_VERSION(11, 0, 11):
2954 case IP_VERSION(11, 0, 12):
2955 case IP_VERSION(11, 0, 13):
2956 ret = smu_get_asic_power_limits(smu,
2957 &smu->current_power_limit,
2958 NULL, NULL, NULL);
2959 break;
2960 default:
2961 break;
2962 }
2963 *limit = smu->current_power_limit;
2964 break;
2965 case SMU_PPT_LIMIT_DEFAULT:
2966 *limit = smu->default_power_limit;
2967 break;
2968 case SMU_PPT_LIMIT_MAX:
2969 *limit = smu->max_power_limit;
2970 break;
2971 case SMU_PPT_LIMIT_MIN:
2972 *limit = smu->min_power_limit;
2973 break;
2974 default:
2975 return -EINVAL;
2976 }
2977 }
2978
2979 return ret;
2980 }
2981
smu_set_power_limit(void * handle,uint32_t limit_type,uint32_t limit)2982 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit)
2983 {
2984 struct smu_context *smu = handle;
2985 int ret = 0;
2986
2987 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2988 return -EOPNOTSUPP;
2989
2990 if (limit_type == SMU_DEFAULT_PPT_LIMIT) {
2991 if (!limit)
2992 limit = smu->current_power_limit;
2993 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) {
2994 dev_err(smu->adev->dev,
2995 "New power limit (%d) is out of range [%d,%d]\n",
2996 limit, smu->min_power_limit, smu->max_power_limit);
2997 return -EINVAL;
2998 }
2999 }
3000
3001 if (smu->ppt_funcs->set_power_limit) {
3002 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
3003 if (ret)
3004 return ret;
3005 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
3006 smu->user_dpm_profile.power_limits[limit_type] = limit;
3007 }
3008
3009 return 0;
3010 }
3011
smu_convert_to_smuclk(enum pp_clock_type type)3012 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
3013 {
3014 enum smu_clk_type clk_type;
3015
3016 switch (type) {
3017 case PP_SCLK:
3018 clk_type = SMU_SCLK; break;
3019 case PP_MCLK:
3020 clk_type = SMU_MCLK; break;
3021 case PP_PCIE:
3022 clk_type = SMU_PCIE; break;
3023 case PP_SOCCLK:
3024 clk_type = SMU_SOCCLK; break;
3025 case PP_FCLK:
3026 clk_type = SMU_FCLK; break;
3027 case PP_DCEFCLK:
3028 clk_type = SMU_DCEFCLK; break;
3029 case PP_VCLK:
3030 clk_type = SMU_VCLK; break;
3031 case PP_VCLK1:
3032 clk_type = SMU_VCLK1; break;
3033 case PP_DCLK:
3034 clk_type = SMU_DCLK; break;
3035 case PP_DCLK1:
3036 clk_type = SMU_DCLK1; break;
3037 case PP_ISPICLK:
3038 clk_type = SMU_ISPICLK;
3039 break;
3040 case PP_ISPXCLK:
3041 clk_type = SMU_ISPXCLK;
3042 break;
3043 case OD_SCLK:
3044 clk_type = SMU_OD_SCLK; break;
3045 case OD_MCLK:
3046 clk_type = SMU_OD_MCLK; break;
3047 case OD_VDDC_CURVE:
3048 clk_type = SMU_OD_VDDC_CURVE; break;
3049 case OD_RANGE:
3050 clk_type = SMU_OD_RANGE; break;
3051 case OD_VDDGFX_OFFSET:
3052 clk_type = SMU_OD_VDDGFX_OFFSET; break;
3053 case OD_CCLK:
3054 clk_type = SMU_OD_CCLK; break;
3055 case OD_FAN_CURVE:
3056 clk_type = SMU_OD_FAN_CURVE; break;
3057 case OD_ACOUSTIC_LIMIT:
3058 clk_type = SMU_OD_ACOUSTIC_LIMIT; break;
3059 case OD_ACOUSTIC_TARGET:
3060 clk_type = SMU_OD_ACOUSTIC_TARGET; break;
3061 case OD_FAN_TARGET_TEMPERATURE:
3062 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break;
3063 case OD_FAN_MINIMUM_PWM:
3064 clk_type = SMU_OD_FAN_MINIMUM_PWM; break;
3065 case OD_FAN_ZERO_RPM_ENABLE:
3066 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break;
3067 case OD_FAN_ZERO_RPM_STOP_TEMP:
3068 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break;
3069 default:
3070 clk_type = SMU_CLK_COUNT; break;
3071 }
3072
3073 return clk_type;
3074 }
3075
smu_emit_ppclk_levels(void * handle,enum pp_clock_type type,char * buf,int * offset)3076 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
3077 {
3078 struct smu_context *smu = handle;
3079 enum smu_clk_type clk_type;
3080
3081 clk_type = smu_convert_to_smuclk(type);
3082 if (clk_type == SMU_CLK_COUNT)
3083 return -EINVAL;
3084
3085 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3086 return -EOPNOTSUPP;
3087
3088 if (!smu->ppt_funcs->emit_clk_levels)
3089 return -ENOENT;
3090
3091 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
3092
3093 }
3094
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)3095 static int smu_od_edit_dpm_table(void *handle,
3096 enum PP_OD_DPM_TABLE_COMMAND type,
3097 long *input, uint32_t size)
3098 {
3099 struct smu_context *smu = handle;
3100 int ret = 0;
3101
3102 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3103 return -EOPNOTSUPP;
3104
3105 if (smu->ppt_funcs->od_edit_dpm_table) {
3106 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
3107 }
3108
3109 return ret;
3110 }
3111
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)3112 static int smu_read_sensor(void *handle,
3113 int sensor,
3114 void *data,
3115 int *size_arg)
3116 {
3117 struct smu_context *smu = handle;
3118 struct amdgpu_device *adev = smu->adev;
3119 struct smu_umd_pstate_table *pstate_table =
3120 &smu->pstate_table;
3121 int i, ret = 0;
3122 uint32_t *size, size_val;
3123
3124 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3125 return -EOPNOTSUPP;
3126
3127 if (!data || !size_arg)
3128 return -EINVAL;
3129
3130 size_val = *size_arg;
3131 size = &size_val;
3132
3133 if (smu->ppt_funcs->read_sensor)
3134 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
3135 goto unlock;
3136
3137 switch (sensor) {
3138 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
3139 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
3140 *size = 4;
3141 break;
3142 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
3143 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
3144 *size = 4;
3145 break;
3146 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
3147 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
3148 *size = 4;
3149 break;
3150 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
3151 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
3152 *size = 4;
3153 break;
3154 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: {
3155 struct smu_feature_bits feature_mask;
3156 uint32_t features[2];
3157
3158 /* TBD: need to handle for > 64 bits */
3159 ret = smu_feature_get_enabled_mask(smu, &feature_mask);
3160 if (!ret) {
3161 smu_feature_bits_to_arr32(&feature_mask, features, 64);
3162 *(uint64_t *)data = *(uint64_t *)features;
3163 }
3164 *size = 8;
3165 break;
3166 }
3167 case AMDGPU_PP_SENSOR_UVD_POWER:
3168 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
3169 *size = 4;
3170 break;
3171 case AMDGPU_PP_SENSOR_VCE_POWER:
3172 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
3173 *size = 4;
3174 break;
3175 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
3176 *(uint32_t *)data = 0;
3177 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
3178 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
3179 *(uint32_t *)data = 1;
3180 break;
3181 }
3182 }
3183 *size = 4;
3184 break;
3185 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
3186 *(uint32_t *)data = 0;
3187 *size = 4;
3188 break;
3189 default:
3190 *size = 0;
3191 ret = -EOPNOTSUPP;
3192 break;
3193 }
3194
3195 unlock:
3196 // assign uint32_t to int
3197 *size_arg = size_val;
3198
3199 return ret;
3200 }
3201
smu_get_apu_thermal_limit(void * handle,uint32_t * limit)3202 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)
3203 {
3204 int ret = -EOPNOTSUPP;
3205 struct smu_context *smu = handle;
3206
3207 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit)
3208 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit);
3209
3210 return ret;
3211 }
3212
smu_set_apu_thermal_limit(void * handle,uint32_t limit)3213 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)
3214 {
3215 int ret = -EOPNOTSUPP;
3216 struct smu_context *smu = handle;
3217
3218 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)
3219 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit);
3220
3221 return ret;
3222 }
3223
smu_get_power_profile_mode(void * handle,char * buf)3224 static int smu_get_power_profile_mode(void *handle, char *buf)
3225 {
3226 struct smu_context *smu = handle;
3227
3228 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3229 !smu->ppt_funcs->get_power_profile_mode)
3230 return -EOPNOTSUPP;
3231 if (!buf)
3232 return -EINVAL;
3233
3234 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
3235 }
3236
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)3237 static int smu_set_power_profile_mode(void *handle,
3238 long *param,
3239 uint32_t param_size)
3240 {
3241 struct smu_context *smu = handle;
3242 bool custom = false;
3243 int ret = 0;
3244
3245 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3246 !smu->ppt_funcs->set_power_profile_mode)
3247 return -EOPNOTSUPP;
3248
3249 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) {
3250 custom = true;
3251 /* clear frontend mask so custom changes propogate */
3252 smu->workload_mask = 0;
3253 }
3254
3255 if ((param[param_size] != smu->power_profile_mode) || custom) {
3256 /* clear the old user preference */
3257 smu_power_profile_mode_put(smu, smu->power_profile_mode);
3258 /* set the new user preference */
3259 smu_power_profile_mode_get(smu, param[param_size]);
3260 ret = smu_bump_power_profile_mode(smu,
3261 custom ? param : NULL,
3262 custom ? param_size : 0);
3263 if (ret)
3264 smu_power_profile_mode_put(smu, param[param_size]);
3265 else
3266 /* store the user's preference */
3267 smu->power_profile_mode = param[param_size];
3268 }
3269
3270 return ret;
3271 }
3272
smu_get_fan_control_mode(void * handle,u32 * fan_mode)3273 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
3274 {
3275 struct smu_context *smu = handle;
3276
3277 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3278 return -EOPNOTSUPP;
3279
3280 if (!smu->ppt_funcs->get_fan_control_mode)
3281 return -EOPNOTSUPP;
3282
3283 if (!fan_mode)
3284 return -EINVAL;
3285
3286 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
3287
3288 return 0;
3289 }
3290
smu_set_fan_control_mode(void * handle,u32 value)3291 static int smu_set_fan_control_mode(void *handle, u32 value)
3292 {
3293 struct smu_context *smu = handle;
3294 int ret = 0;
3295
3296 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3297 return -EOPNOTSUPP;
3298
3299 if (!smu->ppt_funcs->set_fan_control_mode)
3300 return -EOPNOTSUPP;
3301
3302 if (value == U32_MAX)
3303 return -EINVAL;
3304
3305 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
3306 if (ret)
3307 goto out;
3308
3309 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3310 smu->user_dpm_profile.fan_mode = value;
3311
3312 /* reset user dpm fan speed */
3313 if (value != AMD_FAN_CTRL_MANUAL) {
3314 smu->user_dpm_profile.fan_speed_pwm = 0;
3315 smu->user_dpm_profile.fan_speed_rpm = 0;
3316 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
3317 }
3318 }
3319
3320 out:
3321 return ret;
3322 }
3323
smu_get_fan_speed_pwm(void * handle,u32 * speed)3324 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
3325 {
3326 struct smu_context *smu = handle;
3327 int ret = 0;
3328
3329 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3330 return -EOPNOTSUPP;
3331
3332 if (!smu->ppt_funcs->get_fan_speed_pwm)
3333 return -EOPNOTSUPP;
3334
3335 if (!speed)
3336 return -EINVAL;
3337
3338 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
3339
3340 return ret;
3341 }
3342
smu_set_fan_speed_pwm(void * handle,u32 speed)3343 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
3344 {
3345 struct smu_context *smu = handle;
3346 int ret = 0;
3347
3348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3349 return -EOPNOTSUPP;
3350
3351 if (!smu->ppt_funcs->set_fan_speed_pwm)
3352 return -EOPNOTSUPP;
3353
3354 if (speed == U32_MAX)
3355 return -EINVAL;
3356
3357 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
3358 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
3359 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
3360 smu->user_dpm_profile.fan_speed_pwm = speed;
3361
3362 /* Override custom RPM setting as they cannot co-exist */
3363 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
3364 smu->user_dpm_profile.fan_speed_rpm = 0;
3365 }
3366
3367 return ret;
3368 }
3369
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)3370 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
3371 {
3372 struct smu_context *smu = handle;
3373 int ret = 0;
3374
3375 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3376 return -EOPNOTSUPP;
3377
3378 if (!smu->ppt_funcs->get_fan_speed_rpm)
3379 return -EOPNOTSUPP;
3380
3381 if (!speed)
3382 return -EINVAL;
3383
3384 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
3385
3386 return ret;
3387 }
3388
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)3389 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
3390 {
3391 struct smu_context *smu = handle;
3392
3393 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3394 return -EOPNOTSUPP;
3395
3396 return smu_set_min_dcef_deep_sleep(smu, clk);
3397 }
3398
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)3399 static int smu_get_clock_by_type_with_latency(void *handle,
3400 enum amd_pp_clock_type type,
3401 struct pp_clock_levels_with_latency *clocks)
3402 {
3403 struct smu_context *smu = handle;
3404 enum smu_clk_type clk_type;
3405 int ret = 0;
3406
3407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3408 return -EOPNOTSUPP;
3409
3410 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
3411 switch (type) {
3412 case amd_pp_sys_clock:
3413 clk_type = SMU_GFXCLK;
3414 break;
3415 case amd_pp_mem_clock:
3416 clk_type = SMU_MCLK;
3417 break;
3418 case amd_pp_dcef_clock:
3419 clk_type = SMU_DCEFCLK;
3420 break;
3421 case amd_pp_disp_clock:
3422 clk_type = SMU_DISPCLK;
3423 break;
3424 default:
3425 dev_err(smu->adev->dev, "Invalid clock type!\n");
3426 return -EINVAL;
3427 }
3428
3429 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
3430 }
3431
3432 return ret;
3433 }
3434
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)3435 static int smu_display_clock_voltage_request(void *handle,
3436 struct pp_display_clock_request *clock_req)
3437 {
3438 struct smu_context *smu = handle;
3439 int ret = 0;
3440
3441 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3442 return -EOPNOTSUPP;
3443
3444 if (smu->ppt_funcs->display_clock_voltage_request)
3445 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
3446
3447 return ret;
3448 }
3449
3450
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)3451 static int smu_display_disable_memory_clock_switch(void *handle,
3452 bool disable_memory_clock_switch)
3453 {
3454 struct smu_context *smu = handle;
3455 int ret = -EINVAL;
3456
3457 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3458 return -EOPNOTSUPP;
3459
3460 if (smu->ppt_funcs->display_disable_memory_clock_switch)
3461 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
3462
3463 return ret;
3464 }
3465
smu_set_xgmi_pstate(void * handle,uint32_t pstate)3466 static int smu_set_xgmi_pstate(void *handle,
3467 uint32_t pstate)
3468 {
3469 struct smu_context *smu = handle;
3470 int ret = 0;
3471
3472 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3473 return -EOPNOTSUPP;
3474
3475 if (smu->ppt_funcs->set_xgmi_pstate)
3476 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
3477
3478 if (ret)
3479 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
3480
3481 return ret;
3482 }
3483
smu_get_baco_capability(void * handle)3484 static int smu_get_baco_capability(void *handle)
3485 {
3486 struct smu_context *smu = handle;
3487
3488 if (!smu->pm_enabled)
3489 return false;
3490
3491 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support)
3492 return false;
3493
3494 return smu->ppt_funcs->get_bamaco_support(smu);
3495 }
3496
smu_baco_set_state(void * handle,int state)3497 static int smu_baco_set_state(void *handle, int state)
3498 {
3499 struct smu_context *smu = handle;
3500 int ret = 0;
3501
3502 if (!smu->pm_enabled)
3503 return -EOPNOTSUPP;
3504
3505 if (state == 0) {
3506 if (smu->ppt_funcs->baco_exit)
3507 ret = smu->ppt_funcs->baco_exit(smu);
3508 } else if (state == 1) {
3509 if (smu->ppt_funcs->baco_enter)
3510 ret = smu->ppt_funcs->baco_enter(smu);
3511 } else {
3512 return -EINVAL;
3513 }
3514
3515 if (ret)
3516 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
3517 (state)?"enter":"exit");
3518
3519 return ret;
3520 }
3521
smu_mode1_reset_is_support(struct smu_context * smu)3522 bool smu_mode1_reset_is_support(struct smu_context *smu)
3523 {
3524 bool ret = false;
3525
3526 if (!smu->pm_enabled)
3527 return false;
3528
3529 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
3530 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
3531
3532 return ret;
3533 }
3534
smu_link_reset_is_support(struct smu_context * smu)3535 bool smu_link_reset_is_support(struct smu_context *smu)
3536 {
3537 if (!smu->pm_enabled)
3538 return false;
3539
3540 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET);
3541 }
3542
smu_mode1_reset(struct smu_context * smu)3543 int smu_mode1_reset(struct smu_context *smu)
3544 {
3545 int ret = 0;
3546
3547 if (!smu->pm_enabled)
3548 return -EOPNOTSUPP;
3549
3550 if (smu->ppt_funcs->mode1_reset)
3551 ret = smu->ppt_funcs->mode1_reset(smu);
3552
3553 return ret;
3554 }
3555
smu_mode2_reset(void * handle)3556 static int smu_mode2_reset(void *handle)
3557 {
3558 struct smu_context *smu = handle;
3559 int ret = 0;
3560
3561 if (!smu->pm_enabled)
3562 return -EOPNOTSUPP;
3563
3564 if (smu->ppt_funcs->mode2_reset)
3565 ret = smu->ppt_funcs->mode2_reset(smu);
3566
3567 if (ret)
3568 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
3569
3570 return ret;
3571 }
3572
smu_link_reset(struct smu_context * smu)3573 int smu_link_reset(struct smu_context *smu)
3574 {
3575 int ret = 0;
3576
3577 if (!smu->pm_enabled)
3578 return -EOPNOTSUPP;
3579
3580 if (smu->ppt_funcs->link_reset)
3581 ret = smu->ppt_funcs->link_reset(smu);
3582
3583 return ret;
3584 }
3585
smu_enable_gfx_features(void * handle)3586 static int smu_enable_gfx_features(void *handle)
3587 {
3588 struct smu_context *smu = handle;
3589 int ret = 0;
3590
3591 if (!smu->pm_enabled)
3592 return -EOPNOTSUPP;
3593
3594 if (smu->ppt_funcs->enable_gfx_features)
3595 ret = smu->ppt_funcs->enable_gfx_features(smu);
3596
3597 if (ret)
3598 dev_err(smu->adev->dev, "enable gfx features failed!\n");
3599
3600 return ret;
3601 }
3602
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)3603 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
3604 struct pp_smu_nv_clock_table *max_clocks)
3605 {
3606 struct smu_context *smu = handle;
3607 int ret = 0;
3608
3609 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3610 return -EOPNOTSUPP;
3611
3612 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
3613 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
3614
3615 return ret;
3616 }
3617
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)3618 static int smu_get_uclk_dpm_states(void *handle,
3619 unsigned int *clock_values_in_khz,
3620 unsigned int *num_states)
3621 {
3622 struct smu_context *smu = handle;
3623 int ret = 0;
3624
3625 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3626 return -EOPNOTSUPP;
3627
3628 if (smu->ppt_funcs->get_uclk_dpm_states)
3629 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
3630
3631 return ret;
3632 }
3633
smu_get_current_power_state(void * handle)3634 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
3635 {
3636 struct smu_context *smu = handle;
3637 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
3638
3639 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3640 return -EOPNOTSUPP;
3641
3642 if (smu->ppt_funcs->get_current_power_state)
3643 pm_state = smu->ppt_funcs->get_current_power_state(smu);
3644
3645 return pm_state;
3646 }
3647
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)3648 static int smu_get_dpm_clock_table(void *handle,
3649 struct dpm_clocks *clock_table)
3650 {
3651 struct smu_context *smu = handle;
3652 int ret = 0;
3653
3654 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3655 return -EOPNOTSUPP;
3656
3657 if (smu->ppt_funcs->get_dpm_clock_table)
3658 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3659
3660 return ret;
3661 }
3662
smu_sys_get_gpu_metrics(void * handle,void ** table)3663 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3664 {
3665 struct smu_context *smu = handle;
3666 struct smu_table_context *smu_table = &smu->smu_table;
3667 struct smu_driver_table *driver_tables = smu_table->driver_tables;
3668 struct smu_driver_table *gpu_metrics_table;
3669
3670 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3671 return -EOPNOTSUPP;
3672
3673 if (!smu->ppt_funcs->get_gpu_metrics)
3674 return -EOPNOTSUPP;
3675
3676 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS];
3677
3678 /* If cached table is valid, return it */
3679 if (smu_driver_table_is_valid(gpu_metrics_table)) {
3680 *table = gpu_metrics_table->cache.buffer;
3681 return gpu_metrics_table->cache.size;
3682 }
3683
3684 return smu->ppt_funcs->get_gpu_metrics(smu, table);
3685 }
3686
smu_sys_get_pm_metrics(void * handle,void * pm_metrics,size_t size)3687 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics,
3688 size_t size)
3689 {
3690 struct smu_context *smu = handle;
3691
3692 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3693 return -EOPNOTSUPP;
3694
3695 if (!smu->ppt_funcs->get_pm_metrics)
3696 return -EOPNOTSUPP;
3697
3698 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size);
3699 }
3700
smu_enable_mgpu_fan_boost(void * handle)3701 static int smu_enable_mgpu_fan_boost(void *handle)
3702 {
3703 struct smu_context *smu = handle;
3704 int ret = 0;
3705
3706 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3707 return -EOPNOTSUPP;
3708
3709 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3710 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3711
3712 return ret;
3713 }
3714
smu_gfx_state_change_set(void * handle,uint32_t state)3715 static int smu_gfx_state_change_set(void *handle,
3716 uint32_t state)
3717 {
3718 struct smu_context *smu = handle;
3719 int ret = 0;
3720
3721 if (smu->ppt_funcs->gfx_state_change_set)
3722 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3723
3724 return ret;
3725 }
3726
smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)3727 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
3728 {
3729 int ret = 0;
3730
3731 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3732 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
3733
3734 return ret;
3735 }
3736
smu_get_ecc_info(struct smu_context * smu,void * umc_ecc)3737 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
3738 {
3739 int ret = -EOPNOTSUPP;
3740
3741 if (smu->ppt_funcs &&
3742 smu->ppt_funcs->get_ecc_info)
3743 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3744
3745 return ret;
3746
3747 }
3748
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3749 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3750 {
3751 struct smu_context *smu = handle;
3752 struct smu_table_context *smu_table = &smu->smu_table;
3753 struct smu_table *memory_pool = &smu_table->memory_pool;
3754
3755 if (!addr || !size)
3756 return -EINVAL;
3757
3758 *addr = NULL;
3759 *size = 0;
3760 if (memory_pool->bo) {
3761 *addr = memory_pool->cpu_addr;
3762 *size = memory_pool->size;
3763 }
3764
3765 return 0;
3766 }
3767
smu_print_dpm_policy(struct smu_dpm_policy * policy,char * sysbuf,size_t * size)3768 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf,
3769 size_t *size)
3770 {
3771 size_t offset = *size;
3772 int level;
3773
3774 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) {
3775 if (level == policy->current_level)
3776 offset += sysfs_emit_at(sysbuf, offset,
3777 "%d : %s*\n", level,
3778 policy->desc->get_desc(policy, level));
3779 else
3780 offset += sysfs_emit_at(sysbuf, offset,
3781 "%d : %s\n", level,
3782 policy->desc->get_desc(policy, level));
3783 }
3784
3785 *size = offset;
3786 }
3787
smu_get_pm_policy_info(struct smu_context * smu,enum pp_pm_policy p_type,char * sysbuf)3788 ssize_t smu_get_pm_policy_info(struct smu_context *smu,
3789 enum pp_pm_policy p_type, char *sysbuf)
3790 {
3791 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3792 struct smu_dpm_policy_ctxt *policy_ctxt;
3793 struct smu_dpm_policy *dpm_policy;
3794 size_t offset = 0;
3795
3796 policy_ctxt = dpm_ctxt->dpm_policies;
3797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt ||
3798 !policy_ctxt->policy_mask)
3799 return -EOPNOTSUPP;
3800
3801 if (p_type == PP_PM_POLICY_NONE)
3802 return -EINVAL;
3803
3804 dpm_policy = smu_get_pm_policy(smu, p_type);
3805 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc)
3806 return -ENOENT;
3807
3808 if (!sysbuf)
3809 return -EINVAL;
3810
3811 smu_print_dpm_policy(dpm_policy, sysbuf, &offset);
3812
3813 return offset;
3814 }
3815
smu_get_pm_policy(struct smu_context * smu,enum pp_pm_policy p_type)3816 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu,
3817 enum pp_pm_policy p_type)
3818 {
3819 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3820 struct smu_dpm_policy_ctxt *policy_ctxt;
3821 int i;
3822
3823 policy_ctxt = dpm_ctxt->dpm_policies;
3824 if (!policy_ctxt)
3825 return NULL;
3826
3827 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) {
3828 if (policy_ctxt->policies[i].policy_type == p_type)
3829 return &policy_ctxt->policies[i];
3830 }
3831
3832 return NULL;
3833 }
3834
smu_set_pm_policy(struct smu_context * smu,enum pp_pm_policy p_type,int level)3835 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
3836 int level)
3837 {
3838 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm;
3839 struct smu_dpm_policy *dpm_policy = NULL;
3840 struct smu_dpm_policy_ctxt *policy_ctxt;
3841 int ret = -EOPNOTSUPP;
3842
3843 policy_ctxt = dpm_ctxt->dpm_policies;
3844 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt ||
3845 !policy_ctxt->policy_mask)
3846 return ret;
3847
3848 if (level < 0 || level >= PP_POLICY_MAX_LEVELS)
3849 return -EINVAL;
3850
3851 dpm_policy = smu_get_pm_policy(smu, p_type);
3852
3853 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy)
3854 return ret;
3855
3856 if (dpm_policy->current_level == level)
3857 return 0;
3858
3859 ret = dpm_policy->set_policy(smu, level);
3860
3861 if (!ret)
3862 dpm_policy->current_level = level;
3863
3864 return ret;
3865 }
3866
smu_sys_get_temp_metrics(void * handle,enum smu_temp_metric_type type,void * table)3867 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table)
3868 {
3869 struct smu_context *smu = handle;
3870 struct smu_table_context *smu_table = &smu->smu_table;
3871 struct smu_driver_table *driver_tables = smu_table->driver_tables;
3872 enum smu_driver_table_id table_id;
3873 struct smu_driver_table *temp_table;
3874
3875 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3876 return -EOPNOTSUPP;
3877
3878 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics)
3879 return -EOPNOTSUPP;
3880
3881 table_id = smu_metrics_get_temp_table_id(type);
3882
3883 if (table_id == SMU_DRIVER_TABLE_COUNT)
3884 return -EINVAL;
3885
3886 temp_table = &driver_tables[table_id];
3887
3888 /* If the request is to get size alone, return the cached table size */
3889 if (!table && temp_table->cache.size)
3890 return temp_table->cache.size;
3891
3892 if (smu_driver_table_is_valid(temp_table)) {
3893 memcpy(table, temp_table->cache.buffer, temp_table->cache.size);
3894 return temp_table->cache.size;
3895 }
3896
3897 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table);
3898 }
3899
smu_temp_metrics_is_supported(void * handle,enum smu_temp_metric_type type)3900 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type)
3901 {
3902 struct smu_context *smu = handle;
3903 bool ret = false;
3904
3905 if (!smu->pm_enabled)
3906 return false;
3907
3908 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported)
3909 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type);
3910
3911 return ret;
3912 }
3913
smu_sys_get_xcp_metrics(void * handle,int xcp_id,void * table)3914 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table)
3915 {
3916 struct smu_context *smu = handle;
3917
3918 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3919 return -EOPNOTSUPP;
3920
3921 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics)
3922 return -EOPNOTSUPP;
3923
3924 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table);
3925 }
3926
3927 static const struct amd_pm_funcs swsmu_pm_funcs = {
3928 /* export for sysfs */
3929 .set_fan_control_mode = smu_set_fan_control_mode,
3930 .get_fan_control_mode = smu_get_fan_control_mode,
3931 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3932 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3933 .force_clock_level = smu_force_ppclk_levels,
3934 .emit_clock_levels = smu_emit_ppclk_levels,
3935 .force_performance_level = smu_force_performance_level,
3936 .read_sensor = smu_read_sensor,
3937 .get_apu_thermal_limit = smu_get_apu_thermal_limit,
3938 .set_apu_thermal_limit = smu_set_apu_thermal_limit,
3939 .get_performance_level = smu_get_performance_level,
3940 .get_current_power_state = smu_get_current_power_state,
3941 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3942 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3943 .get_pp_num_states = smu_get_power_num_states,
3944 .get_pp_table = smu_sys_get_pp_table,
3945 .set_pp_table = smu_sys_set_pp_table,
3946 .switch_power_profile = smu_switch_power_profile,
3947 .pause_power_profile = smu_pause_power_profile,
3948 /* export to amdgpu */
3949 .dispatch_tasks = smu_handle_dpm_task,
3950 .load_firmware = smu_load_microcode,
3951 .set_powergating_by_smu = smu_dpm_set_power_gate,
3952 .set_power_limit = smu_set_power_limit,
3953 .get_power_limit = smu_get_power_limit,
3954 .get_power_profile_mode = smu_get_power_profile_mode,
3955 .set_power_profile_mode = smu_set_power_profile_mode,
3956 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3957 .set_mp1_state = smu_set_mp1_state,
3958 .gfx_state_change_set = smu_gfx_state_change_set,
3959 /* export to DC */
3960 .get_sclk = smu_get_sclk,
3961 .get_mclk = smu_get_mclk,
3962 .display_configuration_change = smu_display_configuration_change,
3963 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3964 .display_clock_voltage_request = smu_display_clock_voltage_request,
3965 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3966 .set_active_display_count = smu_set_display_count,
3967 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3968 .get_asic_baco_capability = smu_get_baco_capability,
3969 .set_asic_baco_state = smu_baco_set_state,
3970 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3971 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3972 .asic_reset_mode_2 = smu_mode2_reset,
3973 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3974 .set_df_cstate = smu_set_df_cstate,
3975 .set_xgmi_pstate = smu_set_xgmi_pstate,
3976 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3977 .get_pm_metrics = smu_sys_get_pm_metrics,
3978 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3979 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3980 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3981 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3982 .get_dpm_clock_table = smu_get_dpm_clock_table,
3983 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3984 .get_xcp_metrics = smu_sys_get_xcp_metrics,
3985 .get_temp_metrics = smu_sys_get_temp_metrics,
3986 .temp_metrics_is_supported = smu_temp_metrics_is_supported,
3987 };
3988
smu_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)3989 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3990 uint64_t event_arg)
3991 {
3992 int ret = -EINVAL;
3993
3994 if (smu->ppt_funcs->wait_for_event)
3995 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3996
3997 return ret;
3998 }
3999
smu_stb_collect_info(struct smu_context * smu,void * buf,uint32_t size)4000 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
4001 {
4002
4003 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
4004 return -EOPNOTSUPP;
4005
4006 /* Confirm the buffer allocated is of correct size */
4007 if (size != smu->stb_context.stb_buf_size)
4008 return -EINVAL;
4009
4010 /*
4011 * No need to lock smu mutex as we access STB directly through MMIO
4012 * and not going through SMU messaging route (for now at least).
4013 * For registers access rely on implementation internal locking.
4014 */
4015 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
4016 }
4017
4018 #if defined(CONFIG_DEBUG_FS)
4019
smu_stb_debugfs_open(struct inode * inode,struct file * filp)4020 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
4021 {
4022 struct amdgpu_device *adev = filp->f_inode->i_private;
4023 struct smu_context *smu = adev->powerplay.pp_handle;
4024 unsigned char *buf;
4025 int r;
4026
4027 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
4028 if (!buf)
4029 return -ENOMEM;
4030
4031 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
4032 if (r)
4033 goto out;
4034
4035 filp->private_data = buf;
4036
4037 return 0;
4038
4039 out:
4040 kvfree(buf);
4041 return r;
4042 }
4043
smu_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)4044 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
4045 loff_t *pos)
4046 {
4047 struct amdgpu_device *adev = filp->f_inode->i_private;
4048 struct smu_context *smu = adev->powerplay.pp_handle;
4049
4050
4051 if (!filp->private_data)
4052 return -EINVAL;
4053
4054 return simple_read_from_buffer(buf,
4055 size,
4056 pos, filp->private_data,
4057 smu->stb_context.stb_buf_size);
4058 }
4059
smu_stb_debugfs_release(struct inode * inode,struct file * filp)4060 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
4061 {
4062 kvfree(filp->private_data);
4063 filp->private_data = NULL;
4064
4065 return 0;
4066 }
4067
4068 /*
4069 * We have to define not only read method but also
4070 * open and release because .read takes up to PAGE_SIZE
4071 * data each time so and so is invoked multiple times.
4072 * We allocate the STB buffer in .open and release it
4073 * in .release
4074 */
4075 static const struct file_operations smu_stb_debugfs_fops = {
4076 .owner = THIS_MODULE,
4077 .open = smu_stb_debugfs_open,
4078 .read = smu_stb_debugfs_read,
4079 .release = smu_stb_debugfs_release,
4080 .llseek = default_llseek,
4081 };
4082
4083 #endif
4084
amdgpu_smu_stb_debug_fs_init(struct amdgpu_device * adev)4085 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
4086 {
4087 #if defined(CONFIG_DEBUG_FS)
4088
4089 struct smu_context *smu = adev->powerplay.pp_handle;
4090
4091 if (!smu || (!smu->stb_context.stb_buf_size))
4092 return;
4093
4094 debugfs_create_file_size("amdgpu_smu_stb_dump",
4095 S_IRUSR,
4096 adev_to_drm(adev)->primary->debugfs_root,
4097 adev,
4098 &smu_stb_debugfs_fops,
4099 smu->stb_context.stb_buf_size);
4100 #endif
4101 }
4102
smu_send_hbm_bad_pages_num(struct smu_context * smu,uint32_t size)4103 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
4104 {
4105 int ret = 0;
4106
4107 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
4108 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
4109
4110 return ret;
4111 }
4112
smu_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)4113 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
4114 {
4115 int ret = 0;
4116
4117 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
4118 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
4119
4120 return ret;
4121 }
4122
smu_send_rma_reason(struct smu_context * smu)4123 int smu_send_rma_reason(struct smu_context *smu)
4124 {
4125 int ret = 0;
4126
4127 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
4128 ret = smu->ppt_funcs->send_rma_reason(smu);
4129
4130 return ret;
4131 }
4132
4133 /**
4134 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU
4135 * @smu: smu_context pointer
4136 *
4137 * This function checks if the SMU supports resetting the SDMA engine.
4138 * It returns true if supported, false otherwise.
4139 */
smu_reset_sdma_is_supported(struct smu_context * smu)4140 bool smu_reset_sdma_is_supported(struct smu_context *smu)
4141 {
4142 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET);
4143 }
4144
smu_reset_sdma(struct smu_context * smu,uint32_t inst_mask)4145 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
4146 {
4147 int ret = 0;
4148
4149 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma)
4150 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask);
4151
4152 return ret;
4153 }
4154
smu_reset_vcn_is_supported(struct smu_context * smu)4155 bool smu_reset_vcn_is_supported(struct smu_context *smu)
4156 {
4157 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET);
4158 }
4159
smu_reset_vcn(struct smu_context * smu,uint32_t inst_mask)4160 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
4161 {
4162 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn)
4163 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask);
4164
4165 return 0;
4166 }
4167