1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L4
24
25 #include "amdgpu.h"
26 #include "amdgpu_smu.h"
27 #include "smu_cmn.h"
28 #include "soc15_common.h"
29
30 /*
31 * DO NOT use these for err/warn/info/debug messages.
32 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
33 * They are more MGPU friendly.
34 */
35 #undef pr_err
36 #undef pr_warn
37 #undef pr_info
38 #undef pr_debug
39
40 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
41
42 const int link_speed[] = {25, 50, 80, 160, 320, 640};
43
44 #undef __SMU_DUMMY_MAP
45 #define __SMU_DUMMY_MAP(type) #type
46 static const char * const __smu_message_names[] = {
47 SMU_MESSAGE_TYPES
48 };
49
50 #define smu_cmn_call_asic_func(intf, smu, args...) \
51 ((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ? \
52 (smu)->ppt_funcs->intf(smu, ##args) : \
53 -ENOTSUPP) : \
54 -EINVAL)
55
smu_get_message_name(struct smu_context * smu,enum smu_message_type type)56 static const char *smu_get_message_name(struct smu_context *smu,
57 enum smu_message_type type)
58 {
59 if (type >= SMU_MSG_MAX_COUNT)
60 return "unknown smu message";
61
62 return __smu_message_names[type];
63 }
64
smu_cmn_read_arg(struct smu_context * smu,uint32_t * arg)65 static void smu_cmn_read_arg(struct smu_context *smu,
66 uint32_t *arg)
67 {
68 struct amdgpu_device *adev = smu->adev;
69
70 *arg = RREG32(smu->param_reg);
71 }
72
73 /* Redefine the SMU error codes here.
74 *
75 * Note that these definitions are redundant and should be removed
76 * when the SMU has exported a unified header file containing these
77 * macros, which header file we can just include and use the SMU's
78 * macros. At the moment, these error codes are defined by the SMU
79 * per-ASIC unfortunately, yet we're a one driver for all ASICs.
80 */
81 #define SMU_RESP_NONE 0
82 #define SMU_RESP_OK 1
83 #define SMU_RESP_CMD_FAIL 0xFF
84 #define SMU_RESP_CMD_UNKNOWN 0xFE
85 #define SMU_RESP_CMD_BAD_PREREQ 0xFD
86 #define SMU_RESP_BUSY_OTHER 0xFC
87 #define SMU_RESP_DEBUG_END 0xFB
88
89 /**
90 * __smu_cmn_poll_stat -- poll for a status from the SMU
91 * @smu: a pointer to SMU context
92 *
93 * Returns the status of the SMU, which could be,
94 * 0, the SMU is busy with your command;
95 * 1, execution status: success, execution result: success;
96 * 0xFF, execution status: success, execution result: failure;
97 * 0xFE, unknown command;
98 * 0xFD, valid command, but bad (command) prerequisites;
99 * 0xFC, the command was rejected as the SMU is busy;
100 * 0xFB, "SMC_Result_DebugDataDumpEnd".
101 *
102 * The values here are not defined by macros, because I'd rather we
103 * include a single header file which defines them, which is
104 * maintained by the SMU FW team, so that we're impervious to firmware
105 * changes. At the moment those values are defined in various header
106 * files, one for each ASIC, yet here we're a single ASIC-agnostic
107 * interface. Such a change can be followed-up by a subsequent patch.
108 */
__smu_cmn_poll_stat(struct smu_context * smu)109 static u32 __smu_cmn_poll_stat(struct smu_context *smu)
110 {
111 struct amdgpu_device *adev = smu->adev;
112 int timeout = adev->usec_timeout * 20;
113 u32 reg;
114
115 for ( ; timeout > 0; timeout--) {
116 reg = RREG32(smu->resp_reg);
117 if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
118 break;
119
120 udelay(1);
121 }
122
123 return reg;
124 }
125
__smu_cmn_reg_print_error(struct smu_context * smu,u32 reg_c2pmsg_90,int msg_index,u32 param,enum smu_message_type msg)126 static void __smu_cmn_reg_print_error(struct smu_context *smu,
127 u32 reg_c2pmsg_90,
128 int msg_index,
129 u32 param,
130 enum smu_message_type msg)
131 {
132 struct amdgpu_device *adev = smu->adev;
133 const char *message = smu_get_message_name(smu, msg);
134 u32 msg_idx, prm;
135
136 switch (reg_c2pmsg_90) {
137 case SMU_RESP_NONE: {
138 msg_idx = RREG32(smu->msg_reg);
139 prm = RREG32(smu->param_reg);
140 dev_err_ratelimited(adev->dev,
141 "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
142 msg_idx, prm);
143 }
144 break;
145 case SMU_RESP_OK:
146 /* The SMU executed the command. It completed with a
147 * successful result.
148 */
149 break;
150 case SMU_RESP_CMD_FAIL:
151 /* The SMU executed the command. It completed with an
152 * unsuccessful result.
153 */
154 break;
155 case SMU_RESP_CMD_UNKNOWN:
156 dev_err_ratelimited(adev->dev,
157 "SMU: unknown command: index:%d param:0x%08X message:%s",
158 msg_index, param, message);
159 break;
160 case SMU_RESP_CMD_BAD_PREREQ:
161 dev_err_ratelimited(adev->dev,
162 "SMU: valid command, bad prerequisites: index:%d param:0x%08X message:%s",
163 msg_index, param, message);
164 break;
165 case SMU_RESP_BUSY_OTHER:
166 dev_err_ratelimited(adev->dev,
167 "SMU: I'm very busy for your command: index:%d param:0x%08X message:%s",
168 msg_index, param, message);
169 break;
170 case SMU_RESP_DEBUG_END:
171 dev_err_ratelimited(adev->dev,
172 "SMU: I'm debugging!");
173 break;
174 default:
175 dev_err_ratelimited(adev->dev,
176 "SMU: response:0x%08X for index:%d param:0x%08X message:%s?",
177 reg_c2pmsg_90, msg_index, param, message);
178 break;
179 }
180 }
181
__smu_cmn_reg2errno(struct smu_context * smu,u32 reg_c2pmsg_90)182 static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90)
183 {
184 int res;
185
186 switch (reg_c2pmsg_90) {
187 case SMU_RESP_NONE:
188 /* The SMU is busy--still executing your command.
189 */
190 res = -ETIME;
191 break;
192 case SMU_RESP_OK:
193 res = 0;
194 break;
195 case SMU_RESP_CMD_FAIL:
196 /* Command completed successfully, but the command
197 * status was failure.
198 */
199 res = -EIO;
200 break;
201 case SMU_RESP_CMD_UNKNOWN:
202 /* Unknown command--ignored by the SMU.
203 */
204 res = -EOPNOTSUPP;
205 break;
206 case SMU_RESP_CMD_BAD_PREREQ:
207 /* Valid command--bad prerequisites.
208 */
209 res = -EINVAL;
210 break;
211 case SMU_RESP_BUSY_OTHER:
212 /* The SMU is busy with other commands. The client
213 * should retry in 10 us.
214 */
215 res = -EBUSY;
216 break;
217 default:
218 /* Unknown or debug response from the SMU.
219 */
220 res = -EREMOTEIO;
221 break;
222 }
223
224 return res;
225 }
226
__smu_cmn_send_msg(struct smu_context * smu,u16 msg,u32 param)227 static void __smu_cmn_send_msg(struct smu_context *smu,
228 u16 msg,
229 u32 param)
230 {
231 struct amdgpu_device *adev = smu->adev;
232
233 WREG32(smu->resp_reg, 0);
234 WREG32(smu->param_reg, param);
235 WREG32(smu->msg_reg, msg);
236 }
237
__smu_cmn_get_msg_flags(struct smu_context * smu,enum smu_message_type msg)238 static inline uint32_t __smu_cmn_get_msg_flags(struct smu_context *smu,
239 enum smu_message_type msg)
240 {
241 return smu->message_map[msg].flags;
242 }
243
__smu_cmn_ras_filter_msg(struct smu_context * smu,enum smu_message_type msg,bool * poll)244 static int __smu_cmn_ras_filter_msg(struct smu_context *smu,
245 enum smu_message_type msg, bool *poll)
246 {
247 struct amdgpu_device *adev = smu->adev;
248 uint32_t flags, resp;
249 bool fed_status;
250
251 flags = __smu_cmn_get_msg_flags(smu, msg);
252 *poll = true;
253
254 /* When there is RAS fatal error, FW won't process non-RAS priority
255 * messages. Don't allow any messages other than RAS priority messages.
256 */
257 fed_status = amdgpu_ras_get_fed_status(adev);
258 if (fed_status) {
259 if (!(flags & SMU_MSG_RAS_PRI)) {
260 dev_dbg(adev->dev,
261 "RAS error detected, skip sending %s",
262 smu_get_message_name(smu, msg));
263 return -EACCES;
264 }
265
266 /* FW will ignore non-priority messages when a RAS fatal error
267 * is detected. Hence it is possible that a previous message
268 * wouldn't have got response. Allow to continue without polling
269 * for response status for priority messages.
270 */
271 resp = RREG32(smu->resp_reg);
272 dev_dbg(adev->dev,
273 "Sending RAS priority message %s response status: %x",
274 smu_get_message_name(smu, msg), resp);
275 if (resp == 0)
276 *poll = false;
277 }
278
279 return 0;
280 }
281
__smu_cmn_send_debug_msg(struct smu_context * smu,u32 msg,u32 param)282 static int __smu_cmn_send_debug_msg(struct smu_context *smu,
283 u32 msg,
284 u32 param)
285 {
286 struct amdgpu_device *adev = smu->adev;
287
288 WREG32(smu->debug_param_reg, param);
289 WREG32(smu->debug_msg_reg, msg);
290 WREG32(smu->debug_resp_reg, 0);
291
292 return 0;
293 }
294 /**
295 * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status
296 * @smu: pointer to an SMU context
297 * @msg_index: message index
298 * @param: message parameter to send to the SMU
299 *
300 * Send a message to the SMU with the parameter passed. Do not wait
301 * for status/result of the message, thus the "without_waiting".
302 *
303 * Return 0 on success, -errno on error if we weren't able to _send_
304 * the message for some reason. See __smu_cmn_reg2errno() for details
305 * of the -errno.
306 */
smu_cmn_send_msg_without_waiting(struct smu_context * smu,uint16_t msg_index,uint32_t param)307 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
308 uint16_t msg_index,
309 uint32_t param)
310 {
311 struct amdgpu_device *adev = smu->adev;
312 u32 reg;
313 int res;
314
315 if (adev->no_hw_access)
316 return 0;
317
318 if (smu->smc_fw_state == SMU_FW_HANG) {
319 dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n");
320 res = -EREMOTEIO;
321 goto Out;
322 }
323
324 if (smu->smc_fw_state == SMU_FW_INIT) {
325 smu->smc_fw_state = SMU_FW_RUNTIME;
326 } else {
327 reg = __smu_cmn_poll_stat(smu);
328 res = __smu_cmn_reg2errno(smu, reg);
329 if (reg == SMU_RESP_NONE || res == -EREMOTEIO)
330 goto Out;
331 }
332
333 __smu_cmn_send_msg(smu, msg_index, param);
334 res = 0;
335 Out:
336 if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
337 res && (res != -ETIME)) {
338 amdgpu_device_halt(adev);
339 WARN_ON(1);
340 }
341
342 return res;
343 }
344
345 /**
346 * smu_cmn_wait_for_response -- wait for response from the SMU
347 * @smu: pointer to an SMU context
348 *
349 * Wait for status from the SMU.
350 *
351 * Return 0 on success, -errno on error, indicating the execution
352 * status and result of the message being waited for. See
353 * __smu_cmn_reg2errno() for details of the -errno.
354 */
smu_cmn_wait_for_response(struct smu_context * smu)355 int smu_cmn_wait_for_response(struct smu_context *smu)
356 {
357 u32 reg;
358 int res;
359
360 reg = __smu_cmn_poll_stat(smu);
361 res = __smu_cmn_reg2errno(smu, reg);
362
363 if (res == -EREMOTEIO)
364 smu->smc_fw_state = SMU_FW_HANG;
365
366 if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
367 res && (res != -ETIME)) {
368 amdgpu_device_halt(smu->adev);
369 WARN_ON(1);
370 }
371
372 return res;
373 }
374
375 /**
376 * smu_cmn_send_smc_msg_with_param -- send a message with parameter
377 * @smu: pointer to an SMU context
378 * @msg: message to send
379 * @param: parameter to send to the SMU
380 * @read_arg: pointer to u32 to return a value from the SMU back
381 * to the caller
382 *
383 * Send the message @msg with parameter @param to the SMU, wait for
384 * completion of the command, and return back a value from the SMU in
385 * @read_arg pointer.
386 *
387 * Return 0 on success, -errno when a problem is encountered sending
388 * message or receiving reply. If there is a PCI bus recovery or
389 * the destination is a virtual GPU which does not allow this message
390 * type, the message is simply dropped and success is also returned.
391 * See __smu_cmn_reg2errno() for details of the -errno.
392 *
393 * If we weren't able to send the message to the SMU, we also print
394 * the error to the standard log.
395 *
396 * Command completion status is printed only if the -errno is
397 * -EREMOTEIO, indicating that the SMU returned back an
398 * undefined/unknown/unspecified result. All other cases are
399 * well-defined, not printed, but instead given back to the client to
400 * decide what further to do.
401 *
402 * The return value, @read_arg is read back regardless, to give back
403 * more information to the client, which on error would most likely be
404 * @param, but we can't assume that. This also eliminates more
405 * conditionals.
406 */
smu_cmn_send_smc_msg_with_param(struct smu_context * smu,enum smu_message_type msg,uint32_t param,uint32_t * read_arg)407 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
408 enum smu_message_type msg,
409 uint32_t param,
410 uint32_t *read_arg)
411 {
412 struct amdgpu_device *adev = smu->adev;
413 int res, index;
414 bool poll = true;
415 u32 reg;
416
417 if (adev->no_hw_access)
418 return 0;
419
420 index = smu_cmn_to_asic_specific_index(smu,
421 CMN2ASIC_MAPPING_MSG,
422 msg);
423 if (index < 0)
424 return index == -EACCES ? 0 : index;
425
426 mutex_lock(&smu->message_lock);
427
428 if (smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI) {
429 res = __smu_cmn_ras_filter_msg(smu, msg, &poll);
430 if (res)
431 goto Out;
432 }
433
434 if (smu->smc_fw_state == SMU_FW_HANG) {
435 dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n");
436 res = -EREMOTEIO;
437 goto Out;
438 } else if (smu->smc_fw_state == SMU_FW_INIT) {
439 /* Ignore initial smu response register value */
440 poll = false;
441 smu->smc_fw_state = SMU_FW_RUNTIME;
442 }
443
444 if (poll) {
445 reg = __smu_cmn_poll_stat(smu);
446 res = __smu_cmn_reg2errno(smu, reg);
447 if (reg == SMU_RESP_NONE || res == -EREMOTEIO) {
448 __smu_cmn_reg_print_error(smu, reg, index, param, msg);
449 goto Out;
450 }
451 }
452 __smu_cmn_send_msg(smu, (uint16_t) index, param);
453 reg = __smu_cmn_poll_stat(smu);
454 res = __smu_cmn_reg2errno(smu, reg);
455 if (res != 0) {
456 if (res == -EREMOTEIO)
457 smu->smc_fw_state = SMU_FW_HANG;
458 __smu_cmn_reg_print_error(smu, reg, index, param, msg);
459 }
460 if (read_arg) {
461 smu_cmn_read_arg(smu, read_arg);
462 dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x,\
463 readval: 0x%08x\n",
464 smu_get_message_name(smu, msg), index, param, reg, *read_arg);
465 } else {
466 dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x\n",
467 smu_get_message_name(smu, msg), index, param, reg);
468 }
469 Out:
470 if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) {
471 amdgpu_device_halt(adev);
472 WARN_ON(1);
473 }
474
475 mutex_unlock(&smu->message_lock);
476 return res;
477 }
478
smu_cmn_send_smc_msg(struct smu_context * smu,enum smu_message_type msg,uint32_t * read_arg)479 int smu_cmn_send_smc_msg(struct smu_context *smu,
480 enum smu_message_type msg,
481 uint32_t *read_arg)
482 {
483 return smu_cmn_send_smc_msg_with_param(smu,
484 msg,
485 0,
486 read_arg);
487 }
488
smu_cmn_send_debug_smc_msg(struct smu_context * smu,uint32_t msg)489 int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
490 uint32_t msg)
491 {
492 return __smu_cmn_send_debug_msg(smu, msg, 0);
493 }
494
smu_cmn_send_debug_smc_msg_with_param(struct smu_context * smu,uint32_t msg,uint32_t param)495 int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,
496 uint32_t msg, uint32_t param)
497 {
498 return __smu_cmn_send_debug_msg(smu, msg, param);
499 }
500
smu_cmn_to_asic_specific_index(struct smu_context * smu,enum smu_cmn2asic_mapping_type type,uint32_t index)501 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
502 enum smu_cmn2asic_mapping_type type,
503 uint32_t index)
504 {
505 struct cmn2asic_msg_mapping msg_mapping;
506 struct cmn2asic_mapping mapping;
507
508 switch (type) {
509 case CMN2ASIC_MAPPING_MSG:
510 if (index >= SMU_MSG_MAX_COUNT ||
511 !smu->message_map)
512 return -EINVAL;
513
514 msg_mapping = smu->message_map[index];
515 if (!msg_mapping.valid_mapping)
516 return -EINVAL;
517
518 if (amdgpu_sriov_vf(smu->adev) &&
519 !(msg_mapping.flags & SMU_MSG_VF_FLAG))
520 return -EACCES;
521
522 return msg_mapping.map_to;
523
524 case CMN2ASIC_MAPPING_CLK:
525 if (index >= SMU_CLK_COUNT ||
526 !smu->clock_map)
527 return -EINVAL;
528
529 mapping = smu->clock_map[index];
530 if (!mapping.valid_mapping)
531 return -EINVAL;
532
533 return mapping.map_to;
534
535 case CMN2ASIC_MAPPING_FEATURE:
536 if (index >= SMU_FEATURE_COUNT ||
537 !smu->feature_map)
538 return -EINVAL;
539
540 mapping = smu->feature_map[index];
541 if (!mapping.valid_mapping)
542 return -EINVAL;
543
544 return mapping.map_to;
545
546 case CMN2ASIC_MAPPING_TABLE:
547 if (index >= SMU_TABLE_COUNT ||
548 !smu->table_map)
549 return -EINVAL;
550
551 mapping = smu->table_map[index];
552 if (!mapping.valid_mapping)
553 return -EINVAL;
554
555 return mapping.map_to;
556
557 case CMN2ASIC_MAPPING_PWR:
558 if (index >= SMU_POWER_SOURCE_COUNT ||
559 !smu->pwr_src_map)
560 return -EINVAL;
561
562 mapping = smu->pwr_src_map[index];
563 if (!mapping.valid_mapping)
564 return -EINVAL;
565
566 return mapping.map_to;
567
568 case CMN2ASIC_MAPPING_WORKLOAD:
569 if (index >= PP_SMC_POWER_PROFILE_COUNT ||
570 !smu->workload_map)
571 return -EINVAL;
572
573 mapping = smu->workload_map[index];
574 if (!mapping.valid_mapping)
575 return -ENOTSUPP;
576
577 return mapping.map_to;
578
579 default:
580 return -EINVAL;
581 }
582 }
583
smu_cmn_feature_is_supported(struct smu_context * smu,enum smu_feature_mask mask)584 int smu_cmn_feature_is_supported(struct smu_context *smu,
585 enum smu_feature_mask mask)
586 {
587 struct smu_feature *feature = &smu->smu_feature;
588 int feature_id;
589
590 feature_id = smu_cmn_to_asic_specific_index(smu,
591 CMN2ASIC_MAPPING_FEATURE,
592 mask);
593 if (feature_id < 0)
594 return 0;
595
596 WARN_ON(feature_id > feature->feature_num);
597
598 return test_bit(feature_id, feature->supported);
599 }
600
__smu_get_enabled_features(struct smu_context * smu,uint64_t * enabled_features)601 static int __smu_get_enabled_features(struct smu_context *smu,
602 uint64_t *enabled_features)
603 {
604 return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
605 }
606
smu_cmn_feature_is_enabled(struct smu_context * smu,enum smu_feature_mask mask)607 int smu_cmn_feature_is_enabled(struct smu_context *smu,
608 enum smu_feature_mask mask)
609 {
610 struct amdgpu_device *adev = smu->adev;
611 uint64_t enabled_features;
612 int feature_id;
613
614 if (__smu_get_enabled_features(smu, &enabled_features)) {
615 dev_err(adev->dev, "Failed to retrieve enabled ppfeatures!\n");
616 return 0;
617 }
618
619 /*
620 * For Renoir and Cyan Skillfish, they are assumed to have all features
621 * enabled. Also considering they have no feature_map available, the
622 * check here can avoid unwanted feature_map check below.
623 */
624 if (enabled_features == ULLONG_MAX)
625 return 1;
626
627 feature_id = smu_cmn_to_asic_specific_index(smu,
628 CMN2ASIC_MAPPING_FEATURE,
629 mask);
630 if (feature_id < 0)
631 return 0;
632
633 return test_bit(feature_id, (unsigned long *)&enabled_features);
634 }
635
smu_cmn_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)636 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
637 enum smu_clk_type clk_type)
638 {
639 enum smu_feature_mask feature_id = 0;
640
641 switch (clk_type) {
642 case SMU_MCLK:
643 case SMU_UCLK:
644 feature_id = SMU_FEATURE_DPM_UCLK_BIT;
645 break;
646 case SMU_GFXCLK:
647 case SMU_SCLK:
648 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
649 break;
650 case SMU_SOCCLK:
651 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
652 break;
653 case SMU_VCLK:
654 case SMU_VCLK1:
655 feature_id = SMU_FEATURE_DPM_VCLK_BIT;
656 break;
657 case SMU_DCLK:
658 case SMU_DCLK1:
659 feature_id = SMU_FEATURE_DPM_DCLK_BIT;
660 break;
661 case SMU_FCLK:
662 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
663 break;
664 default:
665 return true;
666 }
667
668 if (!smu_cmn_feature_is_enabled(smu, feature_id))
669 return false;
670
671 return true;
672 }
673
smu_cmn_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)674 int smu_cmn_get_enabled_mask(struct smu_context *smu,
675 uint64_t *feature_mask)
676 {
677 uint32_t *feature_mask_high;
678 uint32_t *feature_mask_low;
679 int ret = 0, index = 0;
680
681 if (!feature_mask)
682 return -EINVAL;
683
684 feature_mask_low = &((uint32_t *)feature_mask)[0];
685 feature_mask_high = &((uint32_t *)feature_mask)[1];
686
687 index = smu_cmn_to_asic_specific_index(smu,
688 CMN2ASIC_MAPPING_MSG,
689 SMU_MSG_GetEnabledSmuFeatures);
690 if (index > 0) {
691 ret = smu_cmn_send_smc_msg_with_param(smu,
692 SMU_MSG_GetEnabledSmuFeatures,
693 0,
694 feature_mask_low);
695 if (ret)
696 return ret;
697
698 ret = smu_cmn_send_smc_msg_with_param(smu,
699 SMU_MSG_GetEnabledSmuFeatures,
700 1,
701 feature_mask_high);
702 } else {
703 ret = smu_cmn_send_smc_msg(smu,
704 SMU_MSG_GetEnabledSmuFeaturesHigh,
705 feature_mask_high);
706 if (ret)
707 return ret;
708
709 ret = smu_cmn_send_smc_msg(smu,
710 SMU_MSG_GetEnabledSmuFeaturesLow,
711 feature_mask_low);
712 }
713
714 return ret;
715 }
716
smu_cmn_get_indep_throttler_status(const unsigned long dep_status,const uint8_t * throttler_map)717 uint64_t smu_cmn_get_indep_throttler_status(
718 const unsigned long dep_status,
719 const uint8_t *throttler_map)
720 {
721 uint64_t indep_status = 0;
722 uint8_t dep_bit = 0;
723
724 for_each_set_bit(dep_bit, &dep_status, 32)
725 indep_status |= 1ULL << throttler_map[dep_bit];
726
727 return indep_status;
728 }
729
smu_cmn_feature_update_enable_state(struct smu_context * smu,uint64_t feature_mask,bool enabled)730 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
731 uint64_t feature_mask,
732 bool enabled)
733 {
734 int ret = 0;
735
736 if (enabled) {
737 ret = smu_cmn_send_smc_msg_with_param(smu,
738 SMU_MSG_EnableSmuFeaturesLow,
739 lower_32_bits(feature_mask),
740 NULL);
741 if (ret)
742 return ret;
743 ret = smu_cmn_send_smc_msg_with_param(smu,
744 SMU_MSG_EnableSmuFeaturesHigh,
745 upper_32_bits(feature_mask),
746 NULL);
747 } else {
748 ret = smu_cmn_send_smc_msg_with_param(smu,
749 SMU_MSG_DisableSmuFeaturesLow,
750 lower_32_bits(feature_mask),
751 NULL);
752 if (ret)
753 return ret;
754 ret = smu_cmn_send_smc_msg_with_param(smu,
755 SMU_MSG_DisableSmuFeaturesHigh,
756 upper_32_bits(feature_mask),
757 NULL);
758 }
759
760 return ret;
761 }
762
smu_cmn_feature_set_enabled(struct smu_context * smu,enum smu_feature_mask mask,bool enable)763 int smu_cmn_feature_set_enabled(struct smu_context *smu,
764 enum smu_feature_mask mask,
765 bool enable)
766 {
767 int feature_id;
768
769 feature_id = smu_cmn_to_asic_specific_index(smu,
770 CMN2ASIC_MAPPING_FEATURE,
771 mask);
772 if (feature_id < 0)
773 return -EINVAL;
774
775 return smu_cmn_feature_update_enable_state(smu,
776 1ULL << feature_id,
777 enable);
778 }
779
780 #undef __SMU_DUMMY_MAP
781 #define __SMU_DUMMY_MAP(fea) #fea
782 static const char *__smu_feature_names[] = {
783 SMU_FEATURE_MASKS
784 };
785
smu_get_feature_name(struct smu_context * smu,enum smu_feature_mask feature)786 static const char *smu_get_feature_name(struct smu_context *smu,
787 enum smu_feature_mask feature)
788 {
789 if (feature >= SMU_FEATURE_COUNT)
790 return "unknown smu feature";
791 return __smu_feature_names[feature];
792 }
793
smu_cmn_get_pp_feature_mask(struct smu_context * smu,char * buf)794 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
795 char *buf)
796 {
797 int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)];
798 uint64_t feature_mask;
799 int i, feature_index;
800 uint32_t count = 0;
801 size_t size = 0;
802
803 if (__smu_get_enabled_features(smu, &feature_mask))
804 return 0;
805
806 size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
807 upper_32_bits(feature_mask), lower_32_bits(feature_mask));
808
809 memset(sort_feature, -1, sizeof(sort_feature));
810
811 for (i = 0; i < SMU_FEATURE_COUNT; i++) {
812 feature_index = smu_cmn_to_asic_specific_index(smu,
813 CMN2ASIC_MAPPING_FEATURE,
814 i);
815 if (feature_index < 0)
816 continue;
817
818 sort_feature[feature_index] = i;
819 }
820
821 size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n",
822 "No", "Feature", "Bit", "State");
823
824 for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) {
825 if (sort_feature[feature_index] < 0)
826 continue;
827
828 size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
829 count++,
830 smu_get_feature_name(smu, sort_feature[feature_index]),
831 feature_index,
832 !!test_bit(feature_index, (unsigned long *)&feature_mask) ?
833 "enabled" : "disabled");
834 }
835
836 return size;
837 }
838
smu_cmn_set_pp_feature_mask(struct smu_context * smu,uint64_t new_mask)839 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
840 uint64_t new_mask)
841 {
842 int ret = 0;
843 uint64_t feature_mask;
844 uint64_t feature_2_enabled = 0;
845 uint64_t feature_2_disabled = 0;
846
847 ret = __smu_get_enabled_features(smu, &feature_mask);
848 if (ret)
849 return ret;
850
851 feature_2_enabled = ~feature_mask & new_mask;
852 feature_2_disabled = feature_mask & ~new_mask;
853
854 if (feature_2_enabled) {
855 ret = smu_cmn_feature_update_enable_state(smu,
856 feature_2_enabled,
857 true);
858 if (ret)
859 return ret;
860 }
861 if (feature_2_disabled) {
862 ret = smu_cmn_feature_update_enable_state(smu,
863 feature_2_disabled,
864 false);
865 if (ret)
866 return ret;
867 }
868
869 return ret;
870 }
871
872 /**
873 * smu_cmn_disable_all_features_with_exception - disable all dpm features
874 * except this specified by
875 * @mask
876 *
877 * @smu: smu_context pointer
878 * @mask: the dpm feature which should not be disabled
879 * SMU_FEATURE_COUNT: no exception, all dpm features
880 * to disable
881 *
882 * Returns:
883 * 0 on success or a negative error code on failure.
884 */
smu_cmn_disable_all_features_with_exception(struct smu_context * smu,enum smu_feature_mask mask)885 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
886 enum smu_feature_mask mask)
887 {
888 uint64_t features_to_disable = U64_MAX;
889 int skipped_feature_id;
890
891 if (mask != SMU_FEATURE_COUNT) {
892 skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
893 CMN2ASIC_MAPPING_FEATURE,
894 mask);
895 if (skipped_feature_id < 0)
896 return -EINVAL;
897
898 features_to_disable &= ~(1ULL << skipped_feature_id);
899 }
900
901 return smu_cmn_feature_update_enable_state(smu,
902 features_to_disable,
903 0);
904 }
905
smu_cmn_get_smc_version(struct smu_context * smu,uint32_t * if_version,uint32_t * smu_version)906 int smu_cmn_get_smc_version(struct smu_context *smu,
907 uint32_t *if_version,
908 uint32_t *smu_version)
909 {
910 int ret = 0;
911
912 if (!if_version && !smu_version)
913 return -EINVAL;
914
915 if (smu->smc_fw_if_version && smu->smc_fw_version)
916 {
917 if (if_version)
918 *if_version = smu->smc_fw_if_version;
919
920 if (smu_version)
921 *smu_version = smu->smc_fw_version;
922
923 return 0;
924 }
925
926 if (if_version) {
927 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
928 if (ret)
929 return ret;
930
931 smu->smc_fw_if_version = *if_version;
932 }
933
934 if (smu_version) {
935 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
936 if (ret)
937 return ret;
938
939 smu->smc_fw_version = *smu_version;
940 }
941
942 return ret;
943 }
944
smu_cmn_update_table(struct smu_context * smu,enum smu_table_id table_index,int argument,void * table_data,bool drv2smu)945 int smu_cmn_update_table(struct smu_context *smu,
946 enum smu_table_id table_index,
947 int argument,
948 void *table_data,
949 bool drv2smu)
950 {
951 struct smu_table_context *smu_table = &smu->smu_table;
952 struct amdgpu_device *adev = smu->adev;
953 struct smu_table *table = &smu_table->driver_table;
954 int table_id = smu_cmn_to_asic_specific_index(smu,
955 CMN2ASIC_MAPPING_TABLE,
956 table_index);
957 uint32_t table_size;
958 int ret = 0;
959 if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
960 return -EINVAL;
961
962 table_size = smu_table->tables[table_index].size;
963
964 if (drv2smu) {
965 memcpy(table->cpu_addr, table_data, table_size);
966 /*
967 * Flush hdp cache: to guard the content seen by
968 * GPU is consitent with CPU.
969 */
970 amdgpu_asic_flush_hdp(adev, NULL);
971 }
972
973 ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ?
974 SMU_MSG_TransferTableDram2Smu :
975 SMU_MSG_TransferTableSmu2Dram,
976 table_id | ((argument & 0xFFFF) << 16),
977 NULL);
978 if (ret)
979 return ret;
980
981 if (!drv2smu) {
982 amdgpu_asic_invalidate_hdp(adev, NULL);
983 memcpy(table_data, table->cpu_addr, table_size);
984 }
985
986 return 0;
987 }
988
smu_cmn_write_watermarks_table(struct smu_context * smu)989 int smu_cmn_write_watermarks_table(struct smu_context *smu)
990 {
991 void *watermarks_table = smu->smu_table.watermarks_table;
992
993 if (!watermarks_table)
994 return -EINVAL;
995
996 return smu_cmn_update_table(smu,
997 SMU_TABLE_WATERMARKS,
998 0,
999 watermarks_table,
1000 true);
1001 }
1002
smu_cmn_write_pptable(struct smu_context * smu)1003 int smu_cmn_write_pptable(struct smu_context *smu)
1004 {
1005 void *pptable = smu->smu_table.driver_pptable;
1006
1007 return smu_cmn_update_table(smu,
1008 SMU_TABLE_PPTABLE,
1009 0,
1010 pptable,
1011 true);
1012 }
1013
smu_cmn_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)1014 int smu_cmn_get_metrics_table(struct smu_context *smu,
1015 void *metrics_table,
1016 bool bypass_cache)
1017 {
1018 struct smu_table_context *smu_table = &smu->smu_table;
1019 uint32_t table_size =
1020 smu_table->tables[SMU_TABLE_SMU_METRICS].size;
1021 int ret = 0;
1022
1023 if (bypass_cache ||
1024 !smu_table->metrics_time ||
1025 time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
1026 ret = smu_cmn_update_table(smu,
1027 SMU_TABLE_SMU_METRICS,
1028 0,
1029 smu_table->metrics_table,
1030 false);
1031 if (ret) {
1032 dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
1033 return ret;
1034 }
1035 smu_table->metrics_time = jiffies;
1036 }
1037
1038 if (metrics_table)
1039 memcpy(metrics_table, smu_table->metrics_table, table_size);
1040
1041 return 0;
1042 }
1043
smu_cmn_get_combo_pptable(struct smu_context * smu)1044 int smu_cmn_get_combo_pptable(struct smu_context *smu)
1045 {
1046 void *pptable = smu->smu_table.combo_pptable;
1047
1048 return smu_cmn_update_table(smu,
1049 SMU_TABLE_COMBO_PPTABLE,
1050 0,
1051 pptable,
1052 false);
1053 }
1054
smu_cmn_init_soft_gpu_metrics(void * table,uint8_t frev,uint8_t crev)1055 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
1056 {
1057 struct metrics_table_header *header = (struct metrics_table_header *)table;
1058 uint16_t structure_size;
1059
1060 #define METRICS_VERSION(a, b) ((a << 16) | b)
1061
1062 switch (METRICS_VERSION(frev, crev)) {
1063 case METRICS_VERSION(1, 0):
1064 structure_size = sizeof(struct gpu_metrics_v1_0);
1065 break;
1066 case METRICS_VERSION(1, 1):
1067 structure_size = sizeof(struct gpu_metrics_v1_1);
1068 break;
1069 case METRICS_VERSION(1, 2):
1070 structure_size = sizeof(struct gpu_metrics_v1_2);
1071 break;
1072 case METRICS_VERSION(1, 3):
1073 structure_size = sizeof(struct gpu_metrics_v1_3);
1074 break;
1075 case METRICS_VERSION(1, 4):
1076 structure_size = sizeof(struct gpu_metrics_v1_4);
1077 break;
1078 case METRICS_VERSION(1, 5):
1079 structure_size = sizeof(struct gpu_metrics_v1_5);
1080 break;
1081 case METRICS_VERSION(2, 0):
1082 structure_size = sizeof(struct gpu_metrics_v2_0);
1083 break;
1084 case METRICS_VERSION(2, 1):
1085 structure_size = sizeof(struct gpu_metrics_v2_1);
1086 break;
1087 case METRICS_VERSION(2, 2):
1088 structure_size = sizeof(struct gpu_metrics_v2_2);
1089 break;
1090 case METRICS_VERSION(2, 3):
1091 structure_size = sizeof(struct gpu_metrics_v2_3);
1092 break;
1093 case METRICS_VERSION(2, 4):
1094 structure_size = sizeof(struct gpu_metrics_v2_4);
1095 break;
1096 case METRICS_VERSION(3, 0):
1097 structure_size = sizeof(struct gpu_metrics_v3_0);
1098 break;
1099 default:
1100 return;
1101 }
1102
1103 #undef METRICS_VERSION
1104
1105 memset(header, 0xFF, structure_size);
1106
1107 header->format_revision = frev;
1108 header->content_revision = crev;
1109 header->structure_size = structure_size;
1110
1111 }
1112
smu_cmn_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)1113 int smu_cmn_set_mp1_state(struct smu_context *smu,
1114 enum pp_mp1_state mp1_state)
1115 {
1116 enum smu_message_type msg;
1117 int ret;
1118
1119 switch (mp1_state) {
1120 case PP_MP1_STATE_SHUTDOWN:
1121 msg = SMU_MSG_PrepareMp1ForShutdown;
1122 break;
1123 case PP_MP1_STATE_UNLOAD:
1124 msg = SMU_MSG_PrepareMp1ForUnload;
1125 break;
1126 case PP_MP1_STATE_RESET:
1127 msg = SMU_MSG_PrepareMp1ForReset;
1128 break;
1129 case PP_MP1_STATE_NONE:
1130 default:
1131 return 0;
1132 }
1133
1134 ret = smu_cmn_send_smc_msg(smu, msg, NULL);
1135 if (ret)
1136 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1137
1138 return ret;
1139 }
1140
smu_cmn_is_audio_func_enabled(struct amdgpu_device * adev)1141 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
1142 {
1143 struct pci_dev *p = NULL;
1144 bool snd_driver_loaded;
1145
1146 /*
1147 * If the ASIC comes with no audio function, we always assume
1148 * it is "enabled".
1149 */
1150 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1151 adev->pdev->bus->number, 1);
1152 if (!p)
1153 return true;
1154
1155 snd_driver_loaded = pci_is_enabled(p) ? true : false;
1156
1157 pci_dev_put(p);
1158
1159 return snd_driver_loaded;
1160 }
1161
smu_soc_policy_get_desc(struct smu_dpm_policy * policy,int level)1162 static char *smu_soc_policy_get_desc(struct smu_dpm_policy *policy, int level)
1163 {
1164 if (level < 0 || !(policy->level_mask & BIT(level)))
1165 return "Invalid";
1166
1167 switch (level) {
1168 case SOC_PSTATE_DEFAULT:
1169 return "soc_pstate_default";
1170 case SOC_PSTATE_0:
1171 return "soc_pstate_0";
1172 case SOC_PSTATE_1:
1173 return "soc_pstate_1";
1174 case SOC_PSTATE_2:
1175 return "soc_pstate_2";
1176 }
1177
1178 return "Invalid";
1179 }
1180
1181 static struct smu_dpm_policy_desc pstate_policy_desc = {
1182 .name = STR_SOC_PSTATE_POLICY,
1183 .get_desc = smu_soc_policy_get_desc,
1184 };
1185
smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy * policy)1186 void smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy *policy)
1187 {
1188 policy->desc = &pstate_policy_desc;
1189 }
1190
smu_xgmi_plpd_policy_get_desc(struct smu_dpm_policy * policy,int level)1191 static char *smu_xgmi_plpd_policy_get_desc(struct smu_dpm_policy *policy,
1192 int level)
1193 {
1194 if (level < 0 || !(policy->level_mask & BIT(level)))
1195 return "Invalid";
1196
1197 switch (level) {
1198 case XGMI_PLPD_DISALLOW:
1199 return "plpd_disallow";
1200 case XGMI_PLPD_DEFAULT:
1201 return "plpd_default";
1202 case XGMI_PLPD_OPTIMIZED:
1203 return "plpd_optimized";
1204 }
1205
1206 return "Invalid";
1207 }
1208
1209 static struct smu_dpm_policy_desc xgmi_plpd_policy_desc = {
1210 .name = STR_XGMI_PLPD_POLICY,
1211 .get_desc = smu_xgmi_plpd_policy_get_desc,
1212 };
1213
smu_cmn_generic_plpd_policy_desc(struct smu_dpm_policy * policy)1214 void smu_cmn_generic_plpd_policy_desc(struct smu_dpm_policy *policy)
1215 {
1216 policy->desc = &xgmi_plpd_policy_desc;
1217 }
1218