1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008 Benno Rice. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 /*
29 * Driver for SMSC LAN91C111, may work for older variants.
30 */
31
32 #ifdef HAVE_KERNEL_OPTION_HEADERS
33 #include "opt_device_polling.h"
34 #endif
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/errno.h>
39 #include <sys/kernel.h>
40 #include <sys/sockio.h>
41 #include <sys/malloc.h>
42 #include <sys/mbuf.h>
43 #include <sys/queue.h>
44 #include <sys/socket.h>
45 #include <sys/syslog.h>
46 #include <sys/taskqueue.h>
47
48 #include <sys/module.h>
49 #include <sys/bus.h>
50
51 #include <machine/bus.h>
52 #include <machine/resource.h>
53 #include <sys/rman.h>
54
55 #include <net/ethernet.h>
56 #include <net/if.h>
57 #include <net/if_var.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_types.h>
61 #include <net/if_mib.h>
62 #include <net/if_media.h>
63
64 #ifdef INET
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/in_var.h>
68 #include <netinet/ip.h>
69 #endif
70
71 #include <net/bpf.h>
72 #include <net/bpfdesc.h>
73
74 #include <dev/smc/if_smcreg.h>
75 #include <dev/smc/if_smcvar.h>
76
77 #include <dev/mii/mii.h>
78 #include <dev/mii/mii_bitbang.h>
79 #include <dev/mii/miivar.h>
80
81 #include "miibus_if.h"
82
83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx)
84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx)
85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED)
86
87 #define SMC_INTR_PRIORITY 0
88 #define SMC_RX_PRIORITY 5
89 #define SMC_TX_PRIORITY 10
90
91 static const char *smc_chip_ids[16] = {
92 NULL, NULL, NULL,
93 /* 3 */ "SMSC LAN91C90 or LAN91C92",
94 /* 4 */ "SMSC LAN91C94",
95 /* 5 */ "SMSC LAN91C95",
96 /* 6 */ "SMSC LAN91C96",
97 /* 7 */ "SMSC LAN91C100",
98 /* 8 */ "SMSC LAN91C100FD",
99 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
100 NULL, NULL, NULL,
101 NULL, NULL, NULL
102 };
103
104 static void smc_init(void *);
105 static void smc_start(if_t);
106 static void smc_stop(struct smc_softc *);
107 static int smc_ioctl(if_t, u_long, caddr_t);
108
109 static void smc_init_locked(struct smc_softc *);
110 static void smc_start_locked(if_t);
111 static void smc_reset(struct smc_softc *);
112 static int smc_mii_ifmedia_upd(if_t);
113 static void smc_mii_ifmedia_sts(if_t, struct ifmediareq *);
114 static void smc_mii_tick(void *);
115 static void smc_mii_mediachg(struct smc_softc *);
116 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
117
118 static void smc_task_intr(void *, int);
119 static void smc_task_rx(void *, int);
120 static void smc_task_tx(void *, int);
121
122 static driver_filter_t smc_intr;
123 static callout_func_t smc_watchdog;
124 #ifdef DEVICE_POLLING
125 static poll_handler_t smc_poll;
126 #endif
127
128 /*
129 * MII bit-bang glue
130 */
131 static uint32_t smc_mii_bitbang_read(device_t);
132 static void smc_mii_bitbang_write(device_t, uint32_t);
133
134 static const struct mii_bitbang_ops smc_mii_bitbang_ops = {
135 smc_mii_bitbang_read,
136 smc_mii_bitbang_write,
137 {
138 MGMT_MDO, /* MII_BIT_MDO */
139 MGMT_MDI, /* MII_BIT_MDI */
140 MGMT_MCLK, /* MII_BIT_MDC */
141 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */
142 0, /* MII_BIT_DIR_PHY_HOST */
143 }
144 };
145
146 static __inline void
smc_select_bank(struct smc_softc * sc,uint16_t bank)147 smc_select_bank(struct smc_softc *sc, uint16_t bank)
148 {
149
150 bus_barrier(sc->smc_reg, BSR, 2,
151 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
152 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
153 bus_barrier(sc->smc_reg, BSR, 2,
154 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
155 }
156
157 /* Never call this when not in bank 2. */
158 static __inline void
smc_mmu_wait(struct smc_softc * sc)159 smc_mmu_wait(struct smc_softc *sc)
160 {
161
162 KASSERT((bus_read_2(sc->smc_reg, BSR) &
163 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
164 device_get_nameunit(sc->smc_dev)));
165 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
166 ;
167 }
168
169 static __inline uint8_t
smc_read_1(struct smc_softc * sc,bus_size_t offset)170 smc_read_1(struct smc_softc *sc, bus_size_t offset)
171 {
172
173 return (bus_read_1(sc->smc_reg, offset));
174 }
175
176 static __inline void
smc_write_1(struct smc_softc * sc,bus_size_t offset,uint8_t val)177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
178 {
179
180 bus_write_1(sc->smc_reg, offset, val);
181 }
182
183 static __inline uint16_t
smc_read_2(struct smc_softc * sc,bus_size_t offset)184 smc_read_2(struct smc_softc *sc, bus_size_t offset)
185 {
186
187 return (bus_read_2(sc->smc_reg, offset));
188 }
189
190 static __inline void
smc_write_2(struct smc_softc * sc,bus_size_t offset,uint16_t val)191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
192 {
193
194 bus_write_2(sc->smc_reg, offset, val);
195 }
196
197 static __inline void
smc_read_multi_2(struct smc_softc * sc,bus_size_t offset,uint16_t * datap,bus_size_t count)198 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
199 bus_size_t count)
200 {
201
202 bus_read_multi_2(sc->smc_reg, offset, datap, count);
203 }
204
205 static __inline void
smc_write_multi_2(struct smc_softc * sc,bus_size_t offset,uint16_t * datap,bus_size_t count)206 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
207 bus_size_t count)
208 {
209
210 bus_write_multi_2(sc->smc_reg, offset, datap, count);
211 }
212
213 static __inline void
smc_barrier(struct smc_softc * sc,bus_size_t offset,bus_size_t length,int flags)214 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length,
215 int flags)
216 {
217
218 bus_barrier(sc->smc_reg, offset, length, flags);
219 }
220
221 int
smc_probe(device_t dev)222 smc_probe(device_t dev)
223 {
224 int rid, type, error;
225 uint16_t val;
226 struct smc_softc *sc;
227 struct resource *reg;
228
229 sc = device_get_softc(dev);
230 rid = 0;
231 type = SYS_RES_IOPORT;
232 error = 0;
233
234 if (sc->smc_usemem)
235 type = SYS_RES_MEMORY;
236
237 reg = bus_alloc_resource_anywhere(dev, type, &rid, 16, RF_ACTIVE);
238 if (reg == NULL) {
239 if (bootverbose)
240 device_printf(dev,
241 "could not allocate I/O resource for probe\n");
242 return (ENXIO);
243 }
244
245 /* Check for the identification value in the BSR. */
246 val = bus_read_2(reg, BSR);
247 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
248 if (bootverbose)
249 device_printf(dev, "identification value not in BSR\n");
250 error = ENXIO;
251 goto done;
252 }
253
254 /*
255 * Try switching banks and make sure we still get the identification
256 * value.
257 */
258 bus_write_2(reg, BSR, 0);
259 val = bus_read_2(reg, BSR);
260 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
261 if (bootverbose)
262 device_printf(dev,
263 "identification value not in BSR after write\n");
264 error = ENXIO;
265 goto done;
266 }
267
268 #if 0
269 /* Check the BAR. */
270 bus_write_2(reg, BSR, 1);
271 val = bus_read_2(reg, BAR);
272 val = BAR_ADDRESS(val);
273 if (rman_get_start(reg) != val) {
274 if (bootverbose)
275 device_printf(dev, "BAR address %x does not match "
276 "I/O resource address %lx\n", val,
277 rman_get_start(reg));
278 error = ENXIO;
279 goto done;
280 }
281 #endif
282
283 /* Compare REV against known chip revisions. */
284 bus_write_2(reg, BSR, 3);
285 val = bus_read_2(reg, REV);
286 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
287 if (smc_chip_ids[val] == NULL) {
288 if (bootverbose)
289 device_printf(dev, "Unknown chip revision: %d\n", val);
290 error = ENXIO;
291 goto done;
292 }
293
294 device_set_desc(dev, smc_chip_ids[val]);
295
296 done:
297 bus_release_resource(dev, type, rid, reg);
298 return (error);
299 }
300
301 int
smc_attach(device_t dev)302 smc_attach(device_t dev)
303 {
304 int type, error;
305 uint16_t val;
306 u_char eaddr[ETHER_ADDR_LEN];
307 struct smc_softc *sc;
308 if_t ifp;
309
310 sc = device_get_softc(dev);
311 error = 0;
312
313 sc->smc_dev = dev;
314
315 ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
316
317 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
318
319 /* Set up watchdog callout. */
320 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
321
322 type = SYS_RES_IOPORT;
323 if (sc->smc_usemem)
324 type = SYS_RES_MEMORY;
325
326 sc->smc_reg_rid = 0;
327 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid,
328 16, RF_ACTIVE);
329 if (sc->smc_reg == NULL) {
330 error = ENXIO;
331 goto done;
332 }
333
334 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ,
335 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE);
336 if (sc->smc_irq == NULL) {
337 error = ENXIO;
338 goto done;
339 }
340
341 SMC_LOCK(sc);
342 smc_reset(sc);
343 SMC_UNLOCK(sc);
344
345 smc_select_bank(sc, 3);
346 val = smc_read_2(sc, REV);
347 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
348 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
349 if (bootverbose)
350 device_printf(dev, "revision %x\n", sc->smc_rev);
351
352 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
353 CALLOUT_RETURNUNLOCKED);
354 if (sc->smc_chip >= REV_CHIP_91110FD) {
355 (void)mii_attach(dev, &sc->smc_miibus, ifp,
356 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK,
357 MII_PHY_ANY, MII_OFFSET_ANY, 0);
358 if (sc->smc_miibus != NULL) {
359 sc->smc_mii_tick = smc_mii_tick;
360 sc->smc_mii_mediachg = smc_mii_mediachg;
361 sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
362 }
363 }
364
365 smc_select_bank(sc, 1);
366 eaddr[0] = smc_read_1(sc, IAR0);
367 eaddr[1] = smc_read_1(sc, IAR1);
368 eaddr[2] = smc_read_1(sc, IAR2);
369 eaddr[3] = smc_read_1(sc, IAR3);
370 eaddr[4] = smc_read_1(sc, IAR4);
371 eaddr[5] = smc_read_1(sc, IAR5);
372
373 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
374 if_setsoftc(ifp, sc);
375 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
376 if_setinitfn(ifp, smc_init);
377 if_setioctlfn(ifp, smc_ioctl);
378 if_setstartfn(ifp, smc_start);
379 if_setsendqlen(ifp, ifqmaxlen);
380 if_setsendqready(ifp);
381
382 if_setcapabilities(ifp, if_getcapenable(ifp) );
383
384 #ifdef DEVICE_POLLING
385 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
386 #endif
387
388 ether_ifattach(ifp, eaddr);
389
390 /* Set up taskqueue */
391 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
392 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
393 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
394 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
395 taskqueue_thread_enqueue, &sc->smc_tq);
396 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
397 device_get_nameunit(sc->smc_dev));
398
399 /* Mask all interrupts. */
400 sc->smc_mask = 0;
401 smc_write_1(sc, MSK, 0);
402
403 /* Wire up interrupt */
404 error = bus_setup_intr(dev, sc->smc_irq,
405 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
406 if (error != 0)
407 goto done;
408
409 done:
410 if (error != 0)
411 smc_detach(dev);
412 return (error);
413 }
414
415 int
smc_detach(device_t dev)416 smc_detach(device_t dev)
417 {
418 int type;
419 struct smc_softc *sc;
420
421 sc = device_get_softc(dev);
422 SMC_LOCK(sc);
423 smc_stop(sc);
424 SMC_UNLOCK(sc);
425
426 if (sc->smc_ifp != NULL) {
427 ether_ifdetach(sc->smc_ifp);
428 }
429
430 callout_drain(&sc->smc_watchdog);
431 callout_drain(&sc->smc_mii_tick_ch);
432
433 #ifdef DEVICE_POLLING
434 if (sc->smc_if_getcapenable(ifp) & IFCAP_POLLING)
435 ether_poll_deregister(sc->smc_ifp);
436 #endif
437
438 if (sc->smc_ih != NULL)
439 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
440
441 if (sc->smc_tq != NULL) {
442 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
443 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
444 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
445 taskqueue_free(sc->smc_tq);
446 sc->smc_tq = NULL;
447 }
448
449 if (sc->smc_ifp != NULL) {
450 if_free(sc->smc_ifp);
451 }
452
453 if (sc->smc_miibus != NULL) {
454 device_delete_child(sc->smc_dev, sc->smc_miibus);
455 bus_generic_detach(sc->smc_dev);
456 }
457
458 if (sc->smc_reg != NULL) {
459 type = SYS_RES_IOPORT;
460 if (sc->smc_usemem)
461 type = SYS_RES_MEMORY;
462
463 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
464 sc->smc_reg);
465 }
466
467 if (sc->smc_irq != NULL)
468 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
469 sc->smc_irq);
470
471 if (mtx_initialized(&sc->smc_mtx))
472 mtx_destroy(&sc->smc_mtx);
473
474 return (0);
475 }
476
477 static device_method_t smc_methods[] = {
478 /* Device interface */
479 DEVMETHOD(device_attach, smc_attach),
480 DEVMETHOD(device_detach, smc_detach),
481
482 /* MII interface */
483 DEVMETHOD(miibus_readreg, smc_miibus_readreg),
484 DEVMETHOD(miibus_writereg, smc_miibus_writereg),
485 DEVMETHOD(miibus_statchg, smc_miibus_statchg),
486 { 0, 0 }
487 };
488
489 driver_t smc_driver = {
490 "smc",
491 smc_methods,
492 sizeof(struct smc_softc),
493 };
494
495 DRIVER_MODULE(miibus, smc, miibus_driver, 0, 0);
496
497 static void
smc_start(if_t ifp)498 smc_start(if_t ifp)
499 {
500 struct smc_softc *sc;
501
502 sc = if_getsoftc(ifp);
503 SMC_LOCK(sc);
504 smc_start_locked(ifp);
505 SMC_UNLOCK(sc);
506 }
507
508 static void
smc_start_locked(if_t ifp)509 smc_start_locked(if_t ifp)
510 {
511 struct smc_softc *sc;
512 struct mbuf *m;
513 u_int len, npages, spin_count;
514
515 sc = if_getsoftc(ifp);
516 SMC_ASSERT_LOCKED(sc);
517
518 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
519 return;
520 if (if_sendq_empty(ifp))
521 return;
522
523 /*
524 * Grab the next packet. If it's too big, drop it.
525 */
526 m = if_dequeue(ifp);
527 len = m_length(m, NULL);
528 len += (len & 1);
529 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
530 if_printf(ifp, "large packet discarded\n");
531 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
532 m_freem(m);
533 return; /* XXX readcheck? */
534 }
535
536 /*
537 * Flag that we're busy.
538 */
539 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
540 sc->smc_pending = m;
541
542 /*
543 * Work out how many 256 byte "pages" we need. We have to include the
544 * control data for the packet in this calculation.
545 */
546 npages = (len + PKT_CTRL_DATA_LEN) >> 8;
547 if (npages == 0)
548 npages = 1;
549
550 /*
551 * Request memory.
552 */
553 smc_select_bank(sc, 2);
554 smc_mmu_wait(sc);
555 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
556
557 /*
558 * Spin briefly to see if the allocation succeeds.
559 */
560 spin_count = TX_ALLOC_WAIT_TIME;
561 do {
562 if (smc_read_1(sc, IST) & ALLOC_INT) {
563 smc_write_1(sc, ACK, ALLOC_INT);
564 break;
565 }
566 } while (--spin_count);
567
568 /*
569 * If the allocation is taking too long, unmask the alloc interrupt
570 * and wait.
571 */
572 if (spin_count == 0) {
573 sc->smc_mask |= ALLOC_INT;
574 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0)
575 smc_write_1(sc, MSK, sc->smc_mask);
576 return;
577 }
578
579 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
580 }
581
582 static void
smc_task_tx(void * context,int pending)583 smc_task_tx(void *context, int pending)
584 {
585 if_t ifp;
586 struct smc_softc *sc;
587 struct mbuf *m, *m0;
588 u_int packet, len;
589 int last_len;
590 uint8_t *data;
591
592 (void)pending;
593 ifp = (if_t)context;
594 sc = if_getsoftc(ifp);
595
596 SMC_LOCK(sc);
597
598 if (sc->smc_pending == NULL) {
599 SMC_UNLOCK(sc);
600 goto next_packet;
601 }
602
603 m = m0 = sc->smc_pending;
604 sc->smc_pending = NULL;
605 smc_select_bank(sc, 2);
606
607 /*
608 * Check the allocation result.
609 */
610 packet = smc_read_1(sc, ARR);
611
612 /*
613 * If the allocation failed, requeue the packet and retry.
614 */
615 if (packet & ARR_FAILED) {
616 if_sendq_prepend(ifp, m);
617 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
618 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
619 smc_start_locked(ifp);
620 SMC_UNLOCK(sc);
621 return;
622 }
623
624 /*
625 * Tell the device to write to our packet number.
626 */
627 smc_write_1(sc, PNR, packet);
628 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
629
630 /*
631 * Tell the device how long the packet is (including control data).
632 */
633 len = m_length(m, 0);
634 len += PKT_CTRL_DATA_LEN;
635 smc_write_2(sc, DATA0, 0);
636 smc_write_2(sc, DATA0, len);
637
638 /*
639 * Push the data out to the device.
640 */
641 data = NULL;
642 last_len = 0;
643 for (; m != NULL; m = m->m_next) {
644 data = mtod(m, uint8_t *);
645 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
646 last_len = m->m_len;
647 }
648
649 /*
650 * Push out the control byte and and the odd byte if needed.
651 */
652 if ((len & 1) != 0 && data != NULL)
653 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]);
654 else
655 smc_write_2(sc, DATA0, 0);
656
657 /*
658 * Unmask the TX empty interrupt.
659 */
660 sc->smc_mask |= TX_EMPTY_INT;
661 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0)
662 smc_write_1(sc, MSK, sc->smc_mask);
663
664 /*
665 * Enqueue the packet.
666 */
667 smc_mmu_wait(sc);
668 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
669 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
670
671 /*
672 * Finish up.
673 */
674 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
675 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
676 SMC_UNLOCK(sc);
677 BPF_MTAP(ifp, m0);
678 m_freem(m0);
679
680 next_packet:
681 /*
682 * See if there's anything else to do.
683 */
684 smc_start(ifp);
685 }
686
687 static void
smc_task_rx(void * context,int pending)688 smc_task_rx(void *context, int pending)
689 {
690 u_int packet, status, len;
691 uint8_t *data;
692 if_t ifp;
693 struct smc_softc *sc;
694 struct mbuf *m, *mhead, *mtail;
695
696 (void)pending;
697 ifp = (if_t)context;
698 sc = if_getsoftc(ifp);
699 mhead = mtail = NULL;
700
701 SMC_LOCK(sc);
702
703 packet = smc_read_1(sc, FIFO_RX);
704 while ((packet & FIFO_EMPTY) == 0) {
705 /*
706 * Grab an mbuf and attach a cluster.
707 */
708 MGETHDR(m, M_NOWAIT, MT_DATA);
709 if (m == NULL) {
710 break;
711 }
712 if (!(MCLGET(m, M_NOWAIT))) {
713 m_freem(m);
714 break;
715 }
716
717 /*
718 * Point to the start of the packet.
719 */
720 smc_select_bank(sc, 2);
721 smc_write_1(sc, PNR, packet);
722 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
723
724 /*
725 * Grab status and packet length.
726 */
727 status = smc_read_2(sc, DATA0);
728 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
729 len -= 6;
730 if (status & RX_ODDFRM)
731 len += 1;
732
733 /*
734 * Check for errors.
735 */
736 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
737 smc_mmu_wait(sc);
738 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
739 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
740 m_freem(m);
741 break;
742 }
743
744 /*
745 * Set the mbuf up the way we want it.
746 */
747 m->m_pkthdr.rcvif = ifp;
748 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
749 m_adj(m, ETHER_ALIGN);
750
751 /*
752 * Pull the packet out of the device. Make sure we're in the
753 * right bank first as things may have changed while we were
754 * allocating our mbuf.
755 */
756 smc_select_bank(sc, 2);
757 smc_write_1(sc, PNR, packet);
758 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
759 data = mtod(m, uint8_t *);
760 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
761 if (len & 1) {
762 data += len & ~1;
763 *data = smc_read_1(sc, DATA0);
764 }
765
766 /*
767 * Tell the device we're done.
768 */
769 smc_mmu_wait(sc);
770 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
771 if (m == NULL) {
772 break;
773 }
774
775 if (mhead == NULL) {
776 mhead = mtail = m;
777 m->m_next = NULL;
778 } else {
779 mtail->m_next = m;
780 mtail = m;
781 }
782 packet = smc_read_1(sc, FIFO_RX);
783 }
784
785 sc->smc_mask |= RCV_INT;
786 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0)
787 smc_write_1(sc, MSK, sc->smc_mask);
788
789 SMC_UNLOCK(sc);
790
791 while (mhead != NULL) {
792 m = mhead;
793 mhead = mhead->m_next;
794 m->m_next = NULL;
795 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
796 if_input(ifp, m);
797 }
798 }
799
800 #ifdef DEVICE_POLLING
801 static int
smc_poll(if_t ifp,enum poll_cmd cmd,int count)802 smc_poll(if_t ifp, enum poll_cmd cmd, int count)
803 {
804 struct smc_softc *sc;
805
806 sc = if_getsoftc(ifp);
807
808 SMC_LOCK(sc);
809 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
810 SMC_UNLOCK(sc);
811 return (0);
812 }
813 SMC_UNLOCK(sc);
814
815 if (cmd == POLL_AND_CHECK_STATUS)
816 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
817 return (0);
818 }
819 #endif
820
821 static int
smc_intr(void * context)822 smc_intr(void *context)
823 {
824 struct smc_softc *sc;
825 uint32_t curbank;
826
827 sc = (struct smc_softc *)context;
828
829 /*
830 * Save current bank and restore later in this function
831 */
832 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK);
833
834 /*
835 * Block interrupts in order to let smc_task_intr to kick in
836 */
837 smc_select_bank(sc, 2);
838 smc_write_1(sc, MSK, 0);
839
840 /* Restore bank */
841 smc_select_bank(sc, curbank);
842
843 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
844 return (FILTER_HANDLED);
845 }
846
847 static void
smc_task_intr(void * context,int pending)848 smc_task_intr(void *context, int pending)
849 {
850 struct smc_softc *sc;
851 if_t ifp;
852 u_int status, packet, counter, tcr;
853
854 (void)pending;
855 ifp = (if_t)context;
856 sc = if_getsoftc(ifp);
857
858 SMC_LOCK(sc);
859
860 smc_select_bank(sc, 2);
861
862 /*
863 * Find out what interrupts are flagged.
864 */
865 status = smc_read_1(sc, IST) & sc->smc_mask;
866
867 /*
868 * Transmit error
869 */
870 if (status & TX_INT) {
871 /*
872 * Kill off the packet if there is one and re-enable transmit.
873 */
874 packet = smc_read_1(sc, FIFO_TX);
875 if ((packet & FIFO_EMPTY) == 0) {
876 callout_stop(&sc->smc_watchdog);
877 smc_select_bank(sc, 2);
878 smc_write_1(sc, PNR, packet);
879 smc_write_2(sc, PTR, 0 | PTR_READ |
880 PTR_AUTO_INCR);
881 smc_select_bank(sc, 0);
882 tcr = smc_read_2(sc, EPHSR);
883 #if 0
884 if ((tcr & EPHSR_TX_SUC) == 0)
885 device_printf(sc->smc_dev,
886 "bad packet\n");
887 #endif
888 smc_select_bank(sc, 2);
889 smc_mmu_wait(sc);
890 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
891
892 smc_select_bank(sc, 0);
893 tcr = smc_read_2(sc, TCR);
894 tcr |= TCR_TXENA | TCR_PAD_EN;
895 smc_write_2(sc, TCR, tcr);
896 smc_select_bank(sc, 2);
897 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
898 }
899
900 /*
901 * Ack the interrupt.
902 */
903 smc_write_1(sc, ACK, TX_INT);
904 }
905
906 /*
907 * Receive
908 */
909 if (status & RCV_INT) {
910 smc_write_1(sc, ACK, RCV_INT);
911 sc->smc_mask &= ~RCV_INT;
912 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx);
913 }
914
915 /*
916 * Allocation
917 */
918 if (status & ALLOC_INT) {
919 smc_write_1(sc, ACK, ALLOC_INT);
920 sc->smc_mask &= ~ALLOC_INT;
921 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
922 }
923
924 /*
925 * Receive overrun
926 */
927 if (status & RX_OVRN_INT) {
928 smc_write_1(sc, ACK, RX_OVRN_INT);
929 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
930 }
931
932 /*
933 * Transmit empty
934 */
935 if (status & TX_EMPTY_INT) {
936 smc_write_1(sc, ACK, TX_EMPTY_INT);
937 sc->smc_mask &= ~TX_EMPTY_INT;
938 callout_stop(&sc->smc_watchdog);
939
940 /*
941 * Update collision stats.
942 */
943 smc_select_bank(sc, 0);
944 counter = smc_read_2(sc, ECR);
945 smc_select_bank(sc, 2);
946 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
947 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) +
948 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT));
949
950 /*
951 * See if there are any packets to transmit.
952 */
953 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
954 }
955
956 /*
957 * Update the interrupt mask.
958 */
959 smc_select_bank(sc, 2);
960 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0)
961 smc_write_1(sc, MSK, sc->smc_mask);
962
963 SMC_UNLOCK(sc);
964 }
965
966 static uint32_t
smc_mii_bitbang_read(device_t dev)967 smc_mii_bitbang_read(device_t dev)
968 {
969 struct smc_softc *sc;
970 uint32_t val;
971
972 sc = device_get_softc(dev);
973
974 SMC_ASSERT_LOCKED(sc);
975 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
976 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)",
977 device_get_nameunit(sc->smc_dev),
978 smc_read_2(sc, BSR) & BSR_BANK_MASK));
979
980 val = smc_read_2(sc, MGMT);
981 smc_barrier(sc, MGMT, 2,
982 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
983
984 return (val);
985 }
986
987 static void
smc_mii_bitbang_write(device_t dev,uint32_t val)988 smc_mii_bitbang_write(device_t dev, uint32_t val)
989 {
990 struct smc_softc *sc;
991
992 sc = device_get_softc(dev);
993
994 SMC_ASSERT_LOCKED(sc);
995 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
996 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)",
997 device_get_nameunit(sc->smc_dev),
998 smc_read_2(sc, BSR) & BSR_BANK_MASK));
999
1000 smc_write_2(sc, MGMT, val);
1001 smc_barrier(sc, MGMT, 2,
1002 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
1003 }
1004
1005 int
smc_miibus_readreg(device_t dev,int phy,int reg)1006 smc_miibus_readreg(device_t dev, int phy, int reg)
1007 {
1008 struct smc_softc *sc;
1009 int val;
1010
1011 sc = device_get_softc(dev);
1012
1013 SMC_LOCK(sc);
1014
1015 smc_select_bank(sc, 3);
1016
1017 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
1018
1019 SMC_UNLOCK(sc);
1020 return (val);
1021 }
1022
1023 int
smc_miibus_writereg(device_t dev,int phy,int reg,int data)1024 smc_miibus_writereg(device_t dev, int phy, int reg, int data)
1025 {
1026 struct smc_softc *sc;
1027
1028 sc = device_get_softc(dev);
1029
1030 SMC_LOCK(sc);
1031
1032 smc_select_bank(sc, 3);
1033
1034 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);
1035
1036 SMC_UNLOCK(sc);
1037 return (0);
1038 }
1039
1040 void
smc_miibus_statchg(device_t dev)1041 smc_miibus_statchg(device_t dev)
1042 {
1043 struct smc_softc *sc;
1044 struct mii_data *mii;
1045 uint16_t tcr;
1046
1047 sc = device_get_softc(dev);
1048 mii = device_get_softc(sc->smc_miibus);
1049
1050 SMC_LOCK(sc);
1051
1052 smc_select_bank(sc, 0);
1053 tcr = smc_read_2(sc, TCR);
1054
1055 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1056 tcr |= TCR_SWFDUP;
1057 else
1058 tcr &= ~TCR_SWFDUP;
1059
1060 smc_write_2(sc, TCR, tcr);
1061
1062 SMC_UNLOCK(sc);
1063 }
1064
1065 static int
smc_mii_ifmedia_upd(if_t ifp)1066 smc_mii_ifmedia_upd(if_t ifp)
1067 {
1068 struct smc_softc *sc;
1069 struct mii_data *mii;
1070
1071 sc = if_getsoftc(ifp);
1072 if (sc->smc_miibus == NULL)
1073 return (ENXIO);
1074
1075 mii = device_get_softc(sc->smc_miibus);
1076 return (mii_mediachg(mii));
1077 }
1078
1079 static void
smc_mii_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1080 smc_mii_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1081 {
1082 struct smc_softc *sc;
1083 struct mii_data *mii;
1084
1085 sc = if_getsoftc(ifp);
1086 if (sc->smc_miibus == NULL)
1087 return;
1088
1089 mii = device_get_softc(sc->smc_miibus);
1090 mii_pollstat(mii);
1091 ifmr->ifm_active = mii->mii_media_active;
1092 ifmr->ifm_status = mii->mii_media_status;
1093 }
1094
1095 static void
smc_mii_tick(void * context)1096 smc_mii_tick(void *context)
1097 {
1098 struct smc_softc *sc;
1099
1100 sc = (struct smc_softc *)context;
1101
1102 if (sc->smc_miibus == NULL)
1103 return;
1104
1105 SMC_UNLOCK(sc);
1106
1107 mii_tick(device_get_softc(sc->smc_miibus));
1108 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1109 }
1110
1111 static void
smc_mii_mediachg(struct smc_softc * sc)1112 smc_mii_mediachg(struct smc_softc *sc)
1113 {
1114
1115 if (sc->smc_miibus == NULL)
1116 return;
1117 mii_mediachg(device_get_softc(sc->smc_miibus));
1118 }
1119
1120 static int
smc_mii_mediaioctl(struct smc_softc * sc,struct ifreq * ifr,u_long command)1121 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1122 {
1123 struct mii_data *mii;
1124
1125 if (sc->smc_miibus == NULL)
1126 return (EINVAL);
1127
1128 mii = device_get_softc(sc->smc_miibus);
1129 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1130 }
1131
1132 static void
smc_reset(struct smc_softc * sc)1133 smc_reset(struct smc_softc *sc)
1134 {
1135 u_int ctr;
1136
1137 SMC_ASSERT_LOCKED(sc);
1138
1139 smc_select_bank(sc, 2);
1140
1141 /*
1142 * Mask all interrupts.
1143 */
1144 smc_write_1(sc, MSK, 0);
1145
1146 /*
1147 * Tell the device to reset.
1148 */
1149 smc_select_bank(sc, 0);
1150 smc_write_2(sc, RCR, RCR_SOFT_RST);
1151
1152 /*
1153 * Set up the configuration register.
1154 */
1155 smc_select_bank(sc, 1);
1156 smc_write_2(sc, CR, CR_EPH_POWER_EN);
1157 DELAY(1);
1158
1159 /*
1160 * Turn off transmit and receive.
1161 */
1162 smc_select_bank(sc, 0);
1163 smc_write_2(sc, TCR, 0);
1164 smc_write_2(sc, RCR, 0);
1165
1166 /*
1167 * Set up the control register.
1168 */
1169 smc_select_bank(sc, 1);
1170 ctr = smc_read_2(sc, CTRL);
1171 ctr |= CTRL_LE_ENABLE | CTRL_AUTO_RELEASE;
1172 smc_write_2(sc, CTRL, ctr);
1173
1174 /*
1175 * Reset the MMU.
1176 */
1177 smc_select_bank(sc, 2);
1178 smc_mmu_wait(sc);
1179 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1180 }
1181
1182 static void
smc_enable(struct smc_softc * sc)1183 smc_enable(struct smc_softc *sc)
1184 {
1185 if_t ifp;
1186
1187 SMC_ASSERT_LOCKED(sc);
1188 ifp = sc->smc_ifp;
1189
1190 /*
1191 * Set up the receive/PHY control register.
1192 */
1193 smc_select_bank(sc, 0);
1194 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1195 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1196
1197 /*
1198 * Set up the transmit and receive control registers.
1199 */
1200 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1201 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1202
1203 /*
1204 * Set up the interrupt mask.
1205 */
1206 smc_select_bank(sc, 2);
1207 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1208 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0)
1209 smc_write_1(sc, MSK, sc->smc_mask);
1210 }
1211
1212 static void
smc_stop(struct smc_softc * sc)1213 smc_stop(struct smc_softc *sc)
1214 {
1215
1216 SMC_ASSERT_LOCKED(sc);
1217
1218 /*
1219 * Turn off callouts.
1220 */
1221 callout_stop(&sc->smc_watchdog);
1222 callout_stop(&sc->smc_mii_tick_ch);
1223
1224 /*
1225 * Mask all interrupts.
1226 */
1227 smc_select_bank(sc, 2);
1228 sc->smc_mask = 0;
1229 smc_write_1(sc, MSK, 0);
1230 #ifdef DEVICE_POLLING
1231 ether_poll_deregister(sc->smc_ifp);
1232 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1233 #endif
1234
1235 /*
1236 * Disable transmit and receive.
1237 */
1238 smc_select_bank(sc, 0);
1239 smc_write_2(sc, TCR, 0);
1240 smc_write_2(sc, RCR, 0);
1241
1242 if_setdrvflagbits(sc->smc_ifp, 0, IFF_DRV_RUNNING);
1243 }
1244
1245 static void
smc_watchdog(void * arg)1246 smc_watchdog(void *arg)
1247 {
1248 struct smc_softc *sc;
1249
1250 sc = (struct smc_softc *)arg;
1251 device_printf(sc->smc_dev, "watchdog timeout\n");
1252 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
1253 }
1254
1255 static void
smc_init(void * context)1256 smc_init(void *context)
1257 {
1258 struct smc_softc *sc;
1259
1260 sc = (struct smc_softc *)context;
1261 SMC_LOCK(sc);
1262 smc_init_locked(sc);
1263 SMC_UNLOCK(sc);
1264 }
1265
1266 static void
smc_init_locked(struct smc_softc * sc)1267 smc_init_locked(struct smc_softc *sc)
1268 {
1269 if_t ifp;
1270
1271 SMC_ASSERT_LOCKED(sc);
1272 ifp = sc->smc_ifp;
1273 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1274 return;
1275
1276 smc_reset(sc);
1277 smc_enable(sc);
1278
1279 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1280 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1281
1282 smc_start_locked(ifp);
1283
1284 if (sc->smc_mii_tick != NULL)
1285 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1286
1287 #ifdef DEVICE_POLLING
1288 SMC_UNLOCK(sc);
1289 ether_poll_register(smc_poll, ifp);
1290 SMC_LOCK(sc);
1291 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1292 #endif
1293 }
1294
1295 static int
smc_ioctl(if_t ifp,u_long cmd,caddr_t data)1296 smc_ioctl(if_t ifp, u_long cmd, caddr_t data)
1297 {
1298 struct smc_softc *sc;
1299 int error;
1300
1301 sc = if_getsoftc(ifp);
1302 error = 0;
1303
1304 switch (cmd) {
1305 case SIOCSIFFLAGS:
1306 if ((if_getflags(ifp) & IFF_UP) == 0 &&
1307 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1308 SMC_LOCK(sc);
1309 smc_stop(sc);
1310 SMC_UNLOCK(sc);
1311 } else {
1312 smc_init(sc);
1313 if (sc->smc_mii_mediachg != NULL)
1314 sc->smc_mii_mediachg(sc);
1315 }
1316 break;
1317
1318 case SIOCADDMULTI:
1319 case SIOCDELMULTI:
1320 /* XXX
1321 SMC_LOCK(sc);
1322 smc_setmcast(sc);
1323 SMC_UNLOCK(sc);
1324 */
1325 error = EINVAL;
1326 break;
1327
1328 case SIOCGIFMEDIA:
1329 case SIOCSIFMEDIA:
1330 if (sc->smc_mii_mediaioctl == NULL) {
1331 error = EINVAL;
1332 break;
1333 }
1334 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1335 break;
1336
1337 default:
1338 error = ether_ioctl(ifp, cmd, data);
1339 break;
1340 }
1341
1342 return (error);
1343 }
1344