1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // sma1307.c -- sma1307 ALSA SoC Audio driver
3 //
4 // Copyright 2024 Iron Device Corporation
5 //
6 // Auther: Gyuhwa Park <gyuwha.park@irondevice.com>
7 // Auther: Kiseok Jo <kiseok.jo@irondevice.com>
8
9 #include <linux/firmware.h>
10 #include <linux/i2c.h>
11 #include <linux/regmap.h>
12 #include <sound/pcm_params.h>
13 #include <sound/tlv.h>
14 #include "sma1307.h"
15
16 #define CHECK_PERIOD_TIME 1 /* sec per HZ */
17 #define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\
18 _post_n, _n, _vco, _p_cp)\
19 {\
20 .input_clk_name = _input_clk_name,\
21 .output_clk_name = _output_clk_name,\
22 .input_clk = _input_clk,\
23 .post_n = _post_n,\
24 .n = _n,\
25 .vco = _vco,\
26 .p_cp = _p_cp,\
27 }
28
29 static const char *setting_file = "sma1307_setting.bin";
30 #define SMA1307_SETTING_CHECKSUM 0x100000
31
32 /* PLL clock setting Table */
33 struct sma1307_pll_match {
34 char *input_clk_name;
35 char *output_clk_name;
36 unsigned int input_clk;
37 unsigned int post_n;
38 unsigned int n;
39 unsigned int vco;
40 unsigned int p_cp;
41 };
42
43 struct sma1307_data {
44 char *name;
45 void (*init)(struct regmap *regmap);
46 };
47
48 struct sma1307_priv {
49 bool check_fault_status;
50 bool force_mute_status;
51 bool sw_ot1_prot;
52 char *name;
53 enum sma1307_mode amp_mode;
54 int binary_mode;
55 int dapm_aif_in;
56 int dapm_aif_out0;
57 int dapm_aif_out1;
58 int dapm_sdo_en;
59 int dapm_sdo_setting;
60 int num_of_pll_matches;
61 int check_fault_period;
62 struct delayed_work check_fault_work;
63 struct device *dev;
64 struct kobject *kobj;
65 struct mutex default_lock;
66 struct regmap *regmap;
67 struct sma1307_setting_file set;
68 const struct sma1307_pll_match *pll_matches;
69 const struct sma1307_data *data;
70 unsigned int cur_vol;
71 unsigned int format;
72 unsigned int frame_size;
73 unsigned int init_vol;
74 unsigned int last_bclk;
75 unsigned int otp_trm2;
76 unsigned int otp_trm3;
77 unsigned int rev_num;
78 unsigned int sys_clk_id;
79 unsigned int tdm_slot0_rx;
80 unsigned int tdm_slot1_rx;
81 unsigned int tdm_slot0_tx;
82 unsigned int tdm_slot1_tx;
83 unsigned int tsdw_cnt;
84 };
85
86 static const struct sma1307_pll_match sma1307_pll_matches[] = {
87 /* in_clk_name, out_clk_name, input_clk post_n, n, vco, p_cp */
88 PLL_MATCH("1.411MHz", "24.554MHz",
89 1411200, 0x06, 0xD1, 0x88, 0x00),
90 PLL_MATCH("1.536MHz", "24.576MHz",
91 1536000, 0x06, 0xC0, 0x88, 0x00),
92 PLL_MATCH("2.822MHz", "24.554MHz",
93 2822400, 0x06, 0xD1, 0x88, 0x04),
94 PLL_MATCH("3.072MHz", "24.576MHz",
95 3072000, 0x06, 0x60, 0x88, 0x00),
96 PLL_MATCH("6.144MHz", "24.576MHz",
97 6144000, 0x06, 0x60, 0x88, 0x04),
98 PLL_MATCH("12.288MHz", "24.576MHz",
99 12288000, 0x06, 0x60, 0x88, 0x08),
100 PLL_MATCH("19.2MHz", "24.48MHz",
101 19200000, 0x06, 0x7B, 0x88, 0x0C),
102 PLL_MATCH("24.576MHz", "24.576MHz",
103 24576000, 0x06, 0x60, 0x88, 0x0C),
104 };
105
106 static struct snd_soc_component *sma1307_amp_component;
107
108 static void sma1307_startup(struct snd_soc_component *);
109 static void sma1307_shutdown(struct snd_soc_component *);
110 static void sma1307_reset(struct snd_soc_component *);
111 static void sma1307_set_binary(struct snd_soc_component *);
112 static void sma1307_set_default(struct snd_soc_component *);
113
114 /* Initial register value - 6.0W SPK (8ohm load) */
115 static const struct reg_default sma1307_reg_def[] = {
116 { 0x00, 0x80 },
117 { 0x01, 0x00 },
118 { 0x02, 0x52 },
119 { 0x03, 0x4C },
120 { 0x04, 0x47 },
121 { 0x05, 0x42 },
122 { 0x06, 0x40 },
123 { 0x07, 0x40 },
124 { 0x08, 0x3C },
125 { 0x09, 0x2F },
126 { 0x0A, 0x32 },
127 { 0x0B, 0x50 },
128 { 0x0C, 0x8C },
129 { 0x0D, 0x00 },
130 { 0x0E, 0x3F },
131 { 0x0F, 0x00 },
132 { 0x10, 0x00 },
133 { 0x11, 0x00 },
134 { 0x12, 0x00 },
135 { 0x13, 0x09 },
136 { 0x14, 0x12 },
137 { 0x1C, 0x00 },
138 { 0x1D, 0x85 },
139 { 0x1E, 0xA1 },
140 { 0x1F, 0x67 },
141 { 0x22, 0x00 },
142 { 0x23, 0x1F },
143 { 0x24, 0x7A },
144 { 0x25, 0x00 },
145 { 0x26, 0xFF },
146 { 0x27, 0x39 },
147 { 0x28, 0x54 },
148 { 0x29, 0x92 },
149 { 0x2A, 0xB0 },
150 { 0x2B, 0xED },
151 { 0x2C, 0xED },
152 { 0x2D, 0xFF },
153 { 0x2E, 0xFF },
154 { 0x2F, 0xFF },
155 { 0x30, 0xFF },
156 { 0x31, 0xFF },
157 { 0x32, 0xFF },
158 { 0x34, 0x01 },
159 { 0x35, 0x17 },
160 { 0x36, 0x92 },
161 { 0x37, 0x00 },
162 { 0x38, 0x01 },
163 { 0x39, 0x10 },
164 { 0x3E, 0x01 },
165 { 0x3F, 0x08 },
166 { 0x8B, 0x05 },
167 { 0x8C, 0x50 },
168 { 0x8D, 0x80 },
169 { 0x8E, 0x10 },
170 { 0x8F, 0x02 },
171 { 0x90, 0x02 },
172 { 0x91, 0x83 },
173 { 0x92, 0xC0 },
174 { 0x93, 0x00 },
175 { 0x94, 0xA4 },
176 { 0x95, 0x74 },
177 { 0x96, 0x57 },
178 { 0xA2, 0xCC },
179 { 0xA3, 0x28 },
180 { 0xA4, 0x40 },
181 { 0xA5, 0x01 },
182 { 0xA6, 0x41 },
183 { 0xA7, 0x08 },
184 { 0xA8, 0x04 },
185 { 0xA9, 0x27 },
186 { 0xAA, 0x10 },
187 { 0xAB, 0x10 },
188 { 0xAC, 0x10 },
189 { 0xAD, 0x0F },
190 { 0xAE, 0xCD },
191 { 0xAF, 0x70 },
192 { 0xB0, 0x03 },
193 { 0xB1, 0xEF },
194 { 0xB2, 0x03 },
195 { 0xB3, 0xEF },
196 { 0xB4, 0xF3 },
197 { 0xB5, 0x3D },
198 };
199
sma1307_readable_register(struct device * dev,unsigned int reg)200 static bool sma1307_readable_register(struct device *dev, unsigned int reg)
201 {
202 if (reg > SMA1307_FF_DEVICE_INDEX)
203 return false;
204
205 switch (reg) {
206 case SMA1307_00_SYSTEM_CTRL ... SMA1307_1F_TONE_FINE_VOLUME:
207 case SMA1307_22_COMP_HYS_SEL ... SMA1307_32_BROWN_OUT_PROT19:
208 case SMA1307_34_OCP_SPK ... SMA1307_39_PMT_NZ_VAL:
209 case SMA1307_3B_TEST1 ... SMA1307_3F_ATEST2:
210 case SMA1307_8B_PLL_POST_N ... SMA1307_9A_OTP_TRM3:
211 case SMA1307_A0_PAD_CTRL0 ... SMA1307_BE_MCBS_CTRL2:
212 case SMA1307_F5_READY_FOR_V_SAR:
213 case SMA1307_F7_READY_FOR_T_SAR ... SMA1307_FF_DEVICE_INDEX:
214 break;
215 default:
216 return false;
217 }
218 return true;
219 }
220
sma1307_writeable_register(struct device * dev,unsigned int reg)221 static bool sma1307_writeable_register(struct device *dev, unsigned int reg)
222 {
223 if (reg > SMA1307_FF_DEVICE_INDEX)
224 return false;
225
226 switch (reg) {
227 case SMA1307_00_SYSTEM_CTRL ... SMA1307_1F_TONE_FINE_VOLUME:
228 case SMA1307_22_COMP_HYS_SEL ... SMA1307_32_BROWN_OUT_PROT19:
229 case SMA1307_34_OCP_SPK ... SMA1307_39_PMT_NZ_VAL:
230 case SMA1307_3B_TEST1 ... SMA1307_3F_ATEST2:
231 case SMA1307_8B_PLL_POST_N ... SMA1307_9A_OTP_TRM3:
232 case SMA1307_A0_PAD_CTRL0 ... SMA1307_BE_MCBS_CTRL2:
233 break;
234 default:
235 return false;
236 }
237 return true;
238 }
239
sma1307_volatile_register(struct device * dev,unsigned int reg)240 static bool sma1307_volatile_register(struct device *dev, unsigned int reg)
241 {
242 if (reg > SMA1307_FF_DEVICE_INDEX)
243 return false;
244
245 switch (reg) {
246 case SMA1307_F8_STATUS_T1 ... SMA1307_FF_DEVICE_INDEX:
247 break;
248 default:
249 return false;
250 }
251 return true;
252 }
253
254 /* DB scale conversion of speaker volume */
255 static const DECLARE_TLV_DB_SCALE(sma1307_spk_tlv, -6000, 50, 0);
256
257 static const char *const sma1307_aif_in_source_text[] = {
258 "Mono", "Left", "Right"
259 };
260
261 static const char *const sma1307_sdo_setting_text[] = {
262 "Data_One_48k", "Data_Two_48k", "Data_Two_24k",
263 "Clk_PLL", "Clk_OSC"
264 };
265
266 static const char *const sma1307_aif_out_source_text[] = {
267 "Disable", "After_FmtC", "After_Mixer", "After_DSP",
268 "Vrms2_Avg", "Battery", "Temperature", "After_Delay"
269 };
270
271 static const char *const sma1307_tdm_slot_text[] = {
272 "Slot0", "Slot1", "Slot2", "Slot3",
273 "Slot4", "Slot5", "Slot6", "Slot7"
274 };
275
276 static const char *const sma1307_binary_mode_text[] = {
277 "Mode0", "Mode1", "Mode2", "Mode3", "Mode4"
278 };
279
280 static const char *const sma1307_reset_text[] = {
281 "Reset"
282 };
283
284 static const struct soc_enum sma1307_aif_in_source_enum =
285 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_aif_in_source_text),
286 sma1307_aif_in_source_text);
287 static const struct soc_enum sma1307_sdo_setting_enum =
288 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_sdo_setting_text),
289 sma1307_sdo_setting_text);
290 static const struct soc_enum sma1307_aif_out_source_enum =
291 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_aif_out_source_text),
292 sma1307_aif_out_source_text);
293 static const struct soc_enum sma1307_tdm_slot_enum =
294 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_tdm_slot_text),
295 sma1307_tdm_slot_text);
296 static const struct soc_enum sma1307_binary_mode_enum =
297 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_binary_mode_text),
298 sma1307_binary_mode_text);
299 static const struct soc_enum sma1307_reset_enum =
300 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_reset_text),
301 sma1307_reset_text);
302
sma1307_force_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)303 static int sma1307_force_mute_get(struct snd_kcontrol *kcontrol,
304 struct snd_ctl_elem_value *ucontrol)
305 {
306 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
307 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
308
309 ucontrol->value.integer.value[0] = (int)sma1307->force_mute_status;
310
311 return 0;
312 }
313
sma1307_force_mute_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)314 static int sma1307_force_mute_put(struct snd_kcontrol *kcontrol,
315 struct snd_ctl_elem_value *ucontrol)
316 {
317 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
318 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
319 bool change = false, val = (bool)ucontrol->value.integer.value[0];
320
321 if (sma1307->force_mute_status == val) {
322 change = false;
323 } else {
324 change = true;
325 sma1307->force_mute_status = val;
326 }
327
328 return change;
329 }
330
sma1307_tdm_slot_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)331 static int sma1307_tdm_slot_get(struct snd_kcontrol *kcontrol,
332 struct snd_ctl_elem_value *ucontrol)
333 {
334 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
335 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
336 int val1, val2;
337
338 regmap_read(sma1307->regmap, SMA1307_A5_TDM1, &val1);
339 regmap_read(sma1307->regmap, SMA1307_A6_TDM2, &val2);
340
341 if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX0_POS_NAME)) {
342 ucontrol->value.integer.value[0]
343 = (val1 & SMA1307_TDM_SLOT0_RX_POS_MASK) >> 3;
344 sma1307->tdm_slot0_rx = ucontrol->value.integer.value[0];
345 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX1_POS_NAME)) {
346 ucontrol->value.integer.value[0]
347 = val1 & SMA1307_TDM_SLOT1_RX_POS_MASK;
348 sma1307->tdm_slot1_rx = ucontrol->value.integer.value[0];
349 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX0_POS_NAME)) {
350 ucontrol->value.integer.value[0]
351 = (val2 & SMA1307_TDM_SLOT0_TX_POS_MASK) >> 3;
352 sma1307->tdm_slot0_tx = ucontrol->value.integer.value[0];
353 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX1_POS_NAME)) {
354 ucontrol->value.integer.value[0]
355 = val2 & SMA1307_TDM_SLOT1_TX_POS_MASK;
356 sma1307->tdm_slot1_tx = ucontrol->value.integer.value[0];
357 } else {
358 return -EINVAL;
359 }
360
361 return 0;
362 }
363
sma1307_tdm_slot_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)364 static int sma1307_tdm_slot_put(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_value *ucontrol)
366 {
367 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
368 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
369 int val = (int)ucontrol->value.integer.value[0];
370 bool change;
371
372 if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX0_POS_NAME)) {
373 if (sma1307->tdm_slot0_rx == val)
374 change = false;
375 else {
376 change = true;
377 sma1307->tdm_slot0_rx = val;
378 regmap_update_bits(sma1307->regmap, SMA1307_A5_TDM1,
379 SMA1307_TDM_SLOT0_RX_POS_MASK, val << 3);
380 }
381 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX1_POS_NAME)) {
382 if (sma1307->tdm_slot1_rx == val)
383 change = false;
384 else {
385 change = true;
386 sma1307->tdm_slot1_rx = val;
387 regmap_update_bits(sma1307->regmap, SMA1307_A5_TDM1,
388 SMA1307_TDM_SLOT1_RX_POS_MASK, val);
389 }
390 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX0_POS_NAME)) {
391 if (sma1307->tdm_slot0_tx == val)
392 change = false;
393 else {
394 change = true;
395 sma1307->tdm_slot0_tx = val;
396 regmap_update_bits(sma1307->regmap, SMA1307_A6_TDM2,
397 SMA1307_TDM_SLOT0_TX_POS_MASK, val << 3);
398 }
399 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX1_POS_NAME)) {
400 if (sma1307->tdm_slot1_tx == val)
401 change = false;
402 else {
403 change = true;
404 sma1307->tdm_slot1_tx = val;
405 regmap_update_bits(sma1307->regmap, SMA1307_A6_TDM2,
406 SMA1307_TDM_SLOT1_TX_POS_MASK, val);
407 }
408 } else {
409 dev_err(sma1307->dev, "%s: Invalid Control ID - %s\n",
410 __func__, kcontrol->id.name);
411 return -EINVAL;
412 }
413
414 return change;
415 }
416
sma1307_sw_ot1_prot_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)417 static int sma1307_sw_ot1_prot_get(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol)
419 {
420 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
421 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
422
423 ucontrol->value.integer.value[0] = (int)sma1307->sw_ot1_prot;
424
425 return 0;
426 }
427
sma1307_sw_ot1_prot_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)428 static int sma1307_sw_ot1_prot_put(struct snd_kcontrol *kcontrol,
429 struct snd_ctl_elem_value *ucontrol)
430 {
431 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
432 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
433 bool change = false, val = (bool)ucontrol->value.integer.value[0];
434
435 if (sma1307->sw_ot1_prot == val)
436 change = false;
437 else {
438 change = true;
439 sma1307->sw_ot1_prot = val;
440 }
441
442 return change;
443 }
444
sma1307_check_fault_status_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)445 static int sma1307_check_fault_status_get(struct snd_kcontrol *kcontrol,
446 struct snd_ctl_elem_value *ucontrol)
447 {
448 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
449 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
450
451 ucontrol->value.integer.value[0] = (int)sma1307->check_fault_status;
452
453 return 0;
454 }
455
sma1307_check_fault_status_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)456 static int sma1307_check_fault_status_put(struct snd_kcontrol *kcontrol,
457 struct snd_ctl_elem_value *ucontrol)
458 {
459 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
460 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
461 bool change = false, val = (bool)ucontrol->value.integer.value[0];
462
463 if (sma1307->check_fault_status == val) {
464 change = false;
465 } else {
466 change = true;
467 sma1307->check_fault_status = val;
468 }
469
470 return change;
471 }
472
sma1307_check_fault_period_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)473 static int sma1307_check_fault_period_get(struct snd_kcontrol *kcontrol,
474 struct snd_ctl_elem_value *ucontrol)
475 {
476 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
477 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
478
479 ucontrol->value.integer.value[0] = sma1307->check_fault_period;
480
481 return 0;
482 }
483
sma1307_check_fault_period_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)484 static int sma1307_check_fault_period_put(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486 {
487 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
488 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
489 struct soc_mixer_control *mc =
490 (struct soc_mixer_control *)kcontrol->private_value;
491 bool change = false;
492 int val = ucontrol->value.integer.value[0];
493
494 if (val < mc->min || val > mc->max)
495 return -EINVAL;
496 if (sma1307->check_fault_period == val) {
497 change = false;
498 } else {
499 change = true;
500 sma1307->check_fault_period = val;
501 }
502
503 return change;
504 }
505
sma1307_reset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)506 static int sma1307_reset_put(struct snd_kcontrol *kcontrol,
507 struct snd_ctl_elem_value *ucontrol)
508 {
509 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
510 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
511
512 regmap_update_bits(sma1307->regmap, SMA1307_00_SYSTEM_CTRL,
513 SMA1307_RESET_MASK, SMA1307_RESET_ON);
514 sma1307_reset(component);
515
516 snd_ctl_notify(component->card->snd_card, SNDRV_CTL_EVENT_MASK_VALUE,
517 &kcontrol->id);
518
519 return true;
520 }
521
sma1307_binary_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)522 static int sma1307_binary_mode_put(struct snd_kcontrol *kcontrol,
523 struct snd_ctl_elem_value *ucontrol)
524 {
525 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
526 struct sma1307_priv *sma1307 = snd_kcontrol_chip(kcontrol);
527
528 sma1307->binary_mode = (int)ucontrol->value.enumerated.item[0];
529 if (sma1307->set.status)
530 sma1307_set_binary(component);
531
532 return snd_soc_put_enum_double(kcontrol, ucontrol);
533 }
534
sma1307_startup(struct snd_soc_component * component)535 static void sma1307_startup(struct snd_soc_component *component)
536 {
537 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
538
539 regmap_update_bits(sma1307->regmap, SMA1307_A2_TOP_MAN1,
540 SMA1307_PLL_MASK, SMA1307_PLL_ON);
541 regmap_update_bits(sma1307->regmap, SMA1307_00_SYSTEM_CTRL,
542 SMA1307_POWER_MASK, SMA1307_POWER_ON);
543
544 if (sma1307->amp_mode == SMA1307_MONO_MODE) {
545 regmap_update_bits(sma1307->regmap,
546 SMA1307_10_SYSTEM_CTRL1,
547 SMA1307_SPK_MODE_MASK,
548 SMA1307_SPK_MONO);
549 } else {
550 regmap_update_bits(sma1307->regmap,
551 SMA1307_10_SYSTEM_CTRL1,
552 SMA1307_SPK_MODE_MASK,
553 SMA1307_SPK_STEREO);
554 }
555
556 if (sma1307->check_fault_status) {
557 if (sma1307->check_fault_period > 0)
558 queue_delayed_work(system_freezable_wq,
559 &sma1307->check_fault_work,
560 sma1307->check_fault_period * HZ);
561 else
562 queue_delayed_work(system_freezable_wq,
563 &sma1307->check_fault_work,
564 CHECK_PERIOD_TIME * HZ);
565 }
566 }
567
sma1307_shutdown(struct snd_soc_component * component)568 static void sma1307_shutdown(struct snd_soc_component *component)
569 {
570 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
571
572 /* for SMA1307A */
573 cancel_delayed_work_sync(&sma1307->check_fault_work);
574
575 regmap_update_bits(sma1307->regmap, SMA1307_0E_MUTE_VOL_CTRL,
576 SMA1307_SPK_MUTE_MASK, SMA1307_SPK_MUTE);
577 /* Need to wait time for mute slope */
578 msleep(55);
579
580 regmap_update_bits(sma1307->regmap, SMA1307_10_SYSTEM_CTRL1,
581 SMA1307_SPK_MODE_MASK, SMA1307_SPK_OFF);
582 regmap_update_bits(sma1307->regmap, SMA1307_A2_TOP_MAN1,
583 SMA1307_PLL_MASK, SMA1307_PLL_OFF);
584 regmap_update_bits(sma1307->regmap, SMA1307_00_SYSTEM_CTRL,
585 SMA1307_POWER_MASK, SMA1307_POWER_OFF);
586 }
587
sma1307_aif_in_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)588 static int sma1307_aif_in_event(struct snd_soc_dapm_widget *w,
589 struct snd_kcontrol *kcontrol, int event)
590 {
591 struct snd_soc_component *component =
592 snd_soc_dapm_to_component(w->dapm);
593 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
594 unsigned int mux = sma1307->dapm_aif_in;
595
596 switch (event) {
597 case SND_SOC_DAPM_PRE_PMU:
598 switch (mux) {
599 case SMA1307_MONO_MODE:
600 regmap_update_bits(sma1307->regmap,
601 SMA1307_11_SYSTEM_CTRL2,
602 SMA1307_MONOMIX_MASK,
603 SMA1307_MONOMIX_ON);
604 break;
605 case SMA1307_LEFT_MODE:
606 regmap_update_bits(sma1307->regmap,
607 SMA1307_11_SYSTEM_CTRL2,
608 SMA1307_MONOMIX_MASK,
609 SMA1307_MONOMIX_OFF);
610 regmap_update_bits(sma1307->regmap,
611 SMA1307_11_SYSTEM_CTRL2,
612 SMA1307_LR_DATA_SW_MASK,
613 SMA1307_LR_DATA_SW_NORMAL);
614 break;
615 case SMA1307_RIGHT_MODE:
616 regmap_update_bits(sma1307->regmap,
617 SMA1307_11_SYSTEM_CTRL2,
618 SMA1307_MONOMIX_MASK,
619 SMA1307_MONOMIX_OFF);
620 regmap_update_bits(sma1307->regmap,
621 SMA1307_11_SYSTEM_CTRL2,
622 SMA1307_LR_DATA_SW_MASK,
623 SMA1307_LR_DATA_SW_SWAP);
624 break;
625 default:
626
627 dev_err(sma1307->dev, "%s: Invalid value (%d)\n",
628 __func__, mux);
629 return -EINVAL;
630 }
631 sma1307->amp_mode = mux;
632 break;
633 }
634 return 0;
635 }
636
sma1307_sdo_setting_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)637 static int sma1307_sdo_setting_event(struct snd_soc_dapm_widget *w,
638 struct snd_kcontrol *kcontrol, int event)
639 {
640 struct snd_soc_component *component =
641 snd_soc_dapm_to_component(w->dapm);
642 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
643 unsigned int mux = sma1307->dapm_sdo_setting;
644
645 switch (event) {
646 case SND_SOC_DAPM_PRE_PMU:
647 switch (mux) {
648 case SMA1307_OUT_DATA_ONE_48K:
649 regmap_update_bits(sma1307->regmap,
650 SMA1307_A2_TOP_MAN1,
651 SMA1307_SDO_OUTPUT2_MASK,
652 SMA1307_ONE_SDO_PER_CH);
653 regmap_update_bits(sma1307->regmap,
654 SMA1307_A3_TOP_MAN2,
655 SMA1307_SDO_OUTPUT3_MASK
656 |
657 SMA1307_DATA_CLK_SEL_MASK,
658 SMA1307_SDO_OUTPUT3_DIS
659 | SMA1307_SDO_DATA);
660 break;
661 case SMA1307_OUT_DATA_TWO_48K:
662 regmap_update_bits(sma1307->regmap,
663 SMA1307_A2_TOP_MAN1,
664 SMA1307_SDO_OUTPUT2_MASK,
665 SMA1307_TWO_SDO_PER_CH);
666 regmap_update_bits(sma1307->regmap,
667 SMA1307_A3_TOP_MAN2,
668 SMA1307_SDO_OUTPUT3_MASK
669 |
670 SMA1307_DATA_CLK_SEL_MASK,
671 SMA1307_SDO_OUTPUT3_DIS
672 | SMA1307_SDO_DATA);
673 break;
674 case SMA1307_OUT_DATA_TWO_24K:
675 regmap_update_bits(sma1307->regmap,
676 SMA1307_A2_TOP_MAN1,
677 SMA1307_SDO_OUTPUT2_MASK,
678 SMA1307_TWO_SDO_PER_CH);
679 regmap_update_bits(sma1307->regmap,
680 SMA1307_A3_TOP_MAN2,
681 SMA1307_SDO_OUTPUT3_MASK
682 |
683 SMA1307_DATA_CLK_SEL_MASK,
684 SMA1307_TWO_SDO_PER_CH_24K
685 | SMA1307_SDO_DATA);
686 break;
687 case SMA1307_OUT_CLK_PLL:
688 regmap_update_bits(sma1307->regmap,
689 SMA1307_A3_TOP_MAN2,
690 SMA1307_DATA_CLK_SEL_MASK,
691 SMA1307_SDO_CLK_PLL);
692
693 break;
694 case SMA1307_OUT_CLK_OSC:
695 regmap_update_bits(sma1307->regmap,
696 SMA1307_A3_TOP_MAN2,
697 SMA1307_DATA_CLK_SEL_MASK,
698 SMA1307_SDO_CLK_OSC);
699
700 break;
701 default:
702 dev_err(sma1307->dev, "%s: Invalid value (%d)\n",
703 __func__, mux);
704 return -EINVAL;
705 }
706 break;
707 }
708 return 0;
709 }
710
sma1307_aif_out_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)711 static int sma1307_aif_out_event(struct snd_soc_dapm_widget *w,
712 struct snd_kcontrol *kcontrol, int event)
713 {
714 struct snd_soc_component *component =
715 snd_soc_dapm_to_component(w->dapm);
716 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
717 unsigned int mux = 0, val = 0, mask = 0;
718
719 if (!strcmp(w->name, SMA1307_AIF_OUT0_NAME)) {
720 mux = sma1307->dapm_aif_out0;
721 val = mux;
722 mask = SMA1307_SDO_OUT0_SEL_MASK;
723 } else if (!strcmp(w->name, SMA1307_AIF_OUT1_NAME)) {
724 mux = sma1307->dapm_aif_out1;
725 val = mux << 3;
726 mask = SMA1307_SDO_OUT1_SEL_MASK;
727 } else {
728 dev_err(sma1307->dev, "%s: Invalid widget - %s\n",
729 __func__, w->name);
730 return -EINVAL;
731 }
732 switch (event) {
733 case SND_SOC_DAPM_PRE_PMU:
734 regmap_update_bits(sma1307->regmap, SMA1307_09_OUTPUT_CTRL,
735 mask, val);
736 break;
737 }
738 return 0;
739 }
740
sma1307_sdo_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)741 static int sma1307_sdo_event(struct snd_soc_dapm_widget *w,
742 struct snd_kcontrol *kcontrol, int event)
743 {
744 struct snd_soc_component *component =
745 snd_soc_dapm_to_component(w->dapm);
746 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
747
748 switch (event) {
749 case SND_SOC_DAPM_PRE_PMU:
750 regmap_update_bits(sma1307->regmap,
751 SMA1307_09_OUTPUT_CTRL,
752 SMA1307_PORT_CONFIG_MASK,
753 SMA1307_OUTPUT_PORT_ENABLE);
754 regmap_update_bits(sma1307->regmap,
755 SMA1307_A3_TOP_MAN2,
756 SMA1307_SDO_OUTPUT_MASK,
757 SMA1307_LOGIC_OUTPUT);
758 break;
759 case SND_SOC_DAPM_POST_PMD:
760 regmap_update_bits(sma1307->regmap,
761 SMA1307_09_OUTPUT_CTRL,
762 SMA1307_PORT_CONFIG_MASK,
763 SMA1307_INPUT_PORT_ONLY);
764 regmap_update_bits(sma1307->regmap,
765 SMA1307_A3_TOP_MAN2,
766 SMA1307_SDO_OUTPUT_MASK,
767 SMA1307_HIGH_Z_OUTPUT);
768 break;
769 }
770 return 0;
771 }
772
sma1307_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)773 static int sma1307_power_event(struct snd_soc_dapm_widget *w,
774 struct snd_kcontrol *kcontrol, int event)
775 {
776 struct snd_soc_component *component =
777 snd_soc_dapm_to_component(w->dapm);
778
779 switch (event) {
780 case SND_SOC_DAPM_POST_PMU:
781 sma1307_startup(component);
782 break;
783 case SND_SOC_DAPM_PRE_PMD:
784 sma1307_shutdown(component);
785 break;
786 }
787 return 0;
788 }
789
sma1307_dapm_aif_in_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)790 static int sma1307_dapm_aif_in_get(struct snd_kcontrol *kcontrol,
791 struct snd_ctl_elem_value *ucontrol)
792 {
793 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
794 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
795 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
796
797 ucontrol->value.enumerated.item[0] = (unsigned int)sma1307->dapm_aif_in;
798 snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
799
800 return 0;
801 }
802
sma1307_dapm_aif_in_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)803 static int sma1307_dapm_aif_in_put(struct snd_kcontrol *kcontrol,
804 struct snd_ctl_elem_value *ucontrol)
805 {
806 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
807 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
808 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
809 int val = (int)ucontrol->value.enumerated.item[0];
810 bool change;
811
812 if ((val < 0) || (val >= ARRAY_SIZE(sma1307_aif_in_source_text))) {
813 dev_err(sma1307->dev, "%s: Out of range\n", __func__);
814 return -EINVAL;
815 }
816
817 if (sma1307->dapm_aif_in != val) {
818 change = true;
819 sma1307->dapm_aif_in = val;
820 } else
821 change = false;
822
823 snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
824
825 return change;
826 }
827
sma1307_dapm_sdo_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)828 static int sma1307_dapm_sdo_setting_get(struct snd_kcontrol *kcontrol,
829 struct snd_ctl_elem_value *ucontrol)
830 {
831 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
832 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
833 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
834
835 ucontrol->value.enumerated.item[0] =
836 (unsigned int)sma1307->dapm_sdo_setting;
837 snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
838
839 return 0;
840 }
841
sma1307_dapm_sdo_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)842 static int sma1307_dapm_sdo_setting_put(struct snd_kcontrol *kcontrol,
843 struct snd_ctl_elem_value *ucontrol)
844 {
845 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
846 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
847 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
848 int val = (int)ucontrol->value.enumerated.item[0];
849 bool change;
850
851 if ((val < 0) || (val >= ARRAY_SIZE(sma1307_sdo_setting_text))) {
852 dev_err(sma1307->dev, "%s: Out of range\n", __func__);
853 return -EINVAL;
854 }
855
856 if (sma1307->dapm_sdo_setting != val) {
857 change = true;
858 sma1307->dapm_sdo_setting = val;
859 } else
860 change = false;
861
862 snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
863
864 return change;
865 }
866
sma1307_dapm_aif_out_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)867 static int sma1307_dapm_aif_out_get(struct snd_kcontrol *kcontrol,
868 struct snd_ctl_elem_value *ucontrol)
869 {
870 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
871 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
872 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
873 unsigned int val = 0;
874
875 if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT0_NAME)) {
876 val = (unsigned int)sma1307->dapm_aif_out0;
877 } else if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT1_NAME)) {
878 val = (unsigned int)sma1307->dapm_aif_out1;
879 } else {
880 dev_err(sma1307->dev, "%s: Invalid Control ID - %s\n",
881 __func__, kcontrol->id.name);
882 return -EINVAL;
883 }
884 ucontrol->value.enumerated.item[0] = val;
885 snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
886
887 return 0;
888 }
889
sma1307_dapm_aif_out_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)890 static int sma1307_dapm_aif_out_put(struct snd_kcontrol *kcontrol,
891 struct snd_ctl_elem_value *ucontrol)
892 {
893 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
894 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
895 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
896 int val = (int)ucontrol->value.enumerated.item[0];
897 bool change;
898
899 if ((val < 0) || (val >= ARRAY_SIZE(sma1307_aif_out_source_text))) {
900 dev_err(sma1307->dev, "%s: Out of range\n", __func__);
901 return -EINVAL;
902 }
903
904 if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT0_NAME)) {
905 if (sma1307->dapm_aif_out0 != val) {
906 change = true;
907 sma1307->dapm_aif_out0 = val;
908 } else
909 change = false;
910 } else if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT1_NAME)) {
911 if (sma1307->dapm_aif_out1 != val) {
912 change = true;
913 sma1307->dapm_aif_out1 = val;
914 } else
915 change = false;
916 } else {
917 dev_err(sma1307->dev, "%s: Invalid Control ID - %s\n",
918 __func__, kcontrol->id.name);
919 return -EINVAL;
920 }
921
922 snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
923
924 return change;
925 }
926
sma1307_dapm_sdo_enable_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)927 static int sma1307_dapm_sdo_enable_get(struct snd_kcontrol *kcontrol,
928 struct snd_ctl_elem_value *ucontrol)
929 {
930 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
931 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
932 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
933
934 ucontrol->value.integer.value[0] = (long)sma1307->dapm_sdo_en;
935 snd_soc_dapm_put_volsw(kcontrol, ucontrol);
936
937 return 0;
938 }
939
sma1307_dapm_sdo_enable_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)940 static int sma1307_dapm_sdo_enable_put(struct snd_kcontrol *kcontrol,
941 struct snd_ctl_elem_value *ucontrol)
942 {
943 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol);
944 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
945 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
946 int val = (int)ucontrol->value.integer.value[0];
947 bool change;
948
949 if ((val < 0) || (val > 1)) {
950 dev_err(sma1307->dev, "%s: Out of range\n", __func__);
951 return -EINVAL;
952 }
953
954 if (sma1307->dapm_sdo_en != val) {
955 change = true;
956 sma1307->dapm_sdo_en = val;
957 } else
958 change = false;
959
960 snd_soc_dapm_put_volsw(kcontrol, ucontrol);
961
962 return change;
963 }
964
965 static const struct snd_kcontrol_new sma1307_aif_in_source_control = {
966 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
967 .name = SMA1307_AIF_IN_NAME,
968 .info = snd_soc_info_enum_double,
969 .get = sma1307_dapm_aif_in_get,
970 .put = sma1307_dapm_aif_in_put,
971 .private_value = (unsigned long)&sma1307_aif_in_source_enum
972 };
973
974 static const struct snd_kcontrol_new sma1307_sdo_setting_control = {
975 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
976 .name = "SDO Setting",
977 .info = snd_soc_info_enum_double,
978 .get = sma1307_dapm_sdo_setting_get,
979 .put = sma1307_dapm_sdo_setting_put,
980 .private_value = (unsigned long)&sma1307_sdo_setting_enum
981 };
982
983 static const struct snd_kcontrol_new sma1307_aif_out0_source_control = {
984 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
985 .name = SMA1307_AIF_OUT0_NAME,
986 .info = snd_soc_info_enum_double,
987 .get = sma1307_dapm_aif_out_get,
988 .put = sma1307_dapm_aif_out_put,
989 .private_value = (unsigned long)&sma1307_aif_out_source_enum
990 };
991
992 static const struct snd_kcontrol_new sma1307_aif_out1_source_control = {
993 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
994 .name = SMA1307_AIF_OUT1_NAME,
995 .info = snd_soc_info_enum_double,
996 .get = sma1307_dapm_aif_out_get,
997 .put = sma1307_dapm_aif_out_put,
998 .private_value = (unsigned long)&sma1307_aif_out_source_enum
999 };
1000
1001 static const struct snd_kcontrol_new sma1307_sdo_control =
1002 SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0,
1003 sma1307_dapm_sdo_enable_get, sma1307_dapm_sdo_enable_put);
1004
1005 static const struct snd_kcontrol_new sma1307_enable_control =
1006 SOC_DAPM_SINGLE("Switch", SMA1307_00_SYSTEM_CTRL, 0, 1, 0);
1007
1008 static const struct snd_kcontrol_new sma1307_binary_mode_control[] = {
1009 SOC_ENUM_EXT("Binary Mode", sma1307_binary_mode_enum,
1010 snd_soc_get_enum_double, sma1307_binary_mode_put),
1011 };
1012
1013 static const struct snd_kcontrol_new sma1307_snd_controls[] = {
1014 SOC_SINGLE_TLV(SMA1307_VOL_CTRL_NAME, SMA1307_0A_SPK_VOL,
1015 0, 167, 1, sma1307_spk_tlv),
1016 SOC_ENUM_EXT(SMA1307_TDM_RX0_POS_NAME, sma1307_tdm_slot_enum,
1017 sma1307_tdm_slot_get, sma1307_tdm_slot_put),
1018 SOC_ENUM_EXT(SMA1307_TDM_RX1_POS_NAME, sma1307_tdm_slot_enum,
1019 sma1307_tdm_slot_get, sma1307_tdm_slot_put),
1020 SOC_ENUM_EXT(SMA1307_TDM_TX0_POS_NAME, sma1307_tdm_slot_enum,
1021 sma1307_tdm_slot_get, sma1307_tdm_slot_put),
1022 SOC_ENUM_EXT(SMA1307_TDM_TX1_POS_NAME, sma1307_tdm_slot_enum,
1023 sma1307_tdm_slot_get, sma1307_tdm_slot_put),
1024 SOC_ENUM_EXT(SMA1307_RESET_CTRL_NAME, sma1307_reset_enum,
1025 snd_soc_get_enum_double, sma1307_reset_put),
1026 SOC_SINGLE_BOOL_EXT(SMA1307_FORCE_MUTE_CTRL_NAME, 0,
1027 sma1307_force_mute_get, sma1307_force_mute_put),
1028 SOC_SINGLE_BOOL_EXT(SMA1307_OT1_SW_PROT_CTRL_NAME, 0,
1029 sma1307_sw_ot1_prot_get, sma1307_sw_ot1_prot_put),
1030 SOC_SINGLE_BOOL_EXT(SMA1307_CHECK_FAULT_STATUS_NAME, 0,
1031 sma1307_check_fault_status_get,
1032 sma1307_check_fault_status_put),
1033 SOC_SINGLE_EXT(SMA1307_CHECK_FAULT_PERIOD_NAME, SND_SOC_NOPM, 0, 600, 0,
1034 sma1307_check_fault_period_get,
1035 sma1307_check_fault_period_put),
1036 };
1037
1038 static const struct snd_soc_dapm_widget sma1307_dapm_widgets[] = {
1039 /* platform domain */
1040 SND_SOC_DAPM_OUTPUT("SPK"),
1041 SND_SOC_DAPM_INPUT("SDO"),
1042
1043 /* path domain */
1044 SND_SOC_DAPM_MUX_E(SMA1307_AIF_IN_NAME, SND_SOC_NOPM, 0, 0,
1045 &sma1307_aif_in_source_control,
1046 sma1307_aif_in_event,
1047 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1048 SND_SOC_DAPM_MUX_E("SDO Setting", SND_SOC_NOPM, 0, 0,
1049 &sma1307_sdo_setting_control,
1050 sma1307_sdo_setting_event,
1051 SND_SOC_DAPM_PRE_PMU),
1052 SND_SOC_DAPM_MUX_E(SMA1307_AIF_OUT0_NAME, SND_SOC_NOPM, 0, 0,
1053 &sma1307_aif_out0_source_control,
1054 sma1307_aif_out_event,
1055 SND_SOC_DAPM_PRE_PMU),
1056 SND_SOC_DAPM_MUX_E(SMA1307_AIF_OUT1_NAME, SND_SOC_NOPM, 0, 0,
1057 &sma1307_aif_out1_source_control,
1058 sma1307_aif_out_event,
1059 SND_SOC_DAPM_PRE_PMU),
1060 SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0,
1061 &sma1307_sdo_control,
1062 sma1307_sdo_event,
1063 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1064 SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0),
1065 SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0,
1066 sma1307_power_event,
1067 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD |
1068 SND_SOC_DAPM_POST_PMU),
1069 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 0,
1070 &sma1307_enable_control),
1071
1072 /* stream domain */
1073 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
1074 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
1075 };
1076
1077 static const struct snd_soc_dapm_route sma1307_audio_map[] = {
1078 /* Playback */
1079 { "AIF IN Source", "Mono", "AIF IN" },
1080 { "AIF IN Source", "Left", "AIF IN" },
1081 { "AIF IN Source", "Right", "AIF IN" },
1082
1083 { "SDO Enable", "Switch", "AIF IN" },
1084
1085 { "SDO Setting", "Data_One_48k", "SDO Enable" },
1086 { "SDO Setting", "Data_Two_48k", "SDO Enable" },
1087 { "SDO Setting", "Data_Two_24k", "SDO Enable" },
1088 { "SDO Setting", "Clk_PLL", "SDO Enable" },
1089 { "SDO Setting", "Clk_OSC", "SDO Enable" },
1090
1091 { "AIF OUT0 Source", "Disable", "SDO Setting" },
1092 { "AIF OUT0 Source", "After_FmtC", "SDO Setting" },
1093 { "AIF OUT0 Source", "After_Mixer", "SDO Setting" },
1094 { "AIF OUT0 Source", "After_DSP", "SDO Setting" },
1095 { "AIF OUT0 Source", "Vrms2_Avg", "SDO Setting" },
1096 { "AIF OUT0 Source", "Battery", "SDO Setting" },
1097 { "AIF OUT0 Source", "Temperature", "SDO Setting" },
1098 { "AIF OUT0 Source", "After_Delay", "SDO Setting" },
1099
1100 { "AIF OUT1 Source", "Disable", "SDO Setting" },
1101 { "AIF OUT1 Source", "After_FmtC", "SDO Setting" },
1102 { "AIF OUT1 Source", "After_Mixer", "SDO Setting" },
1103 { "AIF OUT1 Source", "After_DSP", "SDO Setting" },
1104 { "AIF OUT1 Source", "Vrms2_Avg", "SDO Setting" },
1105 { "AIF OUT1 Source", "Battery", "SDO Setting" },
1106 { "AIF OUT1 Source", "Temperature", "SDO Setting" },
1107 { "AIF OUT1 Source", "After_Delay", "SDO Setting" },
1108
1109 { "Entry", NULL, "AIF OUT0 Source" },
1110 { "Entry", NULL, "AIF OUT1 Source" },
1111 { "Entry", NULL, "AIF IN Source" },
1112
1113 { "AMP Power", NULL, "Entry" },
1114
1115 { "AMP Enable", "Switch", "AMP Power" },
1116 { "SPK", NULL, "AMP Enable" },
1117
1118 /* Capture */
1119 { "AIF OUT", NULL, "AMP Enable" },
1120 };
1121
sma1307_setup_pll(struct snd_soc_component * component,unsigned int bclk)1122 static void sma1307_setup_pll(struct snd_soc_component *component,
1123 unsigned int bclk)
1124 {
1125 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1126
1127 int i = 0;
1128
1129 dev_dbg(component->dev, "%s: BCLK = %dHz\n", __func__, bclk);
1130
1131 if (sma1307->sys_clk_id == SMA1307_PLL_CLKIN_MCLK) {
1132 dev_warn(component->dev, "%s: MCLK is not supported\n",
1133 __func__);
1134 } else if (sma1307->sys_clk_id == SMA1307_PLL_CLKIN_BCLK) {
1135 for (i = 0; i < sma1307->num_of_pll_matches; i++) {
1136 if (sma1307->pll_matches[i].input_clk == bclk)
1137 break;
1138 }
1139 if (i == sma1307->num_of_pll_matches) {
1140 dev_warn(component->dev,
1141 "%s: No matching value between pll table and SCK\n",
1142 __func__);
1143 return;
1144 }
1145
1146 regmap_update_bits(sma1307->regmap,
1147 SMA1307_A2_TOP_MAN1,
1148 SMA1307_PLL_MASK, SMA1307_PLL_ON);
1149 }
1150
1151 regmap_write(sma1307->regmap, SMA1307_8B_PLL_POST_N,
1152 sma1307->pll_matches[i].post_n);
1153 regmap_write(sma1307->regmap, SMA1307_8C_PLL_N,
1154 sma1307->pll_matches[i].n);
1155 regmap_write(sma1307->regmap, SMA1307_8D_PLL_A_SETTING,
1156 sma1307->pll_matches[i].vco);
1157 regmap_write(sma1307->regmap, SMA1307_8E_PLL_P_CP,
1158 sma1307->pll_matches[i].p_cp);
1159 }
1160
sma1307_dai_hw_params_amp(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1161 static int sma1307_dai_hw_params_amp(struct snd_pcm_substream *substream,
1162 struct snd_pcm_hw_params *params,
1163 struct snd_soc_dai *dai)
1164 {
1165 struct snd_soc_component *component = dai->component;
1166 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1167 unsigned int bclk = 0;
1168
1169 if (sma1307->format == SND_SOC_DAIFMT_DSP_A)
1170 bclk = params_rate(params) * sma1307->frame_size;
1171 else
1172 bclk = params_rate(params) * params_physical_width(params)
1173 * params_channels(params);
1174
1175 dev_dbg(component->dev,
1176 "%s: rate = %d : bit size = %d : channel = %d\n",
1177 __func__, params_rate(params), params_width(params),
1178 params_channels(params));
1179
1180 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1181 if (sma1307->sys_clk_id == SMA1307_PLL_CLKIN_BCLK) {
1182 if (sma1307->last_bclk != bclk) {
1183 sma1307_setup_pll(component, bclk);
1184 sma1307->last_bclk = bclk;
1185 }
1186 }
1187
1188 switch (params_rate(params)) {
1189 case 8000:
1190 case 12000:
1191 case 16000:
1192 case 24000:
1193 case 32000:
1194 case 44100:
1195 case 48000:
1196 break;
1197
1198 case 96000:
1199 dev_warn(component->dev,
1200 "%s: %d rate not support SDO\n", __func__,
1201 params_rate(params));
1202 break;
1203
1204 default:
1205 dev_err(component->dev, "%s: not support rate : %d\n",
1206 __func__, params_rate(params));
1207
1208 return -EINVAL;
1209 }
1210
1211 /* substream->stream is SNDRV_PCM_STREAM_CAPTURE */
1212 } else {
1213
1214 switch (params_format(params)) {
1215 case SNDRV_PCM_FORMAT_S16_LE:
1216 regmap_update_bits(sma1307->regmap,
1217 SMA1307_A4_TOP_MAN3,
1218 SMA1307_SCK_RATE_MASK
1219 |
1220 SMA1307_DATA_WIDTH_MASK,
1221 SMA1307_SCK_32FS |
1222 SMA1307_DATA_16BIT);
1223 break;
1224
1225 case SNDRV_PCM_FORMAT_S24_LE:
1226 regmap_update_bits(sma1307->regmap,
1227 SMA1307_A4_TOP_MAN3,
1228 SMA1307_SCK_RATE_MASK
1229 |
1230 SMA1307_DATA_WIDTH_MASK,
1231 SMA1307_SCK_64FS |
1232 SMA1307_DATA_24BIT);
1233 break;
1234
1235 case SNDRV_PCM_FORMAT_S32_LE:
1236 regmap_update_bits(sma1307->regmap,
1237 SMA1307_A4_TOP_MAN3,
1238 SMA1307_SCK_RATE_MASK
1239 |
1240 SMA1307_DATA_WIDTH_MASK,
1241 SMA1307_SCK_64FS |
1242 SMA1307_DATA_24BIT);
1243 break;
1244 default:
1245 dev_err(component->dev,
1246 "%s: not support data bit : %d\n", __func__,
1247 params_format(params));
1248 return -EINVAL;
1249 }
1250 }
1251
1252 switch (sma1307->format) {
1253 case SND_SOC_DAIFMT_I2S:
1254 regmap_update_bits(sma1307->regmap,
1255 SMA1307_01_INPUT_CTRL1,
1256 SMA1307_I2S_MODE_MASK,
1257 SMA1307_STANDARD_I2S);
1258 regmap_update_bits(sma1307->regmap,
1259 SMA1307_A4_TOP_MAN3,
1260 SMA1307_INTERFACE_MASK,
1261 SMA1307_I2S_FORMAT);
1262 break;
1263 case SND_SOC_DAIFMT_LEFT_J:
1264 regmap_update_bits(sma1307->regmap,
1265 SMA1307_01_INPUT_CTRL1,
1266 SMA1307_I2S_MODE_MASK, SMA1307_LJ);
1267 regmap_update_bits(sma1307->regmap,
1268 SMA1307_A4_TOP_MAN3,
1269 SMA1307_INTERFACE_MASK,
1270 SMA1307_LJ_FORMAT);
1271 break;
1272 case SND_SOC_DAIFMT_RIGHT_J:
1273 switch (params_width(params)) {
1274 case 16:
1275 regmap_update_bits(sma1307->regmap,
1276 SMA1307_01_INPUT_CTRL1,
1277 SMA1307_I2S_MODE_MASK,
1278 SMA1307_RJ_16BIT);
1279 break;
1280 case 24:
1281 case 32:
1282 regmap_update_bits(sma1307->regmap,
1283 SMA1307_01_INPUT_CTRL1,
1284 SMA1307_I2S_MODE_MASK,
1285 SMA1307_RJ_24BIT);
1286 break;
1287 }
1288 break;
1289 case SND_SOC_DAIFMT_DSP_A:
1290 regmap_update_bits(sma1307->regmap,
1291 SMA1307_01_INPUT_CTRL1,
1292 SMA1307_I2S_MODE_MASK,
1293 SMA1307_STANDARD_I2S);
1294 regmap_update_bits(sma1307->regmap,
1295 SMA1307_A4_TOP_MAN3,
1296 SMA1307_INTERFACE_MASK,
1297 SMA1307_TDM_FORMAT);
1298 break;
1299 }
1300
1301 switch (params_width(params)) {
1302 case 16:
1303 case 24:
1304 case 32:
1305 break;
1306 default:
1307 dev_err(component->dev,
1308 "%s: not support data bit : %d\n", __func__,
1309 params_format(params));
1310 return -EINVAL;
1311 }
1312
1313 return 0;
1314 }
1315
sma1307_dai_set_sysclk_amp(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1316 static int sma1307_dai_set_sysclk_amp(struct snd_soc_dai *dai,
1317 int clk_id, unsigned int freq, int dir)
1318 {
1319 struct snd_soc_component *component = dai->component;
1320 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1321
1322 switch (clk_id) {
1323 case SMA1307_EXTERNAL_CLOCK_19_2:
1324 case SMA1307_EXTERNAL_CLOCK_24_576:
1325 case SMA1307_PLL_CLKIN_MCLK:
1326 case SMA1307_PLL_CLKIN_BCLK:
1327 break;
1328 default:
1329 dev_err(component->dev, "%s: Invalid clk id: %d\n",
1330 __func__, clk_id);
1331 return -EINVAL;
1332 }
1333 sma1307->sys_clk_id = clk_id;
1334
1335 return 0;
1336 }
1337
sma1307_dai_set_fmt_amp(struct snd_soc_dai * dai,unsigned int fmt)1338 static int sma1307_dai_set_fmt_amp(struct snd_soc_dai *dai, unsigned int fmt)
1339 {
1340 struct snd_soc_component *component = dai->component;
1341 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1342
1343 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1344
1345 case SND_SOC_DAIFMT_CBC_CFC:
1346 dev_dbg(component->dev,
1347 "%s: %s\n", __func__, "I2S/TDM Device mode");
1348 regmap_update_bits(sma1307->regmap,
1349 SMA1307_01_INPUT_CTRL1,
1350 SMA1307_CONTROLLER_DEVICE_MASK,
1351 SMA1307_DEVICE_MODE);
1352 break;
1353
1354 case SND_SOC_DAIFMT_CBP_CFP:
1355 dev_dbg(component->dev,
1356 "%s: %s\n", __func__, "I2S/TDM Controller mode");
1357 regmap_update_bits(sma1307->regmap,
1358 SMA1307_01_INPUT_CTRL1,
1359 SMA1307_CONTROLLER_DEVICE_MASK,
1360 SMA1307_CONTROLLER_MODE);
1361 break;
1362
1363 default:
1364 dev_err(component->dev,
1365 "%s: Unsupported Controller/Device : 0x%x\n",
1366 __func__, fmt);
1367 return -EINVAL;
1368 }
1369
1370 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1371 case SND_SOC_DAIFMT_I2S:
1372 case SND_SOC_DAIFMT_RIGHT_J:
1373 case SND_SOC_DAIFMT_LEFT_J:
1374 case SND_SOC_DAIFMT_DSP_A:
1375 case SND_SOC_DAIFMT_DSP_B:
1376 sma1307->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1377 break;
1378 default:
1379 dev_err(component->dev,
1380 "%s: Unsupported Audio Interface Format : 0x%x\n",
1381 __func__, fmt);
1382 return -EINVAL;
1383 }
1384
1385 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1386
1387 case SND_SOC_DAIFMT_IB_NF:
1388 dev_dbg(component->dev, "%s: %s\n",
1389 __func__, "Invert BCLK + Normal Frame");
1390 regmap_update_bits(sma1307->regmap,
1391 SMA1307_01_INPUT_CTRL1,
1392 SMA1307_SCK_RISING_MASK,
1393 SMA1307_SCK_RISING_EDGE);
1394 break;
1395 case SND_SOC_DAIFMT_IB_IF:
1396 dev_dbg(component->dev, "%s: %s\n",
1397 __func__, "Invert BCLK + Invert Frame");
1398 regmap_update_bits(sma1307->regmap,
1399 SMA1307_01_INPUT_CTRL1,
1400 SMA1307_LEFTPOL_MASK
1401 | SMA1307_SCK_RISING_MASK,
1402 SMA1307_HIGH_FIRST_CH
1403 | SMA1307_SCK_RISING_EDGE);
1404 break;
1405 case SND_SOC_DAIFMT_NB_IF:
1406 dev_dbg(component->dev, "%s: %s\n",
1407 __func__, "Normal BCLK + Invert Frame");
1408 regmap_update_bits(sma1307->regmap,
1409 SMA1307_01_INPUT_CTRL1,
1410 SMA1307_LEFTPOL_MASK,
1411 SMA1307_HIGH_FIRST_CH);
1412 break;
1413 case SND_SOC_DAIFMT_NB_NF:
1414 dev_dbg(component->dev, "%s: %s\n",
1415 __func__, "Normal BCLK + Normal Frame");
1416 break;
1417 default:
1418 dev_err(component->dev,
1419 "%s: Unsupported Bit & Frameclock : 0x%x\n",
1420 __func__, fmt);
1421 return -EINVAL;
1422 }
1423
1424 return 0;
1425 }
1426
sma1307_dai_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1427 static int sma1307_dai_set_tdm_slot(struct snd_soc_dai *dai,
1428 unsigned int tx_mask, unsigned int rx_mask,
1429 int slots, int slot_width)
1430 {
1431 struct snd_soc_component *component = dai->component;
1432 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1433
1434 dev_dbg(component->dev, "%s: slots = %d, slot_width - %d\n",
1435 __func__, slots, slot_width);
1436
1437 sma1307->frame_size = slot_width * slots;
1438
1439 regmap_update_bits(sma1307->regmap,
1440 SMA1307_A4_TOP_MAN3,
1441 SMA1307_INTERFACE_MASK, SMA1307_TDM_FORMAT);
1442
1443 regmap_update_bits(sma1307->regmap,
1444 SMA1307_A5_TDM1,
1445 SMA1307_TDM_TX_MODE_MASK,
1446 SMA1307_TDM_TX_MONO);
1447
1448 switch (slot_width) {
1449 case 16:
1450 regmap_update_bits(sma1307->regmap,
1451 SMA1307_A6_TDM2,
1452 SMA1307_TDM_DL_MASK,
1453 SMA1307_TDM_DL_16);
1454 break;
1455 case 32:
1456 regmap_update_bits(sma1307->regmap,
1457 SMA1307_A6_TDM2,
1458 SMA1307_TDM_DL_MASK,
1459 SMA1307_TDM_DL_32);
1460 break;
1461 default:
1462 dev_err(component->dev, "%s: not support TDM %d slot_width\n",
1463 __func__, slot_width);
1464 return -EINVAL;
1465 }
1466
1467 switch (slots) {
1468 case 4:
1469 regmap_update_bits(sma1307->regmap,
1470 SMA1307_A6_TDM2,
1471 SMA1307_TDM_N_SLOT_MASK,
1472 SMA1307_TDM_N_SLOT_4);
1473 break;
1474 case 8:
1475 regmap_update_bits(sma1307->regmap,
1476 SMA1307_A6_TDM2,
1477 SMA1307_TDM_N_SLOT_MASK,
1478 SMA1307_TDM_N_SLOT_8);
1479 break;
1480 default:
1481 dev_err(component->dev, "%s: not support TDM %d slots\n",
1482 __func__, slots);
1483 return -EINVAL;
1484 }
1485
1486 if (sma1307->tdm_slot0_rx < slots)
1487 regmap_update_bits(sma1307->regmap,
1488 SMA1307_A5_TDM1,
1489 SMA1307_TDM_SLOT0_RX_POS_MASK,
1490 sma1307->tdm_slot0_rx << 3);
1491 else
1492 dev_err(component->dev, "%s: Incorrect tdm-slot0-rx %d set\n",
1493 __func__, sma1307->tdm_slot0_rx);
1494
1495 if (sma1307->tdm_slot1_rx < slots)
1496 regmap_update_bits(sma1307->regmap,
1497 SMA1307_A5_TDM1,
1498 SMA1307_TDM_SLOT1_RX_POS_MASK,
1499 sma1307->tdm_slot1_rx);
1500 else
1501 dev_err(component->dev, "%s: Incorrect tdm-slot1-rx %d set\n",
1502 __func__, sma1307->tdm_slot1_rx);
1503
1504 if (sma1307->tdm_slot0_tx < slots)
1505 regmap_update_bits(sma1307->regmap,
1506 SMA1307_A6_TDM2,
1507 SMA1307_TDM_SLOT0_TX_POS_MASK,
1508 sma1307->tdm_slot0_tx << 3);
1509 else
1510 dev_err(component->dev, "%s: Incorrect tdm-slot0-tx %d set\n",
1511 __func__, sma1307->tdm_slot0_tx);
1512
1513 if (sma1307->tdm_slot1_tx < slots)
1514 regmap_update_bits(sma1307->regmap,
1515 SMA1307_A6_TDM2,
1516 SMA1307_TDM_SLOT1_TX_POS_MASK,
1517 sma1307->tdm_slot1_tx);
1518 else
1519 dev_err(component->dev, "%s: Incorrect tdm-slot1-tx %d set\n",
1520 __func__, sma1307->tdm_slot1_tx);
1521
1522 return 0;
1523 }
1524
sma1307_dai_mute_stream(struct snd_soc_dai * dai,int mute,int stream)1525 static int sma1307_dai_mute_stream(struct snd_soc_dai *dai, int mute,
1526 int stream)
1527 {
1528 struct snd_soc_component *component = dai->component;
1529 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1530
1531 if (stream == SNDRV_PCM_STREAM_CAPTURE)
1532 return 0;
1533 if (mute) {
1534 dev_dbg(component->dev, "%s: %s\n", __func__, "MUTE");
1535 regmap_update_bits(sma1307->regmap,
1536 SMA1307_0E_MUTE_VOL_CTRL,
1537 SMA1307_SPK_MUTE_MASK,
1538 SMA1307_SPK_MUTE);
1539 } else {
1540 if (!sma1307->force_mute_status) {
1541 dev_dbg(component->dev, "%s: %s\n", __func__,
1542 "UNMUTE");
1543 regmap_update_bits(sma1307->regmap,
1544 SMA1307_0E_MUTE_VOL_CTRL,
1545 SMA1307_SPK_MUTE_MASK,
1546 SMA1307_SPK_UNMUTE);
1547 } else {
1548 dev_dbg(sma1307->dev, "%s: FORCE MUTE!!!\n", __func__);
1549 }
1550 }
1551
1552 return 0;
1553 }
1554
1555 static const struct snd_soc_dai_ops sma1307_dai_ops_amp = {
1556 .hw_params = sma1307_dai_hw_params_amp,
1557 .set_fmt = sma1307_dai_set_fmt_amp,
1558 .set_sysclk = sma1307_dai_set_sysclk_amp,
1559 .set_tdm_slot = sma1307_dai_set_tdm_slot,
1560 .mute_stream = sma1307_dai_mute_stream,
1561 };
1562
1563 #define SMA1307_RATES_PLAYBACK SNDRV_PCM_RATE_8000_96000
1564 #define SMA1307_RATES_CAPTURE SNDRV_PCM_RATE_8000_48000
1565 #define SMA1307_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
1566 SNDRV_PCM_FMTBIT_S32_LE)
1567
1568 static struct snd_soc_dai_driver sma1307_dai[] = {
1569 {
1570 .name = "sma1307-amplifier",
1571 .id = 0,
1572 .playback = {
1573 .stream_name = "Playback",
1574 .channels_min = 1,
1575 .channels_max = 2,
1576 .rates = SMA1307_RATES_PLAYBACK,
1577 .formats = SMA1307_FORMATS,
1578 },
1579 .capture = {
1580 .stream_name = "Capture",
1581 .channels_min = 1,
1582 .channels_max = 2,
1583 .rates = SMA1307_RATES_CAPTURE,
1584 .formats = SMA1307_FORMATS,
1585 },
1586 .ops = &sma1307_dai_ops_amp,
1587 },
1588 };
1589
sma1307_check_fault_worker(struct work_struct * work)1590 static void sma1307_check_fault_worker(struct work_struct *work)
1591 {
1592 struct sma1307_priv *sma1307 =
1593 container_of(work, struct sma1307_priv, check_fault_work.work);
1594 unsigned int status1_val, status2_val;
1595 char *envp[3] = { NULL, NULL, NULL };
1596
1597 if (sma1307->tsdw_cnt)
1598 regmap_read(sma1307->regmap,
1599 SMA1307_0A_SPK_VOL, &sma1307->cur_vol);
1600 else
1601 regmap_read(sma1307->regmap,
1602 SMA1307_0A_SPK_VOL, &sma1307->init_vol);
1603
1604 regmap_read(sma1307->regmap, SMA1307_FA_STATUS1, &status1_val);
1605 regmap_read(sma1307->regmap, SMA1307_FB_STATUS2, &status2_val);
1606
1607 if (~status1_val & SMA1307_OT1_OK_STATUS) {
1608 dev_crit(sma1307->dev,
1609 "%s: OT1(Over Temperature Level 1)\n", __func__);
1610 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OT1");
1611 if (sma1307->sw_ot1_prot) {
1612 /* Volume control (Current Volume -3dB) */
1613 if ((sma1307->cur_vol + 6) <= 0xFA) {
1614 sma1307->cur_vol += 6;
1615 regmap_write(sma1307->regmap,
1616 SMA1307_0A_SPK_VOL,
1617 sma1307->cur_vol);
1618 envp[1] = kasprintf(GFP_KERNEL,
1619 "VOLUME=0x%02X", sma1307->cur_vol);
1620 }
1621 }
1622 sma1307->tsdw_cnt++;
1623 } else if (sma1307->tsdw_cnt) {
1624 regmap_write(sma1307->regmap,
1625 SMA1307_0A_SPK_VOL, sma1307->init_vol);
1626 sma1307->tsdw_cnt = 0;
1627 sma1307->cur_vol = sma1307->init_vol;
1628 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OT1_CLEAR");
1629 envp[1] = kasprintf(GFP_KERNEL,
1630 "VOLUME=0x%02X", sma1307->cur_vol);
1631 }
1632
1633 if (~status1_val & SMA1307_OT2_OK_STATUS) {
1634 dev_crit(sma1307->dev,
1635 "%s: OT2(Over Temperature Level 2)\n", __func__);
1636 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OT2");
1637 }
1638 if (status1_val & SMA1307_UVLO_STATUS) {
1639 dev_crit(sma1307->dev,
1640 "%s: UVLO(Under Voltage Lock Out)\n", __func__);
1641 envp[0] = kasprintf(GFP_KERNEL, "STATUS=UVLO");
1642 }
1643 if (status1_val & SMA1307_OVP_BST_STATUS) {
1644 dev_crit(sma1307->dev,
1645 "%s: OVP_BST(Over Voltage Protection)\n", __func__);
1646 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OVP_BST");
1647 }
1648 if (status2_val & SMA1307_OCP_SPK_STATUS) {
1649 dev_crit(sma1307->dev,
1650 "%s: OCP_SPK(Over Current Protect SPK)\n", __func__);
1651 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OCP_SPK");
1652 }
1653 if (status2_val & SMA1307_OCP_BST_STATUS) {
1654 dev_crit(sma1307->dev,
1655 "%s: OCP_BST(Over Current Protect Boost)\n", __func__);
1656 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OCP_BST");
1657 }
1658 if (status2_val & SMA1307_CLK_MON_STATUS) {
1659 dev_crit(sma1307->dev,
1660 "%s: CLK_FAULT(No clock input)\n", __func__);
1661 envp[0] = kasprintf(GFP_KERNEL, "STATUS=CLK_FAULT");
1662 }
1663
1664 if (envp[0] != NULL) {
1665 if (kobject_uevent_env(sma1307->kobj, KOBJ_CHANGE, envp))
1666 dev_err(sma1307->dev,
1667 "%s: Error sending uevent\n", __func__);
1668 kfree(envp[0]);
1669 kfree(envp[1]);
1670 }
1671
1672 if (sma1307->check_fault_status) {
1673 if (sma1307->check_fault_period > 0)
1674 queue_delayed_work(system_freezable_wq,
1675 &sma1307->check_fault_work,
1676 sma1307->check_fault_period * HZ);
1677 else
1678 queue_delayed_work(system_freezable_wq,
1679 &sma1307->check_fault_work,
1680 CHECK_PERIOD_TIME * HZ);
1681 }
1682 }
1683
sma1307_setting_loaded(struct sma1307_priv * sma1307,const char * file)1684 static void sma1307_setting_loaded(struct sma1307_priv *sma1307, const char *file)
1685 {
1686 const struct firmware *fw;
1687 int size, offset, num_mode;
1688 int ret;
1689
1690 ret = request_firmware(&fw, file, sma1307->dev);
1691
1692 if (ret) {
1693 dev_err(sma1307->dev, "%s: failed to read \"%s\": %pe\n",
1694 __func__, setting_file, ERR_PTR(ret));
1695 sma1307->set.status = false;
1696 return;
1697 } else if ((fw->size) < SMA1307_SETTING_HEADER_SIZE) {
1698 dev_err(sma1307->dev, "%s: Invalid file\n", __func__);
1699 release_firmware(fw);
1700 sma1307->set.status = false;
1701 return;
1702 }
1703
1704 int *data __free(kfree) = kzalloc(fw->size, GFP_KERNEL);
1705 if (!data) {
1706 release_firmware(fw);
1707 sma1307->set.status = false;
1708 return;
1709 }
1710 size = fw->size >> 2;
1711 memcpy(data, fw->data, fw->size);
1712
1713 release_firmware(fw);
1714
1715 /* HEADER */
1716 sma1307->set.header_size = SMA1307_SETTING_HEADER_SIZE;
1717 sma1307->set.checksum = data[sma1307->set.header_size - 2];
1718 sma1307->set.num_mode = data[sma1307->set.header_size - 1];
1719 num_mode = sma1307->set.num_mode;
1720 sma1307->set.header = devm_kmalloc_array(sma1307->dev,
1721 sma1307->set.header_size,
1722 sizeof(int),
1723 GFP_KERNEL);
1724 if (!sma1307->set.header) {
1725 sma1307->set.status = false;
1726 return;
1727 }
1728
1729 memcpy(sma1307->set.header, data,
1730 sma1307->set.header_size * sizeof(int));
1731
1732 if ((sma1307->set.checksum >> 8) != SMA1307_SETTING_CHECKSUM) {
1733 dev_err(sma1307->dev, "%s: checksum failed \"%s\"\n",
1734 __func__, setting_file);
1735 sma1307->set.status = false;
1736 return;
1737 }
1738
1739 /* DEFAULT */
1740 sma1307->set.def_size = SMA1307_SETTING_DEFAULT_SIZE;
1741 sma1307->set.def
1742 = devm_kzalloc(sma1307->dev,
1743 sma1307->set.def_size * sizeof(int), GFP_KERNEL);
1744 if (!sma1307->set.def) {
1745 sma1307->set.status = false;
1746 return;
1747 }
1748
1749 memcpy(sma1307->set.def,
1750 &data[sma1307->set.header_size],
1751 sma1307->set.def_size * sizeof(int));
1752
1753 /* MODE */
1754 offset = sma1307->set.header_size + sma1307->set.def_size;
1755 sma1307->set.mode_size = DIV_ROUND_CLOSEST(size - offset, num_mode + 1);
1756 for (int i = 0; i < num_mode; i++) {
1757 sma1307->set.mode_set[i]
1758 = devm_kzalloc(sma1307->dev,
1759 sma1307->set.mode_size * 2 * sizeof(int),
1760 GFP_KERNEL);
1761 if (!sma1307->set.mode_set[i]) {
1762 for (int j = 0; j < i; j++) {
1763 devm_kfree(sma1307->dev, sma1307->set.mode_set[j]);
1764 sma1307->set.mode_set[j] = NULL;
1765 }
1766 sma1307->set.status = false;
1767 return;
1768 }
1769
1770 for (int j = 0; j < sma1307->set.mode_size; j++) {
1771 sma1307->set.mode_set[i][2 * j]
1772 = data[offset + ((num_mode + 1) * j)];
1773 sma1307->set.mode_set[i][2 * j + 1]
1774 = data[offset + ((num_mode + 1) * j + i + 1)];
1775 }
1776 }
1777
1778 sma1307->set.status = true;
1779
1780 }
1781
sma1307_reset(struct snd_soc_component * component)1782 static void sma1307_reset(struct snd_soc_component *component)
1783 {
1784 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1785 unsigned int status = 0;
1786
1787 regmap_read(sma1307->regmap, SMA1307_FF_DEVICE_INDEX, &status);
1788
1789 sma1307->rev_num = status & SMA1307_REV_NUM_STATUS;
1790 dev_dbg(component->dev, "%s: SMA1307 Revision %d\n",
1791 __func__, sma1307->rev_num);
1792 regmap_read(sma1307->regmap, SMA1307_99_OTP_TRM2, &sma1307->otp_trm2);
1793 regmap_read(sma1307->regmap, SMA1307_9A_OTP_TRM3, &sma1307->otp_trm3);
1794
1795 if ((sma1307->otp_trm2 & SMA1307_OTP_STAT_MASK) != SMA1307_OTP_STAT_1)
1796 dev_warn(component->dev, "%s: SMA1307 OTP Status Fail\n",
1797 __func__);
1798
1799 /* Register Initial Value Setting */
1800 sma1307_setting_loaded(sma1307, setting_file);
1801 if (sma1307->set.status)
1802 sma1307_set_binary(component);
1803 else
1804 sma1307_set_default(component);
1805
1806 regmap_update_bits(sma1307->regmap,
1807 SMA1307_93_INT_CTRL,
1808 SMA1307_DIS_INT_MASK, SMA1307_HIGH_Z_INT);
1809 regmap_write(sma1307->regmap, SMA1307_0A_SPK_VOL, sma1307->init_vol);
1810 }
1811
sma1307_set_binary(struct snd_soc_component * component)1812 static void sma1307_set_binary(struct snd_soc_component *component)
1813 {
1814 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1815 int i = 0, mode = 0;
1816
1817 for (i = 0; i < (sma1307->set.def_size); i++) {
1818 if (sma1307_writeable_register(sma1307->dev, i)
1819 && ((i < SMA1307_97_OTP_TRM0)
1820 || (i > SMA1307_9A_OTP_TRM3))) {
1821 regmap_write(sma1307->regmap, i, sma1307->set.def[i]);
1822
1823 }
1824 }
1825 for (i = 0; i < (sma1307->set.mode_size); i++) {
1826 if (sma1307_writeable_register(sma1307->dev, i)
1827 && ((i < SMA1307_97_OTP_TRM0)
1828 || (i > SMA1307_9A_OTP_TRM3))) {
1829 mode = sma1307->binary_mode;
1830 regmap_write(sma1307->regmap,
1831 sma1307->set.mode_set[mode][2 * i],
1832 sma1307->set.mode_set[mode][2 * i +
1833 1]);
1834 }
1835 }
1836 }
1837
sma1307_set_default(struct snd_soc_component * component)1838 static void sma1307_set_default(struct snd_soc_component *component)
1839 {
1840 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component);
1841 int i = 0;
1842
1843 for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1307_reg_def); i++)
1844 regmap_write(sma1307->regmap,
1845 sma1307_reg_def[i].reg,
1846 sma1307_reg_def[i].def);
1847
1848 if (!strcmp(sma1307->name, DEVICE_NAME_SMA1307AQ))
1849 sma1307->data->init(sma1307->regmap);
1850 }
1851
sma1307_probe(struct snd_soc_component * component)1852 static int sma1307_probe(struct snd_soc_component *component)
1853 {
1854 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1855
1856 snd_soc_dapm_sync(dapm);
1857
1858 sma1307_amp_component = component;
1859
1860 snd_soc_add_component_controls(component, sma1307_binary_mode_control,
1861 ARRAY_SIZE(sma1307_binary_mode_control));
1862 sma1307_reset(component);
1863
1864 return 0;
1865 }
1866
1867 static const struct snd_soc_component_driver sma1307_component = {
1868 .probe = sma1307_probe,
1869 .controls = sma1307_snd_controls,
1870 .num_controls = ARRAY_SIZE(sma1307_snd_controls),
1871 .dapm_widgets = sma1307_dapm_widgets,
1872 .num_dapm_widgets = ARRAY_SIZE(sma1307_dapm_widgets),
1873 .dapm_routes = sma1307_audio_map,
1874 .num_dapm_routes = ARRAY_SIZE(sma1307_audio_map),
1875 };
1876
1877 static const struct regmap_config sma_i2c_regmap = {
1878 .reg_bits = 8,
1879 .val_bits = 8,
1880
1881 .max_register = SMA1307_FF_DEVICE_INDEX,
1882 .readable_reg = sma1307_readable_register,
1883 .writeable_reg = sma1307_writeable_register,
1884 .volatile_reg = sma1307_volatile_register,
1885
1886 .reg_defaults = sma1307_reg_def,
1887 .num_reg_defaults = ARRAY_SIZE(sma1307_reg_def),
1888 };
1889
sma1307aq_init(struct regmap * regmap)1890 static void sma1307aq_init(struct regmap *regmap)
1891 {
1892 /* Guidelines for driving 4ohm load */
1893 /* Brown Out Protection */
1894 regmap_write(regmap, SMA1307_02_BROWN_OUT_PROT1, 0x62);
1895 regmap_write(regmap, SMA1307_03_BROWN_OUT_PROT2, 0x5D);
1896 regmap_write(regmap, SMA1307_04_BROWN_OUT_PROT3, 0x57);
1897 regmap_write(regmap, SMA1307_05_BROWN_OUT_PROT8, 0x54);
1898 regmap_write(regmap, SMA1307_06_BROWN_OUT_PROT9, 0x51);
1899 regmap_write(regmap,
1900 SMA1307_07_BROWN_OUT_PROT10, 0x4D);
1901 regmap_write(regmap,
1902 SMA1307_08_BROWN_OUT_PROT11, 0x4B);
1903 regmap_write(regmap, SMA1307_27_BROWN_OUT_PROT4, 0x3C);
1904 regmap_write(regmap, SMA1307_28_BROWN_OUT_PROT5, 0x5B);
1905 regmap_write(regmap,
1906 SMA1307_29_BROWN_OUT_PROT12, 0x78);
1907 regmap_write(regmap,
1908 SMA1307_2A_BROWN_OUT_PROT13, 0x96);
1909 regmap_write(regmap,
1910 SMA1307_2B_BROWN_OUT_PROT14, 0xB4);
1911 regmap_write(regmap,
1912 SMA1307_2C_BROWN_OUT_PROT15, 0xD3);
1913 /* FDPEC Gain */
1914 regmap_write(regmap, SMA1307_35_FDPEC_CTRL0, 0x16);
1915 /* FLT Vdd */
1916 regmap_write(regmap, SMA1307_92_FDPEC_CTRL1, 0xA0);
1917 /* Boost Max */
1918 regmap_write(regmap, SMA1307_AB_BOOST_CTRL4, 0x0F);
1919 }
1920
1921 static const struct sma1307_data sma1307aq_data = {
1922 .name = DEVICE_NAME_SMA1307AQ,
1923 .init = sma1307aq_init,
1924 };
1925
sma1307_i2c_probe(struct i2c_client * client)1926 static int sma1307_i2c_probe(struct i2c_client *client)
1927 {
1928 struct sma1307_priv *sma1307;
1929 const struct sma1307_data *data;
1930 int ret = 0;
1931 unsigned int device_info;
1932
1933 sma1307 = devm_kzalloc(&client->dev,
1934 sizeof(*sma1307), GFP_KERNEL);
1935 if (!sma1307)
1936 return -ENOMEM;
1937
1938 sma1307->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap);
1939 if (IS_ERR(sma1307->regmap)) {
1940 return dev_err_probe(&client->dev, PTR_ERR(sma1307->regmap),
1941 "%s: failed to allocate register map\n", __func__);
1942 }
1943
1944 data = device_get_match_data(&client->dev);
1945 if (!data)
1946 return -ENODEV;
1947
1948 sma1307->data = data;
1949
1950 /* set initial value as normal AMP IC status */
1951 sma1307->name = client->name;
1952 sma1307->format = SND_SOC_DAIFMT_I2S;
1953 sma1307->sys_clk_id = SMA1307_PLL_CLKIN_BCLK;
1954 sma1307->num_of_pll_matches = ARRAY_SIZE(sma1307_pll_matches);
1955
1956 sma1307->check_fault_period = CHECK_PERIOD_TIME;
1957 sma1307->check_fault_status = true;
1958 sma1307->init_vol = 0x32;
1959 sma1307->cur_vol = sma1307->init_vol;
1960 sma1307->sw_ot1_prot = true;
1961
1962 mutex_init(&sma1307->default_lock);
1963
1964 INIT_DELAYED_WORK(&sma1307->check_fault_work,
1965 sma1307_check_fault_worker);
1966
1967 sma1307->dev = &client->dev;
1968 sma1307->kobj = &client->dev.kobj;
1969
1970 i2c_set_clientdata(client, sma1307);
1971
1972 sma1307->pll_matches = sma1307_pll_matches;
1973
1974 regmap_read(sma1307->regmap,
1975 SMA1307_FF_DEVICE_INDEX, &device_info);
1976
1977 if ((device_info & 0xF8) != SMA1307_DEVICE_ID) {
1978 dev_err(&client->dev,
1979 "%s: device initialization error (0x%02X)",
1980 __func__, device_info);
1981 return -ENODEV;
1982 }
1983 dev_dbg(&client->dev, "%s: chip version 0x%02X\n",
1984 __func__, device_info);
1985
1986 i2c_set_clientdata(client, sma1307);
1987
1988 ret = devm_snd_soc_register_component(&client->dev,
1989 &sma1307_component, sma1307_dai,
1990 1);
1991
1992 if (ret) {
1993 dev_err(&client->dev, "%s: failed to register component\n",
1994 __func__);
1995
1996 return ret;
1997 }
1998
1999 return ret;
2000 }
2001
sma1307_i2c_remove(struct i2c_client * client)2002 static void sma1307_i2c_remove(struct i2c_client *client)
2003 {
2004 struct sma1307_priv *sma1307 =
2005 (struct sma1307_priv *)i2c_get_clientdata(client);
2006
2007 cancel_delayed_work_sync(&sma1307->check_fault_work);
2008 }
2009
2010 static const struct i2c_device_id sma1307_i2c_id[] = {
2011 { "sma1307a" },
2012 { "sma1307aq" },
2013 { }
2014 };
2015
2016 MODULE_DEVICE_TABLE(i2c, sma1307_i2c_id);
2017
2018 static const struct of_device_id sma1307_of_match[] = {
2019 {
2020 .compatible = "irondevice,sma1307a",
2021 },
2022 {
2023 .compatible = "irondevice,sma1307aq",
2024 .data = &sma1307aq_data //AEC-Q100 Qualificated
2025 },
2026 { }
2027 };
2028
2029 MODULE_DEVICE_TABLE(of, sma1307_of_match);
2030
2031 static struct i2c_driver sma1307_i2c_driver = {
2032 .driver = {
2033 .name = "sma1307",
2034 .of_match_table = sma1307_of_match,
2035 },
2036 .probe = sma1307_i2c_probe,
2037 .remove = sma1307_i2c_remove,
2038 .id_table = sma1307_i2c_id,
2039 };
2040
2041 module_i2c_driver(sma1307_i2c_driver);
2042
2043 MODULE_DESCRIPTION("ALSA SoC SMA1307 driver");
2044 MODULE_AUTHOR("Gyuhwa Park, <gyuhwa.park@irondevice.com>");
2045 MODULE_AUTHOR("KS Jo, <kiseok.jo@irondevice.com>");
2046 MODULE_LICENSE("GPL");
2047