1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <dt-bindings/interconnect/qcom,sm8250.h> 14 15 #include "bcm-voter.h" 16 #include "icc-rpmh.h" 17 18 static struct qcom_icc_node qhm_a1noc_cfg; 19 static struct qcom_icc_node qhm_qspi; 20 static struct qcom_icc_node qhm_qup1; 21 static struct qcom_icc_node qhm_qup2; 22 static struct qcom_icc_node qhm_tsif; 23 static struct qcom_icc_node xm_pcie3_modem; 24 static struct qcom_icc_node xm_sdc4; 25 static struct qcom_icc_node xm_ufs_mem; 26 static struct qcom_icc_node xm_usb3_0; 27 static struct qcom_icc_node xm_usb3_1; 28 static struct qcom_icc_node qhm_a2noc_cfg; 29 static struct qcom_icc_node qhm_qdss_bam; 30 static struct qcom_icc_node qhm_qup0; 31 static struct qcom_icc_node qnm_cnoc; 32 static struct qcom_icc_node qxm_crypto; 33 static struct qcom_icc_node qxm_ipa; 34 static struct qcom_icc_node xm_pcie3_0; 35 static struct qcom_icc_node xm_pcie3_1; 36 static struct qcom_icc_node xm_qdss_etr; 37 static struct qcom_icc_node xm_sdc2; 38 static struct qcom_icc_node xm_ufs_card; 39 static struct qcom_icc_node qnm_npu; 40 static struct qcom_icc_node qnm_snoc; 41 static struct qcom_icc_node xm_qdss_dap; 42 static struct qcom_icc_node qhm_cnoc_dc_noc; 43 static struct qcom_icc_node alm_gpu_tcu; 44 static struct qcom_icc_node alm_sys_tcu; 45 static struct qcom_icc_node chm_apps; 46 static struct qcom_icc_node qhm_gemnoc_cfg; 47 static struct qcom_icc_node qnm_cmpnoc; 48 static struct qcom_icc_node qnm_gpu; 49 static struct qcom_icc_node qnm_mnoc_hf; 50 static struct qcom_icc_node qnm_mnoc_sf; 51 static struct qcom_icc_node qnm_pcie; 52 static struct qcom_icc_node qnm_snoc_gc; 53 static struct qcom_icc_node qnm_snoc_sf; 54 static struct qcom_icc_node llcc_mc; 55 static struct qcom_icc_node qhm_mnoc_cfg; 56 static struct qcom_icc_node qnm_camnoc_hf; 57 static struct qcom_icc_node qnm_camnoc_icp; 58 static struct qcom_icc_node qnm_camnoc_sf; 59 static struct qcom_icc_node qnm_video0; 60 static struct qcom_icc_node qnm_video1; 61 static struct qcom_icc_node qnm_video_cvp; 62 static struct qcom_icc_node qxm_mdp0; 63 static struct qcom_icc_node qxm_mdp1; 64 static struct qcom_icc_node qxm_rot; 65 static struct qcom_icc_node amm_npu_sys; 66 static struct qcom_icc_node amm_npu_sys_cdp_w; 67 static struct qcom_icc_node qhm_cfg; 68 static struct qcom_icc_node qhm_snoc_cfg; 69 static struct qcom_icc_node qnm_aggre1_noc; 70 static struct qcom_icc_node qnm_aggre2_noc; 71 static struct qcom_icc_node qnm_gemnoc; 72 static struct qcom_icc_node qnm_gemnoc_pcie; 73 static struct qcom_icc_node qxm_pimem; 74 static struct qcom_icc_node xm_gic; 75 static struct qcom_icc_node qns_a1noc_snoc; 76 static struct qcom_icc_node qns_pcie_modem_mem_noc; 77 static struct qcom_icc_node srvc_aggre1_noc; 78 static struct qcom_icc_node qns_a2noc_snoc; 79 static struct qcom_icc_node qns_pcie_mem_noc; 80 static struct qcom_icc_node srvc_aggre2_noc; 81 static struct qcom_icc_node qns_cdsp_mem_noc; 82 static struct qcom_icc_node qhs_a1_noc_cfg; 83 static struct qcom_icc_node qhs_a2_noc_cfg; 84 static struct qcom_icc_node qhs_ahb2phy0; 85 static struct qcom_icc_node qhs_ahb2phy1; 86 static struct qcom_icc_node qhs_aoss; 87 static struct qcom_icc_node qhs_camera_cfg; 88 static struct qcom_icc_node qhs_clk_ctl; 89 static struct qcom_icc_node qhs_compute_dsp; 90 static struct qcom_icc_node qhs_cpr_cx; 91 static struct qcom_icc_node qhs_cpr_mmcx; 92 static struct qcom_icc_node qhs_cpr_mx; 93 static struct qcom_icc_node qhs_crypto0_cfg; 94 static struct qcom_icc_node qhs_cx_rdpm; 95 static struct qcom_icc_node qhs_dcc_cfg; 96 static struct qcom_icc_node qhs_ddrss_cfg; 97 static struct qcom_icc_node qhs_display_cfg; 98 static struct qcom_icc_node qhs_gpuss_cfg; 99 static struct qcom_icc_node qhs_imem_cfg; 100 static struct qcom_icc_node qhs_ipa; 101 static struct qcom_icc_node qhs_ipc_router; 102 static struct qcom_icc_node qhs_lpass_cfg; 103 static struct qcom_icc_node qhs_mnoc_cfg; 104 static struct qcom_icc_node qhs_npu_cfg; 105 static struct qcom_icc_node qhs_pcie0_cfg; 106 static struct qcom_icc_node qhs_pcie1_cfg; 107 static struct qcom_icc_node qhs_pcie_modem_cfg; 108 static struct qcom_icc_node qhs_pdm; 109 static struct qcom_icc_node qhs_pimem_cfg; 110 static struct qcom_icc_node qhs_prng; 111 static struct qcom_icc_node qhs_qdss_cfg; 112 static struct qcom_icc_node qhs_qspi; 113 static struct qcom_icc_node qhs_qup0; 114 static struct qcom_icc_node qhs_qup1; 115 static struct qcom_icc_node qhs_qup2; 116 static struct qcom_icc_node qhs_sdc2; 117 static struct qcom_icc_node qhs_sdc4; 118 static struct qcom_icc_node qhs_snoc_cfg; 119 static struct qcom_icc_node qhs_tcsr; 120 static struct qcom_icc_node qhs_tlmm0; 121 static struct qcom_icc_node qhs_tlmm1; 122 static struct qcom_icc_node qhs_tlmm2; 123 static struct qcom_icc_node qhs_tsif; 124 static struct qcom_icc_node qhs_ufs_card_cfg; 125 static struct qcom_icc_node qhs_ufs_mem_cfg; 126 static struct qcom_icc_node qhs_usb3_0; 127 static struct qcom_icc_node qhs_usb3_1; 128 static struct qcom_icc_node qhs_venus_cfg; 129 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 130 static struct qcom_icc_node qns_cnoc_a2noc; 131 static struct qcom_icc_node srvc_cnoc; 132 static struct qcom_icc_node qhs_llcc; 133 static struct qcom_icc_node qhs_memnoc; 134 static struct qcom_icc_node qns_gem_noc_snoc; 135 static struct qcom_icc_node qns_llcc; 136 static struct qcom_icc_node qns_sys_pcie; 137 static struct qcom_icc_node srvc_even_gemnoc; 138 static struct qcom_icc_node srvc_odd_gemnoc; 139 static struct qcom_icc_node srvc_sys_gemnoc; 140 static struct qcom_icc_node ebi; 141 static struct qcom_icc_node qns_mem_noc_hf; 142 static struct qcom_icc_node qns_mem_noc_sf; 143 static struct qcom_icc_node srvc_mnoc; 144 static struct qcom_icc_node qhs_cal_dp0; 145 static struct qcom_icc_node qhs_cal_dp1; 146 static struct qcom_icc_node qhs_cp; 147 static struct qcom_icc_node qhs_dma_bwmon; 148 static struct qcom_icc_node qhs_dpm; 149 static struct qcom_icc_node qhs_isense; 150 static struct qcom_icc_node qhs_llm; 151 static struct qcom_icc_node qhs_tcm; 152 static struct qcom_icc_node qns_npu_sys; 153 static struct qcom_icc_node srvc_noc; 154 static struct qcom_icc_node qhs_apss; 155 static struct qcom_icc_node qns_cnoc; 156 static struct qcom_icc_node qns_gemnoc_gc; 157 static struct qcom_icc_node qns_gemnoc_sf; 158 static struct qcom_icc_node qxs_imem; 159 static struct qcom_icc_node qxs_pimem; 160 static struct qcom_icc_node srvc_snoc; 161 static struct qcom_icc_node xs_pcie_0; 162 static struct qcom_icc_node xs_pcie_1; 163 static struct qcom_icc_node xs_pcie_modem; 164 static struct qcom_icc_node xs_qdss_stm; 165 static struct qcom_icc_node xs_sys_tcu_cfg; 166 static struct qcom_icc_node qup0_core_master; 167 static struct qcom_icc_node qup1_core_master; 168 static struct qcom_icc_node qup2_core_master; 169 static struct qcom_icc_node qup0_core_slave; 170 static struct qcom_icc_node qup1_core_slave; 171 static struct qcom_icc_node qup2_core_slave; 172 173 static struct qcom_icc_node qhm_a1noc_cfg = { 174 .name = "qhm_a1noc_cfg", 175 .channels = 1, 176 .buswidth = 4, 177 .num_links = 1, 178 .link_nodes = { &srvc_aggre1_noc }, 179 }; 180 181 static struct qcom_icc_node qhm_qspi = { 182 .name = "qhm_qspi", 183 .channels = 1, 184 .buswidth = 4, 185 .num_links = 1, 186 .link_nodes = { &qns_a1noc_snoc }, 187 }; 188 189 static struct qcom_icc_node qhm_qup1 = { 190 .name = "qhm_qup1", 191 .channels = 1, 192 .buswidth = 4, 193 .num_links = 1, 194 .link_nodes = { &qns_a1noc_snoc }, 195 }; 196 197 static struct qcom_icc_node qhm_qup2 = { 198 .name = "qhm_qup2", 199 .channels = 1, 200 .buswidth = 4, 201 .num_links = 1, 202 .link_nodes = { &qns_a1noc_snoc }, 203 }; 204 205 static struct qcom_icc_node qhm_tsif = { 206 .name = "qhm_tsif", 207 .channels = 1, 208 .buswidth = 4, 209 .num_links = 1, 210 .link_nodes = { &qns_a1noc_snoc }, 211 }; 212 213 static struct qcom_icc_node xm_pcie3_modem = { 214 .name = "xm_pcie3_modem", 215 .channels = 1, 216 .buswidth = 8, 217 .num_links = 1, 218 .link_nodes = { &qns_pcie_modem_mem_noc }, 219 }; 220 221 static struct qcom_icc_node xm_sdc4 = { 222 .name = "xm_sdc4", 223 .channels = 1, 224 .buswidth = 8, 225 .num_links = 1, 226 .link_nodes = { &qns_a1noc_snoc }, 227 }; 228 229 static struct qcom_icc_node xm_ufs_mem = { 230 .name = "xm_ufs_mem", 231 .channels = 1, 232 .buswidth = 8, 233 .num_links = 1, 234 .link_nodes = { &qns_a1noc_snoc }, 235 }; 236 237 static struct qcom_icc_node xm_usb3_0 = { 238 .name = "xm_usb3_0", 239 .channels = 1, 240 .buswidth = 8, 241 .num_links = 1, 242 .link_nodes = { &qns_a1noc_snoc }, 243 }; 244 245 static struct qcom_icc_node xm_usb3_1 = { 246 .name = "xm_usb3_1", 247 .channels = 1, 248 .buswidth = 8, 249 .num_links = 1, 250 .link_nodes = { &qns_a1noc_snoc }, 251 }; 252 253 static struct qcom_icc_node qhm_a2noc_cfg = { 254 .name = "qhm_a2noc_cfg", 255 .channels = 1, 256 .buswidth = 4, 257 .num_links = 1, 258 .link_nodes = { &srvc_aggre2_noc }, 259 }; 260 261 static struct qcom_icc_node qhm_qdss_bam = { 262 .name = "qhm_qdss_bam", 263 .channels = 1, 264 .buswidth = 4, 265 .num_links = 1, 266 .link_nodes = { &qns_a2noc_snoc }, 267 }; 268 269 static struct qcom_icc_node qhm_qup0 = { 270 .name = "qhm_qup0", 271 .channels = 1, 272 .buswidth = 4, 273 .num_links = 1, 274 .link_nodes = { &qns_a2noc_snoc }, 275 }; 276 277 static struct qcom_icc_node qnm_cnoc = { 278 .name = "qnm_cnoc", 279 .channels = 1, 280 .buswidth = 8, 281 .num_links = 1, 282 .link_nodes = { &qns_a2noc_snoc }, 283 }; 284 285 static struct qcom_icc_node qxm_crypto = { 286 .name = "qxm_crypto", 287 .channels = 1, 288 .buswidth = 8, 289 .num_links = 1, 290 .link_nodes = { &qns_a2noc_snoc }, 291 }; 292 293 static struct qcom_icc_node qxm_ipa = { 294 .name = "qxm_ipa", 295 .channels = 1, 296 .buswidth = 8, 297 .num_links = 1, 298 .link_nodes = { &qns_a2noc_snoc }, 299 }; 300 301 static struct qcom_icc_node xm_pcie3_0 = { 302 .name = "xm_pcie3_0", 303 .channels = 1, 304 .buswidth = 8, 305 .num_links = 1, 306 .link_nodes = { &qns_pcie_mem_noc }, 307 }; 308 309 static struct qcom_icc_node xm_pcie3_1 = { 310 .name = "xm_pcie3_1", 311 .channels = 1, 312 .buswidth = 8, 313 .num_links = 1, 314 .link_nodes = { &qns_pcie_mem_noc }, 315 }; 316 317 static struct qcom_icc_node xm_qdss_etr = { 318 .name = "xm_qdss_etr", 319 .channels = 1, 320 .buswidth = 8, 321 .num_links = 1, 322 .link_nodes = { &qns_a2noc_snoc }, 323 }; 324 325 static struct qcom_icc_node xm_sdc2 = { 326 .name = "xm_sdc2", 327 .channels = 1, 328 .buswidth = 8, 329 .num_links = 1, 330 .link_nodes = { &qns_a2noc_snoc }, 331 }; 332 333 static struct qcom_icc_node xm_ufs_card = { 334 .name = "xm_ufs_card", 335 .channels = 1, 336 .buswidth = 8, 337 .num_links = 1, 338 .link_nodes = { &qns_a2noc_snoc }, 339 }; 340 341 static struct qcom_icc_node qnm_npu = { 342 .name = "qnm_npu", 343 .channels = 2, 344 .buswidth = 32, 345 .num_links = 1, 346 .link_nodes = { &qns_cdsp_mem_noc }, 347 }; 348 349 static struct qcom_icc_node qnm_snoc = { 350 .name = "qnm_snoc", 351 .channels = 1, 352 .buswidth = 8, 353 .num_links = 49, 354 .link_nodes = { &qhs_compute_dsp, 355 &qhs_camera_cfg, 356 &qhs_tlmm1, 357 &qhs_tlmm0, 358 &qhs_sdc4, 359 &qhs_tlmm2, 360 &qhs_sdc2, 361 &qhs_mnoc_cfg, 362 &qhs_ufs_mem_cfg, 363 &qhs_snoc_cfg, 364 &qhs_pdm, 365 &qhs_cx_rdpm, 366 &qhs_pcie1_cfg, 367 &qhs_a2_noc_cfg, 368 &qhs_qdss_cfg, 369 &qhs_display_cfg, 370 &qhs_pcie_modem_cfg, 371 &qhs_tcsr, 372 &qhs_dcc_cfg, 373 &qhs_ddrss_cfg, 374 &qhs_ipc_router, 375 &qhs_pcie0_cfg, 376 &qhs_cpr_mmcx, 377 &qhs_npu_cfg, 378 &qhs_ahb2phy0, 379 &qhs_ahb2phy1, 380 &qhs_gpuss_cfg, 381 &qhs_venus_cfg, 382 &qhs_tsif, 383 &qhs_ipa, 384 &qhs_imem_cfg, 385 &qhs_usb3_0, 386 &srvc_cnoc, 387 &qhs_ufs_card_cfg, 388 &qhs_usb3_1, 389 &qhs_lpass_cfg, 390 &qhs_cpr_cx, 391 &qhs_a1_noc_cfg, 392 &qhs_aoss, 393 &qhs_prng, 394 &qhs_vsense_ctrl_cfg, 395 &qhs_qspi, 396 &qhs_crypto0_cfg, 397 &qhs_pimem_cfg, 398 &qhs_cpr_mx, 399 &qhs_qup0, 400 &qhs_qup1, 401 &qhs_qup2, 402 &qhs_clk_ctl }, 403 }; 404 405 static struct qcom_icc_node xm_qdss_dap = { 406 .name = "xm_qdss_dap", 407 .channels = 1, 408 .buswidth = 8, 409 .num_links = 50, 410 .link_nodes = { &qhs_compute_dsp, 411 &qhs_camera_cfg, 412 &qhs_tlmm1, 413 &qhs_tlmm0, 414 &qhs_sdc4, 415 &qhs_tlmm2, 416 &qhs_sdc2, 417 &qhs_mnoc_cfg, 418 &qhs_ufs_mem_cfg, 419 &qhs_snoc_cfg, 420 &qhs_pdm, 421 &qhs_cx_rdpm, 422 &qhs_pcie1_cfg, 423 &qhs_a2_noc_cfg, 424 &qhs_qdss_cfg, 425 &qhs_display_cfg, 426 &qhs_pcie_modem_cfg, 427 &qhs_tcsr, 428 &qhs_dcc_cfg, 429 &qhs_ddrss_cfg, 430 &qhs_ipc_router, 431 &qns_cnoc_a2noc, 432 &qhs_pcie0_cfg, 433 &qhs_cpr_mmcx, 434 &qhs_npu_cfg, 435 &qhs_ahb2phy0, 436 &qhs_ahb2phy1, 437 &qhs_gpuss_cfg, 438 &qhs_venus_cfg, 439 &qhs_tsif, 440 &qhs_ipa, 441 &qhs_imem_cfg, 442 &qhs_usb3_0, 443 &srvc_cnoc, 444 &qhs_ufs_card_cfg, 445 &qhs_usb3_1, 446 &qhs_lpass_cfg, 447 &qhs_cpr_cx, 448 &qhs_a1_noc_cfg, 449 &qhs_aoss, 450 &qhs_prng, 451 &qhs_vsense_ctrl_cfg, 452 &qhs_qspi, 453 &qhs_crypto0_cfg, 454 &qhs_pimem_cfg, 455 &qhs_cpr_mx, 456 &qhs_qup0, 457 &qhs_qup1, 458 &qhs_qup2, 459 &qhs_clk_ctl }, 460 }; 461 462 static struct qcom_icc_node qhm_cnoc_dc_noc = { 463 .name = "qhm_cnoc_dc_noc", 464 .channels = 1, 465 .buswidth = 4, 466 .num_links = 2, 467 .link_nodes = { &qhs_memnoc, 468 &qhs_llcc }, 469 }; 470 471 static struct qcom_icc_node alm_gpu_tcu = { 472 .name = "alm_gpu_tcu", 473 .channels = 1, 474 .buswidth = 8, 475 .num_links = 2, 476 .link_nodes = { &qns_llcc, 477 &qns_gem_noc_snoc }, 478 }; 479 480 static struct qcom_icc_node alm_sys_tcu = { 481 .name = "alm_sys_tcu", 482 .channels = 1, 483 .buswidth = 8, 484 .num_links = 2, 485 .link_nodes = { &qns_llcc, 486 &qns_gem_noc_snoc }, 487 }; 488 489 static struct qcom_icc_node chm_apps = { 490 .name = "chm_apps", 491 .channels = 2, 492 .buswidth = 32, 493 .num_links = 3, 494 .link_nodes = { &qns_llcc, 495 &qns_gem_noc_snoc, 496 &qns_sys_pcie }, 497 }; 498 499 static struct qcom_icc_node qhm_gemnoc_cfg = { 500 .name = "qhm_gemnoc_cfg", 501 .channels = 1, 502 .buswidth = 4, 503 .num_links = 3, 504 .link_nodes = { &srvc_odd_gemnoc, 505 &srvc_even_gemnoc, 506 &srvc_sys_gemnoc }, 507 }; 508 509 static struct qcom_icc_node qnm_cmpnoc = { 510 .name = "qnm_cmpnoc", 511 .channels = 2, 512 .buswidth = 32, 513 .num_links = 2, 514 .link_nodes = { &qns_llcc, 515 &qns_gem_noc_snoc }, 516 }; 517 518 static struct qcom_icc_node qnm_gpu = { 519 .name = "qnm_gpu", 520 .channels = 2, 521 .buswidth = 32, 522 .num_links = 2, 523 .link_nodes = { &qns_llcc, 524 &qns_gem_noc_snoc }, 525 }; 526 527 static struct qcom_icc_node qnm_mnoc_hf = { 528 .name = "qnm_mnoc_hf", 529 .channels = 2, 530 .buswidth = 32, 531 .num_links = 1, 532 .link_nodes = { &qns_llcc }, 533 }; 534 535 static struct qcom_icc_node qnm_mnoc_sf = { 536 .name = "qnm_mnoc_sf", 537 .channels = 2, 538 .buswidth = 32, 539 .num_links = 2, 540 .link_nodes = { &qns_llcc, 541 &qns_gem_noc_snoc }, 542 }; 543 544 static struct qcom_icc_node qnm_pcie = { 545 .name = "qnm_pcie", 546 .channels = 1, 547 .buswidth = 16, 548 .num_links = 2, 549 .link_nodes = { &qns_llcc, 550 &qns_gem_noc_snoc }, 551 }; 552 553 static struct qcom_icc_node qnm_snoc_gc = { 554 .name = "qnm_snoc_gc", 555 .channels = 1, 556 .buswidth = 8, 557 .num_links = 1, 558 .link_nodes = { &qns_llcc }, 559 }; 560 561 static struct qcom_icc_node qnm_snoc_sf = { 562 .name = "qnm_snoc_sf", 563 .channels = 1, 564 .buswidth = 16, 565 .num_links = 3, 566 .link_nodes = { &qns_llcc, 567 &qns_gem_noc_snoc, 568 &qns_sys_pcie }, 569 }; 570 571 static struct qcom_icc_node llcc_mc = { 572 .name = "llcc_mc", 573 .channels = 4, 574 .buswidth = 4, 575 .num_links = 1, 576 .link_nodes = { &ebi }, 577 }; 578 579 static struct qcom_icc_node qhm_mnoc_cfg = { 580 .name = "qhm_mnoc_cfg", 581 .channels = 1, 582 .buswidth = 4, 583 .num_links = 1, 584 .link_nodes = { &srvc_mnoc }, 585 }; 586 587 static struct qcom_icc_node qnm_camnoc_hf = { 588 .name = "qnm_camnoc_hf", 589 .channels = 2, 590 .buswidth = 32, 591 .num_links = 1, 592 .link_nodes = { &qns_mem_noc_hf }, 593 }; 594 595 static struct qcom_icc_node qnm_camnoc_icp = { 596 .name = "qnm_camnoc_icp", 597 .channels = 1, 598 .buswidth = 8, 599 .num_links = 1, 600 .link_nodes = { &qns_mem_noc_sf }, 601 }; 602 603 static struct qcom_icc_node qnm_camnoc_sf = { 604 .name = "qnm_camnoc_sf", 605 .channels = 2, 606 .buswidth = 32, 607 .num_links = 1, 608 .link_nodes = { &qns_mem_noc_sf }, 609 }; 610 611 static struct qcom_icc_node qnm_video0 = { 612 .name = "qnm_video0", 613 .channels = 1, 614 .buswidth = 32, 615 .num_links = 1, 616 .link_nodes = { &qns_mem_noc_sf }, 617 }; 618 619 static struct qcom_icc_node qnm_video1 = { 620 .name = "qnm_video1", 621 .channels = 1, 622 .buswidth = 32, 623 .num_links = 1, 624 .link_nodes = { &qns_mem_noc_sf }, 625 }; 626 627 static struct qcom_icc_node qnm_video_cvp = { 628 .name = "qnm_video_cvp", 629 .channels = 1, 630 .buswidth = 32, 631 .num_links = 1, 632 .link_nodes = { &qns_mem_noc_sf }, 633 }; 634 635 static struct qcom_icc_node qxm_mdp0 = { 636 .name = "qxm_mdp0", 637 .channels = 1, 638 .buswidth = 32, 639 .num_links = 1, 640 .link_nodes = { &qns_mem_noc_hf }, 641 }; 642 643 static struct qcom_icc_node qxm_mdp1 = { 644 .name = "qxm_mdp1", 645 .channels = 1, 646 .buswidth = 32, 647 .num_links = 1, 648 .link_nodes = { &qns_mem_noc_hf }, 649 }; 650 651 static struct qcom_icc_node qxm_rot = { 652 .name = "qxm_rot", 653 .channels = 1, 654 .buswidth = 32, 655 .num_links = 1, 656 .link_nodes = { &qns_mem_noc_sf }, 657 }; 658 659 static struct qcom_icc_node amm_npu_sys = { 660 .name = "amm_npu_sys", 661 .channels = 4, 662 .buswidth = 32, 663 .num_links = 1, 664 .link_nodes = { &qns_npu_sys }, 665 }; 666 667 static struct qcom_icc_node amm_npu_sys_cdp_w = { 668 .name = "amm_npu_sys_cdp_w", 669 .channels = 2, 670 .buswidth = 16, 671 .num_links = 1, 672 .link_nodes = { &qns_npu_sys }, 673 }; 674 675 static struct qcom_icc_node qhm_cfg = { 676 .name = "qhm_cfg", 677 .channels = 1, 678 .buswidth = 4, 679 .num_links = 9, 680 .link_nodes = { &srvc_noc, 681 &qhs_isense, 682 &qhs_llm, 683 &qhs_dma_bwmon, 684 &qhs_cp, 685 &qhs_tcm, 686 &qhs_cal_dp0, 687 &qhs_cal_dp1, 688 &qhs_dpm }, 689 }; 690 691 static struct qcom_icc_node qhm_snoc_cfg = { 692 .name = "qhm_snoc_cfg", 693 .channels = 1, 694 .buswidth = 4, 695 .num_links = 1, 696 .link_nodes = { &srvc_snoc }, 697 }; 698 699 static struct qcom_icc_node qnm_aggre1_noc = { 700 .name = "qnm_aggre1_noc", 701 .channels = 1, 702 .buswidth = 16, 703 .num_links = 1, 704 .link_nodes = { &qns_gemnoc_sf }, 705 }; 706 707 static struct qcom_icc_node qnm_aggre2_noc = { 708 .name = "qnm_aggre2_noc", 709 .channels = 1, 710 .buswidth = 16, 711 .num_links = 1, 712 .link_nodes = { &qns_gemnoc_sf }, 713 }; 714 715 static struct qcom_icc_node qnm_gemnoc = { 716 .name = "qnm_gemnoc", 717 .channels = 1, 718 .buswidth = 16, 719 .num_links = 6, 720 .link_nodes = { &qxs_pimem, 721 &qxs_imem, 722 &qhs_apss, 723 &qns_cnoc, 724 &xs_sys_tcu_cfg, 725 &xs_qdss_stm }, 726 }; 727 728 static struct qcom_icc_node qnm_gemnoc_pcie = { 729 .name = "qnm_gemnoc_pcie", 730 .channels = 1, 731 .buswidth = 8, 732 .num_links = 3, 733 .link_nodes = { &xs_pcie_modem, 734 &xs_pcie_0, 735 &xs_pcie_1 }, 736 }; 737 738 static struct qcom_icc_node qxm_pimem = { 739 .name = "qxm_pimem", 740 .channels = 1, 741 .buswidth = 8, 742 .num_links = 1, 743 .link_nodes = { &qns_gemnoc_gc }, 744 }; 745 746 static struct qcom_icc_node xm_gic = { 747 .name = "xm_gic", 748 .channels = 1, 749 .buswidth = 8, 750 .num_links = 1, 751 .link_nodes = { &qns_gemnoc_gc }, 752 }; 753 754 static struct qcom_icc_node qns_a1noc_snoc = { 755 .name = "qns_a1noc_snoc", 756 .channels = 1, 757 .buswidth = 16, 758 .num_links = 1, 759 .link_nodes = { &qnm_aggre1_noc }, 760 }; 761 762 static struct qcom_icc_node qns_pcie_modem_mem_noc = { 763 .name = "qns_pcie_modem_mem_noc", 764 .channels = 1, 765 .buswidth = 16, 766 .num_links = 1, 767 .link_nodes = { &qnm_pcie }, 768 }; 769 770 static struct qcom_icc_node srvc_aggre1_noc = { 771 .name = "srvc_aggre1_noc", 772 .channels = 1, 773 .buswidth = 4, 774 }; 775 776 static struct qcom_icc_node qns_a2noc_snoc = { 777 .name = "qns_a2noc_snoc", 778 .channels = 1, 779 .buswidth = 16, 780 .num_links = 1, 781 .link_nodes = { &qnm_aggre2_noc }, 782 }; 783 784 static struct qcom_icc_node qns_pcie_mem_noc = { 785 .name = "qns_pcie_mem_noc", 786 .channels = 1, 787 .buswidth = 16, 788 .num_links = 1, 789 .link_nodes = { &qnm_pcie }, 790 }; 791 792 static struct qcom_icc_node srvc_aggre2_noc = { 793 .name = "srvc_aggre2_noc", 794 .channels = 1, 795 .buswidth = 4, 796 }; 797 798 static struct qcom_icc_node qns_cdsp_mem_noc = { 799 .name = "qns_cdsp_mem_noc", 800 .channels = 2, 801 .buswidth = 32, 802 .num_links = 1, 803 .link_nodes = { &qnm_cmpnoc }, 804 }; 805 806 static struct qcom_icc_node qhs_a1_noc_cfg = { 807 .name = "qhs_a1_noc_cfg", 808 .channels = 1, 809 .buswidth = 4, 810 .num_links = 1, 811 .link_nodes = { &qhm_a1noc_cfg }, 812 }; 813 814 static struct qcom_icc_node qhs_a2_noc_cfg = { 815 .name = "qhs_a2_noc_cfg", 816 .channels = 1, 817 .buswidth = 4, 818 .num_links = 1, 819 .link_nodes = { &qhm_a2noc_cfg }, 820 }; 821 822 static struct qcom_icc_node qhs_ahb2phy0 = { 823 .name = "qhs_ahb2phy0", 824 .channels = 1, 825 .buswidth = 4, 826 }; 827 828 static struct qcom_icc_node qhs_ahb2phy1 = { 829 .name = "qhs_ahb2phy1", 830 .channels = 1, 831 .buswidth = 4, 832 }; 833 834 static struct qcom_icc_node qhs_aoss = { 835 .name = "qhs_aoss", 836 .channels = 1, 837 .buswidth = 4, 838 }; 839 840 static struct qcom_icc_node qhs_camera_cfg = { 841 .name = "qhs_camera_cfg", 842 .channels = 1, 843 .buswidth = 4, 844 }; 845 846 static struct qcom_icc_node qhs_clk_ctl = { 847 .name = "qhs_clk_ctl", 848 .channels = 1, 849 .buswidth = 4, 850 }; 851 852 static struct qcom_icc_node qhs_compute_dsp = { 853 .name = "qhs_compute_dsp", 854 .channels = 1, 855 .buswidth = 4, 856 }; 857 858 static struct qcom_icc_node qhs_cpr_cx = { 859 .name = "qhs_cpr_cx", 860 .channels = 1, 861 .buswidth = 4, 862 }; 863 864 static struct qcom_icc_node qhs_cpr_mmcx = { 865 .name = "qhs_cpr_mmcx", 866 .channels = 1, 867 .buswidth = 4, 868 }; 869 870 static struct qcom_icc_node qhs_cpr_mx = { 871 .name = "qhs_cpr_mx", 872 .channels = 1, 873 .buswidth = 4, 874 }; 875 876 static struct qcom_icc_node qhs_crypto0_cfg = { 877 .name = "qhs_crypto0_cfg", 878 .channels = 1, 879 .buswidth = 4, 880 }; 881 882 static struct qcom_icc_node qhs_cx_rdpm = { 883 .name = "qhs_cx_rdpm", 884 .channels = 1, 885 .buswidth = 4, 886 }; 887 888 static struct qcom_icc_node qhs_dcc_cfg = { 889 .name = "qhs_dcc_cfg", 890 .channels = 1, 891 .buswidth = 4, 892 }; 893 894 static struct qcom_icc_node qhs_ddrss_cfg = { 895 .name = "qhs_ddrss_cfg", 896 .channels = 1, 897 .buswidth = 4, 898 .num_links = 1, 899 .link_nodes = { &qhm_cnoc_dc_noc }, 900 }; 901 902 static struct qcom_icc_node qhs_display_cfg = { 903 .name = "qhs_display_cfg", 904 .channels = 1, 905 .buswidth = 4, 906 }; 907 908 static struct qcom_icc_node qhs_gpuss_cfg = { 909 .name = "qhs_gpuss_cfg", 910 .channels = 1, 911 .buswidth = 8, 912 }; 913 914 static struct qcom_icc_node qhs_imem_cfg = { 915 .name = "qhs_imem_cfg", 916 .channels = 1, 917 .buswidth = 4, 918 }; 919 920 static struct qcom_icc_node qhs_ipa = { 921 .name = "qhs_ipa", 922 .channels = 1, 923 .buswidth = 4, 924 }; 925 926 static struct qcom_icc_node qhs_ipc_router = { 927 .name = "qhs_ipc_router", 928 .channels = 1, 929 .buswidth = 4, 930 }; 931 932 static struct qcom_icc_node qhs_lpass_cfg = { 933 .name = "qhs_lpass_cfg", 934 .channels = 1, 935 .buswidth = 4, 936 }; 937 938 static struct qcom_icc_node qhs_mnoc_cfg = { 939 .name = "qhs_mnoc_cfg", 940 .channels = 1, 941 .buswidth = 4, 942 .num_links = 1, 943 .link_nodes = { &qhm_mnoc_cfg }, 944 }; 945 946 static struct qcom_icc_node qhs_npu_cfg = { 947 .name = "qhs_npu_cfg", 948 .channels = 1, 949 .buswidth = 4, 950 .num_links = 1, 951 .link_nodes = { &qhm_cfg }, 952 }; 953 954 static struct qcom_icc_node qhs_pcie0_cfg = { 955 .name = "qhs_pcie0_cfg", 956 .channels = 1, 957 .buswidth = 4, 958 }; 959 960 static struct qcom_icc_node qhs_pcie1_cfg = { 961 .name = "qhs_pcie1_cfg", 962 .channels = 1, 963 .buswidth = 4, 964 }; 965 966 static struct qcom_icc_node qhs_pcie_modem_cfg = { 967 .name = "qhs_pcie_modem_cfg", 968 .channels = 1, 969 .buswidth = 4, 970 }; 971 972 static struct qcom_icc_node qhs_pdm = { 973 .name = "qhs_pdm", 974 .channels = 1, 975 .buswidth = 4, 976 }; 977 978 static struct qcom_icc_node qhs_pimem_cfg = { 979 .name = "qhs_pimem_cfg", 980 .channels = 1, 981 .buswidth = 4, 982 }; 983 984 static struct qcom_icc_node qhs_prng = { 985 .name = "qhs_prng", 986 .channels = 1, 987 .buswidth = 4, 988 }; 989 990 static struct qcom_icc_node qhs_qdss_cfg = { 991 .name = "qhs_qdss_cfg", 992 .channels = 1, 993 .buswidth = 4, 994 }; 995 996 static struct qcom_icc_node qhs_qspi = { 997 .name = "qhs_qspi", 998 .channels = 1, 999 .buswidth = 4, 1000 }; 1001 1002 static struct qcom_icc_node qhs_qup0 = { 1003 .name = "qhs_qup0", 1004 .channels = 1, 1005 .buswidth = 4, 1006 }; 1007 1008 static struct qcom_icc_node qhs_qup1 = { 1009 .name = "qhs_qup1", 1010 .channels = 1, 1011 .buswidth = 4, 1012 }; 1013 1014 static struct qcom_icc_node qhs_qup2 = { 1015 .name = "qhs_qup2", 1016 .channels = 1, 1017 .buswidth = 4, 1018 }; 1019 1020 static struct qcom_icc_node qhs_sdc2 = { 1021 .name = "qhs_sdc2", 1022 .channels = 1, 1023 .buswidth = 4, 1024 }; 1025 1026 static struct qcom_icc_node qhs_sdc4 = { 1027 .name = "qhs_sdc4", 1028 .channels = 1, 1029 .buswidth = 4, 1030 }; 1031 1032 static struct qcom_icc_node qhs_snoc_cfg = { 1033 .name = "qhs_snoc_cfg", 1034 .channels = 1, 1035 .buswidth = 4, 1036 .num_links = 1, 1037 .link_nodes = { &qhm_snoc_cfg }, 1038 }; 1039 1040 static struct qcom_icc_node qhs_tcsr = { 1041 .name = "qhs_tcsr", 1042 .channels = 1, 1043 .buswidth = 4, 1044 }; 1045 1046 static struct qcom_icc_node qhs_tlmm0 = { 1047 .name = "qhs_tlmm0", 1048 .channels = 1, 1049 .buswidth = 4, 1050 }; 1051 1052 static struct qcom_icc_node qhs_tlmm1 = { 1053 .name = "qhs_tlmm1", 1054 .channels = 1, 1055 .buswidth = 4, 1056 }; 1057 1058 static struct qcom_icc_node qhs_tlmm2 = { 1059 .name = "qhs_tlmm2", 1060 .channels = 1, 1061 .buswidth = 4, 1062 }; 1063 1064 static struct qcom_icc_node qhs_tsif = { 1065 .name = "qhs_tsif", 1066 .channels = 1, 1067 .buswidth = 4, 1068 }; 1069 1070 static struct qcom_icc_node qhs_ufs_card_cfg = { 1071 .name = "qhs_ufs_card_cfg", 1072 .channels = 1, 1073 .buswidth = 4, 1074 }; 1075 1076 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1077 .name = "qhs_ufs_mem_cfg", 1078 .channels = 1, 1079 .buswidth = 4, 1080 }; 1081 1082 static struct qcom_icc_node qhs_usb3_0 = { 1083 .name = "qhs_usb3_0", 1084 .channels = 1, 1085 .buswidth = 4, 1086 }; 1087 1088 static struct qcom_icc_node qhs_usb3_1 = { 1089 .name = "qhs_usb3_1", 1090 .channels = 1, 1091 .buswidth = 4, 1092 }; 1093 1094 static struct qcom_icc_node qhs_venus_cfg = { 1095 .name = "qhs_venus_cfg", 1096 .channels = 1, 1097 .buswidth = 4, 1098 }; 1099 1100 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1101 .name = "qhs_vsense_ctrl_cfg", 1102 .channels = 1, 1103 .buswidth = 4, 1104 }; 1105 1106 static struct qcom_icc_node qns_cnoc_a2noc = { 1107 .name = "qns_cnoc_a2noc", 1108 .channels = 1, 1109 .buswidth = 8, 1110 .num_links = 1, 1111 .link_nodes = { &qnm_cnoc }, 1112 }; 1113 1114 static struct qcom_icc_node srvc_cnoc = { 1115 .name = "srvc_cnoc", 1116 .channels = 1, 1117 .buswidth = 4, 1118 }; 1119 1120 static struct qcom_icc_node qhs_llcc = { 1121 .name = "qhs_llcc", 1122 .channels = 1, 1123 .buswidth = 4, 1124 }; 1125 1126 static struct qcom_icc_node qhs_memnoc = { 1127 .name = "qhs_memnoc", 1128 .channels = 1, 1129 .buswidth = 4, 1130 .num_links = 1, 1131 .link_nodes = { &qhm_gemnoc_cfg }, 1132 }; 1133 1134 static struct qcom_icc_node qns_gem_noc_snoc = { 1135 .name = "qns_gem_noc_snoc", 1136 .channels = 1, 1137 .buswidth = 16, 1138 .num_links = 1, 1139 .link_nodes = { &qnm_gemnoc }, 1140 }; 1141 1142 static struct qcom_icc_node qns_llcc = { 1143 .name = "qns_llcc", 1144 .channels = 4, 1145 .buswidth = 16, 1146 .num_links = 1, 1147 .link_nodes = { &llcc_mc }, 1148 }; 1149 1150 static struct qcom_icc_node qns_sys_pcie = { 1151 .name = "qns_sys_pcie", 1152 .channels = 1, 1153 .buswidth = 8, 1154 .num_links = 1, 1155 .link_nodes = { &qnm_gemnoc_pcie }, 1156 }; 1157 1158 static struct qcom_icc_node srvc_even_gemnoc = { 1159 .name = "srvc_even_gemnoc", 1160 .channels = 1, 1161 .buswidth = 4, 1162 }; 1163 1164 static struct qcom_icc_node srvc_odd_gemnoc = { 1165 .name = "srvc_odd_gemnoc", 1166 .channels = 1, 1167 .buswidth = 4, 1168 }; 1169 1170 static struct qcom_icc_node srvc_sys_gemnoc = { 1171 .name = "srvc_sys_gemnoc", 1172 .channels = 1, 1173 .buswidth = 4, 1174 }; 1175 1176 static struct qcom_icc_node ebi = { 1177 .name = "ebi", 1178 .channels = 4, 1179 .buswidth = 4, 1180 }; 1181 1182 static struct qcom_icc_node qns_mem_noc_hf = { 1183 .name = "qns_mem_noc_hf", 1184 .channels = 2, 1185 .buswidth = 32, 1186 .num_links = 1, 1187 .link_nodes = { &qnm_mnoc_hf }, 1188 }; 1189 1190 static struct qcom_icc_node qns_mem_noc_sf = { 1191 .name = "qns_mem_noc_sf", 1192 .channels = 2, 1193 .buswidth = 32, 1194 .num_links = 1, 1195 .link_nodes = { &qnm_mnoc_sf }, 1196 }; 1197 1198 static struct qcom_icc_node srvc_mnoc = { 1199 .name = "srvc_mnoc", 1200 .channels = 1, 1201 .buswidth = 4, 1202 }; 1203 1204 static struct qcom_icc_node qhs_cal_dp0 = { 1205 .name = "qhs_cal_dp0", 1206 .channels = 1, 1207 .buswidth = 4, 1208 }; 1209 1210 static struct qcom_icc_node qhs_cal_dp1 = { 1211 .name = "qhs_cal_dp1", 1212 .channels = 1, 1213 .buswidth = 4, 1214 }; 1215 1216 static struct qcom_icc_node qhs_cp = { 1217 .name = "qhs_cp", 1218 .channels = 1, 1219 .buswidth = 4, 1220 }; 1221 1222 static struct qcom_icc_node qhs_dma_bwmon = { 1223 .name = "qhs_dma_bwmon", 1224 .channels = 1, 1225 .buswidth = 4, 1226 }; 1227 1228 static struct qcom_icc_node qhs_dpm = { 1229 .name = "qhs_dpm", 1230 .channels = 1, 1231 .buswidth = 4, 1232 }; 1233 1234 static struct qcom_icc_node qhs_isense = { 1235 .name = "qhs_isense", 1236 .channels = 1, 1237 .buswidth = 4, 1238 }; 1239 1240 static struct qcom_icc_node qhs_llm = { 1241 .name = "qhs_llm", 1242 .channels = 1, 1243 .buswidth = 4, 1244 }; 1245 1246 static struct qcom_icc_node qhs_tcm = { 1247 .name = "qhs_tcm", 1248 .channels = 1, 1249 .buswidth = 4, 1250 }; 1251 1252 static struct qcom_icc_node qns_npu_sys = { 1253 .name = "qns_npu_sys", 1254 .channels = 2, 1255 .buswidth = 32, 1256 }; 1257 1258 static struct qcom_icc_node srvc_noc = { 1259 .name = "srvc_noc", 1260 .channels = 1, 1261 .buswidth = 4, 1262 }; 1263 1264 static struct qcom_icc_node qhs_apss = { 1265 .name = "qhs_apss", 1266 .channels = 1, 1267 .buswidth = 8, 1268 }; 1269 1270 static struct qcom_icc_node qns_cnoc = { 1271 .name = "qns_cnoc", 1272 .channels = 1, 1273 .buswidth = 8, 1274 .num_links = 1, 1275 .link_nodes = { &qnm_snoc }, 1276 }; 1277 1278 static struct qcom_icc_node qns_gemnoc_gc = { 1279 .name = "qns_gemnoc_gc", 1280 .channels = 1, 1281 .buswidth = 8, 1282 .num_links = 1, 1283 .link_nodes = { &qnm_snoc_gc }, 1284 }; 1285 1286 static struct qcom_icc_node qns_gemnoc_sf = { 1287 .name = "qns_gemnoc_sf", 1288 .channels = 1, 1289 .buswidth = 16, 1290 .num_links = 1, 1291 .link_nodes = { &qnm_snoc_sf }, 1292 }; 1293 1294 static struct qcom_icc_node qxs_imem = { 1295 .name = "qxs_imem", 1296 .channels = 1, 1297 .buswidth = 8, 1298 }; 1299 1300 static struct qcom_icc_node qxs_pimem = { 1301 .name = "qxs_pimem", 1302 .channels = 1, 1303 .buswidth = 8, 1304 }; 1305 1306 static struct qcom_icc_node srvc_snoc = { 1307 .name = "srvc_snoc", 1308 .channels = 1, 1309 .buswidth = 4, 1310 }; 1311 1312 static struct qcom_icc_node xs_pcie_0 = { 1313 .name = "xs_pcie_0", 1314 .channels = 1, 1315 .buswidth = 8, 1316 }; 1317 1318 static struct qcom_icc_node xs_pcie_1 = { 1319 .name = "xs_pcie_1", 1320 .channels = 1, 1321 .buswidth = 8, 1322 }; 1323 1324 static struct qcom_icc_node xs_pcie_modem = { 1325 .name = "xs_pcie_modem", 1326 .channels = 1, 1327 .buswidth = 8, 1328 }; 1329 1330 static struct qcom_icc_node xs_qdss_stm = { 1331 .name = "xs_qdss_stm", 1332 .channels = 1, 1333 .buswidth = 4, 1334 }; 1335 1336 static struct qcom_icc_node xs_sys_tcu_cfg = { 1337 .name = "xs_sys_tcu_cfg", 1338 .channels = 1, 1339 .buswidth = 8, 1340 }; 1341 1342 static struct qcom_icc_node qup0_core_master = { 1343 .name = "qup0_core_master", 1344 .channels = 1, 1345 .buswidth = 4, 1346 .num_links = 1, 1347 .link_nodes = { &qup0_core_slave }, 1348 }; 1349 1350 static struct qcom_icc_node qup1_core_master = { 1351 .name = "qup1_core_master", 1352 .channels = 1, 1353 .buswidth = 4, 1354 .num_links = 1, 1355 .link_nodes = { &qup1_core_slave }, 1356 }; 1357 1358 static struct qcom_icc_node qup2_core_master = { 1359 .name = "qup2_core_master", 1360 .channels = 1, 1361 .buswidth = 4, 1362 .num_links = 1, 1363 .link_nodes = { &qup2_core_slave }, 1364 }; 1365 1366 static struct qcom_icc_node qup0_core_slave = { 1367 .name = "qup0_core_slave", 1368 .channels = 1, 1369 .buswidth = 4, 1370 }; 1371 1372 static struct qcom_icc_node qup1_core_slave = { 1373 .name = "qup1_core_slave", 1374 .channels = 1, 1375 .buswidth = 4, 1376 }; 1377 1378 static struct qcom_icc_node qup2_core_slave = { 1379 .name = "qup2_core_slave", 1380 .channels = 1, 1381 .buswidth = 4, 1382 }; 1383 1384 static struct qcom_icc_bcm bcm_acv = { 1385 .name = "ACV", 1386 .enable_mask = BIT(3), 1387 .keepalive = false, 1388 .num_nodes = 1, 1389 .nodes = { &ebi }, 1390 }; 1391 1392 static struct qcom_icc_bcm bcm_mc0 = { 1393 .name = "MC0", 1394 .keepalive = true, 1395 .num_nodes = 1, 1396 .nodes = { &ebi }, 1397 }; 1398 1399 static struct qcom_icc_bcm bcm_sh0 = { 1400 .name = "SH0", 1401 .keepalive = true, 1402 .num_nodes = 1, 1403 .nodes = { &qns_llcc }, 1404 }; 1405 1406 static struct qcom_icc_bcm bcm_mm0 = { 1407 .name = "MM0", 1408 .keepalive = true, 1409 .num_nodes = 1, 1410 .nodes = { &qns_mem_noc_hf }, 1411 }; 1412 1413 static struct qcom_icc_bcm bcm_ce0 = { 1414 .name = "CE0", 1415 .keepalive = false, 1416 .num_nodes = 1, 1417 .nodes = { &qxm_crypto }, 1418 }; 1419 1420 static struct qcom_icc_bcm bcm_mm1 = { 1421 .name = "MM1", 1422 .keepalive = false, 1423 .num_nodes = 3, 1424 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, 1425 }; 1426 1427 static struct qcom_icc_bcm bcm_sh2 = { 1428 .name = "SH2", 1429 .keepalive = false, 1430 .num_nodes = 2, 1431 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1432 }; 1433 1434 static struct qcom_icc_bcm bcm_mm2 = { 1435 .name = "MM2", 1436 .keepalive = false, 1437 .num_nodes = 1, 1438 .nodes = { &qns_mem_noc_sf }, 1439 }; 1440 1441 static struct qcom_icc_bcm bcm_qup0 = { 1442 .name = "QUP0", 1443 .keepalive = false, 1444 .num_nodes = 3, 1445 .nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master }, 1446 }; 1447 1448 static struct qcom_icc_bcm bcm_sh3 = { 1449 .name = "SH3", 1450 .keepalive = false, 1451 .num_nodes = 1, 1452 .nodes = { &qnm_cmpnoc }, 1453 }; 1454 1455 static struct qcom_icc_bcm bcm_mm3 = { 1456 .name = "MM3", 1457 .keepalive = false, 1458 .num_nodes = 5, 1459 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp }, 1460 }; 1461 1462 static struct qcom_icc_bcm bcm_sh4 = { 1463 .name = "SH4", 1464 .keepalive = false, 1465 .num_nodes = 1, 1466 .nodes = { &chm_apps }, 1467 }; 1468 1469 static struct qcom_icc_bcm bcm_sn0 = { 1470 .name = "SN0", 1471 .keepalive = true, 1472 .num_nodes = 1, 1473 .nodes = { &qns_gemnoc_sf }, 1474 }; 1475 1476 static struct qcom_icc_bcm bcm_co0 = { 1477 .name = "CO0", 1478 .keepalive = false, 1479 .num_nodes = 1, 1480 .nodes = { &qns_cdsp_mem_noc }, 1481 }; 1482 1483 static struct qcom_icc_bcm bcm_cn0 = { 1484 .name = "CN0", 1485 .keepalive = true, 1486 .num_nodes = 52, 1487 .nodes = { &qnm_snoc, 1488 &xm_qdss_dap, 1489 &qhs_a1_noc_cfg, 1490 &qhs_a2_noc_cfg, 1491 &qhs_ahb2phy0, 1492 &qhs_ahb2phy1, 1493 &qhs_aoss, 1494 &qhs_camera_cfg, 1495 &qhs_clk_ctl, 1496 &qhs_compute_dsp, 1497 &qhs_cpr_cx, 1498 &qhs_cpr_mmcx, 1499 &qhs_cpr_mx, 1500 &qhs_crypto0_cfg, 1501 &qhs_cx_rdpm, 1502 &qhs_dcc_cfg, 1503 &qhs_ddrss_cfg, 1504 &qhs_display_cfg, 1505 &qhs_gpuss_cfg, 1506 &qhs_imem_cfg, 1507 &qhs_ipa, 1508 &qhs_ipc_router, 1509 &qhs_lpass_cfg, 1510 &qhs_mnoc_cfg, 1511 &qhs_npu_cfg, 1512 &qhs_pcie0_cfg, 1513 &qhs_pcie1_cfg, 1514 &qhs_pcie_modem_cfg, 1515 &qhs_pdm, 1516 &qhs_pimem_cfg, 1517 &qhs_prng, 1518 &qhs_qdss_cfg, 1519 &qhs_qspi, 1520 &qhs_qup0, 1521 &qhs_qup1, 1522 &qhs_qup2, 1523 &qhs_sdc2, 1524 &qhs_sdc4, 1525 &qhs_snoc_cfg, 1526 &qhs_tcsr, 1527 &qhs_tlmm0, 1528 &qhs_tlmm1, 1529 &qhs_tlmm2, 1530 &qhs_tsif, 1531 &qhs_ufs_card_cfg, 1532 &qhs_ufs_mem_cfg, 1533 &qhs_usb3_0, 1534 &qhs_usb3_1, 1535 &qhs_venus_cfg, 1536 &qhs_vsense_ctrl_cfg, 1537 &qns_cnoc_a2noc, 1538 &srvc_cnoc 1539 }, 1540 }; 1541 1542 static struct qcom_icc_bcm bcm_sn1 = { 1543 .name = "SN1", 1544 .keepalive = false, 1545 .num_nodes = 1, 1546 .nodes = { &qxs_imem }, 1547 }; 1548 1549 static struct qcom_icc_bcm bcm_sn2 = { 1550 .name = "SN2", 1551 .keepalive = false, 1552 .num_nodes = 1, 1553 .nodes = { &qns_gemnoc_gc }, 1554 }; 1555 1556 static struct qcom_icc_bcm bcm_co2 = { 1557 .name = "CO2", 1558 .keepalive = false, 1559 .num_nodes = 1, 1560 .nodes = { &qnm_npu }, 1561 }; 1562 1563 static struct qcom_icc_bcm bcm_sn3 = { 1564 .name = "SN3", 1565 .keepalive = false, 1566 .num_nodes = 1, 1567 .nodes = { &qxs_pimem }, 1568 }; 1569 1570 static struct qcom_icc_bcm bcm_sn4 = { 1571 .name = "SN4", 1572 .keepalive = false, 1573 .num_nodes = 1, 1574 .nodes = { &xs_qdss_stm }, 1575 }; 1576 1577 static struct qcom_icc_bcm bcm_sn5 = { 1578 .name = "SN5", 1579 .keepalive = false, 1580 .num_nodes = 1, 1581 .nodes = { &xs_pcie_modem }, 1582 }; 1583 1584 static struct qcom_icc_bcm bcm_sn6 = { 1585 .name = "SN6", 1586 .keepalive = false, 1587 .num_nodes = 2, 1588 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1589 }; 1590 1591 static struct qcom_icc_bcm bcm_sn7 = { 1592 .name = "SN7", 1593 .keepalive = false, 1594 .num_nodes = 1, 1595 .nodes = { &qnm_aggre1_noc }, 1596 }; 1597 1598 static struct qcom_icc_bcm bcm_sn8 = { 1599 .name = "SN8", 1600 .keepalive = false, 1601 .num_nodes = 1, 1602 .nodes = { &qnm_aggre2_noc }, 1603 }; 1604 1605 static struct qcom_icc_bcm bcm_sn9 = { 1606 .name = "SN9", 1607 .keepalive = false, 1608 .num_nodes = 1, 1609 .nodes = { &qnm_gemnoc_pcie }, 1610 }; 1611 1612 static struct qcom_icc_bcm bcm_sn11 = { 1613 .name = "SN11", 1614 .keepalive = false, 1615 .num_nodes = 1, 1616 .nodes = { &qnm_gemnoc }, 1617 }; 1618 1619 static struct qcom_icc_bcm bcm_sn12 = { 1620 .name = "SN12", 1621 .keepalive = false, 1622 .num_nodes = 2, 1623 .nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc }, 1624 }; 1625 1626 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1627 &bcm_sn12, 1628 }; 1629 1630 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1631 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1632 [MASTER_QSPI_0] = &qhm_qspi, 1633 [MASTER_QUP_1] = &qhm_qup1, 1634 [MASTER_QUP_2] = &qhm_qup2, 1635 [MASTER_TSIF] = &qhm_tsif, 1636 [MASTER_PCIE_2] = &xm_pcie3_modem, 1637 [MASTER_SDCC_4] = &xm_sdc4, 1638 [MASTER_UFS_MEM] = &xm_ufs_mem, 1639 [MASTER_USB3] = &xm_usb3_0, 1640 [MASTER_USB3_1] = &xm_usb3_1, 1641 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1642 [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc, 1643 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1644 }; 1645 1646 static const struct qcom_icc_desc sm8250_aggre1_noc = { 1647 .nodes = aggre1_noc_nodes, 1648 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1649 .bcms = aggre1_noc_bcms, 1650 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1651 }; 1652 1653 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1654 &bcm_ce0, 1655 &bcm_sn12, 1656 }; 1657 1658 static struct qcom_icc_bcm * const qup_virt_bcms[] = { 1659 &bcm_qup0, 1660 }; 1661 1662 static struct qcom_icc_node * const qup_virt_nodes[] = { 1663 [MASTER_QUP_CORE_0] = &qup0_core_master, 1664 [MASTER_QUP_CORE_1] = &qup1_core_master, 1665 [MASTER_QUP_CORE_2] = &qup2_core_master, 1666 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1667 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1668 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1669 }; 1670 1671 static const struct qcom_icc_desc sm8250_qup_virt = { 1672 .nodes = qup_virt_nodes, 1673 .num_nodes = ARRAY_SIZE(qup_virt_nodes), 1674 .bcms = qup_virt_bcms, 1675 .num_bcms = ARRAY_SIZE(qup_virt_bcms), 1676 }; 1677 1678 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1679 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1680 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1681 [MASTER_QUP_0] = &qhm_qup0, 1682 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1683 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1684 [MASTER_IPA] = &qxm_ipa, 1685 [MASTER_PCIE] = &xm_pcie3_0, 1686 [MASTER_PCIE_1] = &xm_pcie3_1, 1687 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1688 [MASTER_SDCC_2] = &xm_sdc2, 1689 [MASTER_UFS_CARD] = &xm_ufs_card, 1690 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1691 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1692 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1693 }; 1694 1695 static const struct qcom_icc_desc sm8250_aggre2_noc = { 1696 .nodes = aggre2_noc_nodes, 1697 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1698 .bcms = aggre2_noc_bcms, 1699 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1700 }; 1701 1702 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1703 &bcm_co0, 1704 &bcm_co2, 1705 }; 1706 1707 static struct qcom_icc_node * const compute_noc_nodes[] = { 1708 [MASTER_NPU] = &qnm_npu, 1709 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, 1710 }; 1711 1712 static const struct qcom_icc_desc sm8250_compute_noc = { 1713 .nodes = compute_noc_nodes, 1714 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1715 .bcms = compute_noc_bcms, 1716 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1717 }; 1718 1719 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1720 &bcm_cn0, 1721 }; 1722 1723 static struct qcom_icc_node * const config_noc_nodes[] = { 1724 [SNOC_CNOC_MAS] = &qnm_snoc, 1725 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1726 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1727 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1728 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1729 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1730 [SLAVE_AOSS] = &qhs_aoss, 1731 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1732 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1733 [SLAVE_CDSP_CFG] = &qhs_compute_dsp, 1734 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1735 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1736 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1737 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1738 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1739 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1740 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1741 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1742 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1743 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1744 [SLAVE_IPA_CFG] = &qhs_ipa, 1745 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1746 [SLAVE_LPASS] = &qhs_lpass_cfg, 1747 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1748 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1749 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1750 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1751 [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg, 1752 [SLAVE_PDM] = &qhs_pdm, 1753 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1754 [SLAVE_PRNG] = &qhs_prng, 1755 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1756 [SLAVE_QSPI_0] = &qhs_qspi, 1757 [SLAVE_QUP_0] = &qhs_qup0, 1758 [SLAVE_QUP_1] = &qhs_qup1, 1759 [SLAVE_QUP_2] = &qhs_qup2, 1760 [SLAVE_SDCC_2] = &qhs_sdc2, 1761 [SLAVE_SDCC_4] = &qhs_sdc4, 1762 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1763 [SLAVE_TCSR] = &qhs_tcsr, 1764 [SLAVE_TLMM_NORTH] = &qhs_tlmm0, 1765 [SLAVE_TLMM_SOUTH] = &qhs_tlmm1, 1766 [SLAVE_TLMM_WEST] = &qhs_tlmm2, 1767 [SLAVE_TSIF] = &qhs_tsif, 1768 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1769 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1770 [SLAVE_USB3] = &qhs_usb3_0, 1771 [SLAVE_USB3_1] = &qhs_usb3_1, 1772 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1773 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1774 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1775 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1776 }; 1777 1778 static const struct qcom_icc_desc sm8250_config_noc = { 1779 .nodes = config_noc_nodes, 1780 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1781 .bcms = config_noc_bcms, 1782 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1783 }; 1784 1785 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1786 }; 1787 1788 static struct qcom_icc_node * const dc_noc_nodes[] = { 1789 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1790 [SLAVE_LLCC_CFG] = &qhs_llcc, 1791 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, 1792 }; 1793 1794 static const struct qcom_icc_desc sm8250_dc_noc = { 1795 .nodes = dc_noc_nodes, 1796 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1797 .bcms = dc_noc_bcms, 1798 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1799 }; 1800 1801 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1802 &bcm_sh0, 1803 &bcm_sh2, 1804 &bcm_sh3, 1805 &bcm_sh4, 1806 }; 1807 1808 static struct qcom_icc_node * const gem_noc_nodes[] = { 1809 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1810 [MASTER_SYS_TCU] = &alm_sys_tcu, 1811 [MASTER_AMPSS_M0] = &chm_apps, 1812 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1813 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1814 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1815 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1816 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1817 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1818 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1819 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1820 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1821 [SLAVE_LLCC] = &qns_llcc, 1822 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 1823 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1824 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1825 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1826 }; 1827 1828 static const struct qcom_icc_desc sm8250_gem_noc = { 1829 .nodes = gem_noc_nodes, 1830 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1831 .bcms = gem_noc_bcms, 1832 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1833 }; 1834 1835 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1836 &bcm_acv, 1837 &bcm_mc0, 1838 }; 1839 1840 static struct qcom_icc_node * const mc_virt_nodes[] = { 1841 [MASTER_LLCC] = &llcc_mc, 1842 [SLAVE_EBI_CH0] = &ebi, 1843 }; 1844 1845 static const struct qcom_icc_desc sm8250_mc_virt = { 1846 .nodes = mc_virt_nodes, 1847 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1848 .bcms = mc_virt_bcms, 1849 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1850 }; 1851 1852 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1853 &bcm_mm0, 1854 &bcm_mm1, 1855 &bcm_mm2, 1856 &bcm_mm3, 1857 }; 1858 1859 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1860 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1861 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1862 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1863 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1864 [MASTER_VIDEO_P0] = &qnm_video0, 1865 [MASTER_VIDEO_P1] = &qnm_video1, 1866 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1867 [MASTER_MDP_PORT0] = &qxm_mdp0, 1868 [MASTER_MDP_PORT1] = &qxm_mdp1, 1869 [MASTER_ROTATOR] = &qxm_rot, 1870 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1871 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1872 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1873 }; 1874 1875 static const struct qcom_icc_desc sm8250_mmss_noc = { 1876 .nodes = mmss_noc_nodes, 1877 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1878 .bcms = mmss_noc_bcms, 1879 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1880 }; 1881 1882 static struct qcom_icc_bcm * const npu_noc_bcms[] = { 1883 }; 1884 1885 static struct qcom_icc_node * const npu_noc_nodes[] = { 1886 [MASTER_NPU_SYS] = &amm_npu_sys, 1887 [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w, 1888 [MASTER_NPU_NOC_CFG] = &qhm_cfg, 1889 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 1890 [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1, 1891 [SLAVE_NPU_CP] = &qhs_cp, 1892 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 1893 [SLAVE_NPU_DPM] = &qhs_dpm, 1894 [SLAVE_ISENSE_CFG] = &qhs_isense, 1895 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 1896 [SLAVE_NPU_TCM] = &qhs_tcm, 1897 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 1898 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 1899 }; 1900 1901 static const struct qcom_icc_desc sm8250_npu_noc = { 1902 .nodes = npu_noc_nodes, 1903 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 1904 .bcms = npu_noc_bcms, 1905 .num_bcms = ARRAY_SIZE(npu_noc_bcms), 1906 }; 1907 1908 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1909 &bcm_sn0, 1910 &bcm_sn1, 1911 &bcm_sn11, 1912 &bcm_sn2, 1913 &bcm_sn3, 1914 &bcm_sn4, 1915 &bcm_sn5, 1916 &bcm_sn6, 1917 &bcm_sn7, 1918 &bcm_sn8, 1919 &bcm_sn9, 1920 }; 1921 1922 static struct qcom_icc_node * const system_noc_nodes[] = { 1923 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1924 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1925 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1926 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1927 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1928 [MASTER_PIMEM] = &qxm_pimem, 1929 [MASTER_GIC] = &xm_gic, 1930 [SLAVE_APPSS] = &qhs_apss, 1931 [SNOC_CNOC_SLV] = &qns_cnoc, 1932 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1933 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1934 [SLAVE_OCIMEM] = &qxs_imem, 1935 [SLAVE_PIMEM] = &qxs_pimem, 1936 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1937 [SLAVE_PCIE_0] = &xs_pcie_0, 1938 [SLAVE_PCIE_1] = &xs_pcie_1, 1939 [SLAVE_PCIE_2] = &xs_pcie_modem, 1940 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1941 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1942 }; 1943 1944 static const struct qcom_icc_desc sm8250_system_noc = { 1945 .nodes = system_noc_nodes, 1946 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1947 .bcms = system_noc_bcms, 1948 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1949 }; 1950 1951 static const struct of_device_id qnoc_of_match[] = { 1952 { .compatible = "qcom,sm8250-aggre1-noc", 1953 .data = &sm8250_aggre1_noc}, 1954 { .compatible = "qcom,sm8250-aggre2-noc", 1955 .data = &sm8250_aggre2_noc}, 1956 { .compatible = "qcom,sm8250-compute-noc", 1957 .data = &sm8250_compute_noc}, 1958 { .compatible = "qcom,sm8250-config-noc", 1959 .data = &sm8250_config_noc}, 1960 { .compatible = "qcom,sm8250-dc-noc", 1961 .data = &sm8250_dc_noc}, 1962 { .compatible = "qcom,sm8250-gem-noc", 1963 .data = &sm8250_gem_noc}, 1964 { .compatible = "qcom,sm8250-mc-virt", 1965 .data = &sm8250_mc_virt}, 1966 { .compatible = "qcom,sm8250-mmss-noc", 1967 .data = &sm8250_mmss_noc}, 1968 { .compatible = "qcom,sm8250-npu-noc", 1969 .data = &sm8250_npu_noc}, 1970 { .compatible = "qcom,sm8250-qup-virt", 1971 .data = &sm8250_qup_virt }, 1972 { .compatible = "qcom,sm8250-system-noc", 1973 .data = &sm8250_system_noc}, 1974 { } 1975 }; 1976 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1977 1978 static struct platform_driver qnoc_driver = { 1979 .probe = qcom_icc_rpmh_probe, 1980 .remove = qcom_icc_rpmh_remove, 1981 .driver = { 1982 .name = "qnoc-sm8250", 1983 .of_match_table = qnoc_of_match, 1984 .sync_state = icc_sync_state, 1985 }, 1986 }; 1987 module_platform_driver(qnoc_driver); 1988 1989 MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver"); 1990 MODULE_LICENSE("GPL v2"); 1991