1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
14
15 #include "bcm-voter.h"
16 #include "icc-rpmh.h"
17
18 static struct qcom_icc_node qhm_a1noc_cfg;
19 static struct qcom_icc_node qhm_qup_center;
20 static struct qcom_icc_node qhm_tsif;
21 static struct qcom_icc_node xm_emmc;
22 static struct qcom_icc_node xm_sdc2;
23 static struct qcom_icc_node xm_sdc4;
24 static struct qcom_icc_node xm_ufs_mem;
25 static struct qcom_icc_node qhm_a2noc_cfg;
26 static struct qcom_icc_node qhm_qdss_bam;
27 static struct qcom_icc_node qhm_qup_north;
28 static struct qcom_icc_node qnm_cnoc;
29 static struct qcom_icc_node qxm_crypto;
30 static struct qcom_icc_node qxm_ipa;
31 static struct qcom_icc_node xm_pcie3_0;
32 static struct qcom_icc_node xm_qdss_etr;
33 static struct qcom_icc_node xm_usb3_0;
34 static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
35 static struct qcom_icc_node qxm_camnoc_rt_uncomp;
36 static struct qcom_icc_node qxm_camnoc_sf_uncomp;
37 static struct qcom_icc_node qxm_camnoc_nrt_uncomp;
38 static struct qcom_icc_node qnm_npu;
39 static struct qcom_icc_node qhm_spdm;
40 static struct qcom_icc_node qnm_snoc;
41 static struct qcom_icc_node xm_qdss_dap;
42 static struct qcom_icc_node qhm_cnoc_dc_noc;
43 static struct qcom_icc_node acm_apps;
44 static struct qcom_icc_node acm_sys_tcu;
45 static struct qcom_icc_node qhm_gemnoc_cfg;
46 static struct qcom_icc_node qnm_cmpnoc;
47 static struct qcom_icc_node qnm_mnoc_hf;
48 static struct qcom_icc_node qnm_mnoc_sf;
49 static struct qcom_icc_node qnm_pcie;
50 static struct qcom_icc_node qnm_snoc_gc;
51 static struct qcom_icc_node qnm_snoc_sf;
52 static struct qcom_icc_node qxm_gpu;
53 static struct qcom_icc_node llcc_mc;
54 static struct qcom_icc_node qhm_mnoc_cfg;
55 static struct qcom_icc_node qxm_camnoc_hf;
56 static struct qcom_icc_node qxm_camnoc_nrt;
57 static struct qcom_icc_node qxm_camnoc_rt;
58 static struct qcom_icc_node qxm_camnoc_sf;
59 static struct qcom_icc_node qxm_mdp0;
60 static struct qcom_icc_node qxm_mdp1;
61 static struct qcom_icc_node qxm_rot;
62 static struct qcom_icc_node qxm_venus0;
63 static struct qcom_icc_node qxm_venus1;
64 static struct qcom_icc_node qxm_venus_arm9;
65 static struct qcom_icc_node qhm_snoc_cfg;
66 static struct qcom_icc_node qnm_aggre1_noc;
67 static struct qcom_icc_node qnm_aggre2_noc;
68 static struct qcom_icc_node qnm_gemnoc;
69 static struct qcom_icc_node qxm_pimem;
70 static struct qcom_icc_node xm_gic;
71 static struct qcom_icc_node qns_a1noc_snoc;
72 static struct qcom_icc_node srvc_aggre1_noc;
73 static struct qcom_icc_node qns_a2noc_snoc;
74 static struct qcom_icc_node qns_pcie_gemnoc;
75 static struct qcom_icc_node srvc_aggre2_noc;
76 static struct qcom_icc_node qns_camnoc_uncomp;
77 static struct qcom_icc_node qns_cdsp_gemnoc;
78 static struct qcom_icc_node qhs_a1_noc_cfg;
79 static struct qcom_icc_node qhs_a2_noc_cfg;
80 static struct qcom_icc_node qhs_ahb2phy_north;
81 static struct qcom_icc_node qhs_ahb2phy_south;
82 static struct qcom_icc_node qhs_ahb2phy_west;
83 static struct qcom_icc_node qhs_aop;
84 static struct qcom_icc_node qhs_aoss;
85 static struct qcom_icc_node qhs_camera_cfg;
86 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg;
87 static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
88 static struct qcom_icc_node qhs_clk_ctl;
89 static struct qcom_icc_node qhs_compute_dsp_cfg;
90 static struct qcom_icc_node qhs_cpr_cx;
91 static struct qcom_icc_node qhs_cpr_mx;
92 static struct qcom_icc_node qhs_crypto0_cfg;
93 static struct qcom_icc_node qhs_ddrss_cfg;
94 static struct qcom_icc_node qhs_display_cfg;
95 static struct qcom_icc_node qhs_display_throttle_cfg;
96 static struct qcom_icc_node qhs_emmc_cfg;
97 static struct qcom_icc_node qhs_glm;
98 static struct qcom_icc_node qhs_gpuss_cfg;
99 static struct qcom_icc_node qhs_imem_cfg;
100 static struct qcom_icc_node qhs_ipa;
101 static struct qcom_icc_node qhs_mnoc_cfg;
102 static struct qcom_icc_node qhs_pcie_cfg;
103 static struct qcom_icc_node qhs_pdm;
104 static struct qcom_icc_node qhs_pimem_cfg;
105 static struct qcom_icc_node qhs_prng;
106 static struct qcom_icc_node qhs_qdss_cfg;
107 static struct qcom_icc_node qhs_qupv3_center;
108 static struct qcom_icc_node qhs_qupv3_north;
109 static struct qcom_icc_node qhs_sdc2;
110 static struct qcom_icc_node qhs_sdc4;
111 static struct qcom_icc_node qhs_snoc_cfg;
112 static struct qcom_icc_node qhs_spdm;
113 static struct qcom_icc_node qhs_tcsr;
114 static struct qcom_icc_node qhs_tlmm_north;
115 static struct qcom_icc_node qhs_tlmm_south;
116 static struct qcom_icc_node qhs_tlmm_west;
117 static struct qcom_icc_node qhs_tsif;
118 static struct qcom_icc_node qhs_ufs_mem_cfg;
119 static struct qcom_icc_node qhs_usb3_0;
120 static struct qcom_icc_node qhs_venus_cfg;
121 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
122 static struct qcom_icc_node qhs_venus_throttle_cfg;
123 static struct qcom_icc_node qhs_vsense_ctrl_cfg;
124 static struct qcom_icc_node qns_cnoc_a2noc;
125 static struct qcom_icc_node srvc_cnoc;
126 static struct qcom_icc_node qhs_gemnoc;
127 static struct qcom_icc_node qhs_llcc;
128 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
129 static struct qcom_icc_node qns_gem_noc_snoc;
130 static struct qcom_icc_node qns_llcc;
131 static struct qcom_icc_node srvc_gemnoc;
132 static struct qcom_icc_node ebi;
133 static struct qcom_icc_node qns2_mem_noc;
134 static struct qcom_icc_node qns_mem_noc_hf;
135 static struct qcom_icc_node srvc_mnoc;
136 static struct qcom_icc_node qhs_apss;
137 static struct qcom_icc_node qns_cnoc;
138 static struct qcom_icc_node qns_gemnoc_gc;
139 static struct qcom_icc_node qns_gemnoc_sf;
140 static struct qcom_icc_node qxs_imem;
141 static struct qcom_icc_node qxs_pimem;
142 static struct qcom_icc_node srvc_snoc;
143 static struct qcom_icc_node xs_qdss_stm;
144 static struct qcom_icc_node xs_sys_tcu_cfg;
145
146 static struct qcom_icc_node qhm_a1noc_cfg = {
147 .name = "qhm_a1noc_cfg",
148 .channels = 1,
149 .buswidth = 4,
150 .num_links = 1,
151 .link_nodes = { &srvc_aggre1_noc },
152 };
153
154 static struct qcom_icc_node qhm_qup_center = {
155 .name = "qhm_qup_center",
156 .channels = 1,
157 .buswidth = 4,
158 .num_links = 1,
159 .link_nodes = { &qns_a1noc_snoc },
160 };
161
162 static struct qcom_icc_node qhm_tsif = {
163 .name = "qhm_tsif",
164 .channels = 1,
165 .buswidth = 4,
166 .num_links = 1,
167 .link_nodes = { &qns_a1noc_snoc },
168 };
169
170 static struct qcom_icc_node xm_emmc = {
171 .name = "xm_emmc",
172 .channels = 1,
173 .buswidth = 8,
174 .num_links = 1,
175 .link_nodes = { &qns_a1noc_snoc },
176 };
177
178 static struct qcom_icc_node xm_sdc2 = {
179 .name = "xm_sdc2",
180 .channels = 1,
181 .buswidth = 8,
182 .num_links = 1,
183 .link_nodes = { &qns_a1noc_snoc },
184 };
185
186 static struct qcom_icc_node xm_sdc4 = {
187 .name = "xm_sdc4",
188 .channels = 1,
189 .buswidth = 8,
190 .num_links = 1,
191 .link_nodes = { &qns_a1noc_snoc },
192 };
193
194 static struct qcom_icc_node xm_ufs_mem = {
195 .name = "xm_ufs_mem",
196 .channels = 1,
197 .buswidth = 8,
198 .num_links = 1,
199 .link_nodes = { &qns_a1noc_snoc },
200 };
201
202 static struct qcom_icc_node qhm_a2noc_cfg = {
203 .name = "qhm_a2noc_cfg",
204 .channels = 1,
205 .buswidth = 4,
206 .num_links = 1,
207 .link_nodes = { &srvc_aggre2_noc },
208 };
209
210 static struct qcom_icc_node qhm_qdss_bam = {
211 .name = "qhm_qdss_bam",
212 .channels = 1,
213 .buswidth = 4,
214 .num_links = 1,
215 .link_nodes = { &qns_a2noc_snoc },
216 };
217
218 static struct qcom_icc_node qhm_qup_north = {
219 .name = "qhm_qup_north",
220 .channels = 1,
221 .buswidth = 4,
222 .num_links = 1,
223 .link_nodes = { &qns_a2noc_snoc },
224 };
225
226 static struct qcom_icc_node qnm_cnoc = {
227 .name = "qnm_cnoc",
228 .channels = 1,
229 .buswidth = 8,
230 .num_links = 1,
231 .link_nodes = { &qns_a2noc_snoc },
232 };
233
234 static struct qcom_icc_node qxm_crypto = {
235 .name = "qxm_crypto",
236 .channels = 1,
237 .buswidth = 8,
238 .num_links = 1,
239 .link_nodes = { &qns_a2noc_snoc },
240 };
241
242 static struct qcom_icc_node qxm_ipa = {
243 .name = "qxm_ipa",
244 .channels = 1,
245 .buswidth = 8,
246 .num_links = 1,
247 .link_nodes = { &qns_a2noc_snoc },
248 };
249
250 static struct qcom_icc_node xm_pcie3_0 = {
251 .name = "xm_pcie3_0",
252 .channels = 1,
253 .buswidth = 8,
254 .num_links = 1,
255 .link_nodes = { &qns_pcie_gemnoc },
256 };
257
258 static struct qcom_icc_node xm_qdss_etr = {
259 .name = "xm_qdss_etr",
260 .channels = 1,
261 .buswidth = 8,
262 .num_links = 1,
263 .link_nodes = { &qns_a2noc_snoc },
264 };
265
266 static struct qcom_icc_node xm_usb3_0 = {
267 .name = "xm_usb3_0",
268 .channels = 1,
269 .buswidth = 8,
270 .num_links = 1,
271 .link_nodes = { &qns_a2noc_snoc },
272 };
273
274 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
275 .name = "qxm_camnoc_hf0_uncomp",
276 .channels = 2,
277 .buswidth = 32,
278 .num_links = 1,
279 .link_nodes = { &qns_camnoc_uncomp },
280 };
281
282 static struct qcom_icc_node qxm_camnoc_rt_uncomp = {
283 .name = "qxm_camnoc_rt_uncomp",
284 .channels = 1,
285 .buswidth = 32,
286 .num_links = 1,
287 .link_nodes = { &qns_camnoc_uncomp },
288 };
289
290 static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
291 .name = "qxm_camnoc_sf_uncomp",
292 .channels = 1,
293 .buswidth = 32,
294 .num_links = 1,
295 .link_nodes = { &qns_camnoc_uncomp },
296 };
297
298 static struct qcom_icc_node qxm_camnoc_nrt_uncomp = {
299 .name = "qxm_camnoc_nrt_uncomp",
300 .channels = 1,
301 .buswidth = 32,
302 .num_links = 1,
303 .link_nodes = { &qns_camnoc_uncomp },
304 };
305
306 static struct qcom_icc_node qnm_npu = {
307 .name = "qnm_npu",
308 .channels = 1,
309 .buswidth = 32,
310 .num_links = 1,
311 .link_nodes = { &qns_cdsp_gemnoc },
312 };
313
314 static struct qcom_icc_node qhm_spdm = {
315 .name = "qhm_spdm",
316 .channels = 1,
317 .buswidth = 4,
318 .num_links = 1,
319 .link_nodes = { &qns_cnoc_a2noc },
320 };
321
322 static struct qcom_icc_node qnm_snoc = {
323 .name = "qnm_snoc",
324 .channels = 1,
325 .buswidth = 8,
326 .num_links = 47,
327 .link_nodes = { &qhs_tlmm_south,
328 &qhs_camera_cfg,
329 &qhs_sdc4,
330 &qhs_sdc2,
331 &qhs_mnoc_cfg,
332 &qhs_ufs_mem_cfg,
333 &qhs_qupv3_center,
334 &qhs_glm,
335 &qhs_pdm,
336 &qhs_camera_nrt_thrott_cfg,
337 &qhs_a2_noc_cfg,
338 &qhs_qdss_cfg,
339 &qhs_camera_rt_throttle_cfg,
340 &qhs_display_cfg,
341 &qhs_pcie_cfg,
342 &qhs_display_throttle_cfg,
343 &qhs_tcsr,
344 &qhs_venus_cvp_throttle_cfg,
345 &qhs_ddrss_cfg,
346 &qhs_ahb2phy_north,
347 &qhs_snoc_cfg,
348 &qhs_gpuss_cfg,
349 &qhs_venus_cfg,
350 &qhs_tsif,
351 &qhs_compute_dsp_cfg,
352 &qhs_clk_ctl,
353 &qhs_aop,
354 &qhs_qupv3_north,
355 &qhs_ahb2phy_south,
356 &srvc_cnoc,
357 &qhs_ahb2phy_west,
358 &qhs_usb3_0,
359 &qhs_venus_throttle_cfg,
360 &qhs_ipa,
361 &qhs_cpr_cx,
362 &qhs_tlmm_west,
363 &qhs_a1_noc_cfg,
364 &qhs_aoss,
365 &qhs_prng,
366 &qhs_vsense_ctrl_cfg,
367 &qhs_emmc_cfg,
368 &qhs_spdm,
369 &qhs_crypto0_cfg,
370 &qhs_pimem_cfg,
371 &qhs_tlmm_north,
372 &qhs_cpr_mx,
373 &qhs_imem_cfg },
374 };
375
376 static struct qcom_icc_node xm_qdss_dap = {
377 .name = "xm_qdss_dap",
378 .channels = 1,
379 .buswidth = 8,
380 .num_links = 48,
381 .link_nodes = { &qhs_tlmm_south,
382 &qhs_camera_cfg,
383 &qhs_sdc4,
384 &qhs_sdc2,
385 &qhs_mnoc_cfg,
386 &qhs_ufs_mem_cfg,
387 &qhs_qupv3_center,
388 &qhs_glm,
389 &qhs_pdm,
390 &qhs_camera_nrt_thrott_cfg,
391 &qhs_a2_noc_cfg,
392 &qhs_qdss_cfg,
393 &qhs_camera_rt_throttle_cfg,
394 &qhs_display_cfg,
395 &qhs_pcie_cfg,
396 &qhs_display_throttle_cfg,
397 &qhs_tcsr,
398 &qhs_venus_cvp_throttle_cfg,
399 &qhs_ddrss_cfg,
400 &qns_cnoc_a2noc,
401 &qhs_ahb2phy_north,
402 &qhs_snoc_cfg,
403 &qhs_gpuss_cfg,
404 &qhs_venus_cfg,
405 &qhs_tsif,
406 &qhs_compute_dsp_cfg,
407 &qhs_clk_ctl,
408 &qhs_aop,
409 &qhs_qupv3_north,
410 &qhs_ahb2phy_south,
411 &srvc_cnoc,
412 &qhs_ahb2phy_west,
413 &qhs_usb3_0,
414 &qhs_venus_throttle_cfg,
415 &qhs_ipa,
416 &qhs_cpr_cx,
417 &qhs_tlmm_west,
418 &qhs_a1_noc_cfg,
419 &qhs_aoss,
420 &qhs_prng,
421 &qhs_vsense_ctrl_cfg,
422 &qhs_emmc_cfg,
423 &qhs_spdm,
424 &qhs_crypto0_cfg,
425 &qhs_pimem_cfg,
426 &qhs_tlmm_north,
427 &qhs_cpr_mx,
428 &qhs_imem_cfg },
429 };
430
431 static struct qcom_icc_node qhm_cnoc_dc_noc = {
432 .name = "qhm_cnoc_dc_noc",
433 .channels = 1,
434 .buswidth = 4,
435 .num_links = 2,
436 .link_nodes = { &qhs_llcc,
437 &qhs_gemnoc },
438 };
439
440 static struct qcom_icc_node acm_apps = {
441 .name = "acm_apps",
442 .channels = 1,
443 .buswidth = 16,
444 .num_links = 2,
445 .link_nodes = { &qns_llcc,
446 &qns_gem_noc_snoc },
447 };
448
449 static struct qcom_icc_node acm_sys_tcu = {
450 .name = "acm_sys_tcu",
451 .channels = 1,
452 .buswidth = 8,
453 .num_links = 2,
454 .link_nodes = { &qns_llcc,
455 &qns_gem_noc_snoc },
456 };
457
458 static struct qcom_icc_node qhm_gemnoc_cfg = {
459 .name = "qhm_gemnoc_cfg",
460 .channels = 1,
461 .buswidth = 4,
462 .num_links = 2,
463 .link_nodes = { &srvc_gemnoc,
464 &qhs_mdsp_ms_mpu_cfg },
465 };
466
467 static struct qcom_icc_node qnm_cmpnoc = {
468 .name = "qnm_cmpnoc",
469 .channels = 1,
470 .buswidth = 32,
471 .num_links = 2,
472 .link_nodes = { &qns_llcc,
473 &qns_gem_noc_snoc },
474 };
475
476 static struct qcom_icc_node qnm_mnoc_hf = {
477 .name = "qnm_mnoc_hf",
478 .channels = 2,
479 .buswidth = 32,
480 .num_links = 1,
481 .link_nodes = { &qns_llcc },
482 };
483
484 static struct qcom_icc_node qnm_mnoc_sf = {
485 .name = "qnm_mnoc_sf",
486 .channels = 1,
487 .buswidth = 32,
488 .num_links = 2,
489 .link_nodes = { &qns_llcc,
490 &qns_gem_noc_snoc },
491 };
492
493 static struct qcom_icc_node qnm_pcie = {
494 .name = "qnm_pcie",
495 .channels = 1,
496 .buswidth = 8,
497 .num_links = 2,
498 .link_nodes = { &qns_llcc,
499 &qns_gem_noc_snoc },
500 };
501
502 static struct qcom_icc_node qnm_snoc_gc = {
503 .name = "qnm_snoc_gc",
504 .channels = 1,
505 .buswidth = 8,
506 .num_links = 1,
507 .link_nodes = { &qns_llcc },
508 };
509
510 static struct qcom_icc_node qnm_snoc_sf = {
511 .name = "qnm_snoc_sf",
512 .channels = 1,
513 .buswidth = 16,
514 .num_links = 1,
515 .link_nodes = { &qns_llcc },
516 };
517
518 static struct qcom_icc_node qxm_gpu = {
519 .name = "qxm_gpu",
520 .channels = 2,
521 .buswidth = 32,
522 .num_links = 2,
523 .link_nodes = { &qns_llcc,
524 &qns_gem_noc_snoc },
525 };
526
527 static struct qcom_icc_node llcc_mc = {
528 .name = "llcc_mc",
529 .channels = 2,
530 .buswidth = 4,
531 .num_links = 1,
532 .link_nodes = { &ebi },
533 };
534
535 static struct qcom_icc_node qhm_mnoc_cfg = {
536 .name = "qhm_mnoc_cfg",
537 .channels = 1,
538 .buswidth = 4,
539 .num_links = 1,
540 .link_nodes = { &srvc_mnoc },
541 };
542
543 static struct qcom_icc_node qxm_camnoc_hf = {
544 .name = "qxm_camnoc_hf",
545 .channels = 2,
546 .buswidth = 32,
547 .num_links = 1,
548 .link_nodes = { &qns_mem_noc_hf },
549 };
550
551 static struct qcom_icc_node qxm_camnoc_nrt = {
552 .name = "qxm_camnoc_nrt",
553 .channels = 1,
554 .buswidth = 8,
555 .num_links = 1,
556 .link_nodes = { &qns2_mem_noc },
557 };
558
559 static struct qcom_icc_node qxm_camnoc_rt = {
560 .name = "qxm_camnoc_rt",
561 .channels = 1,
562 .buswidth = 32,
563 .num_links = 1,
564 .link_nodes = { &qns_mem_noc_hf },
565 };
566
567 static struct qcom_icc_node qxm_camnoc_sf = {
568 .name = "qxm_camnoc_sf",
569 .channels = 1,
570 .buswidth = 32,
571 .num_links = 1,
572 .link_nodes = { &qns2_mem_noc },
573 };
574
575 static struct qcom_icc_node qxm_mdp0 = {
576 .name = "qxm_mdp0",
577 .channels = 1,
578 .buswidth = 32,
579 .num_links = 1,
580 .link_nodes = { &qns_mem_noc_hf },
581 };
582
583 static struct qcom_icc_node qxm_mdp1 = {
584 .name = "qxm_mdp1",
585 .channels = 1,
586 .buswidth = 32,
587 .num_links = 1,
588 .link_nodes = { &qns_mem_noc_hf },
589 };
590
591 static struct qcom_icc_node qxm_rot = {
592 .name = "qxm_rot",
593 .channels = 1,
594 .buswidth = 32,
595 .num_links = 1,
596 .link_nodes = { &qns2_mem_noc },
597 };
598
599 static struct qcom_icc_node qxm_venus0 = {
600 .name = "qxm_venus0",
601 .channels = 1,
602 .buswidth = 32,
603 .num_links = 1,
604 .link_nodes = { &qns2_mem_noc },
605 };
606
607 static struct qcom_icc_node qxm_venus1 = {
608 .name = "qxm_venus1",
609 .channels = 1,
610 .buswidth = 32,
611 .num_links = 1,
612 .link_nodes = { &qns2_mem_noc },
613 };
614
615 static struct qcom_icc_node qxm_venus_arm9 = {
616 .name = "qxm_venus_arm9",
617 .channels = 1,
618 .buswidth = 8,
619 .num_links = 1,
620 .link_nodes = { &qns2_mem_noc },
621 };
622
623 static struct qcom_icc_node qhm_snoc_cfg = {
624 .name = "qhm_snoc_cfg",
625 .channels = 1,
626 .buswidth = 4,
627 .num_links = 1,
628 .link_nodes = { &srvc_snoc },
629 };
630
631 static struct qcom_icc_node qnm_aggre1_noc = {
632 .name = "qnm_aggre1_noc",
633 .channels = 1,
634 .buswidth = 16,
635 .num_links = 6,
636 .link_nodes = { &qns_gemnoc_sf,
637 &qxs_pimem,
638 &qxs_imem,
639 &qhs_apss,
640 &qns_cnoc,
641 &xs_qdss_stm },
642 };
643
644 static struct qcom_icc_node qnm_aggre2_noc = {
645 .name = "qnm_aggre2_noc",
646 .channels = 1,
647 .buswidth = 16,
648 .num_links = 7,
649 .link_nodes = { &qns_gemnoc_sf,
650 &qxs_pimem,
651 &qxs_imem,
652 &qhs_apss,
653 &qns_cnoc,
654 &xs_sys_tcu_cfg,
655 &xs_qdss_stm },
656 };
657
658 static struct qcom_icc_node qnm_gemnoc = {
659 .name = "qnm_gemnoc",
660 .channels = 1,
661 .buswidth = 8,
662 .num_links = 6,
663 .link_nodes = { &qxs_pimem,
664 &qxs_imem,
665 &qhs_apss,
666 &qns_cnoc,
667 &xs_sys_tcu_cfg,
668 &xs_qdss_stm },
669 };
670
671 static struct qcom_icc_node qxm_pimem = {
672 .name = "qxm_pimem",
673 .channels = 1,
674 .buswidth = 8,
675 .num_links = 2,
676 .link_nodes = { &qns_gemnoc_gc,
677 &qxs_imem },
678 };
679
680 static struct qcom_icc_node xm_gic = {
681 .name = "xm_gic",
682 .channels = 1,
683 .buswidth = 8,
684 .num_links = 2,
685 .link_nodes = { &qns_gemnoc_gc,
686 &qxs_imem },
687 };
688
689 static struct qcom_icc_node qns_a1noc_snoc = {
690 .name = "qns_a1noc_snoc",
691 .channels = 1,
692 .buswidth = 16,
693 .num_links = 1,
694 .link_nodes = { &qnm_aggre1_noc },
695 };
696
697 static struct qcom_icc_node srvc_aggre1_noc = {
698 .name = "srvc_aggre1_noc",
699 .channels = 1,
700 .buswidth = 4,
701 };
702
703 static struct qcom_icc_node qns_a2noc_snoc = {
704 .name = "qns_a2noc_snoc",
705 .channels = 1,
706 .buswidth = 16,
707 .num_links = 1,
708 .link_nodes = { &qnm_aggre2_noc },
709 };
710
711 static struct qcom_icc_node qns_pcie_gemnoc = {
712 .name = "qns_pcie_gemnoc",
713 .channels = 1,
714 .buswidth = 8,
715 .num_links = 1,
716 .link_nodes = { &qnm_pcie },
717 };
718
719 static struct qcom_icc_node srvc_aggre2_noc = {
720 .name = "srvc_aggre2_noc",
721 .channels = 1,
722 .buswidth = 4,
723 };
724
725 static struct qcom_icc_node qns_camnoc_uncomp = {
726 .name = "qns_camnoc_uncomp",
727 .channels = 1,
728 .buswidth = 32,
729 };
730
731 static struct qcom_icc_node qns_cdsp_gemnoc = {
732 .name = "qns_cdsp_gemnoc",
733 .channels = 1,
734 .buswidth = 32,
735 .num_links = 1,
736 .link_nodes = { &qnm_cmpnoc },
737 };
738
739 static struct qcom_icc_node qhs_a1_noc_cfg = {
740 .name = "qhs_a1_noc_cfg",
741 .channels = 1,
742 .buswidth = 4,
743 .num_links = 1,
744 .link_nodes = { &qhm_a1noc_cfg },
745 };
746
747 static struct qcom_icc_node qhs_a2_noc_cfg = {
748 .name = "qhs_a2_noc_cfg",
749 .channels = 1,
750 .buswidth = 4,
751 .num_links = 1,
752 .link_nodes = { &qhm_a2noc_cfg },
753 };
754
755 static struct qcom_icc_node qhs_ahb2phy_north = {
756 .name = "qhs_ahb2phy_north",
757 .channels = 1,
758 .buswidth = 4,
759 };
760
761 static struct qcom_icc_node qhs_ahb2phy_south = {
762 .name = "qhs_ahb2phy_south",
763 .channels = 1,
764 .buswidth = 4,
765 };
766
767 static struct qcom_icc_node qhs_ahb2phy_west = {
768 .name = "qhs_ahb2phy_west",
769 .channels = 1,
770 .buswidth = 4,
771 };
772
773 static struct qcom_icc_node qhs_aop = {
774 .name = "qhs_aop",
775 .channels = 1,
776 .buswidth = 4,
777 };
778
779 static struct qcom_icc_node qhs_aoss = {
780 .name = "qhs_aoss",
781 .channels = 1,
782 .buswidth = 4,
783 };
784
785 static struct qcom_icc_node qhs_camera_cfg = {
786 .name = "qhs_camera_cfg",
787 .channels = 1,
788 .buswidth = 4,
789 };
790
791 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = {
792 .name = "qhs_camera_nrt_thrott_cfg",
793 .channels = 1,
794 .buswidth = 4,
795 };
796
797 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
798 .name = "qhs_camera_rt_throttle_cfg",
799 .channels = 1,
800 .buswidth = 4,
801 };
802
803 static struct qcom_icc_node qhs_clk_ctl = {
804 .name = "qhs_clk_ctl",
805 .channels = 1,
806 .buswidth = 4,
807 };
808
809 static struct qcom_icc_node qhs_compute_dsp_cfg = {
810 .name = "qhs_compute_dsp_cfg",
811 .channels = 1,
812 .buswidth = 4,
813 };
814
815 static struct qcom_icc_node qhs_cpr_cx = {
816 .name = "qhs_cpr_cx",
817 .channels = 1,
818 .buswidth = 4,
819 };
820
821 static struct qcom_icc_node qhs_cpr_mx = {
822 .name = "qhs_cpr_mx",
823 .channels = 1,
824 .buswidth = 4,
825 };
826
827 static struct qcom_icc_node qhs_crypto0_cfg = {
828 .name = "qhs_crypto0_cfg",
829 .channels = 1,
830 .buswidth = 4,
831 };
832
833 static struct qcom_icc_node qhs_ddrss_cfg = {
834 .name = "qhs_ddrss_cfg",
835 .channels = 1,
836 .buswidth = 4,
837 .num_links = 1,
838 .link_nodes = { &qhm_cnoc_dc_noc },
839 };
840
841 static struct qcom_icc_node qhs_display_cfg = {
842 .name = "qhs_display_cfg",
843 .channels = 1,
844 .buswidth = 4,
845 };
846
847 static struct qcom_icc_node qhs_display_throttle_cfg = {
848 .name = "qhs_display_throttle_cfg",
849 .channels = 1,
850 .buswidth = 4,
851 };
852
853 static struct qcom_icc_node qhs_emmc_cfg = {
854 .name = "qhs_emmc_cfg",
855 .channels = 1,
856 .buswidth = 4,
857 };
858
859 static struct qcom_icc_node qhs_glm = {
860 .name = "qhs_glm",
861 .channels = 1,
862 .buswidth = 4,
863 };
864
865 static struct qcom_icc_node qhs_gpuss_cfg = {
866 .name = "qhs_gpuss_cfg",
867 .channels = 1,
868 .buswidth = 8,
869 };
870
871 static struct qcom_icc_node qhs_imem_cfg = {
872 .name = "qhs_imem_cfg",
873 .channels = 1,
874 .buswidth = 4,
875 };
876
877 static struct qcom_icc_node qhs_ipa = {
878 .name = "qhs_ipa",
879 .channels = 1,
880 .buswidth = 4,
881 };
882
883 static struct qcom_icc_node qhs_mnoc_cfg = {
884 .name = "qhs_mnoc_cfg",
885 .channels = 1,
886 .buswidth = 4,
887 .num_links = 1,
888 .link_nodes = { &qhm_mnoc_cfg },
889 };
890
891 static struct qcom_icc_node qhs_pcie_cfg = {
892 .name = "qhs_pcie_cfg",
893 .channels = 1,
894 .buswidth = 4,
895 };
896
897 static struct qcom_icc_node qhs_pdm = {
898 .name = "qhs_pdm",
899 .channels = 1,
900 .buswidth = 4,
901 };
902
903 static struct qcom_icc_node qhs_pimem_cfg = {
904 .name = "qhs_pimem_cfg",
905 .channels = 1,
906 .buswidth = 4,
907 };
908
909 static struct qcom_icc_node qhs_prng = {
910 .name = "qhs_prng",
911 .channels = 1,
912 .buswidth = 4,
913 };
914
915 static struct qcom_icc_node qhs_qdss_cfg = {
916 .name = "qhs_qdss_cfg",
917 .channels = 1,
918 .buswidth = 4,
919 };
920
921 static struct qcom_icc_node qhs_qupv3_center = {
922 .name = "qhs_qupv3_center",
923 .channels = 1,
924 .buswidth = 4,
925 };
926
927 static struct qcom_icc_node qhs_qupv3_north = {
928 .name = "qhs_qupv3_north",
929 .channels = 1,
930 .buswidth = 4,
931 };
932
933 static struct qcom_icc_node qhs_sdc2 = {
934 .name = "qhs_sdc2",
935 .channels = 1,
936 .buswidth = 4,
937 };
938
939 static struct qcom_icc_node qhs_sdc4 = {
940 .name = "qhs_sdc4",
941 .channels = 1,
942 .buswidth = 4,
943 };
944
945 static struct qcom_icc_node qhs_snoc_cfg = {
946 .name = "qhs_snoc_cfg",
947 .channels = 1,
948 .buswidth = 4,
949 .num_links = 1,
950 .link_nodes = { &qhm_snoc_cfg },
951 };
952
953 static struct qcom_icc_node qhs_spdm = {
954 .name = "qhs_spdm",
955 .channels = 1,
956 .buswidth = 4,
957 };
958
959 static struct qcom_icc_node qhs_tcsr = {
960 .name = "qhs_tcsr",
961 .channels = 1,
962 .buswidth = 4,
963 };
964
965 static struct qcom_icc_node qhs_tlmm_north = {
966 .name = "qhs_tlmm_north",
967 .channels = 1,
968 .buswidth = 4,
969 };
970
971 static struct qcom_icc_node qhs_tlmm_south = {
972 .name = "qhs_tlmm_south",
973 .channels = 1,
974 .buswidth = 4,
975 };
976
977 static struct qcom_icc_node qhs_tlmm_west = {
978 .name = "qhs_tlmm_west",
979 .channels = 1,
980 .buswidth = 4,
981 };
982
983 static struct qcom_icc_node qhs_tsif = {
984 .name = "qhs_tsif",
985 .channels = 1,
986 .buswidth = 4,
987 };
988
989 static struct qcom_icc_node qhs_ufs_mem_cfg = {
990 .name = "qhs_ufs_mem_cfg",
991 .channels = 1,
992 .buswidth = 4,
993 };
994
995 static struct qcom_icc_node qhs_usb3_0 = {
996 .name = "qhs_usb3_0",
997 .channels = 1,
998 .buswidth = 4,
999 };
1000
1001 static struct qcom_icc_node qhs_venus_cfg = {
1002 .name = "qhs_venus_cfg",
1003 .channels = 1,
1004 .buswidth = 4,
1005 };
1006
1007 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1008 .name = "qhs_venus_cvp_throttle_cfg",
1009 .channels = 1,
1010 .buswidth = 4,
1011 };
1012
1013 static struct qcom_icc_node qhs_venus_throttle_cfg = {
1014 .name = "qhs_venus_throttle_cfg",
1015 .channels = 1,
1016 .buswidth = 4,
1017 };
1018
1019 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1020 .name = "qhs_vsense_ctrl_cfg",
1021 .channels = 1,
1022 .buswidth = 4,
1023 };
1024
1025 static struct qcom_icc_node qns_cnoc_a2noc = {
1026 .name = "qns_cnoc_a2noc",
1027 .channels = 1,
1028 .buswidth = 8,
1029 .num_links = 1,
1030 .link_nodes = { &qnm_cnoc },
1031 };
1032
1033 static struct qcom_icc_node srvc_cnoc = {
1034 .name = "srvc_cnoc",
1035 .channels = 1,
1036 .buswidth = 4,
1037 };
1038
1039 static struct qcom_icc_node qhs_gemnoc = {
1040 .name = "qhs_gemnoc",
1041 .channels = 1,
1042 .buswidth = 4,
1043 .num_links = 1,
1044 .link_nodes = { &qhm_gemnoc_cfg },
1045 };
1046
1047 static struct qcom_icc_node qhs_llcc = {
1048 .name = "qhs_llcc",
1049 .channels = 1,
1050 .buswidth = 4,
1051 };
1052
1053 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1054 .name = "qhs_mdsp_ms_mpu_cfg",
1055 .channels = 1,
1056 .buswidth = 4,
1057 };
1058
1059 static struct qcom_icc_node qns_gem_noc_snoc = {
1060 .name = "qns_gem_noc_snoc",
1061 .channels = 1,
1062 .buswidth = 8,
1063 .num_links = 1,
1064 .link_nodes = { &qnm_gemnoc },
1065 };
1066
1067 static struct qcom_icc_node qns_llcc = {
1068 .name = "qns_llcc",
1069 .channels = 2,
1070 .buswidth = 16,
1071 .num_links = 1,
1072 .link_nodes = { &llcc_mc },
1073 };
1074
1075 static struct qcom_icc_node srvc_gemnoc = {
1076 .name = "srvc_gemnoc",
1077 .channels = 1,
1078 .buswidth = 4,
1079 };
1080
1081 static struct qcom_icc_node ebi = {
1082 .name = "ebi",
1083 .channels = 2,
1084 .buswidth = 4,
1085 };
1086
1087 static struct qcom_icc_node qns2_mem_noc = {
1088 .name = "qns2_mem_noc",
1089 .channels = 1,
1090 .buswidth = 32,
1091 .num_links = 1,
1092 .link_nodes = { &qnm_mnoc_sf },
1093 };
1094
1095 static struct qcom_icc_node qns_mem_noc_hf = {
1096 .name = "qns_mem_noc_hf",
1097 .channels = 2,
1098 .buswidth = 32,
1099 .num_links = 1,
1100 .link_nodes = { &qnm_mnoc_hf },
1101 };
1102
1103 static struct qcom_icc_node srvc_mnoc = {
1104 .name = "srvc_mnoc",
1105 .channels = 1,
1106 .buswidth = 4,
1107 };
1108
1109 static struct qcom_icc_node qhs_apss = {
1110 .name = "qhs_apss",
1111 .channels = 1,
1112 .buswidth = 8,
1113 };
1114
1115 static struct qcom_icc_node qns_cnoc = {
1116 .name = "qns_cnoc",
1117 .channels = 1,
1118 .buswidth = 8,
1119 .num_links = 1,
1120 .link_nodes = { &qnm_snoc },
1121 };
1122
1123 static struct qcom_icc_node qns_gemnoc_gc = {
1124 .name = "qns_gemnoc_gc",
1125 .channels = 1,
1126 .buswidth = 8,
1127 .num_links = 1,
1128 .link_nodes = { &qnm_snoc_gc },
1129 };
1130
1131 static struct qcom_icc_node qns_gemnoc_sf = {
1132 .name = "qns_gemnoc_sf",
1133 .channels = 1,
1134 .buswidth = 16,
1135 .num_links = 1,
1136 .link_nodes = { &qnm_snoc_sf },
1137 };
1138
1139 static struct qcom_icc_node qxs_imem = {
1140 .name = "qxs_imem",
1141 .channels = 1,
1142 .buswidth = 8,
1143 };
1144
1145 static struct qcom_icc_node qxs_pimem = {
1146 .name = "qxs_pimem",
1147 .channels = 1,
1148 .buswidth = 8,
1149 };
1150
1151 static struct qcom_icc_node srvc_snoc = {
1152 .name = "srvc_snoc",
1153 .channels = 1,
1154 .buswidth = 4,
1155 };
1156
1157 static struct qcom_icc_node xs_qdss_stm = {
1158 .name = "xs_qdss_stm",
1159 .channels = 1,
1160 .buswidth = 4,
1161 };
1162
1163 static struct qcom_icc_node xs_sys_tcu_cfg = {
1164 .name = "xs_sys_tcu_cfg",
1165 .channels = 1,
1166 .buswidth = 8,
1167 };
1168
1169 static struct qcom_icc_bcm bcm_acv = {
1170 .name = "ACV",
1171 .enable_mask = BIT(3),
1172 .keepalive = false,
1173 .num_nodes = 1,
1174 .nodes = { &ebi },
1175 };
1176
1177 static struct qcom_icc_bcm bcm_mc0 = {
1178 .name = "MC0",
1179 .keepalive = true,
1180 .num_nodes = 1,
1181 .nodes = { &ebi },
1182 };
1183
1184 static struct qcom_icc_bcm bcm_sh0 = {
1185 .name = "SH0",
1186 .keepalive = true,
1187 .num_nodes = 1,
1188 .nodes = { &qns_llcc },
1189 };
1190
1191 static struct qcom_icc_bcm bcm_mm0 = {
1192 .name = "MM0",
1193 .keepalive = true,
1194 .num_nodes = 1,
1195 .nodes = { &qns_mem_noc_hf },
1196 };
1197
1198 static struct qcom_icc_bcm bcm_mm1 = {
1199 .name = "MM1",
1200 .keepalive = true,
1201 .num_nodes = 8,
1202 .nodes = { &qxm_camnoc_hf0_uncomp,
1203 &qxm_camnoc_rt_uncomp,
1204 &qxm_camnoc_sf_uncomp,
1205 &qxm_camnoc_nrt_uncomp,
1206 &qxm_camnoc_hf,
1207 &qxm_camnoc_rt,
1208 &qxm_mdp0,
1209 &qxm_mdp1
1210 },
1211 };
1212
1213 static struct qcom_icc_bcm bcm_sh2 = {
1214 .name = "SH2",
1215 .keepalive = false,
1216 .num_nodes = 1,
1217 .nodes = { &qns_gem_noc_snoc },
1218 };
1219
1220 static struct qcom_icc_bcm bcm_sh3 = {
1221 .name = "SH3",
1222 .keepalive = false,
1223 .num_nodes = 1,
1224 .nodes = { &acm_sys_tcu },
1225 };
1226
1227 static struct qcom_icc_bcm bcm_mm2 = {
1228 .name = "MM2",
1229 .keepalive = false,
1230 .num_nodes = 2,
1231 .nodes = { &qxm_camnoc_nrt,
1232 &qns2_mem_noc
1233 },
1234 };
1235
1236 static struct qcom_icc_bcm bcm_mm3 = {
1237 .name = "MM3",
1238 .keepalive = false,
1239 .num_nodes = 5,
1240 .nodes = { &qxm_camnoc_sf,
1241 &qxm_rot,
1242 &qxm_venus0,
1243 &qxm_venus1,
1244 &qxm_venus_arm9
1245 },
1246 };
1247
1248 static struct qcom_icc_bcm bcm_sh5 = {
1249 .name = "SH5",
1250 .keepalive = false,
1251 .num_nodes = 1,
1252 .nodes = { &acm_apps },
1253 };
1254
1255 static struct qcom_icc_bcm bcm_sn0 = {
1256 .name = "SN0",
1257 .keepalive = true,
1258 .num_nodes = 1,
1259 .nodes = { &qns_gemnoc_sf },
1260 };
1261
1262 static struct qcom_icc_bcm bcm_sh8 = {
1263 .name = "SH8",
1264 .keepalive = false,
1265 .num_nodes = 1,
1266 .nodes = { &qns_cdsp_gemnoc },
1267 };
1268
1269 static struct qcom_icc_bcm bcm_sh10 = {
1270 .name = "SH10",
1271 .keepalive = false,
1272 .num_nodes = 1,
1273 .nodes = { &qnm_npu },
1274 };
1275
1276 static struct qcom_icc_bcm bcm_ce0 = {
1277 .name = "CE0",
1278 .keepalive = false,
1279 .num_nodes = 1,
1280 .nodes = { &qxm_crypto },
1281 };
1282
1283 static struct qcom_icc_bcm bcm_cn0 = {
1284 .name = "CN0",
1285 .keepalive = true,
1286 .num_nodes = 54,
1287 .nodes = { &qhm_tsif,
1288 &xm_emmc,
1289 &xm_sdc2,
1290 &xm_sdc4,
1291 &qhm_spdm,
1292 &qnm_snoc,
1293 &qhs_a1_noc_cfg,
1294 &qhs_a2_noc_cfg,
1295 &qhs_ahb2phy_north,
1296 &qhs_ahb2phy_south,
1297 &qhs_ahb2phy_west,
1298 &qhs_aop,
1299 &qhs_aoss,
1300 &qhs_camera_cfg,
1301 &qhs_camera_nrt_thrott_cfg,
1302 &qhs_camera_rt_throttle_cfg,
1303 &qhs_clk_ctl,
1304 &qhs_compute_dsp_cfg,
1305 &qhs_cpr_cx,
1306 &qhs_cpr_mx,
1307 &qhs_crypto0_cfg,
1308 &qhs_ddrss_cfg,
1309 &qhs_display_cfg,
1310 &qhs_display_throttle_cfg,
1311 &qhs_emmc_cfg,
1312 &qhs_glm,
1313 &qhs_gpuss_cfg,
1314 &qhs_imem_cfg,
1315 &qhs_ipa,
1316 &qhs_mnoc_cfg,
1317 &qhs_pcie_cfg,
1318 &qhs_pdm,
1319 &qhs_pimem_cfg,
1320 &qhs_prng,
1321 &qhs_qdss_cfg,
1322 &qhs_qupv3_center,
1323 &qhs_qupv3_north,
1324 &qhs_sdc2,
1325 &qhs_sdc4,
1326 &qhs_snoc_cfg,
1327 &qhs_spdm,
1328 &qhs_tcsr,
1329 &qhs_tlmm_north,
1330 &qhs_tlmm_south,
1331 &qhs_tlmm_west,
1332 &qhs_tsif,
1333 &qhs_ufs_mem_cfg,
1334 &qhs_usb3_0,
1335 &qhs_venus_cfg,
1336 &qhs_venus_cvp_throttle_cfg,
1337 &qhs_venus_throttle_cfg,
1338 &qhs_vsense_ctrl_cfg,
1339 &qns_cnoc_a2noc,
1340 &srvc_cnoc
1341 },
1342 };
1343
1344 static struct qcom_icc_bcm bcm_qup0 = {
1345 .name = "QUP0",
1346 .keepalive = false,
1347 .num_nodes = 2,
1348 .nodes = { &qhm_qup_center,
1349 &qhm_qup_north
1350 },
1351 };
1352
1353 static struct qcom_icc_bcm bcm_sn1 = {
1354 .name = "SN1",
1355 .keepalive = false,
1356 .num_nodes = 1,
1357 .nodes = { &qxs_imem },
1358 };
1359
1360 static struct qcom_icc_bcm bcm_sn2 = {
1361 .name = "SN2",
1362 .keepalive = false,
1363 .num_nodes = 1,
1364 .nodes = { &qns_gemnoc_gc },
1365 };
1366
1367 static struct qcom_icc_bcm bcm_sn4 = {
1368 .name = "SN4",
1369 .keepalive = false,
1370 .num_nodes = 1,
1371 .nodes = { &qxs_pimem },
1372 };
1373
1374 static struct qcom_icc_bcm bcm_sn9 = {
1375 .name = "SN9",
1376 .keepalive = false,
1377 .num_nodes = 2,
1378 .nodes = { &qnm_aggre1_noc,
1379 &qns_a1noc_snoc
1380 },
1381 };
1382
1383 static struct qcom_icc_bcm bcm_sn11 = {
1384 .name = "SN11",
1385 .keepalive = false,
1386 .num_nodes = 2,
1387 .nodes = { &qnm_aggre2_noc,
1388 &qns_a2noc_snoc
1389 },
1390 };
1391
1392 static struct qcom_icc_bcm bcm_sn12 = {
1393 .name = "SN12",
1394 .keepalive = false,
1395 .num_nodes = 2,
1396 .nodes = { &qxm_pimem,
1397 &xm_gic
1398 },
1399 };
1400
1401 static struct qcom_icc_bcm bcm_sn14 = {
1402 .name = "SN14",
1403 .keepalive = false,
1404 .num_nodes = 1,
1405 .nodes = { &qns_pcie_gemnoc },
1406 };
1407
1408 static struct qcom_icc_bcm bcm_sn15 = {
1409 .name = "SN15",
1410 .keepalive = false,
1411 .num_nodes = 1,
1412 .nodes = { &qnm_gemnoc },
1413 };
1414
1415 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1416 &bcm_cn0,
1417 &bcm_qup0,
1418 &bcm_sn9,
1419 };
1420
1421 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1422 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1423 [MASTER_QUP_0] = &qhm_qup_center,
1424 [MASTER_TSIF] = &qhm_tsif,
1425 [MASTER_EMMC] = &xm_emmc,
1426 [MASTER_SDCC_2] = &xm_sdc2,
1427 [MASTER_SDCC_4] = &xm_sdc4,
1428 [MASTER_UFS_MEM] = &xm_ufs_mem,
1429 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
1430 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1431 };
1432
1433 static const struct qcom_icc_desc sm7150_aggre1_noc = {
1434 .nodes = aggre1_noc_nodes,
1435 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1436 .bcms = aggre1_noc_bcms,
1437 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1438 };
1439
1440 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1441 &bcm_ce0,
1442 &bcm_qup0,
1443 &bcm_sn11,
1444 &bcm_sn14,
1445 };
1446
1447 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1448 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1449 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1450 [MASTER_QUP_1] = &qhm_qup_north,
1451 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
1452 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
1453 [MASTER_IPA] = &qxm_ipa,
1454 [MASTER_PCIE] = &xm_pcie3_0,
1455 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1456 [MASTER_USB3] = &xm_usb3_0,
1457 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
1458 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
1459 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1460 };
1461
1462 static const struct qcom_icc_desc sm7150_aggre2_noc = {
1463 .nodes = aggre2_noc_nodes,
1464 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1465 .bcms = aggre2_noc_bcms,
1466 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1467 };
1468
1469 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1470 &bcm_mm1,
1471 };
1472
1473 static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1474 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1475 [MASTER_CAMNOC_RT_UNCOMP] = &qxm_camnoc_rt_uncomp,
1476 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1477 [MASTER_CAMNOC_NRT_UNCOMP] = &qxm_camnoc_nrt_uncomp,
1478 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1479 };
1480
1481 static const struct qcom_icc_desc sm7150_camnoc_virt = {
1482 .nodes = camnoc_virt_nodes,
1483 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1484 .bcms = camnoc_virt_bcms,
1485 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1486 };
1487
1488 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1489 &bcm_sh10,
1490 &bcm_sh8,
1491 };
1492
1493 static struct qcom_icc_node * const compute_noc_nodes[] = {
1494 [MASTER_NPU] = &qnm_npu,
1495 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
1496 };
1497
1498 static const struct qcom_icc_desc sm7150_compute_noc = {
1499 .nodes = compute_noc_nodes,
1500 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
1501 .bcms = compute_noc_bcms,
1502 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
1503 };
1504
1505 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1506 &bcm_cn0,
1507 };
1508
1509 static struct qcom_icc_node * const config_noc_nodes[] = {
1510 [MASTER_SPDM] = &qhm_spdm,
1511 [SNOC_CNOC_MAS] = &qnm_snoc,
1512 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1513 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1514 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1515 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy_north,
1516 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
1517 [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west,
1518 [SLAVE_AOP] = &qhs_aop,
1519 [SLAVE_AOSS] = &qhs_aoss,
1520 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1521 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg,
1522 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1523 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1524 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
1525 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1526 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1527 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1528 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1529 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1530 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
1531 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
1532 [SLAVE_GLM] = &qhs_glm,
1533 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
1534 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1535 [SLAVE_IPA_CFG] = &qhs_ipa,
1536 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1537 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
1538 [SLAVE_PDM] = &qhs_pdm,
1539 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1540 [SLAVE_PRNG] = &qhs_prng,
1541 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1542 [SLAVE_QUP_0] = &qhs_qupv3_center,
1543 [SLAVE_QUP_1] = &qhs_qupv3_north,
1544 [SLAVE_SDCC_2] = &qhs_sdc2,
1545 [SLAVE_SDCC_4] = &qhs_sdc4,
1546 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1547 [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1548 [SLAVE_TCSR] = &qhs_tcsr,
1549 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
1550 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1551 [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
1552 [SLAVE_TSIF] = &qhs_tsif,
1553 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1554 [SLAVE_USB3] = &qhs_usb3_0,
1555 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1556 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
1557 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
1558 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1559 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1560 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1561 };
1562
1563 static const struct qcom_icc_desc sm7150_config_noc = {
1564 .nodes = config_noc_nodes,
1565 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1566 .bcms = config_noc_bcms,
1567 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1568 };
1569
1570 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1571 };
1572
1573 static struct qcom_icc_node * const dc_noc_nodes[] = {
1574 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
1575 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
1576 [SLAVE_LLCC_CFG] = &qhs_llcc,
1577 };
1578
1579 static const struct qcom_icc_desc sm7150_dc_noc = {
1580 .nodes = dc_noc_nodes,
1581 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1582 .bcms = dc_noc_bcms,
1583 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1584 };
1585
1586 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1587 &bcm_sh0,
1588 &bcm_sh2,
1589 &bcm_sh3,
1590 &bcm_sh5,
1591 };
1592
1593 static struct qcom_icc_node * const gem_noc_nodes[] = {
1594 [MASTER_AMPSS_M0] = &acm_apps,
1595 [MASTER_SYS_TCU] = &acm_sys_tcu,
1596 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1597 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1598 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1599 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1600 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
1601 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1602 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1603 [MASTER_GRAPHICS_3D] = &qxm_gpu,
1604 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1605 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1606 [SLAVE_LLCC] = &qns_llcc,
1607 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1608 };
1609
1610 static const struct qcom_icc_desc sm7150_gem_noc = {
1611 .nodes = gem_noc_nodes,
1612 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1613 .bcms = gem_noc_bcms,
1614 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1615 };
1616
1617 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1618 &bcm_acv,
1619 &bcm_mc0,
1620 };
1621
1622 static struct qcom_icc_node * const mc_virt_nodes[] = {
1623 [MASTER_LLCC] = &llcc_mc,
1624 [SLAVE_EBI_CH0] = &ebi,
1625 };
1626
1627 static const struct qcom_icc_desc sm7150_mc_virt = {
1628 .nodes = mc_virt_nodes,
1629 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1630 .bcms = mc_virt_bcms,
1631 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1632 };
1633
1634 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1635 &bcm_mm0,
1636 &bcm_mm1,
1637 &bcm_mm2,
1638 &bcm_mm3,
1639 };
1640
1641 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1642 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1643 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf,
1644 [MASTER_CAMNOC_NRT] = &qxm_camnoc_nrt,
1645 [MASTER_CAMNOC_RT] = &qxm_camnoc_rt,
1646 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1647 [MASTER_MDP_PORT0] = &qxm_mdp0,
1648 [MASTER_MDP_PORT1] = &qxm_mdp1,
1649 [MASTER_ROTATOR] = &qxm_rot,
1650 [MASTER_VIDEO_P0] = &qxm_venus0,
1651 [MASTER_VIDEO_P1] = &qxm_venus1,
1652 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1653 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1654 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1655 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1656 };
1657
1658 static const struct qcom_icc_desc sm7150_mmss_noc = {
1659 .nodes = mmss_noc_nodes,
1660 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1661 .bcms = mmss_noc_bcms,
1662 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1663 };
1664
1665 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1666 &bcm_sn0,
1667 &bcm_sn1,
1668 &bcm_sn11,
1669 &bcm_sn12,
1670 &bcm_sn15,
1671 &bcm_sn2,
1672 &bcm_sn4,
1673 &bcm_sn9,
1674 };
1675
1676 static struct qcom_icc_node * const system_noc_nodes[] = {
1677 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1678 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
1679 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
1680 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1681 [MASTER_PIMEM] = &qxm_pimem,
1682 [MASTER_GIC] = &xm_gic,
1683 [SLAVE_APPSS] = &qhs_apss,
1684 [SNOC_CNOC_SLV] = &qns_cnoc,
1685 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1686 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1687 [SLAVE_OCIMEM] = &qxs_imem,
1688 [SLAVE_PIMEM] = &qxs_pimem,
1689 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1690 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1691 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1692 };
1693
1694 static const struct qcom_icc_desc sm7150_system_noc = {
1695 .nodes = system_noc_nodes,
1696 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1697 .bcms = system_noc_bcms,
1698 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1699 };
1700
1701 static const struct of_device_id qnoc_of_match[] = {
1702 { .compatible = "qcom,sm7150-aggre1-noc", .data = &sm7150_aggre1_noc },
1703 { .compatible = "qcom,sm7150-aggre2-noc", .data = &sm7150_aggre2_noc },
1704 { .compatible = "qcom,sm7150-camnoc-virt", .data = &sm7150_camnoc_virt },
1705 { .compatible = "qcom,sm7150-compute-noc", .data = &sm7150_compute_noc },
1706 { .compatible = "qcom,sm7150-config-noc", .data = &sm7150_config_noc },
1707 { .compatible = "qcom,sm7150-dc-noc", .data = &sm7150_dc_noc },
1708 { .compatible = "qcom,sm7150-gem-noc", .data = &sm7150_gem_noc },
1709 { .compatible = "qcom,sm7150-mc-virt", .data = &sm7150_mc_virt },
1710 { .compatible = "qcom,sm7150-mmss-noc", .data = &sm7150_mmss_noc },
1711 { .compatible = "qcom,sm7150-system-noc", .data = &sm7150_system_noc },
1712 { }
1713 };
1714 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1715
1716 static struct platform_driver qnoc_driver = {
1717 .probe = qcom_icc_rpmh_probe,
1718 .remove = qcom_icc_rpmh_remove,
1719 .driver = {
1720 .name = "qnoc-sm7150",
1721 .of_match_table = qnoc_of_match,
1722 .sync_state = icc_sync_state,
1723 },
1724 };
1725
qnoc_driver_init(void)1726 static int __init qnoc_driver_init(void)
1727 {
1728 return platform_driver_register(&qnoc_driver);
1729 }
1730 core_initcall(qnoc_driver_init);
1731
qnoc_driver_exit(void)1732 static void __exit qnoc_driver_exit(void)
1733 {
1734 platform_driver_unregister(&qnoc_driver);
1735 }
1736 module_exit(qnoc_driver_exit);
1737
1738 MODULE_DESCRIPTION("Qualcomm SM7150 NoC driver");
1739 MODULE_LICENSE("GPL");
1740