1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10
11 #include "pinctrl-msm.h"
12
13 #define REG_SIZE 0x1000
14 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
15 { \
16 .grp = PINCTRL_PINGROUP("gpio" #id, \
17 gpio##id##_pins, \
18 ARRAY_SIZE(gpio##id##_pins)), \
19 .funcs = (int[]){ \
20 msm_mux_gpio, /* gpio mode */ \
21 msm_mux_##f1, \
22 msm_mux_##f2, \
23 msm_mux_##f3, \
24 msm_mux_##f4, \
25 msm_mux_##f5, \
26 msm_mux_##f6, \
27 msm_mux_##f7, \
28 msm_mux_##f8, \
29 msm_mux_##f9 \
30 }, \
31 .nfuncs = 10, \
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
37 .mux_bit = 2, \
38 .pull_bit = 0, \
39 .drv_bit = 6, \
40 .oe_bit = 9, \
41 .in_bit = 0, \
42 .out_bit = 1, \
43 .intr_enable_bit = 0, \
44 .intr_status_bit = 0, \
45 .intr_target_bit = 5, \
46 .intr_target_kpss_val = 3, \
47 .intr_raw_status_bit = 4, \
48 .intr_polarity_bit = 1, \
49 .intr_detection_bit = 2, \
50 .intr_detection_width = 2, \
51 }
52
53 #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
54 { \
55 .grp = PINCTRL_PINGROUP(#pg_name, \
56 pg_name##_pins, \
57 ARRAY_SIZE(pg_name##_pins)), \
58 .ctl_reg = ctl, \
59 .io_reg = 0, \
60 .intr_cfg_reg = 0, \
61 .intr_status_reg = 0, \
62 .intr_target_reg = 0, \
63 .mux_bit = -1, \
64 .pull_bit = pull, \
65 .drv_bit = drv, \
66 .oe_bit = -1, \
67 .in_bit = -1, \
68 .out_bit = -1, \
69 .intr_enable_bit = -1, \
70 .intr_status_bit = -1, \
71 .intr_target_bit = -1, \
72 .intr_raw_status_bit = -1, \
73 .intr_polarity_bit = -1, \
74 .intr_detection_bit = -1, \
75 .intr_detection_width = -1, \
76 }
77
78 #define UFS_RESET(pg_name, offset) \
79 { \
80 .grp = PINCTRL_PINGROUP(#pg_name, \
81 pg_name##_pins, \
82 ARRAY_SIZE(pg_name##_pins)), \
83 .ctl_reg = offset, \
84 .io_reg = offset + 0x4, \
85 .intr_cfg_reg = 0, \
86 .intr_status_reg = 0, \
87 .intr_target_reg = 0, \
88 .mux_bit = -1, \
89 .pull_bit = 3, \
90 .drv_bit = 0, \
91 .oe_bit = -1, \
92 .in_bit = -1, \
93 .out_bit = 0, \
94 .intr_enable_bit = -1, \
95 .intr_status_bit = -1, \
96 .intr_target_bit = -1, \
97 .intr_raw_status_bit = -1, \
98 .intr_polarity_bit = -1, \
99 .intr_detection_bit = -1, \
100 .intr_detection_width = -1, \
101 }
102 static const struct pinctrl_pin_desc sm6350_pins[] = {
103 PINCTRL_PIN(0, "GPIO_0"),
104 PINCTRL_PIN(1, "GPIO_1"),
105 PINCTRL_PIN(2, "GPIO_2"),
106 PINCTRL_PIN(3, "GPIO_3"),
107 PINCTRL_PIN(4, "GPIO_4"),
108 PINCTRL_PIN(5, "GPIO_5"),
109 PINCTRL_PIN(6, "GPIO_6"),
110 PINCTRL_PIN(7, "GPIO_7"),
111 PINCTRL_PIN(8, "GPIO_8"),
112 PINCTRL_PIN(9, "GPIO_9"),
113 PINCTRL_PIN(10, "GPIO_10"),
114 PINCTRL_PIN(11, "GPIO_11"),
115 PINCTRL_PIN(12, "GPIO_12"),
116 PINCTRL_PIN(13, "GPIO_13"),
117 PINCTRL_PIN(14, "GPIO_14"),
118 PINCTRL_PIN(15, "GPIO_15"),
119 PINCTRL_PIN(16, "GPIO_16"),
120 PINCTRL_PIN(17, "GPIO_17"),
121 PINCTRL_PIN(18, "GPIO_18"),
122 PINCTRL_PIN(19, "GPIO_19"),
123 PINCTRL_PIN(20, "GPIO_20"),
124 PINCTRL_PIN(21, "GPIO_21"),
125 PINCTRL_PIN(22, "GPIO_22"),
126 PINCTRL_PIN(23, "GPIO_23"),
127 PINCTRL_PIN(24, "GPIO_24"),
128 PINCTRL_PIN(25, "GPIO_25"),
129 PINCTRL_PIN(26, "GPIO_26"),
130 PINCTRL_PIN(27, "GPIO_27"),
131 PINCTRL_PIN(28, "GPIO_28"),
132 PINCTRL_PIN(29, "GPIO_29"),
133 PINCTRL_PIN(30, "GPIO_30"),
134 PINCTRL_PIN(31, "GPIO_31"),
135 PINCTRL_PIN(32, "GPIO_32"),
136 PINCTRL_PIN(33, "GPIO_33"),
137 PINCTRL_PIN(34, "GPIO_34"),
138 PINCTRL_PIN(35, "GPIO_35"),
139 PINCTRL_PIN(36, "GPIO_36"),
140 PINCTRL_PIN(37, "GPIO_37"),
141 PINCTRL_PIN(38, "GPIO_38"),
142 PINCTRL_PIN(39, "GPIO_39"),
143 PINCTRL_PIN(40, "GPIO_40"),
144 PINCTRL_PIN(41, "GPIO_41"),
145 PINCTRL_PIN(42, "GPIO_42"),
146 PINCTRL_PIN(43, "GPIO_43"),
147 PINCTRL_PIN(44, "GPIO_44"),
148 PINCTRL_PIN(45, "GPIO_45"),
149 PINCTRL_PIN(46, "GPIO_46"),
150 PINCTRL_PIN(47, "GPIO_47"),
151 PINCTRL_PIN(48, "GPIO_48"),
152 PINCTRL_PIN(49, "GPIO_49"),
153 PINCTRL_PIN(50, "GPIO_50"),
154 PINCTRL_PIN(51, "GPIO_51"),
155 PINCTRL_PIN(52, "GPIO_52"),
156 PINCTRL_PIN(53, "GPIO_53"),
157 PINCTRL_PIN(54, "GPIO_54"),
158 PINCTRL_PIN(55, "GPIO_55"),
159 PINCTRL_PIN(56, "GPIO_56"),
160 PINCTRL_PIN(57, "GPIO_57"),
161 PINCTRL_PIN(58, "GPIO_58"),
162 PINCTRL_PIN(59, "GPIO_59"),
163 PINCTRL_PIN(60, "GPIO_60"),
164 PINCTRL_PIN(61, "GPIO_61"),
165 PINCTRL_PIN(62, "GPIO_62"),
166 PINCTRL_PIN(63, "GPIO_63"),
167 PINCTRL_PIN(64, "GPIO_64"),
168 PINCTRL_PIN(65, "GPIO_65"),
169 PINCTRL_PIN(66, "GPIO_66"),
170 PINCTRL_PIN(67, "GPIO_67"),
171 PINCTRL_PIN(68, "GPIO_68"),
172 PINCTRL_PIN(69, "GPIO_69"),
173 PINCTRL_PIN(70, "GPIO_70"),
174 PINCTRL_PIN(71, "GPIO_71"),
175 PINCTRL_PIN(72, "GPIO_72"),
176 PINCTRL_PIN(73, "GPIO_73"),
177 PINCTRL_PIN(74, "GPIO_74"),
178 PINCTRL_PIN(75, "GPIO_75"),
179 PINCTRL_PIN(76, "GPIO_76"),
180 PINCTRL_PIN(77, "GPIO_77"),
181 PINCTRL_PIN(78, "GPIO_78"),
182 PINCTRL_PIN(79, "GPIO_79"),
183 PINCTRL_PIN(80, "GPIO_80"),
184 PINCTRL_PIN(81, "GPIO_81"),
185 PINCTRL_PIN(82, "GPIO_82"),
186 PINCTRL_PIN(83, "GPIO_83"),
187 PINCTRL_PIN(84, "GPIO_84"),
188 PINCTRL_PIN(85, "GPIO_85"),
189 PINCTRL_PIN(86, "GPIO_86"),
190 PINCTRL_PIN(87, "GPIO_87"),
191 PINCTRL_PIN(88, "GPIO_88"),
192 PINCTRL_PIN(89, "GPIO_89"),
193 PINCTRL_PIN(90, "GPIO_90"),
194 PINCTRL_PIN(91, "GPIO_91"),
195 PINCTRL_PIN(92, "GPIO_92"),
196 PINCTRL_PIN(93, "GPIO_93"),
197 PINCTRL_PIN(94, "GPIO_94"),
198 PINCTRL_PIN(95, "GPIO_95"),
199 PINCTRL_PIN(96, "GPIO_96"),
200 PINCTRL_PIN(97, "GPIO_97"),
201 PINCTRL_PIN(98, "GPIO_98"),
202 PINCTRL_PIN(99, "GPIO_99"),
203 PINCTRL_PIN(100, "GPIO_100"),
204 PINCTRL_PIN(101, "GPIO_101"),
205 PINCTRL_PIN(102, "GPIO_102"),
206 PINCTRL_PIN(103, "GPIO_103"),
207 PINCTRL_PIN(104, "GPIO_104"),
208 PINCTRL_PIN(105, "GPIO_105"),
209 PINCTRL_PIN(106, "GPIO_106"),
210 PINCTRL_PIN(107, "GPIO_107"),
211 PINCTRL_PIN(108, "GPIO_108"),
212 PINCTRL_PIN(109, "GPIO_109"),
213 PINCTRL_PIN(110, "GPIO_110"),
214 PINCTRL_PIN(111, "GPIO_111"),
215 PINCTRL_PIN(112, "GPIO_112"),
216 PINCTRL_PIN(113, "GPIO_113"),
217 PINCTRL_PIN(114, "GPIO_114"),
218 PINCTRL_PIN(115, "GPIO_115"),
219 PINCTRL_PIN(116, "GPIO_116"),
220 PINCTRL_PIN(117, "GPIO_117"),
221 PINCTRL_PIN(118, "GPIO_118"),
222 PINCTRL_PIN(119, "GPIO_119"),
223 PINCTRL_PIN(120, "GPIO_120"),
224 PINCTRL_PIN(121, "GPIO_121"),
225 PINCTRL_PIN(122, "GPIO_122"),
226 PINCTRL_PIN(123, "GPIO_123"),
227 PINCTRL_PIN(124, "GPIO_124"),
228 PINCTRL_PIN(125, "GPIO_125"),
229 PINCTRL_PIN(126, "GPIO_126"),
230 PINCTRL_PIN(127, "GPIO_127"),
231 PINCTRL_PIN(128, "GPIO_128"),
232 PINCTRL_PIN(129, "GPIO_129"),
233 PINCTRL_PIN(130, "GPIO_130"),
234 PINCTRL_PIN(131, "GPIO_131"),
235 PINCTRL_PIN(132, "GPIO_132"),
236 PINCTRL_PIN(133, "GPIO_133"),
237 PINCTRL_PIN(134, "GPIO_134"),
238 PINCTRL_PIN(135, "GPIO_135"),
239 PINCTRL_PIN(136, "GPIO_136"),
240 PINCTRL_PIN(137, "GPIO_137"),
241 PINCTRL_PIN(138, "GPIO_138"),
242 PINCTRL_PIN(139, "GPIO_139"),
243 PINCTRL_PIN(140, "GPIO_140"),
244 PINCTRL_PIN(141, "GPIO_141"),
245 PINCTRL_PIN(142, "GPIO_142"),
246 PINCTRL_PIN(143, "GPIO_143"),
247 PINCTRL_PIN(144, "GPIO_144"),
248 PINCTRL_PIN(145, "GPIO_145"),
249 PINCTRL_PIN(146, "GPIO_146"),
250 PINCTRL_PIN(147, "GPIO_147"),
251 PINCTRL_PIN(148, "GPIO_148"),
252 PINCTRL_PIN(149, "GPIO_149"),
253 PINCTRL_PIN(150, "GPIO_150"),
254 PINCTRL_PIN(151, "GPIO_151"),
255 PINCTRL_PIN(152, "GPIO_152"),
256 PINCTRL_PIN(153, "GPIO_153"),
257 PINCTRL_PIN(154, "GPIO_154"),
258 PINCTRL_PIN(155, "GPIO_155"),
259 PINCTRL_PIN(156, "UFS_RESET"),
260 PINCTRL_PIN(157, "SDC1_RCLK"),
261 PINCTRL_PIN(158, "SDC1_CLK"),
262 PINCTRL_PIN(159, "SDC1_CMD"),
263 PINCTRL_PIN(160, "SDC1_DATA"),
264 PINCTRL_PIN(161, "SDC2_CLK"),
265 PINCTRL_PIN(162, "SDC2_CMD"),
266 PINCTRL_PIN(163, "SDC2_DATA"),
267 };
268
269 #define DECLARE_MSM_GPIO_PINS(pin) \
270 static const unsigned int gpio##pin##_pins[] = { pin }
271 DECLARE_MSM_GPIO_PINS(0);
272 DECLARE_MSM_GPIO_PINS(1);
273 DECLARE_MSM_GPIO_PINS(2);
274 DECLARE_MSM_GPIO_PINS(3);
275 DECLARE_MSM_GPIO_PINS(4);
276 DECLARE_MSM_GPIO_PINS(5);
277 DECLARE_MSM_GPIO_PINS(6);
278 DECLARE_MSM_GPIO_PINS(7);
279 DECLARE_MSM_GPIO_PINS(8);
280 DECLARE_MSM_GPIO_PINS(9);
281 DECLARE_MSM_GPIO_PINS(10);
282 DECLARE_MSM_GPIO_PINS(11);
283 DECLARE_MSM_GPIO_PINS(12);
284 DECLARE_MSM_GPIO_PINS(13);
285 DECLARE_MSM_GPIO_PINS(14);
286 DECLARE_MSM_GPIO_PINS(15);
287 DECLARE_MSM_GPIO_PINS(16);
288 DECLARE_MSM_GPIO_PINS(17);
289 DECLARE_MSM_GPIO_PINS(18);
290 DECLARE_MSM_GPIO_PINS(19);
291 DECLARE_MSM_GPIO_PINS(20);
292 DECLARE_MSM_GPIO_PINS(21);
293 DECLARE_MSM_GPIO_PINS(22);
294 DECLARE_MSM_GPIO_PINS(23);
295 DECLARE_MSM_GPIO_PINS(24);
296 DECLARE_MSM_GPIO_PINS(25);
297 DECLARE_MSM_GPIO_PINS(26);
298 DECLARE_MSM_GPIO_PINS(27);
299 DECLARE_MSM_GPIO_PINS(28);
300 DECLARE_MSM_GPIO_PINS(29);
301 DECLARE_MSM_GPIO_PINS(30);
302 DECLARE_MSM_GPIO_PINS(31);
303 DECLARE_MSM_GPIO_PINS(32);
304 DECLARE_MSM_GPIO_PINS(33);
305 DECLARE_MSM_GPIO_PINS(34);
306 DECLARE_MSM_GPIO_PINS(35);
307 DECLARE_MSM_GPIO_PINS(36);
308 DECLARE_MSM_GPIO_PINS(37);
309 DECLARE_MSM_GPIO_PINS(38);
310 DECLARE_MSM_GPIO_PINS(39);
311 DECLARE_MSM_GPIO_PINS(40);
312 DECLARE_MSM_GPIO_PINS(41);
313 DECLARE_MSM_GPIO_PINS(42);
314 DECLARE_MSM_GPIO_PINS(43);
315 DECLARE_MSM_GPIO_PINS(44);
316 DECLARE_MSM_GPIO_PINS(45);
317 DECLARE_MSM_GPIO_PINS(46);
318 DECLARE_MSM_GPIO_PINS(47);
319 DECLARE_MSM_GPIO_PINS(48);
320 DECLARE_MSM_GPIO_PINS(49);
321 DECLARE_MSM_GPIO_PINS(50);
322 DECLARE_MSM_GPIO_PINS(51);
323 DECLARE_MSM_GPIO_PINS(52);
324 DECLARE_MSM_GPIO_PINS(53);
325 DECLARE_MSM_GPIO_PINS(54);
326 DECLARE_MSM_GPIO_PINS(55);
327 DECLARE_MSM_GPIO_PINS(56);
328 DECLARE_MSM_GPIO_PINS(57);
329 DECLARE_MSM_GPIO_PINS(58);
330 DECLARE_MSM_GPIO_PINS(59);
331 DECLARE_MSM_GPIO_PINS(60);
332 DECLARE_MSM_GPIO_PINS(61);
333 DECLARE_MSM_GPIO_PINS(62);
334 DECLARE_MSM_GPIO_PINS(63);
335 DECLARE_MSM_GPIO_PINS(64);
336 DECLARE_MSM_GPIO_PINS(65);
337 DECLARE_MSM_GPIO_PINS(66);
338 DECLARE_MSM_GPIO_PINS(67);
339 DECLARE_MSM_GPIO_PINS(68);
340 DECLARE_MSM_GPIO_PINS(69);
341 DECLARE_MSM_GPIO_PINS(70);
342 DECLARE_MSM_GPIO_PINS(71);
343 DECLARE_MSM_GPIO_PINS(72);
344 DECLARE_MSM_GPIO_PINS(73);
345 DECLARE_MSM_GPIO_PINS(74);
346 DECLARE_MSM_GPIO_PINS(75);
347 DECLARE_MSM_GPIO_PINS(76);
348 DECLARE_MSM_GPIO_PINS(77);
349 DECLARE_MSM_GPIO_PINS(78);
350 DECLARE_MSM_GPIO_PINS(79);
351 DECLARE_MSM_GPIO_PINS(80);
352 DECLARE_MSM_GPIO_PINS(81);
353 DECLARE_MSM_GPIO_PINS(82);
354 DECLARE_MSM_GPIO_PINS(83);
355 DECLARE_MSM_GPIO_PINS(84);
356 DECLARE_MSM_GPIO_PINS(85);
357 DECLARE_MSM_GPIO_PINS(86);
358 DECLARE_MSM_GPIO_PINS(87);
359 DECLARE_MSM_GPIO_PINS(88);
360 DECLARE_MSM_GPIO_PINS(89);
361 DECLARE_MSM_GPIO_PINS(90);
362 DECLARE_MSM_GPIO_PINS(91);
363 DECLARE_MSM_GPIO_PINS(92);
364 DECLARE_MSM_GPIO_PINS(93);
365 DECLARE_MSM_GPIO_PINS(94);
366 DECLARE_MSM_GPIO_PINS(95);
367 DECLARE_MSM_GPIO_PINS(96);
368 DECLARE_MSM_GPIO_PINS(97);
369 DECLARE_MSM_GPIO_PINS(98);
370 DECLARE_MSM_GPIO_PINS(99);
371 DECLARE_MSM_GPIO_PINS(100);
372 DECLARE_MSM_GPIO_PINS(101);
373 DECLARE_MSM_GPIO_PINS(102);
374 DECLARE_MSM_GPIO_PINS(103);
375 DECLARE_MSM_GPIO_PINS(104);
376 DECLARE_MSM_GPIO_PINS(105);
377 DECLARE_MSM_GPIO_PINS(106);
378 DECLARE_MSM_GPIO_PINS(107);
379 DECLARE_MSM_GPIO_PINS(108);
380 DECLARE_MSM_GPIO_PINS(109);
381 DECLARE_MSM_GPIO_PINS(110);
382 DECLARE_MSM_GPIO_PINS(111);
383 DECLARE_MSM_GPIO_PINS(112);
384 DECLARE_MSM_GPIO_PINS(113);
385 DECLARE_MSM_GPIO_PINS(114);
386 DECLARE_MSM_GPIO_PINS(115);
387 DECLARE_MSM_GPIO_PINS(116);
388 DECLARE_MSM_GPIO_PINS(117);
389 DECLARE_MSM_GPIO_PINS(118);
390 DECLARE_MSM_GPIO_PINS(119);
391 DECLARE_MSM_GPIO_PINS(120);
392 DECLARE_MSM_GPIO_PINS(121);
393 DECLARE_MSM_GPIO_PINS(122);
394 DECLARE_MSM_GPIO_PINS(123);
395 DECLARE_MSM_GPIO_PINS(124);
396 DECLARE_MSM_GPIO_PINS(125);
397 DECLARE_MSM_GPIO_PINS(126);
398 DECLARE_MSM_GPIO_PINS(127);
399 DECLARE_MSM_GPIO_PINS(128);
400 DECLARE_MSM_GPIO_PINS(129);
401 DECLARE_MSM_GPIO_PINS(130);
402 DECLARE_MSM_GPIO_PINS(131);
403 DECLARE_MSM_GPIO_PINS(132);
404 DECLARE_MSM_GPIO_PINS(133);
405 DECLARE_MSM_GPIO_PINS(134);
406 DECLARE_MSM_GPIO_PINS(135);
407 DECLARE_MSM_GPIO_PINS(136);
408 DECLARE_MSM_GPIO_PINS(137);
409 DECLARE_MSM_GPIO_PINS(138);
410 DECLARE_MSM_GPIO_PINS(139);
411 DECLARE_MSM_GPIO_PINS(140);
412 DECLARE_MSM_GPIO_PINS(141);
413 DECLARE_MSM_GPIO_PINS(142);
414 DECLARE_MSM_GPIO_PINS(143);
415 DECLARE_MSM_GPIO_PINS(144);
416 DECLARE_MSM_GPIO_PINS(145);
417 DECLARE_MSM_GPIO_PINS(146);
418 DECLARE_MSM_GPIO_PINS(147);
419 DECLARE_MSM_GPIO_PINS(148);
420 DECLARE_MSM_GPIO_PINS(149);
421 DECLARE_MSM_GPIO_PINS(150);
422 DECLARE_MSM_GPIO_PINS(151);
423 DECLARE_MSM_GPIO_PINS(152);
424 DECLARE_MSM_GPIO_PINS(153);
425 DECLARE_MSM_GPIO_PINS(154);
426 DECLARE_MSM_GPIO_PINS(155);
427
428 static const unsigned int ufs_reset_pins[] = { 156 };
429 static const unsigned int sdc1_rclk_pins[] = { 157 };
430 static const unsigned int sdc1_clk_pins[] = { 158 };
431 static const unsigned int sdc1_cmd_pins[] = { 159 };
432 static const unsigned int sdc1_data_pins[] = { 160 };
433 static const unsigned int sdc2_clk_pins[] = { 161 };
434 static const unsigned int sdc2_cmd_pins[] = { 162 };
435 static const unsigned int sdc2_data_pins[] = { 163 };
436
437 enum sm6350_functions {
438 msm_mux_adsp_ext,
439 msm_mux_agera_pll,
440 msm_mux_atest_char,
441 msm_mux_atest_char0,
442 msm_mux_atest_char1,
443 msm_mux_atest_char2,
444 msm_mux_atest_char3,
445 msm_mux_atest_tsens,
446 msm_mux_atest_tsens2,
447 msm_mux_atest_usb,
448 msm_mux_audio_ref,
449 msm_mux_btfm_slimbus,
450 msm_mux_cam_mclk0,
451 msm_mux_cam_mclk1,
452 msm_mux_cam_mclk2,
453 msm_mux_cam_mclk3,
454 msm_mux_cam_mclk4,
455 msm_mux_cci_async,
456 msm_mux_cci_i2c,
457 msm_mux_cci_timer0,
458 msm_mux_cci_timer1,
459 msm_mux_cci_timer2,
460 msm_mux_cci_timer3,
461 msm_mux_cci_timer4,
462 msm_mux_cri_trng,
463 msm_mux_dbg_out,
464 msm_mux_ddr_bist,
465 msm_mux_ddr_pxi0,
466 msm_mux_ddr_pxi1,
467 msm_mux_ddr_pxi2,
468 msm_mux_ddr_pxi3,
469 msm_mux_dp_hot,
470 msm_mux_edp_lcd,
471 msm_mux_gcc_gp1,
472 msm_mux_gcc_gp2,
473 msm_mux_gcc_gp3,
474 msm_mux_gp_pdm0,
475 msm_mux_gp_pdm1,
476 msm_mux_gp_pdm2,
477 msm_mux_gpio,
478 msm_mux_gps_tx,
479 msm_mux_ibi_i3c,
480 msm_mux_jitter_bist,
481 msm_mux_ldo_en,
482 msm_mux_ldo_update,
483 msm_mux_lpass_ext,
484 msm_mux_m_voc,
485 msm_mux_mclk,
486 msm_mux_mdp_vsync,
487 msm_mux_mdp_vsync0,
488 msm_mux_mdp_vsync1,
489 msm_mux_mdp_vsync2,
490 msm_mux_mdp_vsync3,
491 msm_mux_mi2s_0,
492 msm_mux_mi2s_1,
493 msm_mux_mi2s_2,
494 msm_mux_mss_lte,
495 msm_mux_nav_gpio,
496 msm_mux_nav_pps,
497 msm_mux_pa_indicator,
498 msm_mux_pcie0_clk,
499 msm_mux_phase_flag,
500 msm_mux_pll_bist,
501 msm_mux_pll_bypassnl,
502 msm_mux_pll_reset,
503 msm_mux_prng_rosc,
504 msm_mux_qdss_cti,
505 msm_mux_qdss_gpio,
506 msm_mux_qdss_gpio0,
507 msm_mux_qdss_gpio1,
508 msm_mux_qdss_gpio10,
509 msm_mux_qdss_gpio11,
510 msm_mux_qdss_gpio12,
511 msm_mux_qdss_gpio13,
512 msm_mux_qdss_gpio14,
513 msm_mux_qdss_gpio15,
514 msm_mux_qdss_gpio2,
515 msm_mux_qdss_gpio3,
516 msm_mux_qdss_gpio4,
517 msm_mux_qdss_gpio5,
518 msm_mux_qdss_gpio6,
519 msm_mux_qdss_gpio7,
520 msm_mux_qdss_gpio8,
521 msm_mux_qdss_gpio9,
522 msm_mux_qlink0_enable,
523 msm_mux_qlink0_request,
524 msm_mux_qlink0_wmss,
525 msm_mux_qlink1_enable,
526 msm_mux_qlink1_request,
527 msm_mux_qlink1_wmss,
528 msm_mux_qup00,
529 msm_mux_qup01,
530 msm_mux_qup02,
531 msm_mux_qup10,
532 msm_mux_qup11,
533 msm_mux_qup12,
534 msm_mux_qup13_f1,
535 msm_mux_qup13_f2,
536 msm_mux_qup14,
537 msm_mux_rffe0_clk,
538 msm_mux_rffe0_data,
539 msm_mux_rffe1_clk,
540 msm_mux_rffe1_data,
541 msm_mux_rffe2_clk,
542 msm_mux_rffe2_data,
543 msm_mux_rffe3_clk,
544 msm_mux_rffe3_data,
545 msm_mux_rffe4_clk,
546 msm_mux_rffe4_data,
547 msm_mux_sd_write,
548 msm_mux_sdc1_tb,
549 msm_mux_sdc2_tb,
550 msm_mux_sp_cmu,
551 msm_mux_tgu_ch0,
552 msm_mux_tgu_ch1,
553 msm_mux_tgu_ch2,
554 msm_mux_tgu_ch3,
555 msm_mux_tsense_pwm1,
556 msm_mux_tsense_pwm2,
557 msm_mux_uim1_clk,
558 msm_mux_uim1_data,
559 msm_mux_uim1_present,
560 msm_mux_uim1_reset,
561 msm_mux_uim2_clk,
562 msm_mux_uim2_data,
563 msm_mux_uim2_present,
564 msm_mux_uim2_reset,
565 msm_mux_usb_phy,
566 msm_mux_vfr_1,
567 msm_mux_vsense_trigger,
568 msm_mux_wlan1_adc0,
569 msm_mux_wlan1_adc1,
570 msm_mux_wlan2_adc0,
571 msm_mux_wlan2_adc1,
572 msm_mux__,
573 };
574
575 static const char * const ibi_i3c_groups[] = {
576 "gpio0", "gpio1",
577 };
578 static const char * const gpio_groups[] = {
579 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
580 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
581 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
582 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
583 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
584 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
585 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
586 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
587 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
588 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
589 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
590 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
591 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
592 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
593 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
594 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
595 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
596 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
597 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
598 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
599 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
600 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
601 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
602 "gpio153", "gpio154", "gpio155",
603 };
604 static const char * const cri_trng_groups[] = {
605 "gpio0", "gpio1", "gpio2",
606 };
607 static const char * const qup00_groups[] = {
608 "gpio0", "gpio1", "gpio2", "gpio3",
609 };
610 static const char * const cci_i2c_groups[] = {
611 "gpio2", "gpio3", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
612 "gpio44",
613 };
614 static const char * const qdss_cti_groups[] = {
615 "gpio2", "gpio3", "gpio6", "gpio7", "gpio61", "gpio62", "gpio86",
616 "gpio87",
617 };
618 static const char * const sp_cmu_groups[] = {
619 "gpio3",
620 };
621 static const char * const dbg_out_groups[] = {
622 "gpio3",
623 };
624 static const char * const qup14_groups[] = {
625 "gpio4", "gpio4", "gpio5", "gpio5",
626 };
627 static const char * const sdc1_tb_groups[] = {
628 "gpio4",
629 };
630 static const char * const sdc2_tb_groups[] = {
631 "gpio5",
632 };
633 static const char * const mdp_vsync_groups[] = {
634 "gpio6", "gpio23", "gpio24", "gpio27", "gpio28",
635 };
636 static const char * const gp_pdm1_groups[] = {
637 "gpio8", "gpio52",
638 };
639 static const char * const qdss_gpio_groups[] = {
640 "gpio8", "gpio9", "gpio63", "gpio64",
641 };
642 static const char * const m_voc_groups[] = {
643 "gpio12",
644 };
645 static const char * const dp_hot_groups[] = {
646 "gpio12", "gpio118",
647 };
648 static const char * const phase_flag_groups[] = {
649 "gpio12", "gpio17", "gpio18", "gpio34", "gpio35",
650 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40",
651 "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
652 "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
653 "gpio51", "gpio52", "gpio53", "gpio56", "gpio57",
654 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64",
655 "gpio67", "gpio68",
656 };
657 static const char * const qup10_groups[] = {
658 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
659 };
660 static const char * const pll_bypassnl_groups[] = {
661 "gpio13",
662 };
663 static const char * const pll_reset_groups[] = {
664 "gpio14",
665 };
666 static const char * const qup12_groups[] = {
667 "gpio19", "gpio19", "gpio20", "gpio20",
668 };
669 static const char * const ddr_bist_groups[] = {
670 "gpio19", "gpio20", "gpio21", "gpio22",
671 };
672 static const char * const gcc_gp2_groups[] = {
673 "gpio21",
674 };
675 static const char * const gcc_gp3_groups[] = {
676 "gpio22",
677 };
678 static const char * const edp_lcd_groups[] = {
679 "gpio23",
680 };
681 static const char * const qup13_f1_groups[] = {
682 "gpio25", "gpio26",
683 };
684 static const char * const qup13_f2_groups[] = {
685 "gpio25", "gpio26",
686 };
687 static const char * const qup11_groups[] = {
688 "gpio27", "gpio27", "gpio28", "gpio28",
689 };
690 static const char * const pll_bist_groups[] = {
691 "gpio27",
692 };
693 static const char * const qdss_gpio14_groups[] = {
694 "gpio27", "gpio36",
695 };
696 static const char * const qdss_gpio15_groups[] = {
697 "gpio28", "gpio37",
698 };
699 static const char * const cam_mclk0_groups[] = {
700 "gpio29",
701 };
702 static const char * const cam_mclk1_groups[] = {
703 "gpio30",
704 };
705 static const char * const cam_mclk2_groups[] = {
706 "gpio31",
707 };
708 static const char * const cam_mclk3_groups[] = {
709 "gpio32",
710 };
711 static const char * const cam_mclk4_groups[] = {
712 "gpio33",
713 };
714 static const char * const cci_timer0_groups[] = {
715 "gpio34",
716 };
717 static const char * const qdss_gpio12_groups[] = {
718 "gpio34", "gpio52",
719 };
720 static const char * const cci_timer1_groups[] = {
721 "gpio35",
722 };
723 static const char * const cci_async_groups[] = {
724 "gpio35", "gpio36", "gpio48", "gpio52", "gpio53",
725 };
726 static const char * const qdss_gpio13_groups[] = {
727 "gpio35", "gpio53",
728 };
729 static const char * const cci_timer2_groups[] = {
730 "gpio36",
731 };
732 static const char * const cci_timer3_groups[] = {
733 "gpio37",
734 };
735 static const char * const gp_pdm0_groups[] = {
736 "gpio37", "gpio68",
737 };
738 static const char * const cci_timer4_groups[] = {
739 "gpio38",
740 };
741 static const char * const qdss_gpio2_groups[] = {
742 "gpio38", "gpio41",
743 };
744 static const char * const qdss_gpio0_groups[] = {
745 "gpio39", "gpio65",
746 };
747 static const char * const qdss_gpio1_groups[] = {
748 "gpio40", "gpio66",
749 };
750 static const char * const qdss_gpio3_groups[] = {
751 "gpio42", "gpio47",
752 };
753 static const char * const qdss_gpio4_groups[] = {
754 "gpio43", "gpio88",
755 };
756 static const char * const qdss_gpio5_groups[] = {
757 "gpio44", "gpio89",
758 };
759 static const char * const qup02_groups[] = {
760 "gpio45", "gpio46", "gpio48", "gpio56", "gpio57",
761 };
762 static const char * const qdss_gpio6_groups[] = {
763 "gpio45", "gpio90",
764 };
765 static const char * const qdss_gpio7_groups[] = {
766 "gpio46", "gpio91",
767 };
768 static const char * const mdp_vsync0_groups[] = {
769 "gpio47",
770 };
771 static const char * const mdp_vsync1_groups[] = {
772 "gpio48",
773 };
774 static const char * const gcc_gp1_groups[] = {
775 "gpio48", "gpio58",
776 };
777 static const char * const qdss_gpio8_groups[] = {
778 "gpio48", "gpio92",
779 };
780 static const char * const vfr_1_groups[] = {
781 "gpio49",
782 };
783 static const char * const qdss_gpio9_groups[] = {
784 "gpio49", "gpio93",
785 };
786 static const char * const qdss_gpio10_groups[] = {
787 "gpio50", "gpio56",
788 };
789 static const char * const qdss_gpio11_groups[] = {
790 "gpio51", "gpio57",
791 };
792 static const char * const mdp_vsync2_groups[] = {
793 "gpio56",
794 };
795 static const char * const mdp_vsync3_groups[] = {
796 "gpio57",
797 };
798 static const char * const gp_pdm2_groups[] = {
799 "gpio57",
800 };
801 static const char * const audio_ref_groups[] = {
802 "gpio60",
803 };
804 static const char * const lpass_ext_groups[] = {
805 "gpio60", "gpio93",
806 };
807 static const char * const mi2s_2_groups[] = {
808 "gpio60", "gpio72", "gpio73", "gpio74",
809 };
810 static const char * const qup01_groups[] = {
811 "gpio61", "gpio62", "gpio63", "gpio64",
812 };
813 static const char * const tgu_ch0_groups[] = {
814 "gpio61",
815 };
816 static const char * const tgu_ch1_groups[] = {
817 "gpio62",
818 };
819 static const char * const tgu_ch2_groups[] = {
820 "gpio63",
821 };
822 static const char * const tgu_ch3_groups[] = {
823 "gpio64",
824 };
825 static const char * const mss_lte_groups[] = {
826 "gpio65", "gpio66",
827 };
828 static const char * const btfm_slimbus_groups[] = {
829 "gpio67", "gpio68", "gpio86", "gpio87",
830 };
831 static const char * const mi2s_1_groups[] = {
832 "gpio67", "gpio68", "gpio86", "gpio87",
833 };
834 static const char * const uim2_data_groups[] = {
835 "gpio75",
836 };
837 static const char * const uim2_clk_groups[] = {
838 "gpio76",
839 };
840 static const char * const uim2_reset_groups[] = {
841 "gpio77",
842 };
843 static const char * const uim2_present_groups[] = {
844 "gpio78",
845 };
846 static const char * const uim1_data_groups[] = {
847 "gpio79",
848 };
849 static const char * const uim1_clk_groups[] = {
850 "gpio80",
851 };
852 static const char * const uim1_reset_groups[] = {
853 "gpio81",
854 };
855 static const char * const uim1_present_groups[] = {
856 "gpio82",
857 };
858 static const char * const atest_usb_groups[] = {
859 "gpio83", "gpio84", "gpio85", "gpio86",
860 "gpio87", "gpio88", "gpio89", "gpio90",
861 "gpio91", "gpio92",
862 };
863 static const char * const sd_write_groups[] = {
864 "gpio85",
865 };
866 static const char * const ddr_pxi0_groups[] = {
867 "gpio86", "gpio90",
868 };
869 static const char * const adsp_ext_groups[] = {
870 "gpio87",
871 };
872 static const char * const ddr_pxi1_groups[] = {
873 "gpio87", "gpio91",
874 };
875 static const char * const mi2s_0_groups[] = {
876 "gpio88", "gpio89", "gpio90", "gpio91",
877 };
878 static const char * const ddr_pxi2_groups[] = {
879 "gpio88", "gpio92",
880 };
881 static const char * const tsense_pwm1_groups[] = {
882 "gpio88",
883 };
884 static const char * const tsense_pwm2_groups[] = {
885 "gpio88",
886 };
887 static const char * const agera_pll_groups[] = {
888 "gpio89",
889 };
890 static const char * const vsense_trigger_groups[] = {
891 "gpio89",
892 };
893 static const char * const ddr_pxi3_groups[] = {
894 "gpio89", "gpio93",
895 };
896 static const char * const jitter_bist_groups[] = {
897 "gpio90",
898 };
899 static const char * const wlan1_adc0_groups[] = {
900 "gpio90",
901 };
902 static const char * const wlan2_adc0_groups[] = {
903 "gpio91",
904 };
905 static const char * const atest_tsens_groups[] = {
906 "gpio92",
907 };
908 static const char * const wlan1_adc1_groups[] = {
909 "gpio92",
910 };
911 static const char * const mclk_groups[] = {
912 "gpio93",
913 };
914 static const char * const atest_tsens2_groups[] = {
915 "gpio93",
916 };
917 static const char * const wlan2_adc1_groups[] = {
918 "gpio93",
919 };
920 static const char * const ldo_en_groups[] = {
921 "gpio95",
922 };
923 static const char * const atest_char_groups[] = {
924 "gpio95",
925 };
926 static const char * const ldo_update_groups[] = {
927 "gpio96",
928 };
929 static const char * const atest_char0_groups[] = {
930 "gpio96",
931 };
932 static const char * const prng_rosc_groups[] = {
933 "gpio97",
934 };
935 static const char * const atest_char1_groups[] = {
936 "gpio97",
937 };
938 static const char * const atest_char2_groups[] = {
939 "gpio98",
940 };
941 static const char * const atest_char3_groups[] = {
942 "gpio99",
943 };
944 static const char * const nav_gpio_groups[] = {
945 "gpio101", "gpio102",
946 };
947 static const char * const nav_pps_groups[] = {
948 "gpio101", "gpio101", "gpio102", "gpio102",
949 };
950 static const char * const gps_tx_groups[] = {
951 "gpio101", "gpio102", "gpio107", "gpio108",
952 };
953 static const char * const qlink0_wmss_groups[] = {
954 "gpio103",
955 };
956 static const char * const qlink0_request_groups[] = {
957 "gpio104",
958 };
959 static const char * const qlink0_enable_groups[] = {
960 "gpio105",
961 };
962 static const char * const qlink1_wmss_groups[] = {
963 "gpio106",
964 };
965 static const char * const qlink1_request_groups[] = {
966 "gpio107",
967 };
968 static const char * const qlink1_enable_groups[] = {
969 "gpio108",
970 };
971 static const char * const rffe0_data_groups[] = {
972 "gpio109",
973 };
974 static const char * const rffe0_clk_groups[] = {
975 "gpio110",
976 };
977 static const char * const rffe1_data_groups[] = {
978 "gpio111",
979 };
980 static const char * const rffe1_clk_groups[] = {
981 "gpio112",
982 };
983 static const char * const rffe2_data_groups[] = {
984 "gpio113",
985 };
986 static const char * const rffe2_clk_groups[] = {
987 "gpio114",
988 };
989 static const char * const rffe3_data_groups[] = {
990 "gpio115",
991 };
992 static const char * const rffe3_clk_groups[] = {
993 "gpio116",
994 };
995 static const char * const rffe4_data_groups[] = {
996 "gpio117",
997 };
998 static const char * const rffe4_clk_groups[] = {
999 "gpio118",
1000 };
1001 static const char * const pa_indicator_groups[] = {
1002 "gpio118",
1003 };
1004 static const char * const pcie0_clk_groups[] = {
1005 "gpio122",
1006 };
1007 static const char * const usb_phy_groups[] = {
1008 "gpio124",
1009 };
1010
1011 static const struct pinfunction sm6350_functions[] = {
1012 MSM_PIN_FUNCTION(adsp_ext),
1013 MSM_PIN_FUNCTION(agera_pll),
1014 MSM_PIN_FUNCTION(atest_char),
1015 MSM_PIN_FUNCTION(atest_char0),
1016 MSM_PIN_FUNCTION(atest_char1),
1017 MSM_PIN_FUNCTION(atest_char2),
1018 MSM_PIN_FUNCTION(atest_char3),
1019 MSM_PIN_FUNCTION(atest_tsens),
1020 MSM_PIN_FUNCTION(atest_tsens2),
1021 MSM_PIN_FUNCTION(atest_usb),
1022 MSM_PIN_FUNCTION(audio_ref),
1023 MSM_PIN_FUNCTION(btfm_slimbus),
1024 MSM_PIN_FUNCTION(cam_mclk0),
1025 MSM_PIN_FUNCTION(cam_mclk1),
1026 MSM_PIN_FUNCTION(cam_mclk2),
1027 MSM_PIN_FUNCTION(cam_mclk3),
1028 MSM_PIN_FUNCTION(cam_mclk4),
1029 MSM_PIN_FUNCTION(cci_async),
1030 MSM_PIN_FUNCTION(cci_i2c),
1031 MSM_PIN_FUNCTION(cci_timer0),
1032 MSM_PIN_FUNCTION(cci_timer1),
1033 MSM_PIN_FUNCTION(cci_timer2),
1034 MSM_PIN_FUNCTION(cci_timer3),
1035 MSM_PIN_FUNCTION(cci_timer4),
1036 MSM_PIN_FUNCTION(cri_trng),
1037 MSM_PIN_FUNCTION(dbg_out),
1038 MSM_PIN_FUNCTION(ddr_bist),
1039 MSM_PIN_FUNCTION(ddr_pxi0),
1040 MSM_PIN_FUNCTION(ddr_pxi1),
1041 MSM_PIN_FUNCTION(ddr_pxi2),
1042 MSM_PIN_FUNCTION(ddr_pxi3),
1043 MSM_PIN_FUNCTION(dp_hot),
1044 MSM_PIN_FUNCTION(edp_lcd),
1045 MSM_PIN_FUNCTION(gcc_gp1),
1046 MSM_PIN_FUNCTION(gcc_gp2),
1047 MSM_PIN_FUNCTION(gcc_gp3),
1048 MSM_PIN_FUNCTION(gp_pdm0),
1049 MSM_PIN_FUNCTION(gp_pdm1),
1050 MSM_PIN_FUNCTION(gp_pdm2),
1051 MSM_PIN_FUNCTION(gpio),
1052 MSM_PIN_FUNCTION(gps_tx),
1053 MSM_PIN_FUNCTION(ibi_i3c),
1054 MSM_PIN_FUNCTION(jitter_bist),
1055 MSM_PIN_FUNCTION(ldo_en),
1056 MSM_PIN_FUNCTION(ldo_update),
1057 MSM_PIN_FUNCTION(lpass_ext),
1058 MSM_PIN_FUNCTION(m_voc),
1059 MSM_PIN_FUNCTION(mclk),
1060 MSM_PIN_FUNCTION(mdp_vsync),
1061 MSM_PIN_FUNCTION(mdp_vsync0),
1062 MSM_PIN_FUNCTION(mdp_vsync1),
1063 MSM_PIN_FUNCTION(mdp_vsync2),
1064 MSM_PIN_FUNCTION(mdp_vsync3),
1065 MSM_PIN_FUNCTION(mi2s_0),
1066 MSM_PIN_FUNCTION(mi2s_1),
1067 MSM_PIN_FUNCTION(mi2s_2),
1068 MSM_PIN_FUNCTION(mss_lte),
1069 MSM_PIN_FUNCTION(nav_gpio),
1070 MSM_PIN_FUNCTION(nav_pps),
1071 MSM_PIN_FUNCTION(pa_indicator),
1072 MSM_PIN_FUNCTION(pcie0_clk),
1073 MSM_PIN_FUNCTION(phase_flag),
1074 MSM_PIN_FUNCTION(pll_bist),
1075 MSM_PIN_FUNCTION(pll_bypassnl),
1076 MSM_PIN_FUNCTION(pll_reset),
1077 MSM_PIN_FUNCTION(prng_rosc),
1078 MSM_PIN_FUNCTION(qdss_cti),
1079 MSM_PIN_FUNCTION(qdss_gpio),
1080 MSM_PIN_FUNCTION(qdss_gpio0),
1081 MSM_PIN_FUNCTION(qdss_gpio1),
1082 MSM_PIN_FUNCTION(qdss_gpio10),
1083 MSM_PIN_FUNCTION(qdss_gpio11),
1084 MSM_PIN_FUNCTION(qdss_gpio12),
1085 MSM_PIN_FUNCTION(qdss_gpio13),
1086 MSM_PIN_FUNCTION(qdss_gpio14),
1087 MSM_PIN_FUNCTION(qdss_gpio15),
1088 MSM_PIN_FUNCTION(qdss_gpio2),
1089 MSM_PIN_FUNCTION(qdss_gpio3),
1090 MSM_PIN_FUNCTION(qdss_gpio4),
1091 MSM_PIN_FUNCTION(qdss_gpio5),
1092 MSM_PIN_FUNCTION(qdss_gpio6),
1093 MSM_PIN_FUNCTION(qdss_gpio7),
1094 MSM_PIN_FUNCTION(qdss_gpio8),
1095 MSM_PIN_FUNCTION(qdss_gpio9),
1096 MSM_PIN_FUNCTION(qlink0_enable),
1097 MSM_PIN_FUNCTION(qlink0_request),
1098 MSM_PIN_FUNCTION(qlink0_wmss),
1099 MSM_PIN_FUNCTION(qlink1_enable),
1100 MSM_PIN_FUNCTION(qlink1_request),
1101 MSM_PIN_FUNCTION(qlink1_wmss),
1102 MSM_PIN_FUNCTION(qup00),
1103 MSM_PIN_FUNCTION(qup01),
1104 MSM_PIN_FUNCTION(qup02),
1105 MSM_PIN_FUNCTION(qup10),
1106 MSM_PIN_FUNCTION(qup11),
1107 MSM_PIN_FUNCTION(qup12),
1108 MSM_PIN_FUNCTION(qup13_f1),
1109 MSM_PIN_FUNCTION(qup13_f2),
1110 MSM_PIN_FUNCTION(qup14),
1111 MSM_PIN_FUNCTION(rffe0_clk),
1112 MSM_PIN_FUNCTION(rffe0_data),
1113 MSM_PIN_FUNCTION(rffe1_clk),
1114 MSM_PIN_FUNCTION(rffe1_data),
1115 MSM_PIN_FUNCTION(rffe2_clk),
1116 MSM_PIN_FUNCTION(rffe2_data),
1117 MSM_PIN_FUNCTION(rffe3_clk),
1118 MSM_PIN_FUNCTION(rffe3_data),
1119 MSM_PIN_FUNCTION(rffe4_clk),
1120 MSM_PIN_FUNCTION(rffe4_data),
1121 MSM_PIN_FUNCTION(sd_write),
1122 MSM_PIN_FUNCTION(sdc1_tb),
1123 MSM_PIN_FUNCTION(sdc2_tb),
1124 MSM_PIN_FUNCTION(sp_cmu),
1125 MSM_PIN_FUNCTION(tgu_ch0),
1126 MSM_PIN_FUNCTION(tgu_ch1),
1127 MSM_PIN_FUNCTION(tgu_ch2),
1128 MSM_PIN_FUNCTION(tgu_ch3),
1129 MSM_PIN_FUNCTION(tsense_pwm1),
1130 MSM_PIN_FUNCTION(tsense_pwm2),
1131 MSM_PIN_FUNCTION(uim1_clk),
1132 MSM_PIN_FUNCTION(uim1_data),
1133 MSM_PIN_FUNCTION(uim1_present),
1134 MSM_PIN_FUNCTION(uim1_reset),
1135 MSM_PIN_FUNCTION(uim2_clk),
1136 MSM_PIN_FUNCTION(uim2_data),
1137 MSM_PIN_FUNCTION(uim2_present),
1138 MSM_PIN_FUNCTION(uim2_reset),
1139 MSM_PIN_FUNCTION(usb_phy),
1140 MSM_PIN_FUNCTION(vfr_1),
1141 MSM_PIN_FUNCTION(vsense_trigger),
1142 MSM_PIN_FUNCTION(wlan1_adc0),
1143 MSM_PIN_FUNCTION(wlan1_adc1),
1144 MSM_PIN_FUNCTION(wlan2_adc0),
1145 MSM_PIN_FUNCTION(wlan2_adc1),
1146 };
1147
1148 /*
1149 * Every pin is maintained as a single group, and missing or non-existing pin
1150 * would be maintained as dummy group to synchronize pin group index with
1151 * pin descriptor registered with pinctrl core.
1152 * Clients would not be able to request these dummy pin groups.
1153 */
1154 static const struct msm_pingroup sm6350_groups[] = {
1155 [0] = PINGROUP(0, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _),
1156 [1] = PINGROUP(1, ibi_i3c, qup00, cri_trng, _, _, _, _, _, _),
1157 [2] = PINGROUP(2, qup00, cci_i2c, cri_trng, qdss_cti, _, _, _, _, _),
1158 [3] = PINGROUP(3, qup00, cci_i2c, sp_cmu, dbg_out, qdss_cti, _, _, _, _),
1159 [4] = PINGROUP(4, qup14, qup14, sdc1_tb, _, _, _, _, _, _),
1160 [5] = PINGROUP(5, qup14, qup14, sdc2_tb, _, _, _, _, _, _),
1161 [6] = PINGROUP(6, mdp_vsync, qdss_cti, _, _, _, _, _, _, _),
1162 [7] = PINGROUP(7, qdss_cti, _, _, _, _, _, _, _, _),
1163 [8] = PINGROUP(8, gp_pdm1, qdss_gpio, _, _, _, _, _, _, _),
1164 [9] = PINGROUP(9, qdss_gpio, _, _, _, _, _, _, _, _),
1165 [10] = PINGROUP(10, _, _, _, _, _, _, _, _, _),
1166 [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _),
1167 [12] = PINGROUP(12, m_voc, dp_hot, _, phase_flag, _, _, _, _, _),
1168 [13] = PINGROUP(13, qup10, pll_bypassnl, _, _, _, _, _, _, _),
1169 [14] = PINGROUP(14, qup10, pll_reset, _, _, _, _, _, _, _),
1170 [15] = PINGROUP(15, qup10, _, _, _, _, _, _, _, _),
1171 [16] = PINGROUP(16, qup10, _, _, _, _, _, _, _, _),
1172 [17] = PINGROUP(17, _, phase_flag, qup10, _, _, _, _, _, _),
1173 [18] = PINGROUP(18, _, phase_flag, _, _, _, _, _, _, _),
1174 [19] = PINGROUP(19, qup12, qup12, ddr_bist, _, _, _, _, _, _),
1175 [20] = PINGROUP(20, qup12, qup12, ddr_bist, _, _, _, _, _, _),
1176 [21] = PINGROUP(21, gcc_gp2, ddr_bist, _, _, _, _, _, _, _),
1177 [22] = PINGROUP(22, gcc_gp3, ddr_bist, _, _, _, _, _, _, _),
1178 [23] = PINGROUP(23, mdp_vsync, edp_lcd, _, _, _, _, _, _, _),
1179 [24] = PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _),
1180 [25] = PINGROUP(25, qup13_f1, qup13_f2, _, _, _, _, _, _, _),
1181 [26] = PINGROUP(26, qup13_f1, qup13_f2, _, _, _, _, _, _, _),
1182 [27] = PINGROUP(27, qup11, qup11, mdp_vsync, pll_bist, _, qdss_gpio14, _, _, _),
1183 [28] = PINGROUP(28, qup11, qup11, mdp_vsync, _, qdss_gpio15, _, _, _, _),
1184 [29] = PINGROUP(29, cam_mclk0, _, _, _, _, _, _, _, _),
1185 [30] = PINGROUP(30, cam_mclk1, _, _, _, _, _, _, _, _),
1186 [31] = PINGROUP(31, cam_mclk2, _, _, _, _, _, _, _, _),
1187 [32] = PINGROUP(32, cam_mclk3, _, _, _, _, _, _, _, _),
1188 [33] = PINGROUP(33, cam_mclk4, _, _, _, _, _, _, _, _),
1189 [34] = PINGROUP(34, cci_timer0, _, phase_flag, qdss_gpio12, _, _, _, _, _),
1190 [35] = PINGROUP(35, cci_timer1, cci_async, _, phase_flag, qdss_gpio13, _, _, _, _),
1191 [36] = PINGROUP(36, cci_timer2, cci_async, _, phase_flag, qdss_gpio14, _, _, _, _),
1192 [37] = PINGROUP(37, cci_timer3, gp_pdm0, _, phase_flag, qdss_gpio15, _, _, _, _),
1193 [38] = PINGROUP(38, cci_timer4, _, phase_flag, qdss_gpio2, _, _, _, _, _),
1194 [39] = PINGROUP(39, cci_i2c, _, phase_flag, qdss_gpio0, _, _, _, _, _),
1195 [40] = PINGROUP(40, cci_i2c, _, phase_flag, qdss_gpio1, _, _, _, _, _),
1196 [41] = PINGROUP(41, cci_i2c, _, phase_flag, qdss_gpio2, _, _, _, _, _),
1197 [42] = PINGROUP(42, cci_i2c, _, phase_flag, qdss_gpio3, _, _, _, _, _),
1198 [43] = PINGROUP(43, cci_i2c, _, phase_flag, qdss_gpio4, _, _, _, _, _),
1199 [44] = PINGROUP(44, cci_i2c, _, phase_flag, qdss_gpio5, _, _, _, _, _),
1200 [45] = PINGROUP(45, qup02, _, phase_flag, qdss_gpio6, _, _, _, _, _),
1201 [46] = PINGROUP(46, qup02, _, phase_flag, qdss_gpio7, _, _, _, _, _),
1202 [47] = PINGROUP(47, mdp_vsync0, _, phase_flag, qdss_gpio3, _, _, _, _, _),
1203 [48] = PINGROUP(48, cci_async, mdp_vsync1, gcc_gp1, _, phase_flag, qdss_gpio8, qup02, _, _),
1204 [49] = PINGROUP(49, vfr_1, _, phase_flag, qdss_gpio9, _, _, _, _, _),
1205 [50] = PINGROUP(50, _, phase_flag, qdss_gpio10, _, _, _, _, _, _),
1206 [51] = PINGROUP(51, _, phase_flag, qdss_gpio11, _, _, _, _, _, _),
1207 [52] = PINGROUP(52, cci_async, gp_pdm1, _, phase_flag, qdss_gpio12, _, _, _, _),
1208 [53] = PINGROUP(53, cci_async, _, phase_flag, qdss_gpio13, _, _, _, _, _),
1209 [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _),
1210 [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _),
1211 [56] = PINGROUP(56, qup02, mdp_vsync2, _, phase_flag, qdss_gpio10, _, _, _, _),
1212 [57] = PINGROUP(57, qup02, mdp_vsync3, gp_pdm2, _, phase_flag, qdss_gpio11, _, _, _),
1213 [58] = PINGROUP(58, gcc_gp1, _, _, _, _, _, _, _, _),
1214 [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _),
1215 [60] = PINGROUP(60, audio_ref, lpass_ext, mi2s_2, _, phase_flag, _, _, _, _),
1216 [61] = PINGROUP(61, qup01, tgu_ch0, _, phase_flag, qdss_cti, _, _, _, _),
1217 [62] = PINGROUP(62, qup01, tgu_ch1, _, phase_flag, qdss_cti, _, _, _, _),
1218 [63] = PINGROUP(63, qup01, tgu_ch2, _, phase_flag, qdss_gpio, _, _, _, _),
1219 [64] = PINGROUP(64, qup01, tgu_ch3, _, phase_flag, qdss_gpio, _, _, _, _),
1220 [65] = PINGROUP(65, mss_lte, _, qdss_gpio0, _, _, _, _, _, _),
1221 [66] = PINGROUP(66, mss_lte, _, qdss_gpio1, _, _, _, _, _, _),
1222 [67] = PINGROUP(67, btfm_slimbus, mi2s_1, _, phase_flag, _, _, _, _, _),
1223 [68] = PINGROUP(68, btfm_slimbus, mi2s_1, gp_pdm0, _, phase_flag, _, _, _, _),
1224 [69] = PINGROUP(69, _, _, _, _, _, _, _, _, _),
1225 [70] = PINGROUP(70, _, _, _, _, _, _, _, _, _),
1226 [71] = PINGROUP(71, _, _, _, _, _, _, _, _, _),
1227 [72] = PINGROUP(72, mi2s_2, _, _, _, _, _, _, _, _),
1228 [73] = PINGROUP(73, mi2s_2, _, _, _, _, _, _, _, _),
1229 [74] = PINGROUP(74, mi2s_2, _, _, _, _, _, _, _, _),
1230 [75] = PINGROUP(75, uim2_data, _, _, _, _, _, _, _, _),
1231 [76] = PINGROUP(76, uim2_clk, _, _, _, _, _, _, _, _),
1232 [77] = PINGROUP(77, uim2_reset, _, _, _, _, _, _, _, _),
1233 [78] = PINGROUP(78, uim2_present, _, _, _, _, _, _, _, _),
1234 [79] = PINGROUP(79, uim1_data, _, _, _, _, _, _, _, _),
1235 [80] = PINGROUP(80, uim1_clk, _, _, _, _, _, _, _, _),
1236 [81] = PINGROUP(81, uim1_reset, _, _, _, _, _, _, _, _),
1237 [82] = PINGROUP(82, uim1_present, _, _, _, _, _, _, _, _),
1238 [83] = PINGROUP(83, atest_usb, _, _, _, _, _, _, _, _),
1239 [84] = PINGROUP(84, _, atest_usb, _, _, _, _, _, _, _),
1240 [85] = PINGROUP(85, sd_write, _, atest_usb, _, _, _, _, _, _),
1241 [86] = PINGROUP(86, btfm_slimbus, mi2s_1, _, qdss_cti, atest_usb, ddr_pxi0, _, _, _),
1242 [87] = PINGROUP(87, btfm_slimbus, mi2s_1, adsp_ext, _, qdss_cti, atest_usb, ddr_pxi1, _, _),
1243 [88] = PINGROUP(88, mi2s_0, _, qdss_gpio4, _, atest_usb, ddr_pxi2,
1244 tsense_pwm1, tsense_pwm2, _),
1245 [89] = PINGROUP(89, mi2s_0, agera_pll, _, qdss_gpio5, _,
1246 vsense_trigger, atest_usb, ddr_pxi3, _),
1247 [90] = PINGROUP(90, mi2s_0, jitter_bist, _, qdss_gpio6, _,
1248 wlan1_adc0, atest_usb, ddr_pxi0, _),
1249 [91] = PINGROUP(91, mi2s_0, _, qdss_gpio7, _, wlan2_adc0,
1250 atest_usb, ddr_pxi1, _, _),
1251 [92] = PINGROUP(92, _, qdss_gpio8, atest_tsens, wlan1_adc1,
1252 atest_usb, ddr_pxi2, _, _, _),
1253 [93] = PINGROUP(93, mclk, lpass_ext, _, qdss_gpio9, atest_tsens2,
1254 wlan2_adc1, ddr_pxi3, _, _),
1255 [94] = PINGROUP(94, _, _, _, _, _, _, _, _, _),
1256 [95] = PINGROUP(95, ldo_en, _, atest_char, _, _, _, _, _, _),
1257 [96] = PINGROUP(96, ldo_update, _, atest_char0, _, _, _, _, _, _),
1258 [97] = PINGROUP(97, prng_rosc, _, atest_char1, _, _, _, _, _, _),
1259 [98] = PINGROUP(98, _, atest_char2, _, _, _, _, _, _, _),
1260 [99] = PINGROUP(99, _, atest_char3, _, _, _, _, _, _, _),
1261 [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
1262 [101] = PINGROUP(101, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1263 [102] = PINGROUP(102, nav_gpio, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1264 [103] = PINGROUP(103, qlink0_wmss, _, _, _, _, _, _, _, _),
1265 [104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _),
1266 [105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _),
1267 [106] = PINGROUP(106, qlink1_wmss, _, _, _, _, _, _, _, _),
1268 [107] = PINGROUP(107, qlink1_request, gps_tx, _, _, _, _, _, _, _),
1269 [108] = PINGROUP(108, qlink1_enable, gps_tx, _, _, _, _, _, _, _),
1270 [109] = PINGROUP(109, rffe0_data, _, _, _, _, _, _, _, _),
1271 [110] = PINGROUP(110, rffe0_clk, _, _, _, _, _, _, _, _),
1272 [111] = PINGROUP(111, rffe1_data, _, _, _, _, _, _, _, _),
1273 [112] = PINGROUP(112, rffe1_clk, _, _, _, _, _, _, _, _),
1274 [113] = PINGROUP(113, rffe2_data, _, _, _, _, _, _, _, _),
1275 [114] = PINGROUP(114, rffe2_clk, _, _, _, _, _, _, _, _),
1276 [115] = PINGROUP(115, rffe3_data, _, _, _, _, _, _, _, _),
1277 [116] = PINGROUP(116, rffe3_clk, _, _, _, _, _, _, _, _),
1278 [117] = PINGROUP(117, rffe4_data, _, _, _, _, _, _, _, _),
1279 [118] = PINGROUP(118, rffe4_clk, _, pa_indicator, dp_hot, _, _, _, _, _),
1280 [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
1281 [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
1282 [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _),
1283 [122] = PINGROUP(122, pcie0_clk, _, _, _, _, _, _, _, _),
1284 [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
1285 [124] = PINGROUP(124, usb_phy, _, _, _, _, _, _, _, _),
1286 [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
1287 [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
1288 [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _),
1289 [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _),
1290 [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
1291 [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
1292 [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
1293 [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
1294 [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _),
1295 [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _),
1296 [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _),
1297 [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _),
1298 [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _),
1299 [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _),
1300 [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
1301 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _),
1302 [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
1303 [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
1304 [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
1305 [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _),
1306 [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
1307 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
1308 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
1309 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
1310 [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _),
1311 [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _),
1312 [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _),
1313 [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _),
1314 [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _),
1315 [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _),
1316 [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _),
1317 [156] = UFS_RESET(ufs_reset, 0xae000),
1318 [157] = SDC_PINGROUP(sdc1_rclk, 0xa1000, 15, 0),
1319 [158] = SDC_PINGROUP(sdc1_clk, 0xa0000, 13, 6),
1320 [159] = SDC_PINGROUP(sdc1_cmd, 0xa0000, 11, 3),
1321 [160] = SDC_PINGROUP(sdc1_data, 0xa0000, 9, 0),
1322 [161] = SDC_PINGROUP(sdc2_clk, 0xa2000, 14, 6),
1323 [162] = SDC_PINGROUP(sdc2_cmd, 0xa2000, 11, 3),
1324 [163] = SDC_PINGROUP(sdc2_data, 0xa2000, 9, 0),
1325 };
1326
1327 static const struct msm_gpio_wakeirq_map sm6350_pdc_map[] = {
1328 { 3, 126 }, { 4, 151 }, { 7, 58 }, { 8, 113 }, { 9, 66 }, { 11, 106 },
1329 { 12, 59 }, { 13, 112 }, { 16, 73 }, { 17, 74 }, { 18, 75 }, { 19, 76 },
1330 { 21, 130 }, { 22, 96 }, { 23, 146 }, { 24, 114 }, { 25, 83 },
1331 { 27, 84 }, { 28, 85 }, { 34, 147 }, { 35, 92 }, { 36, 93 }, { 37, 94 },
1332 { 38, 68 }, { 48, 100 }, { 50, 57 }, { 51, 81 }, { 52, 80 }, { 53, 69 },
1333 { 54, 71 }, { 55, 70 }, { 57, 152 }, { 58, 115 }, { 59, 116 }, { 60, 117 },
1334 { 61, 118 }, { 62, 119 }, { 64, 121 }, { 66, 127 }, { 67, 128 },
1335 { 69, 60 }, { 73, 78 }, { 78, 135 }, { 82, 138 }, { 83, 140 },
1336 { 84, 141 }, { 85, 98 }, { 87, 88 }, { 88, 107 }, { 89, 109 },
1337 { 90, 110 }, { 91, 111 }, { 92, 149 }, { 93, 101 }, { 94, 61 },
1338 { 95, 65 }, { 96, 95 }, { 97, 72 }, { 98, 145 }, { 99, 150 },
1339 { 100, 108 }, { 104, 129 }, { 107, 131 }, { 110, 132 }, { 112, 133 },
1340 { 114, 134 }, { 116, 136 }, { 118, 137 }, { 122, 97 }, { 123, 99 },
1341 { 124, 148 }, { 125, 82 }, { 128, 144 }, { 129, 86 }, { 131, 87 },
1342 { 133, 142 }, { 134, 143 }, { 136, 102 }, { 137, 91 }, { 138, 77 },
1343 { 139, 79 }, { 140, 90 }, { 142, 103 }, { 144, 105 }, { 147, 104 },
1344 { 153, 120 }, { 155, 67 }
1345 };
1346
1347 static const struct msm_pinctrl_soc_data sm6350_tlmm = {
1348 .pins = sm6350_pins,
1349 .npins = ARRAY_SIZE(sm6350_pins),
1350 .functions = sm6350_functions,
1351 .nfunctions = ARRAY_SIZE(sm6350_functions),
1352 .groups = sm6350_groups,
1353 .ngroups = ARRAY_SIZE(sm6350_groups),
1354 .ngpios = 157,
1355 .wakeirq_map = sm6350_pdc_map,
1356 .nwakeirq_map = ARRAY_SIZE(sm6350_pdc_map),
1357 .wakeirq_dual_edge_errata = true,
1358 };
1359
sm6350_tlmm_probe(struct platform_device * pdev)1360 static int sm6350_tlmm_probe(struct platform_device *pdev)
1361 {
1362 return msm_pinctrl_probe(pdev, &sm6350_tlmm);
1363 }
1364
1365 static const struct of_device_id sm6350_tlmm_of_match[] = {
1366 { .compatible = "qcom,sm6350-tlmm" },
1367 { },
1368 };
1369
1370 static struct platform_driver sm6350_tlmm_driver = {
1371 .driver = {
1372 .name = "sm6350-tlmm",
1373 .of_match_table = sm6350_tlmm_of_match,
1374 },
1375 .probe = sm6350_tlmm_probe,
1376 .remove_new = msm_pinctrl_remove,
1377 };
1378
sm6350_tlmm_init(void)1379 static int __init sm6350_tlmm_init(void)
1380 {
1381 return platform_driver_register(&sm6350_tlmm_driver);
1382 }
1383 arch_initcall(sm6350_tlmm_init);
1384
sm6350_tlmm_exit(void)1385 static void __exit sm6350_tlmm_exit(void)
1386 {
1387 platform_driver_unregister(&sm6350_tlmm_driver);
1388 }
1389 module_exit(sm6350_tlmm_exit);
1390
1391 MODULE_DESCRIPTION("QTI SM6350 TLMM driver");
1392 MODULE_LICENSE("GPL v2");
1393 MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match);
1394