1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Brian Masney <masneyb@onstation.org>
4 *
5 * Based on MSM bus code from downstream MSM kernel sources.
6 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
7 *
8 * Based on qcs404.c
9 * Copyright (C) 2019 Linaro Ltd
10 *
11 * Here's a rough representation that shows the various buses that form the
12 * Network On Chip (NOC) for the msm8974:
13 *
14 * Multimedia Subsystem (MMSS)
15 * |----------+-----------------------------------+-----------|
16 * | |
17 * | |
18 * Config | Bus Interface | Memory Controller
19 * |------------+-+-----------| |------------+-+-----------|
20 * | |
21 * | |
22 * | System |
23 * |--------------+-+---------------------------------+-+-------------|
24 * | |
25 * | |
26 * Peripheral | On Chip | Memory (OCMEM)
27 * |------------+-------------| |------------+-------------|
28 */
29
30 #include <dt-bindings/interconnect/qcom,msm8974.h>
31
32 #include <linux/args.h>
33 #include <linux/clk.h>
34 #include <linux/device.h>
35 #include <linux/interconnect-provider.h>
36 #include <linux/io.h>
37 #include <linux/module.h>
38 #include <linux/of.h>
39 #include <linux/platform_device.h>
40 #include <linux/slab.h>
41
42 #include "icc-rpm.h"
43
44 enum {
45 MSM8974_BIMC_MAS_AMPSS_M0 = 1,
46 MSM8974_BIMC_MAS_AMPSS_M1,
47 MSM8974_BIMC_MAS_MSS_PROC,
48 MSM8974_BIMC_TO_MNOC,
49 MSM8974_BIMC_TO_SNOC,
50 MSM8974_BIMC_SLV_EBI_CH0,
51 MSM8974_BIMC_SLV_AMPSS_L2,
52 MSM8974_CNOC_MAS_RPM_INST,
53 MSM8974_CNOC_MAS_RPM_DATA,
54 MSM8974_CNOC_MAS_RPM_SYS,
55 MSM8974_CNOC_MAS_DEHR,
56 MSM8974_CNOC_MAS_QDSS_DAP,
57 MSM8974_CNOC_MAS_SPDM,
58 MSM8974_CNOC_MAS_TIC,
59 MSM8974_CNOC_SLV_CLK_CTL,
60 MSM8974_CNOC_SLV_CNOC_MSS,
61 MSM8974_CNOC_SLV_SECURITY,
62 MSM8974_CNOC_SLV_TCSR,
63 MSM8974_CNOC_SLV_TLMM,
64 MSM8974_CNOC_SLV_CRYPTO_0_CFG,
65 MSM8974_CNOC_SLV_CRYPTO_1_CFG,
66 MSM8974_CNOC_SLV_IMEM_CFG,
67 MSM8974_CNOC_SLV_MESSAGE_RAM,
68 MSM8974_CNOC_SLV_BIMC_CFG,
69 MSM8974_CNOC_SLV_BOOT_ROM,
70 MSM8974_CNOC_SLV_PMIC_ARB,
71 MSM8974_CNOC_SLV_SPDM_WRAPPER,
72 MSM8974_CNOC_SLV_DEHR_CFG,
73 MSM8974_CNOC_SLV_MPM,
74 MSM8974_CNOC_SLV_QDSS_CFG,
75 MSM8974_CNOC_SLV_RBCPR_CFG,
76 MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG,
77 MSM8974_CNOC_TO_SNOC,
78 MSM8974_CNOC_SLV_CNOC_ONOC_CFG,
79 MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG,
80 MSM8974_CNOC_SLV_CNOC_MNOC_CFG,
81 MSM8974_CNOC_SLV_PNOC_CFG,
82 MSM8974_CNOC_SLV_SNOC_MPU_CFG,
83 MSM8974_CNOC_SLV_SNOC_CFG,
84 MSM8974_CNOC_SLV_EBI1_DLL_CFG,
85 MSM8974_CNOC_SLV_PHY_APU_CFG,
86 MSM8974_CNOC_SLV_EBI1_PHY_CFG,
87 MSM8974_CNOC_SLV_RPM,
88 MSM8974_CNOC_SLV_SERVICE_CNOC,
89 MSM8974_MNOC_MAS_GRAPHICS_3D,
90 MSM8974_MNOC_MAS_JPEG,
91 MSM8974_MNOC_MAS_MDP_PORT0,
92 MSM8974_MNOC_MAS_VIDEO_P0,
93 MSM8974_MNOC_MAS_VIDEO_P1,
94 MSM8974_MNOC_MAS_VFE,
95 MSM8974_MNOC_TO_CNOC,
96 MSM8974_MNOC_TO_BIMC,
97 MSM8974_MNOC_SLV_CAMERA_CFG,
98 MSM8974_MNOC_SLV_DISPLAY_CFG,
99 MSM8974_MNOC_SLV_OCMEM_CFG,
100 MSM8974_MNOC_SLV_CPR_CFG,
101 MSM8974_MNOC_SLV_CPR_XPU_CFG,
102 MSM8974_MNOC_SLV_MISC_CFG,
103 MSM8974_MNOC_SLV_MISC_XPU_CFG,
104 MSM8974_MNOC_SLV_VENUS_CFG,
105 MSM8974_MNOC_SLV_GRAPHICS_3D_CFG,
106 MSM8974_MNOC_SLV_MMSS_CLK_CFG,
107 MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG,
108 MSM8974_MNOC_SLV_MNOC_MPU_CFG,
109 MSM8974_MNOC_SLV_ONOC_MPU_CFG,
110 MSM8974_MNOC_SLV_SERVICE_MNOC,
111 MSM8974_OCMEM_NOC_TO_OCMEM_VNOC,
112 MSM8974_OCMEM_MAS_JPEG_OCMEM,
113 MSM8974_OCMEM_MAS_MDP_OCMEM,
114 MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM,
115 MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM,
116 MSM8974_OCMEM_MAS_VFE_OCMEM,
117 MSM8974_OCMEM_MAS_CNOC_ONOC_CFG,
118 MSM8974_OCMEM_SLV_SERVICE_ONOC,
119 MSM8974_OCMEM_VNOC_TO_SNOC,
120 MSM8974_OCMEM_VNOC_TO_OCMEM_NOC,
121 MSM8974_OCMEM_VNOC_MAS_GFX3D,
122 MSM8974_OCMEM_SLV_OCMEM,
123 MSM8974_PNOC_MAS_PNOC_CFG,
124 MSM8974_PNOC_MAS_SDCC_1,
125 MSM8974_PNOC_MAS_SDCC_3,
126 MSM8974_PNOC_MAS_SDCC_4,
127 MSM8974_PNOC_MAS_SDCC_2,
128 MSM8974_PNOC_MAS_TSIF,
129 MSM8974_PNOC_MAS_BAM_DMA,
130 MSM8974_PNOC_MAS_BLSP_2,
131 MSM8974_PNOC_MAS_USB_HSIC,
132 MSM8974_PNOC_MAS_BLSP_1,
133 MSM8974_PNOC_MAS_USB_HS,
134 MSM8974_PNOC_TO_SNOC,
135 MSM8974_PNOC_SLV_SDCC_1,
136 MSM8974_PNOC_SLV_SDCC_3,
137 MSM8974_PNOC_SLV_SDCC_2,
138 MSM8974_PNOC_SLV_SDCC_4,
139 MSM8974_PNOC_SLV_TSIF,
140 MSM8974_PNOC_SLV_BAM_DMA,
141 MSM8974_PNOC_SLV_BLSP_2,
142 MSM8974_PNOC_SLV_USB_HSIC,
143 MSM8974_PNOC_SLV_BLSP_1,
144 MSM8974_PNOC_SLV_USB_HS,
145 MSM8974_PNOC_SLV_PDM,
146 MSM8974_PNOC_SLV_PERIPH_APU_CFG,
147 MSM8974_PNOC_SLV_PNOC_MPU_CFG,
148 MSM8974_PNOC_SLV_PRNG,
149 MSM8974_PNOC_SLV_SERVICE_PNOC,
150 MSM8974_SNOC_MAS_LPASS_AHB,
151 MSM8974_SNOC_MAS_QDSS_BAM,
152 MSM8974_SNOC_MAS_SNOC_CFG,
153 MSM8974_SNOC_TO_BIMC,
154 MSM8974_SNOC_TO_CNOC,
155 MSM8974_SNOC_TO_PNOC,
156 MSM8974_SNOC_TO_OCMEM_VNOC,
157 MSM8974_SNOC_MAS_CRYPTO_CORE0,
158 MSM8974_SNOC_MAS_CRYPTO_CORE1,
159 MSM8974_SNOC_MAS_LPASS_PROC,
160 MSM8974_SNOC_MAS_MSS,
161 MSM8974_SNOC_MAS_MSS_NAV,
162 MSM8974_SNOC_MAS_OCMEM_DMA,
163 MSM8974_SNOC_MAS_WCSS,
164 MSM8974_SNOC_MAS_QDSS_ETR,
165 MSM8974_SNOC_MAS_USB3,
166 MSM8974_SNOC_SLV_AMPSS,
167 MSM8974_SNOC_SLV_LPASS,
168 MSM8974_SNOC_SLV_USB3,
169 MSM8974_SNOC_SLV_WCSS,
170 MSM8974_SNOC_SLV_OCIMEM,
171 MSM8974_SNOC_SLV_SNOC_OCMEM,
172 MSM8974_SNOC_SLV_SERVICE_SNOC,
173 MSM8974_SNOC_SLV_QDSS_STM,
174 };
175
msm8974_get_bw(struct icc_node * node,u32 * avg,u32 * peak)176 static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
177 {
178 *avg = 0;
179 *peak = 0;
180
181 return 0;
182 };
183
184 static struct qcom_icc_node mas_ampss_m0 = {
185 .name = "mas_ampss_m0",
186 .id = MSM8974_BIMC_MAS_AMPSS_M0,
187 .buswidth = 8,
188 .mas_rpm_id = 0,
189 .slv_rpm_id = -1,
190 };
191
192 static struct qcom_icc_node mas_ampss_m1 = {
193 .name = "mas_ampss_m1",
194 .id = MSM8974_BIMC_MAS_AMPSS_M1,
195 .buswidth = 8,
196 .mas_rpm_id = 0,
197 .slv_rpm_id = -1,
198 };
199
200 static struct qcom_icc_node mas_mss_proc = {
201 .name = "mas_mss_proc",
202 .id = MSM8974_BIMC_MAS_MSS_PROC,
203 .buswidth = 8,
204 .mas_rpm_id = 1,
205 .slv_rpm_id = -1,
206 };
207
208 static const u16 bimc_to_mnoc_links[] = {
209 MSM8974_BIMC_SLV_EBI_CH0
210 };
211
212 static struct qcom_icc_node bimc_to_mnoc = {
213 .name = "bimc_to_mnoc",
214 .id = MSM8974_BIMC_TO_MNOC,
215 .buswidth = 8,
216 .mas_rpm_id = 2,
217 .slv_rpm_id = -1,
218 .num_links = ARRAY_SIZE(bimc_to_mnoc_links),
219 .links = bimc_to_mnoc_links,
220 };
221
222 static const u16 bimc_to_snoc_links[] = {
223 MSM8974_SNOC_TO_BIMC,
224 MSM8974_BIMC_SLV_EBI_CH0,
225 MSM8974_BIMC_MAS_AMPSS_M0
226 };
227
228 static struct qcom_icc_node bimc_to_snoc = {
229 .name = "bimc_to_snoc",
230 .id = MSM8974_BIMC_TO_SNOC,
231 .buswidth = 8,
232 .mas_rpm_id = 3,
233 .slv_rpm_id = 2,
234 .num_links = ARRAY_SIZE(bimc_to_snoc_links),
235 .links = bimc_to_snoc_links,
236 };
237
238 static struct qcom_icc_node slv_ebi_ch0 = {
239 .name = "slv_ebi_ch0",
240 .id = MSM8974_BIMC_SLV_EBI_CH0,
241 .buswidth = 8,
242 .mas_rpm_id = -1,
243 .slv_rpm_id = 0,
244 };
245
246 static struct qcom_icc_node slv_ampss_l2 = {
247 .name = "slv_ampss_l2",
248 .id = MSM8974_BIMC_SLV_AMPSS_L2,
249 .buswidth = 8,
250 .mas_rpm_id = -1,
251 .slv_rpm_id = 1,
252 };
253
254 static struct qcom_icc_node * const msm8974_bimc_nodes[] = {
255 [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0,
256 [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1,
257 [BIMC_MAS_MSS_PROC] = &mas_mss_proc,
258 [BIMC_TO_MNOC] = &bimc_to_mnoc,
259 [BIMC_TO_SNOC] = &bimc_to_snoc,
260 [BIMC_SLV_EBI_CH0] = &slv_ebi_ch0,
261 [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2,
262 };
263
264 static const struct qcom_icc_desc msm8974_bimc = {
265 .nodes = msm8974_bimc_nodes,
266 .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes),
267 .bus_clk_desc = &bimc_clk,
268 .get_bw = msm8974_get_bw,
269 .ignore_enxio = true,
270 };
271
272 static struct qcom_icc_node mas_rpm_inst = {
273 .name = "mas_rpm_inst",
274 .id = MSM8974_CNOC_MAS_RPM_INST,
275 .buswidth = 8,
276 .mas_rpm_id = 45,
277 .slv_rpm_id = -1,
278 };
279
280 static struct qcom_icc_node mas_rpm_data = {
281 .name = "mas_rpm_data",
282 .id = MSM8974_CNOC_MAS_RPM_DATA,
283 .buswidth = 8,
284 .mas_rpm_id = 46,
285 .slv_rpm_id = -1,
286 };
287
288 static struct qcom_icc_node mas_rpm_sys = {
289 .name = "mas_rpm_sys",
290 .id = MSM8974_CNOC_MAS_RPM_SYS,
291 .buswidth = 8,
292 .mas_rpm_id = 47,
293 .slv_rpm_id = -1,
294 };
295
296 static struct qcom_icc_node mas_dehr = {
297 .name = "mas_dehr",
298 .id = MSM8974_CNOC_MAS_DEHR,
299 .buswidth = 8,
300 .mas_rpm_id = 48,
301 .slv_rpm_id = -1,
302 };
303
304 static struct qcom_icc_node mas_qdss_dap = {
305 .name = "mas_qdss_dap",
306 .id = MSM8974_CNOC_MAS_QDSS_DAP,
307 .buswidth = 8,
308 .mas_rpm_id = 49,
309 .slv_rpm_id = -1,
310 };
311
312 static struct qcom_icc_node mas_spdm = {
313 .name = "mas_spdm",
314 .id = MSM8974_CNOC_MAS_SPDM,
315 .buswidth = 8,
316 .mas_rpm_id = 50,
317 .slv_rpm_id = -1,
318 };
319
320 static struct qcom_icc_node mas_tic = {
321 .name = "mas_tic",
322 .id = MSM8974_CNOC_MAS_TIC,
323 .buswidth = 8,
324 .mas_rpm_id = 51,
325 .slv_rpm_id = -1,
326 };
327
328 static struct qcom_icc_node slv_clk_ctl = {
329 .name = "slv_clk_ctl",
330 .id = MSM8974_CNOC_SLV_CLK_CTL,
331 .buswidth = 8,
332 .mas_rpm_id = -1,
333 .slv_rpm_id = 47,
334 };
335
336 static struct qcom_icc_node slv_cnoc_mss = {
337 .name = "slv_cnoc_mss",
338 .id = MSM8974_CNOC_SLV_CNOC_MSS,
339 .buswidth = 8,
340 .mas_rpm_id = -1,
341 .slv_rpm_id = 48,
342 };
343
344 static struct qcom_icc_node slv_security = {
345 .name = "slv_security",
346 .id = MSM8974_CNOC_SLV_SECURITY,
347 .buswidth = 8,
348 .mas_rpm_id = -1,
349 .slv_rpm_id = 49,
350 };
351
352 static struct qcom_icc_node slv_tcsr = {
353 .name = "slv_tcsr",
354 .id = MSM8974_CNOC_SLV_TCSR,
355 .buswidth = 8,
356 .mas_rpm_id = -1,
357 .slv_rpm_id = 50,
358 };
359
360 static struct qcom_icc_node slv_tlmm = {
361 .name = "slv_tlmm",
362 .id = MSM8974_CNOC_SLV_TLMM,
363 .buswidth = 8,
364 .mas_rpm_id = -1,
365 .slv_rpm_id = 51,
366 };
367
368 static struct qcom_icc_node slv_crypto_0_cfg = {
369 .name = "slv_crypto_0_cfg",
370 .id = MSM8974_CNOC_SLV_CRYPTO_0_CFG,
371 .buswidth = 8,
372 .mas_rpm_id = -1,
373 .slv_rpm_id = 52,
374 };
375
376 static struct qcom_icc_node slv_crypto_1_cfg = {
377 .name = "slv_crypto_1_cfg",
378 .id = MSM8974_CNOC_SLV_CRYPTO_1_CFG,
379 .buswidth = 8,
380 .mas_rpm_id = -1,
381 .slv_rpm_id = 53,
382 };
383
384 static struct qcom_icc_node slv_imem_cfg = {
385 .name = "slv_imem_cfg",
386 .id = MSM8974_CNOC_SLV_IMEM_CFG,
387 .buswidth = 8,
388 .mas_rpm_id = -1,
389 .slv_rpm_id = 54,
390 };
391
392 static struct qcom_icc_node slv_message_ram = {
393 .name = "slv_message_ram",
394 .id = MSM8974_CNOC_SLV_MESSAGE_RAM,
395 .buswidth = 8,
396 .mas_rpm_id = -1,
397 .slv_rpm_id = 55,
398 };
399
400 static struct qcom_icc_node slv_bimc_cfg = {
401 .name = "slv_bimc_cfg",
402 .id = MSM8974_CNOC_SLV_BIMC_CFG,
403 .buswidth = 8,
404 .mas_rpm_id = -1,
405 .slv_rpm_id = 56,
406 };
407
408 static struct qcom_icc_node slv_boot_rom = {
409 .name = "slv_boot_rom",
410 .id = MSM8974_CNOC_SLV_BOOT_ROM,
411 .buswidth = 8,
412 .mas_rpm_id = -1,
413 .slv_rpm_id = 57,
414 };
415
416 static struct qcom_icc_node slv_pmic_arb = {
417 .name = "slv_pmic_arb",
418 .id = MSM8974_CNOC_SLV_PMIC_ARB,
419 .buswidth = 8,
420 .mas_rpm_id = -1,
421 .slv_rpm_id = 59,
422 };
423
424 static struct qcom_icc_node slv_spdm_wrapper = {
425 .name = "slv_spdm_wrapper",
426 .id = MSM8974_CNOC_SLV_SPDM_WRAPPER,
427 .buswidth = 8,
428 .mas_rpm_id = -1,
429 .slv_rpm_id = 60,
430 };
431
432 static struct qcom_icc_node slv_dehr_cfg = {
433 .name = "slv_dehr_cfg",
434 .id = MSM8974_CNOC_SLV_DEHR_CFG,
435 .buswidth = 8,
436 .mas_rpm_id = -1,
437 .slv_rpm_id = 61,
438 };
439
440 static struct qcom_icc_node slv_mpm = {
441 .name = "slv_mpm",
442 .id = MSM8974_CNOC_SLV_MPM,
443 .buswidth = 8,
444 .mas_rpm_id = -1,
445 .slv_rpm_id = 62,
446 };
447
448 static struct qcom_icc_node slv_qdss_cfg = {
449 .name = "slv_qdss_cfg",
450 .id = MSM8974_CNOC_SLV_QDSS_CFG,
451 .buswidth = 8,
452 .mas_rpm_id = -1,
453 .slv_rpm_id = 63,
454 };
455
456 static struct qcom_icc_node slv_rbcpr_cfg = {
457 .name = "slv_rbcpr_cfg",
458 .id = MSM8974_CNOC_SLV_RBCPR_CFG,
459 .buswidth = 8,
460 .mas_rpm_id = -1,
461 .slv_rpm_id = 64,
462 };
463
464 static struct qcom_icc_node slv_rbcpr_qdss_apu_cfg = {
465 .name = "slv_rbcpr_qdss_apu_cfg",
466 .id = MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG,
467 .buswidth = 8,
468 .mas_rpm_id = -1,
469 .slv_rpm_id = 65,
470 };
471
472 static struct qcom_icc_node cnoc_to_snoc = {
473 .name = "cnoc_to_snoc",
474 .id = MSM8974_CNOC_TO_SNOC,
475 .buswidth = 8,
476 .mas_rpm_id = 52,
477 .slv_rpm_id = 75,
478 };
479
480 static struct qcom_icc_node slv_cnoc_onoc_cfg = {
481 .name = "slv_cnoc_onoc_cfg",
482 .id = MSM8974_CNOC_SLV_CNOC_ONOC_CFG,
483 .buswidth = 8,
484 .mas_rpm_id = -1,
485 .slv_rpm_id = 68,
486 };
487
488 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
489 .name = "slv_cnoc_mnoc_mmss_cfg",
490 .id = MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG,
491 .buswidth = 8,
492 .mas_rpm_id = -1,
493 .slv_rpm_id = 58,
494 };
495
496 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
497 .name = "slv_cnoc_mnoc_cfg",
498 .id = MSM8974_CNOC_SLV_CNOC_MNOC_CFG,
499 .buswidth = 8,
500 .mas_rpm_id = -1,
501 .slv_rpm_id = 66,
502 };
503
504 static struct qcom_icc_node slv_pnoc_cfg = {
505 .name = "slv_pnoc_cfg",
506 .id = MSM8974_CNOC_SLV_PNOC_CFG,
507 .buswidth = 8,
508 .mas_rpm_id = -1,
509 .slv_rpm_id = 69,
510 };
511
512 static struct qcom_icc_node slv_snoc_mpu_cfg = {
513 .name = "slv_snoc_mpu_cfg",
514 .id = MSM8974_CNOC_SLV_SNOC_MPU_CFG,
515 .buswidth = 8,
516 .mas_rpm_id = -1,
517 .slv_rpm_id = 67,
518 };
519
520 static struct qcom_icc_node slv_snoc_cfg = {
521 .name = "slv_snoc_cfg",
522 .id = MSM8974_CNOC_SLV_SNOC_CFG,
523 .buswidth = 8,
524 .mas_rpm_id = -1,
525 .slv_rpm_id = 70,
526 };
527
528 static struct qcom_icc_node slv_ebi1_dll_cfg = {
529 .name = "slv_ebi1_dll_cfg",
530 .id = MSM8974_CNOC_SLV_EBI1_DLL_CFG,
531 .buswidth = 8,
532 .mas_rpm_id = -1,
533 .slv_rpm_id = 71,
534 };
535
536 static struct qcom_icc_node slv_phy_apu_cfg = {
537 .name = "slv_phy_apu_cfg",
538 .id = MSM8974_CNOC_SLV_PHY_APU_CFG,
539 .buswidth = 8,
540 .mas_rpm_id = -1,
541 .slv_rpm_id = 72,
542 };
543
544 static struct qcom_icc_node slv_ebi1_phy_cfg = {
545 .name = "slv_ebi1_phy_cfg",
546 .id = MSM8974_CNOC_SLV_EBI1_PHY_CFG,
547 .buswidth = 8,
548 .mas_rpm_id = -1,
549 .slv_rpm_id = 73,
550 };
551
552 static struct qcom_icc_node slv_rpm = {
553 .name = "slv_rpm",
554 .id = MSM8974_CNOC_SLV_RPM,
555 .buswidth = 8,
556 .mas_rpm_id = -1,
557 .slv_rpm_id = 74,
558 };
559
560 static struct qcom_icc_node slv_service_cnoc = {
561 .name = "slv_service_cnoc",
562 .id = MSM8974_CNOC_SLV_SERVICE_CNOC,
563 .buswidth = 8,
564 .mas_rpm_id = -1,
565 .slv_rpm_id = 76,
566 };
567
568 static struct qcom_icc_node * const msm8974_cnoc_nodes[] = {
569 [CNOC_MAS_RPM_INST] = &mas_rpm_inst,
570 [CNOC_MAS_RPM_DATA] = &mas_rpm_data,
571 [CNOC_MAS_RPM_SYS] = &mas_rpm_sys,
572 [CNOC_MAS_DEHR] = &mas_dehr,
573 [CNOC_MAS_QDSS_DAP] = &mas_qdss_dap,
574 [CNOC_MAS_SPDM] = &mas_spdm,
575 [CNOC_MAS_TIC] = &mas_tic,
576 [CNOC_SLV_CLK_CTL] = &slv_clk_ctl,
577 [CNOC_SLV_CNOC_MSS] = &slv_cnoc_mss,
578 [CNOC_SLV_SECURITY] = &slv_security,
579 [CNOC_SLV_TCSR] = &slv_tcsr,
580 [CNOC_SLV_TLMM] = &slv_tlmm,
581 [CNOC_SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
582 [CNOC_SLV_CRYPTO_1_CFG] = &slv_crypto_1_cfg,
583 [CNOC_SLV_IMEM_CFG] = &slv_imem_cfg,
584 [CNOC_SLV_MESSAGE_RAM] = &slv_message_ram,
585 [CNOC_SLV_BIMC_CFG] = &slv_bimc_cfg,
586 [CNOC_SLV_BOOT_ROM] = &slv_boot_rom,
587 [CNOC_SLV_PMIC_ARB] = &slv_pmic_arb,
588 [CNOC_SLV_SPDM_WRAPPER] = &slv_spdm_wrapper,
589 [CNOC_SLV_DEHR_CFG] = &slv_dehr_cfg,
590 [CNOC_SLV_MPM] = &slv_mpm,
591 [CNOC_SLV_QDSS_CFG] = &slv_qdss_cfg,
592 [CNOC_SLV_RBCPR_CFG] = &slv_rbcpr_cfg,
593 [CNOC_SLV_RBCPR_QDSS_APU_CFG] = &slv_rbcpr_qdss_apu_cfg,
594 [CNOC_TO_SNOC] = &cnoc_to_snoc,
595 [CNOC_SLV_CNOC_ONOC_CFG] = &slv_cnoc_onoc_cfg,
596 [CNOC_SLV_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
597 [CNOC_SLV_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
598 [CNOC_SLV_PNOC_CFG] = &slv_pnoc_cfg,
599 [CNOC_SLV_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
600 [CNOC_SLV_SNOC_CFG] = &slv_snoc_cfg,
601 [CNOC_SLV_EBI1_DLL_CFG] = &slv_ebi1_dll_cfg,
602 [CNOC_SLV_PHY_APU_CFG] = &slv_phy_apu_cfg,
603 [CNOC_SLV_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
604 [CNOC_SLV_RPM] = &slv_rpm,
605 [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc,
606 };
607
608 static const struct qcom_icc_desc msm8974_cnoc = {
609 .nodes = msm8974_cnoc_nodes,
610 .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes),
611 .bus_clk_desc = &bus_2_clk,
612 .get_bw = msm8974_get_bw,
613 .ignore_enxio = true,
614 };
615
616 static const u16 mas_graphics_3d_links[] = {
617 MSM8974_MNOC_TO_BIMC
618 };
619
620 static struct qcom_icc_node mas_graphics_3d = {
621 .name = "mas_graphics_3d",
622 .id = MSM8974_MNOC_MAS_GRAPHICS_3D,
623 .buswidth = 16,
624 .mas_rpm_id = 6,
625 .slv_rpm_id = -1,
626 .num_links = ARRAY_SIZE(mas_graphics_3d_links),
627 .links = mas_graphics_3d_links,
628 };
629
630 static const u16 mas_jpeg_links[] = {
631 MSM8974_MNOC_TO_BIMC
632 };
633
634 static struct qcom_icc_node mas_jpeg = {
635 .name = "mas_jpeg",
636 .id = MSM8974_MNOC_MAS_JPEG,
637 .buswidth = 16,
638 .mas_rpm_id = 7,
639 .slv_rpm_id = -1,
640 .num_links = ARRAY_SIZE(mas_jpeg_links),
641 .links = mas_jpeg_links,
642 };
643
644 static const u16 mas_mdp_port0_links[] = {
645 MSM8974_MNOC_TO_BIMC
646 };
647
648 static struct qcom_icc_node mas_mdp_port0 = {
649 .name = "mas_mdp_port0",
650 .id = MSM8974_MNOC_MAS_MDP_PORT0,
651 .buswidth = 16,
652 .mas_rpm_id = 8,
653 .slv_rpm_id = -1,
654 .num_links = ARRAY_SIZE(mas_mdp_port0_links),
655 .links = mas_mdp_port0_links,
656 };
657
658 static struct qcom_icc_node mas_video_p0 = {
659 .name = "mas_video_p0",
660 .id = MSM8974_MNOC_MAS_VIDEO_P0,
661 .buswidth = 16,
662 .mas_rpm_id = 9,
663 .slv_rpm_id = -1,
664 };
665
666 static struct qcom_icc_node mas_video_p1 = {
667 .name = "mas_video_p1",
668 .id = MSM8974_MNOC_MAS_VIDEO_P1,
669 .buswidth = 16,
670 .mas_rpm_id = 10,
671 .slv_rpm_id = -1,
672 };
673
674 static const u16 mas_vfe_links[] = {
675 MSM8974_MNOC_TO_BIMC
676 };
677
678 static struct qcom_icc_node mas_vfe = {
679 .name = "mas_vfe",
680 .id = MSM8974_MNOC_MAS_VFE,
681 .buswidth = 16,
682 .mas_rpm_id = 11,
683 .slv_rpm_id = -1,
684 .num_links = ARRAY_SIZE(mas_vfe_links),
685 .links = mas_vfe_links,
686 };
687
688 static struct qcom_icc_node mnoc_to_cnoc = {
689 .name = "mnoc_to_cnoc",
690 .id = MSM8974_MNOC_TO_CNOC,
691 .buswidth = 16,
692 .mas_rpm_id = 4,
693 .slv_rpm_id = -1,
694 };
695
696 static const u16 mnoc_to_bimc_links[] = {
697 MSM8974_BIMC_TO_MNOC
698 };
699
700 static struct qcom_icc_node mnoc_to_bimc = {
701 .name = "mnoc_to_bimc",
702 .id = MSM8974_MNOC_TO_BIMC,
703 .buswidth = 16,
704 .mas_rpm_id = -1,
705 .slv_rpm_id = 16,
706 .num_links = ARRAY_SIZE(mnoc_to_bimc_links),
707 .links = mnoc_to_bimc_links,
708 };
709
710 static struct qcom_icc_node slv_camera_cfg = {
711 .name = "slv_camera_cfg",
712 .id = MSM8974_MNOC_SLV_CAMERA_CFG,
713 .buswidth = 16,
714 .mas_rpm_id = -1,
715 .slv_rpm_id = 3,
716 };
717
718 static struct qcom_icc_node slv_display_cfg = {
719 .name = "slv_display_cfg",
720 .id = MSM8974_MNOC_SLV_DISPLAY_CFG,
721 .buswidth = 16,
722 .mas_rpm_id = -1,
723 .slv_rpm_id = 4,
724 };
725
726 static struct qcom_icc_node slv_ocmem_cfg = {
727 .name = "slv_ocmem_cfg",
728 .id = MSM8974_MNOC_SLV_OCMEM_CFG,
729 .buswidth = 16,
730 .mas_rpm_id = -1,
731 .slv_rpm_id = 5,
732 };
733
734 static struct qcom_icc_node slv_cpr_cfg = {
735 .name = "slv_cpr_cfg",
736 .id = MSM8974_MNOC_SLV_CPR_CFG,
737 .buswidth = 16,
738 .mas_rpm_id = -1,
739 .slv_rpm_id = 6,
740 };
741
742 static struct qcom_icc_node slv_cpr_xpu_cfg = {
743 .name = "slv_cpr_xpu_cfg",
744 .id = MSM8974_MNOC_SLV_CPR_XPU_CFG,
745 .buswidth = 16,
746 .mas_rpm_id = -1,
747 .slv_rpm_id = 7,
748 };
749
750 static struct qcom_icc_node slv_misc_cfg = {
751 .name = "slv_misc_cfg",
752 .id = MSM8974_MNOC_SLV_MISC_CFG,
753 .buswidth = 16,
754 .mas_rpm_id = -1,
755 .slv_rpm_id = 8,
756 };
757
758 static struct qcom_icc_node slv_misc_xpu_cfg = {
759 .name = "slv_misc_xpu_cfg",
760 .id = MSM8974_MNOC_SLV_MISC_XPU_CFG,
761 .buswidth = 16,
762 .mas_rpm_id = -1,
763 .slv_rpm_id = 9,
764 };
765
766 static struct qcom_icc_node slv_venus_cfg = {
767 .name = "slv_venus_cfg",
768 .id = MSM8974_MNOC_SLV_VENUS_CFG,
769 .buswidth = 16,
770 .mas_rpm_id = -1,
771 .slv_rpm_id = 10,
772 };
773
774 static struct qcom_icc_node slv_graphics_3d_cfg = {
775 .name = "slv_graphics_3d_cfg",
776 .id = MSM8974_MNOC_SLV_GRAPHICS_3D_CFG,
777 .buswidth = 16,
778 .mas_rpm_id = -1,
779 .slv_rpm_id = 11,
780 };
781
782 static struct qcom_icc_node slv_mmss_clk_cfg = {
783 .name = "slv_mmss_clk_cfg",
784 .id = MSM8974_MNOC_SLV_MMSS_CLK_CFG,
785 .buswidth = 16,
786 .mas_rpm_id = -1,
787 .slv_rpm_id = 12,
788 };
789
790 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
791 .name = "slv_mmss_clk_xpu_cfg",
792 .id = MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG,
793 .buswidth = 16,
794 .mas_rpm_id = -1,
795 .slv_rpm_id = 13,
796 };
797
798 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
799 .name = "slv_mnoc_mpu_cfg",
800 .id = MSM8974_MNOC_SLV_MNOC_MPU_CFG,
801 .buswidth = 16,
802 .mas_rpm_id = -1,
803 .slv_rpm_id = 14,
804 };
805
806 static struct qcom_icc_node slv_onoc_mpu_cfg = {
807 .name = "slv_onoc_mpu_cfg",
808 .id = MSM8974_MNOC_SLV_ONOC_MPU_CFG,
809 .buswidth = 16,
810 .mas_rpm_id = -1,
811 .slv_rpm_id = 15,
812 };
813
814 static struct qcom_icc_node slv_service_mnoc = {
815 .name = "slv_service_mnoc",
816 .id = MSM8974_MNOC_SLV_SERVICE_MNOC,
817 .buswidth = 16,
818 .mas_rpm_id = -1,
819 .slv_rpm_id = 17,
820 };
821
822 static struct qcom_icc_node * const msm8974_mnoc_nodes[] = {
823 [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d,
824 [MNOC_MAS_JPEG] = &mas_jpeg,
825 [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0,
826 [MNOC_MAS_VIDEO_P0] = &mas_video_p0,
827 [MNOC_MAS_VIDEO_P1] = &mas_video_p1,
828 [MNOC_MAS_VFE] = &mas_vfe,
829 [MNOC_TO_CNOC] = &mnoc_to_cnoc,
830 [MNOC_TO_BIMC] = &mnoc_to_bimc,
831 [MNOC_SLV_CAMERA_CFG] = &slv_camera_cfg,
832 [MNOC_SLV_DISPLAY_CFG] = &slv_display_cfg,
833 [MNOC_SLV_OCMEM_CFG] = &slv_ocmem_cfg,
834 [MNOC_SLV_CPR_CFG] = &slv_cpr_cfg,
835 [MNOC_SLV_CPR_XPU_CFG] = &slv_cpr_xpu_cfg,
836 [MNOC_SLV_MISC_CFG] = &slv_misc_cfg,
837 [MNOC_SLV_MISC_XPU_CFG] = &slv_misc_xpu_cfg,
838 [MNOC_SLV_VENUS_CFG] = &slv_venus_cfg,
839 [MNOC_SLV_GRAPHICS_3D_CFG] = &slv_graphics_3d_cfg,
840 [MNOC_SLV_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
841 [MNOC_SLV_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
842 [MNOC_SLV_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
843 [MNOC_SLV_ONOC_MPU_CFG] = &slv_onoc_mpu_cfg,
844 [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc,
845 };
846
847 static const struct qcom_icc_desc msm8974_mnoc = {
848 .nodes = msm8974_mnoc_nodes,
849 .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes),
850 .get_bw = msm8974_get_bw,
851 .ignore_enxio = true,
852 };
853
854 static const u16 ocmem_noc_to_ocmem_vnoc_links[] = {
855 MSM8974_OCMEM_SLV_OCMEM
856 };
857
858 static struct qcom_icc_node ocmem_noc_to_ocmem_vnoc = {
859 .name = "ocmem_noc_to_ocmem_vnoc",
860 .id = MSM8974_OCMEM_NOC_TO_OCMEM_VNOC,
861 .buswidth = 16,
862 .mas_rpm_id = 54,
863 .slv_rpm_id = 78,
864 .num_links = ARRAY_SIZE(ocmem_noc_to_ocmem_vnoc_links),
865 .links = ocmem_noc_to_ocmem_vnoc_links,
866 };
867
868 static struct qcom_icc_node mas_jpeg_ocmem = {
869 .name = "mas_jpeg_ocmem",
870 .id = MSM8974_OCMEM_MAS_JPEG_OCMEM,
871 .buswidth = 16,
872 .mas_rpm_id = 13,
873 .slv_rpm_id = -1,
874 };
875
876 static struct qcom_icc_node mas_mdp_ocmem = {
877 .name = "mas_mdp_ocmem",
878 .id = MSM8974_OCMEM_MAS_MDP_OCMEM,
879 .buswidth = 16,
880 .mas_rpm_id = 14,
881 .slv_rpm_id = -1,
882 };
883
884 static struct qcom_icc_node mas_video_p0_ocmem = {
885 .name = "mas_video_p0_ocmem",
886 .id = MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM,
887 .buswidth = 16,
888 .mas_rpm_id = 15,
889 .slv_rpm_id = -1,
890 };
891
892 static struct qcom_icc_node mas_video_p1_ocmem = {
893 .name = "mas_video_p1_ocmem",
894 .id = MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM,
895 .buswidth = 16,
896 .mas_rpm_id = 16,
897 .slv_rpm_id = -1,
898 };
899
900 static struct qcom_icc_node mas_vfe_ocmem = {
901 .name = "mas_vfe_ocmem",
902 .id = MSM8974_OCMEM_MAS_VFE_OCMEM,
903 .buswidth = 16,
904 .mas_rpm_id = 17,
905 .slv_rpm_id = -1,
906 };
907
908 static struct qcom_icc_node mas_cnoc_onoc_cfg = {
909 .name = "mas_cnoc_onoc_cfg",
910 .id = MSM8974_OCMEM_MAS_CNOC_ONOC_CFG,
911 .buswidth = 16,
912 .mas_rpm_id = 12,
913 .slv_rpm_id = -1,
914 };
915
916 static struct qcom_icc_node slv_service_onoc = {
917 .name = "slv_service_onoc",
918 .id = MSM8974_OCMEM_SLV_SERVICE_ONOC,
919 .buswidth = 16,
920 .mas_rpm_id = -1,
921 .slv_rpm_id = 19,
922 };
923
924 static struct qcom_icc_node slv_ocmem = {
925 .name = "slv_ocmem",
926 .id = MSM8974_OCMEM_SLV_OCMEM,
927 .buswidth = 16,
928 .mas_rpm_id = -1,
929 .slv_rpm_id = 18,
930 };
931
932 /* Virtual NoC is needed for connection to OCMEM */
933 static const u16 ocmem_vnoc_to_onoc_links[] = {
934 MSM8974_OCMEM_NOC_TO_OCMEM_VNOC
935 };
936
937 static struct qcom_icc_node ocmem_vnoc_to_onoc = {
938 .name = "ocmem_vnoc_to_onoc",
939 .id = MSM8974_OCMEM_VNOC_TO_OCMEM_NOC,
940 .buswidth = 16,
941 .mas_rpm_id = 56,
942 .slv_rpm_id = 79,
943 .num_links = ARRAY_SIZE(ocmem_vnoc_to_onoc_links),
944 .links = ocmem_vnoc_to_onoc_links,
945 };
946
947 static struct qcom_icc_node ocmem_vnoc_to_snoc = {
948 .name = "ocmem_vnoc_to_snoc",
949 .id = MSM8974_OCMEM_VNOC_TO_SNOC,
950 .buswidth = 8,
951 .mas_rpm_id = 57,
952 .slv_rpm_id = 80,
953 };
954
955 static const u16 mas_v_ocmem_gfx3d_links[] = {
956 MSM8974_OCMEM_VNOC_TO_OCMEM_NOC
957 };
958
959 static struct qcom_icc_node mas_v_ocmem_gfx3d = {
960 .name = "mas_v_ocmem_gfx3d",
961 .id = MSM8974_OCMEM_VNOC_MAS_GFX3D,
962 .buswidth = 8,
963 .mas_rpm_id = 55,
964 .slv_rpm_id = -1,
965 .num_links = ARRAY_SIZE(mas_v_ocmem_gfx3d_links),
966 .links = mas_v_ocmem_gfx3d_links,
967 };
968
969
970 static struct qcom_icc_node * const msm8974_onoc_nodes[] = {
971 [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc,
972 [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem,
973 [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem,
974 [OCMEM_MAS_VIDEO_P0_OCMEM] = &mas_video_p0_ocmem,
975 [OCMEM_MAS_VIDEO_P1_OCMEM] = &mas_video_p1_ocmem,
976 [OCMEM_MAS_VFE_OCMEM] = &mas_vfe_ocmem,
977 [OCMEM_MAS_CNOC_ONOC_CFG] = &mas_cnoc_onoc_cfg,
978 [OCMEM_SLV_SERVICE_ONOC] = &slv_service_onoc,
979 [OCMEM_VNOC_TO_SNOC] = &ocmem_vnoc_to_snoc,
980 [OCMEM_VNOC_TO_OCMEM_NOC] = &ocmem_vnoc_to_onoc,
981 [OCMEM_VNOC_MAS_GFX3D] = &mas_v_ocmem_gfx3d,
982 [OCMEM_SLV_OCMEM] = &slv_ocmem,
983 };
984
985 static const struct qcom_icc_desc msm8974_onoc = {
986 .nodes = msm8974_onoc_nodes,
987 .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes),
988 .bus_clk_desc = &gpu_mem_2_clk,
989 .get_bw = msm8974_get_bw,
990 .ignore_enxio = true,
991 };
992
993 static struct qcom_icc_node mas_pnoc_cfg = {
994 .name = "mas_pnoc_cfg",
995 .id = MSM8974_PNOC_MAS_PNOC_CFG,
996 .buswidth = 8,
997 .mas_rpm_id = 43,
998 .slv_rpm_id = -1,
999 };
1000
1001 static const u16 mas_sdcc_1_links[] = {
1002 MSM8974_PNOC_TO_SNOC
1003 };
1004
1005 static struct qcom_icc_node mas_sdcc_1 = {
1006 .name = "mas_sdcc_1",
1007 .id = MSM8974_PNOC_MAS_SDCC_1,
1008 .buswidth = 8,
1009 .mas_rpm_id = 33,
1010 .slv_rpm_id = -1,
1011 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
1012 .links = mas_sdcc_1_links,
1013 };
1014
1015 static const u16 mas_sdcc_3_links[] = {
1016 MSM8974_PNOC_TO_SNOC
1017 };
1018
1019 static struct qcom_icc_node mas_sdcc_3 = {
1020 .name = "mas_sdcc_3",
1021 .id = MSM8974_PNOC_MAS_SDCC_3,
1022 .buswidth = 8,
1023 .mas_rpm_id = 34,
1024 .slv_rpm_id = -1,
1025 .num_links = ARRAY_SIZE(mas_sdcc_3_links),
1026 .links = mas_sdcc_3_links,
1027 };
1028
1029 static const u16 mas_sdcc_4_links[] = {
1030 MSM8974_PNOC_TO_SNOC
1031 };
1032
1033 static struct qcom_icc_node mas_sdcc_4 = {
1034 .name = "mas_sdcc_4",
1035 .id = MSM8974_PNOC_MAS_SDCC_4,
1036 .buswidth = 8,
1037 .mas_rpm_id = 36,
1038 .slv_rpm_id = -1,
1039 .num_links = ARRAY_SIZE(mas_sdcc_4_links),
1040 .links = mas_sdcc_4_links,
1041 };
1042
1043 static const u16 mas_sdcc_2_links[] = {
1044 MSM8974_PNOC_TO_SNOC
1045 };
1046
1047 static struct qcom_icc_node mas_sdcc_2 = {
1048 .name = "mas_sdcc_2",
1049 .id = MSM8974_PNOC_MAS_SDCC_2,
1050 .buswidth = 8,
1051 .mas_rpm_id = 35,
1052 .slv_rpm_id = -1,
1053 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
1054 .links = mas_sdcc_2_links,
1055 };
1056
1057 static const u16 mas_tsif_links[] = {
1058 MSM8974_PNOC_TO_SNOC
1059 };
1060
1061 static struct qcom_icc_node mas_tsif = {
1062 .name = "mas_tsif",
1063 .id = MSM8974_PNOC_MAS_TSIF,
1064 .buswidth = 8,
1065 .mas_rpm_id = 37,
1066 .slv_rpm_id = -1,
1067 .num_links = ARRAY_SIZE(mas_tsif_links),
1068 .links = mas_tsif_links,
1069 };
1070
1071 static struct qcom_icc_node mas_bam_dma = {
1072 .name = "mas_bam_dma",
1073 .id = MSM8974_PNOC_MAS_BAM_DMA,
1074 .buswidth = 8,
1075 .mas_rpm_id = 38,
1076 .slv_rpm_id = -1,
1077 };
1078
1079 static const u16 mas_blsp_2_links[] = {
1080 MSM8974_PNOC_TO_SNOC
1081 };
1082
1083 static struct qcom_icc_node mas_blsp_2 = {
1084 .name = "mas_blsp_2",
1085 .id = MSM8974_PNOC_MAS_BLSP_2,
1086 .buswidth = 8,
1087 .mas_rpm_id = 39,
1088 .slv_rpm_id = -1,
1089 .num_links = ARRAY_SIZE(mas_blsp_2_links),
1090 .links = mas_blsp_2_links,
1091 };
1092
1093 static const u16 mas_usb_hsic_links[] = {
1094 MSM8974_PNOC_TO_SNOC
1095 };
1096
1097 static struct qcom_icc_node mas_usb_hsic = {
1098 .name = "mas_usb_hsic",
1099 .id = MSM8974_PNOC_MAS_USB_HSIC,
1100 .buswidth = 8,
1101 .mas_rpm_id = 40,
1102 .slv_rpm_id = -1,
1103 .num_links = ARRAY_SIZE(mas_usb_hsic_links),
1104 .links = mas_usb_hsic_links,
1105 };
1106
1107 static const u16 mas_blsp_1_links[] = {
1108 MSM8974_PNOC_TO_SNOC
1109 };
1110
1111 static struct qcom_icc_node mas_blsp_1 = {
1112 .name = "mas_blsp_1",
1113 .id = MSM8974_PNOC_MAS_BLSP_1,
1114 .buswidth = 8,
1115 .mas_rpm_id = 41,
1116 .slv_rpm_id = -1,
1117 .num_links = ARRAY_SIZE(mas_blsp_1_links),
1118 .links = mas_blsp_1_links,
1119 };
1120
1121 static const u16 mas_usb_hs_links[] = {
1122 MSM8974_PNOC_TO_SNOC
1123 };
1124
1125 static struct qcom_icc_node mas_usb_hs = {
1126 .name = "mas_usb_hs",
1127 .id = MSM8974_PNOC_MAS_USB_HS,
1128 .buswidth = 8,
1129 .mas_rpm_id = 42,
1130 .slv_rpm_id = -1,
1131 .num_links = ARRAY_SIZE(mas_usb_hs_links),
1132 .links = mas_usb_hs_links,
1133 };
1134
1135 static const u16 pnoc_to_snoc_links[] = {
1136 MSM8974_SNOC_TO_PNOC,
1137 MSM8974_PNOC_SLV_PRNG
1138 };
1139
1140 static struct qcom_icc_node pnoc_to_snoc = {
1141 .name = "pnoc_to_snoc",
1142 .id = MSM8974_PNOC_TO_SNOC,
1143 .buswidth = 8,
1144 .mas_rpm_id = 44,
1145 .slv_rpm_id = 45,
1146 .num_links = ARRAY_SIZE(pnoc_to_snoc_links),
1147 .links = pnoc_to_snoc_links,
1148 };
1149
1150 static struct qcom_icc_node slv_sdcc_1 = {
1151 .name = "slv_sdcc_1",
1152 .id = MSM8974_PNOC_SLV_SDCC_1,
1153 .buswidth = 8,
1154 .mas_rpm_id = -1,
1155 .slv_rpm_id = 31,
1156 };
1157
1158 static struct qcom_icc_node slv_sdcc_3 = {
1159 .name = "slv_sdcc_3",
1160 .id = MSM8974_PNOC_SLV_SDCC_3,
1161 .buswidth = 8,
1162 .mas_rpm_id = -1,
1163 .slv_rpm_id = 32,
1164 };
1165
1166 static struct qcom_icc_node slv_sdcc_2 = {
1167 .name = "slv_sdcc_2",
1168 .id = MSM8974_PNOC_SLV_SDCC_2,
1169 .buswidth = 8,
1170 .mas_rpm_id = -1,
1171 .slv_rpm_id = 33,
1172 };
1173
1174 static struct qcom_icc_node slv_sdcc_4 = {
1175 .name = "slv_sdcc_4",
1176 .id = MSM8974_PNOC_SLV_SDCC_4,
1177 .buswidth = 8,
1178 .mas_rpm_id = -1,
1179 .slv_rpm_id = 34,
1180 };
1181
1182 static struct qcom_icc_node slv_tsif = {
1183 .name = "slv_tsif",
1184 .id = MSM8974_PNOC_SLV_TSIF,
1185 .buswidth = 8,
1186 .mas_rpm_id = -1,
1187 .slv_rpm_id = 35,
1188 };
1189
1190 static struct qcom_icc_node slv_bam_dma = {
1191 .name = "slv_bam_dma",
1192 .id = MSM8974_PNOC_SLV_BAM_DMA,
1193 .buswidth = 8,
1194 .mas_rpm_id = -1,
1195 .slv_rpm_id = 36,
1196 };
1197
1198 static struct qcom_icc_node slv_blsp_2 = {
1199 .name = "slv_blsp_2",
1200 .id = MSM8974_PNOC_SLV_BLSP_2,
1201 .buswidth = 8,
1202 .mas_rpm_id = -1,
1203 .slv_rpm_id = 37,
1204 };
1205
1206 static struct qcom_icc_node slv_usb_hsic = {
1207 .name = "slv_usb_hsic",
1208 .id = MSM8974_PNOC_SLV_USB_HSIC,
1209 .buswidth = 8,
1210 .mas_rpm_id = -1,
1211 .slv_rpm_id = 38,
1212 };
1213
1214 static struct qcom_icc_node slv_blsp_1 = {
1215 .name = "slv_blsp_1",
1216 .id = MSM8974_PNOC_SLV_BLSP_1,
1217 .buswidth = 8,
1218 .mas_rpm_id = -1,
1219 .slv_rpm_id = 39,
1220 };
1221
1222 static struct qcom_icc_node slv_usb_hs = {
1223 .name = "slv_usb_hs",
1224 .id = MSM8974_PNOC_SLV_USB_HS,
1225 .buswidth = 8,
1226 .mas_rpm_id = -1,
1227 .slv_rpm_id = 40,
1228 };
1229
1230 static struct qcom_icc_node slv_pdm = {
1231 .name = "slv_pdm",
1232 .id = MSM8974_PNOC_SLV_PDM,
1233 .buswidth = 8,
1234 .mas_rpm_id = -1,
1235 .slv_rpm_id = 41,
1236 };
1237
1238 static struct qcom_icc_node slv_periph_apu_cfg = {
1239 .name = "slv_periph_apu_cfg",
1240 .id = MSM8974_PNOC_SLV_PERIPH_APU_CFG,
1241 .buswidth = 8,
1242 .mas_rpm_id = -1,
1243 .slv_rpm_id = 42,
1244 };
1245
1246 static struct qcom_icc_node slv_pnoc_mpu_cfg = {
1247 .name = "slv_pnoc_mpu_cfg",
1248 .id = MSM8974_PNOC_SLV_PNOC_MPU_CFG,
1249 .buswidth = 8,
1250 .mas_rpm_id = -1,
1251 .slv_rpm_id = 43,
1252 };
1253
1254 static const u16 slv_prng_links[] = {
1255 MSM8974_PNOC_TO_SNOC
1256 };
1257
1258 static struct qcom_icc_node slv_prng = {
1259 .name = "slv_prng",
1260 .id = MSM8974_PNOC_SLV_PRNG,
1261 .buswidth = 8,
1262 .mas_rpm_id = -1,
1263 .slv_rpm_id = 44,
1264 .num_links = ARRAY_SIZE(slv_prng_links),
1265 .links = slv_prng_links,
1266 };
1267
1268 static struct qcom_icc_node slv_service_pnoc = {
1269 .name = "slv_service_pnoc",
1270 .id = MSM8974_PNOC_SLV_SERVICE_PNOC,
1271 .buswidth = 8,
1272 .mas_rpm_id = -1,
1273 .slv_rpm_id = 46,
1274 };
1275
1276 static struct qcom_icc_node * const msm8974_pnoc_nodes[] = {
1277 [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg,
1278 [PNOC_MAS_SDCC_1] = &mas_sdcc_1,
1279 [PNOC_MAS_SDCC_3] = &mas_sdcc_3,
1280 [PNOC_MAS_SDCC_4] = &mas_sdcc_4,
1281 [PNOC_MAS_SDCC_2] = &mas_sdcc_2,
1282 [PNOC_MAS_TSIF] = &mas_tsif,
1283 [PNOC_MAS_BAM_DMA] = &mas_bam_dma,
1284 [PNOC_MAS_BLSP_2] = &mas_blsp_2,
1285 [PNOC_MAS_USB_HSIC] = &mas_usb_hsic,
1286 [PNOC_MAS_BLSP_1] = &mas_blsp_1,
1287 [PNOC_MAS_USB_HS] = &mas_usb_hs,
1288 [PNOC_TO_SNOC] = &pnoc_to_snoc,
1289 [PNOC_SLV_SDCC_1] = &slv_sdcc_1,
1290 [PNOC_SLV_SDCC_3] = &slv_sdcc_3,
1291 [PNOC_SLV_SDCC_2] = &slv_sdcc_2,
1292 [PNOC_SLV_SDCC_4] = &slv_sdcc_4,
1293 [PNOC_SLV_TSIF] = &slv_tsif,
1294 [PNOC_SLV_BAM_DMA] = &slv_bam_dma,
1295 [PNOC_SLV_BLSP_2] = &slv_blsp_2,
1296 [PNOC_SLV_USB_HSIC] = &slv_usb_hsic,
1297 [PNOC_SLV_BLSP_1] = &slv_blsp_1,
1298 [PNOC_SLV_USB_HS] = &slv_usb_hs,
1299 [PNOC_SLV_PDM] = &slv_pdm,
1300 [PNOC_SLV_PERIPH_APU_CFG] = &slv_periph_apu_cfg,
1301 [PNOC_SLV_PNOC_MPU_CFG] = &slv_pnoc_mpu_cfg,
1302 [PNOC_SLV_PRNG] = &slv_prng,
1303 [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc,
1304 };
1305
1306 static const struct qcom_icc_desc msm8974_pnoc = {
1307 .nodes = msm8974_pnoc_nodes,
1308 .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes),
1309 .bus_clk_desc = &bus_0_clk,
1310 .get_bw = msm8974_get_bw,
1311 .keep_alive = true,
1312 .ignore_enxio = true,
1313 };
1314
1315 static struct qcom_icc_node mas_lpass_ahb = {
1316 .name = "mas_lpass_ahb",
1317 .id = MSM8974_SNOC_MAS_LPASS_AHB,
1318 .buswidth = 8,
1319 .mas_rpm_id = 18,
1320 .slv_rpm_id = -1,
1321 };
1322
1323 static struct qcom_icc_node mas_qdss_bam = {
1324 .name = "mas_qdss_bam",
1325 .id = MSM8974_SNOC_MAS_QDSS_BAM,
1326 .buswidth = 8,
1327 .mas_rpm_id = 19,
1328 .slv_rpm_id = -1,
1329 };
1330
1331 static struct qcom_icc_node mas_snoc_cfg = {
1332 .name = "mas_snoc_cfg",
1333 .id = MSM8974_SNOC_MAS_SNOC_CFG,
1334 .buswidth = 8,
1335 .mas_rpm_id = 20,
1336 .slv_rpm_id = -1,
1337 };
1338
1339 static const u16 snoc_to_bimc_links[] = {
1340 MSM8974_BIMC_TO_SNOC
1341 };
1342
1343 static struct qcom_icc_node snoc_to_bimc = {
1344 .name = "snoc_to_bimc",
1345 .id = MSM8974_SNOC_TO_BIMC,
1346 .buswidth = 8,
1347 .mas_rpm_id = 21,
1348 .slv_rpm_id = 24,
1349 .num_links = ARRAY_SIZE(snoc_to_bimc_links),
1350 .links = snoc_to_bimc_links,
1351 };
1352
1353 static struct qcom_icc_node snoc_to_cnoc = {
1354 .name = "snoc_to_cnoc",
1355 .id = MSM8974_SNOC_TO_CNOC,
1356 .buswidth = 8,
1357 .mas_rpm_id = 22,
1358 .slv_rpm_id = 25,
1359 };
1360
1361 static const u16 snoc_to_pnoc_links[] = {
1362 MSM8974_PNOC_TO_SNOC
1363 };
1364
1365 static struct qcom_icc_node snoc_to_pnoc = {
1366 .name = "snoc_to_pnoc",
1367 .id = MSM8974_SNOC_TO_PNOC,
1368 .buswidth = 8,
1369 .mas_rpm_id = 29,
1370 .slv_rpm_id = 28,
1371 .num_links = ARRAY_SIZE(snoc_to_pnoc_links),
1372 .links = snoc_to_pnoc_links,
1373 };
1374
1375 static const u16 snoc_to_ocmem_vnoc_links[] = {
1376 MSM8974_OCMEM_VNOC_TO_OCMEM_NOC
1377 };
1378
1379 static struct qcom_icc_node snoc_to_ocmem_vnoc = {
1380 .name = "snoc_to_ocmem_vnoc",
1381 .id = MSM8974_SNOC_TO_OCMEM_VNOC,
1382 .buswidth = 8,
1383 .mas_rpm_id = 53,
1384 .slv_rpm_id = 77,
1385 .num_links = ARRAY_SIZE(snoc_to_ocmem_vnoc_links),
1386 .links = snoc_to_ocmem_vnoc_links,
1387 };
1388
1389 static const u16 mas_crypto_core0_links[] = {
1390 MSM8974_SNOC_TO_BIMC
1391 };
1392
1393 static struct qcom_icc_node mas_crypto_core0 = {
1394 .name = "mas_crypto_core0",
1395 .id = MSM8974_SNOC_MAS_CRYPTO_CORE0,
1396 .buswidth = 8,
1397 .mas_rpm_id = 23,
1398 .slv_rpm_id = -1,
1399 .num_links = ARRAY_SIZE(mas_crypto_core0_links),
1400 .links = mas_crypto_core0_links,
1401 };
1402
1403 static struct qcom_icc_node mas_crypto_core1 = {
1404 .name = "mas_crypto_core1",
1405 .id = MSM8974_SNOC_MAS_CRYPTO_CORE1,
1406 .buswidth = 8,
1407 .mas_rpm_id = 24,
1408 .slv_rpm_id = -1,
1409 };
1410
1411 static const u16 mas_lpass_proc_links[] = {
1412 MSM8974_SNOC_TO_OCMEM_VNOC
1413 };
1414
1415 static struct qcom_icc_node mas_lpass_proc = {
1416 .name = "mas_lpass_proc",
1417 .id = MSM8974_SNOC_MAS_LPASS_PROC,
1418 .buswidth = 8,
1419 .mas_rpm_id = 25,
1420 .slv_rpm_id = -1,
1421 .num_links = ARRAY_SIZE(mas_lpass_proc_links),
1422 .links = mas_lpass_proc_links,
1423 };
1424
1425 static struct qcom_icc_node mas_mss = {
1426 .name = "mas_mss",
1427 .id = MSM8974_SNOC_MAS_MSS,
1428 .buswidth = 8,
1429 .mas_rpm_id = 26,
1430 .slv_rpm_id = -1,
1431 };
1432
1433 static struct qcom_icc_node mas_mss_nav = {
1434 .name = "mas_mss_nav",
1435 .id = MSM8974_SNOC_MAS_MSS_NAV,
1436 .buswidth = 8,
1437 .mas_rpm_id = 27,
1438 .slv_rpm_id = -1,
1439 };
1440
1441 static struct qcom_icc_node mas_ocmem_dma = {
1442 .name = "mas_ocmem_dma",
1443 .id = MSM8974_SNOC_MAS_OCMEM_DMA,
1444 .buswidth = 8,
1445 .mas_rpm_id = 28,
1446 .slv_rpm_id = -1,
1447 };
1448
1449 static struct qcom_icc_node mas_wcss = {
1450 .name = "mas_wcss",
1451 .id = MSM8974_SNOC_MAS_WCSS,
1452 .buswidth = 8,
1453 .mas_rpm_id = 30,
1454 .slv_rpm_id = -1,
1455 };
1456
1457 static struct qcom_icc_node mas_qdss_etr = {
1458 .name = "mas_qdss_etr",
1459 .id = MSM8974_SNOC_MAS_QDSS_ETR,
1460 .buswidth = 8,
1461 .mas_rpm_id = 31,
1462 .slv_rpm_id = -1,
1463 };
1464
1465 static const u16 mas_usb3_links[] = {
1466 MSM8974_SNOC_TO_BIMC
1467 };
1468
1469 static struct qcom_icc_node mas_usb3 = {
1470 .name = "mas_usb3",
1471 .id = MSM8974_SNOC_MAS_USB3,
1472 .buswidth = 8,
1473 .mas_rpm_id = 32,
1474 .slv_rpm_id = -1,
1475 .num_links = ARRAY_SIZE(mas_usb3_links),
1476 .links = mas_usb3_links,
1477 };
1478
1479 static struct qcom_icc_node slv_ampss = {
1480 .name = "slv_ampss",
1481 .id = MSM8974_SNOC_SLV_AMPSS,
1482 .buswidth = 8,
1483 .mas_rpm_id = -1,
1484 .slv_rpm_id = 20,
1485 };
1486
1487 static struct qcom_icc_node slv_lpass = {
1488 .name = "slv_lpass",
1489 .id = MSM8974_SNOC_SLV_LPASS,
1490 .buswidth = 8,
1491 .mas_rpm_id = -1,
1492 .slv_rpm_id = 21,
1493 };
1494
1495 static struct qcom_icc_node slv_usb3 = {
1496 .name = "slv_usb3",
1497 .id = MSM8974_SNOC_SLV_USB3,
1498 .buswidth = 8,
1499 .mas_rpm_id = -1,
1500 .slv_rpm_id = 22,
1501 };
1502
1503 static struct qcom_icc_node slv_wcss = {
1504 .name = "slv_wcss",
1505 .id = MSM8974_SNOC_SLV_WCSS,
1506 .buswidth = 8,
1507 .mas_rpm_id = -1,
1508 .slv_rpm_id = 23,
1509 };
1510
1511 static struct qcom_icc_node slv_ocimem = {
1512 .name = "slv_ocimem",
1513 .id = MSM8974_SNOC_SLV_OCIMEM,
1514 .buswidth = 8,
1515 .mas_rpm_id = -1,
1516 .slv_rpm_id = 26,
1517 };
1518
1519 static struct qcom_icc_node slv_snoc_ocmem = {
1520 .name = "slv_snoc_ocmem",
1521 .id = MSM8974_SNOC_SLV_SNOC_OCMEM,
1522 .buswidth = 8,
1523 .mas_rpm_id = -1,
1524 .slv_rpm_id = 27,
1525 };
1526
1527 static struct qcom_icc_node slv_service_snoc = {
1528 .name = "slv_service_snoc",
1529 .id = MSM8974_SNOC_SLV_SERVICE_SNOC,
1530 .buswidth = 8,
1531 .mas_rpm_id = -1,
1532 .slv_rpm_id = 29,
1533 };
1534
1535 static struct qcom_icc_node slv_qdss_stm = {
1536 .name = "slv_qdss_stm",
1537 .id = MSM8974_SNOC_SLV_QDSS_STM,
1538 .buswidth = 8,
1539 .mas_rpm_id = -1,
1540 .slv_rpm_id = 30,
1541 };
1542
1543 static struct qcom_icc_node * const msm8974_snoc_nodes[] = {
1544 [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb,
1545 [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam,
1546 [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg,
1547 [SNOC_TO_BIMC] = &snoc_to_bimc,
1548 [SNOC_TO_CNOC] = &snoc_to_cnoc,
1549 [SNOC_TO_PNOC] = &snoc_to_pnoc,
1550 [SNOC_TO_OCMEM_VNOC] = &snoc_to_ocmem_vnoc,
1551 [SNOC_MAS_CRYPTO_CORE0] = &mas_crypto_core0,
1552 [SNOC_MAS_CRYPTO_CORE1] = &mas_crypto_core1,
1553 [SNOC_MAS_LPASS_PROC] = &mas_lpass_proc,
1554 [SNOC_MAS_MSS] = &mas_mss,
1555 [SNOC_MAS_MSS_NAV] = &mas_mss_nav,
1556 [SNOC_MAS_OCMEM_DMA] = &mas_ocmem_dma,
1557 [SNOC_MAS_WCSS] = &mas_wcss,
1558 [SNOC_MAS_QDSS_ETR] = &mas_qdss_etr,
1559 [SNOC_MAS_USB3] = &mas_usb3,
1560 [SNOC_SLV_AMPSS] = &slv_ampss,
1561 [SNOC_SLV_LPASS] = &slv_lpass,
1562 [SNOC_SLV_USB3] = &slv_usb3,
1563 [SNOC_SLV_WCSS] = &slv_wcss,
1564 [SNOC_SLV_OCIMEM] = &slv_ocimem,
1565 [SNOC_SLV_SNOC_OCMEM] = &slv_snoc_ocmem,
1566 [SNOC_SLV_SERVICE_SNOC] = &slv_service_snoc,
1567 [SNOC_SLV_QDSS_STM] = &slv_qdss_stm,
1568 };
1569
1570 static const struct qcom_icc_desc msm8974_snoc = {
1571 .nodes = msm8974_snoc_nodes,
1572 .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes),
1573 .bus_clk_desc = &bus_1_clk,
1574 .get_bw = msm8974_get_bw,
1575 .ignore_enxio = true,
1576 };
1577
1578 static const struct of_device_id msm8974_noc_of_match[] = {
1579 { .compatible = "qcom,msm8974-bimc", .data = &msm8974_bimc},
1580 { .compatible = "qcom,msm8974-cnoc", .data = &msm8974_cnoc},
1581 { .compatible = "qcom,msm8974-mmssnoc", .data = &msm8974_mnoc},
1582 { .compatible = "qcom,msm8974-ocmemnoc", .data = &msm8974_onoc},
1583 { .compatible = "qcom,msm8974-pnoc", .data = &msm8974_pnoc},
1584 { .compatible = "qcom,msm8974-snoc", .data = &msm8974_snoc},
1585 { },
1586 };
1587 MODULE_DEVICE_TABLE(of, msm8974_noc_of_match);
1588
1589 static struct platform_driver msm8974_noc_driver = {
1590 .probe = qnoc_probe,
1591 .remove = qnoc_remove,
1592 .driver = {
1593 .name = "qnoc-msm8974",
1594 .of_match_table = msm8974_noc_of_match,
1595 .sync_state = icc_sync_state,
1596 },
1597 };
1598 module_platform_driver(msm8974_noc_driver);
1599 MODULE_DESCRIPTION("Qualcomm MSM8974 NoC driver");
1600 MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>");
1601 MODULE_LICENSE("GPL v2");
1602