1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Linaro Ltd 4 * Author: Jun Nie <jun.nie@linaro.org> 5 * With reference of msm8916 interconnect driver of Georgi Djakov. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/interconnect/qcom,msm8939.h> 16 17 #include "icc-rpm.h" 18 19 enum { 20 MSM8939_BIMC_SNOC_MAS = 1, 21 MSM8939_BIMC_SNOC_SLV, 22 MSM8939_MASTER_AMPSS_M0, 23 MSM8939_MASTER_LPASS, 24 MSM8939_MASTER_BLSP_1, 25 MSM8939_MASTER_DEHR, 26 MSM8939_MASTER_GRAPHICS_3D, 27 MSM8939_MASTER_JPEG, 28 MSM8939_MASTER_MDP_PORT0, 29 MSM8939_MASTER_MDP_PORT1, 30 MSM8939_MASTER_CPP, 31 MSM8939_MASTER_CRYPTO_CORE0, 32 MSM8939_MASTER_SDCC_1, 33 MSM8939_MASTER_SDCC_2, 34 MSM8939_MASTER_QDSS_BAM, 35 MSM8939_MASTER_QDSS_ETR, 36 MSM8939_MASTER_SNOC_CFG, 37 MSM8939_MASTER_SPDM, 38 MSM8939_MASTER_TCU0, 39 MSM8939_MASTER_USB_HS1, 40 MSM8939_MASTER_USB_HS2, 41 MSM8939_MASTER_VFE, 42 MSM8939_MASTER_VIDEO_P0, 43 MSM8939_SNOC_MM_INT_0, 44 MSM8939_SNOC_MM_INT_1, 45 MSM8939_SNOC_MM_INT_2, 46 MSM8939_PNOC_INT_0, 47 MSM8939_PNOC_INT_1, 48 MSM8939_PNOC_MAS_0, 49 MSM8939_PNOC_MAS_1, 50 MSM8939_PNOC_SLV_0, 51 MSM8939_PNOC_SLV_1, 52 MSM8939_PNOC_SLV_2, 53 MSM8939_PNOC_SLV_3, 54 MSM8939_PNOC_SLV_4, 55 MSM8939_PNOC_SLV_8, 56 MSM8939_PNOC_SLV_9, 57 MSM8939_PNOC_SNOC_MAS, 58 MSM8939_PNOC_SNOC_SLV, 59 MSM8939_SNOC_QDSS_INT, 60 MSM8939_SLAVE_AMPSS_L2, 61 MSM8939_SLAVE_APSS, 62 MSM8939_SLAVE_LPASS, 63 MSM8939_SLAVE_BIMC_CFG, 64 MSM8939_SLAVE_BLSP_1, 65 MSM8939_SLAVE_BOOT_ROM, 66 MSM8939_SLAVE_CAMERA_CFG, 67 MSM8939_SLAVE_CATS_128, 68 MSM8939_SLAVE_OCMEM_64, 69 MSM8939_SLAVE_CLK_CTL, 70 MSM8939_SLAVE_CRYPTO_0_CFG, 71 MSM8939_SLAVE_DEHR_CFG, 72 MSM8939_SLAVE_DISPLAY_CFG, 73 MSM8939_SLAVE_EBI_CH0, 74 MSM8939_SLAVE_GRAPHICS_3D_CFG, 75 MSM8939_SLAVE_IMEM_CFG, 76 MSM8939_SLAVE_IMEM, 77 MSM8939_SLAVE_MPM, 78 MSM8939_SLAVE_MSG_RAM, 79 MSM8939_SLAVE_MSS, 80 MSM8939_SLAVE_PDM, 81 MSM8939_SLAVE_PMIC_ARB, 82 MSM8939_SLAVE_PNOC_CFG, 83 MSM8939_SLAVE_PRNG, 84 MSM8939_SLAVE_QDSS_CFG, 85 MSM8939_SLAVE_QDSS_STM, 86 MSM8939_SLAVE_RBCPR_CFG, 87 MSM8939_SLAVE_SDCC_1, 88 MSM8939_SLAVE_SDCC_2, 89 MSM8939_SLAVE_SECURITY, 90 MSM8939_SLAVE_SNOC_CFG, 91 MSM8939_SLAVE_SPDM, 92 MSM8939_SLAVE_SRVC_SNOC, 93 MSM8939_SLAVE_TCSR, 94 MSM8939_SLAVE_TLMM, 95 MSM8939_SLAVE_USB_HS1, 96 MSM8939_SLAVE_USB_HS2, 97 MSM8939_SLAVE_VENUS_CFG, 98 MSM8939_SNOC_BIMC_0_MAS, 99 MSM8939_SNOC_BIMC_0_SLV, 100 MSM8939_SNOC_BIMC_1_MAS, 101 MSM8939_SNOC_BIMC_1_SLV, 102 MSM8939_SNOC_BIMC_2_MAS, 103 MSM8939_SNOC_BIMC_2_SLV, 104 MSM8939_SNOC_INT_0, 105 MSM8939_SNOC_INT_1, 106 MSM8939_SNOC_INT_BIMC, 107 MSM8939_SNOC_PNOC_MAS, 108 MSM8939_SNOC_PNOC_SLV, 109 }; 110 111 static const u16 bimc_snoc_mas_links[] = { 112 MSM8939_BIMC_SNOC_SLV 113 }; 114 115 static struct qcom_icc_node bimc_snoc_mas = { 116 .name = "bimc_snoc_mas", 117 .id = MSM8939_BIMC_SNOC_MAS, 118 .buswidth = 8, 119 .mas_rpm_id = -1, 120 .slv_rpm_id = -1, 121 .qos.ap_owned = true, 122 .qos.qos_mode = NOC_QOS_MODE_INVALID, 123 .num_links = ARRAY_SIZE(bimc_snoc_mas_links), 124 .links = bimc_snoc_mas_links, 125 }; 126 127 static const u16 bimc_snoc_slv_links[] = { 128 MSM8939_SNOC_INT_0, 129 MSM8939_SNOC_INT_1 130 }; 131 132 static struct qcom_icc_node bimc_snoc_slv = { 133 .name = "bimc_snoc_slv", 134 .id = MSM8939_BIMC_SNOC_SLV, 135 .buswidth = 16, 136 .mas_rpm_id = -1, 137 .slv_rpm_id = 2, 138 .num_links = ARRAY_SIZE(bimc_snoc_slv_links), 139 .links = bimc_snoc_slv_links, 140 }; 141 142 static const u16 mas_apss_links[] = { 143 MSM8939_SLAVE_EBI_CH0, 144 MSM8939_BIMC_SNOC_MAS, 145 MSM8939_SLAVE_AMPSS_L2 146 }; 147 148 static struct qcom_icc_node mas_apss = { 149 .name = "mas_apss", 150 .id = MSM8939_MASTER_AMPSS_M0, 151 .buswidth = 16, 152 .mas_rpm_id = -1, 153 .slv_rpm_id = -1, 154 .qos.ap_owned = true, 155 .qos.qos_mode = NOC_QOS_MODE_FIXED, 156 .qos.areq_prio = 0, 157 .qos.prio_level = 0, 158 .qos.qos_port = 0, 159 .num_links = ARRAY_SIZE(mas_apss_links), 160 .links = mas_apss_links, 161 }; 162 163 static const u16 mas_audio_links[] = { 164 MSM8939_PNOC_MAS_0 165 }; 166 167 static struct qcom_icc_node mas_audio = { 168 .name = "mas_audio", 169 .id = MSM8939_MASTER_LPASS, 170 .buswidth = 4, 171 .mas_rpm_id = -1, 172 .slv_rpm_id = -1, 173 .num_links = ARRAY_SIZE(mas_audio_links), 174 .links = mas_audio_links, 175 }; 176 177 static const u16 mas_blsp_1_links[] = { 178 MSM8939_PNOC_MAS_1 179 }; 180 181 static struct qcom_icc_node mas_blsp_1 = { 182 .name = "mas_blsp_1", 183 .id = MSM8939_MASTER_BLSP_1, 184 .buswidth = 4, 185 .mas_rpm_id = -1, 186 .slv_rpm_id = -1, 187 .num_links = ARRAY_SIZE(mas_blsp_1_links), 188 .links = mas_blsp_1_links, 189 }; 190 191 static const u16 mas_dehr_links[] = { 192 MSM8939_PNOC_MAS_0 193 }; 194 195 static struct qcom_icc_node mas_dehr = { 196 .name = "mas_dehr", 197 .id = MSM8939_MASTER_DEHR, 198 .buswidth = 4, 199 .mas_rpm_id = -1, 200 .slv_rpm_id = -1, 201 .num_links = ARRAY_SIZE(mas_dehr_links), 202 .links = mas_dehr_links, 203 }; 204 205 static const u16 mas_gfx_links[] = { 206 MSM8939_SLAVE_EBI_CH0, 207 MSM8939_BIMC_SNOC_MAS, 208 MSM8939_SLAVE_AMPSS_L2 209 }; 210 211 static struct qcom_icc_node mas_gfx = { 212 .name = "mas_gfx", 213 .id = MSM8939_MASTER_GRAPHICS_3D, 214 .buswidth = 16, 215 .mas_rpm_id = -1, 216 .slv_rpm_id = -1, 217 .qos.ap_owned = true, 218 .qos.qos_mode = NOC_QOS_MODE_FIXED, 219 .qos.areq_prio = 0, 220 .qos.prio_level = 0, 221 .qos.qos_port = 2, 222 .num_links = ARRAY_SIZE(mas_gfx_links), 223 .links = mas_gfx_links, 224 }; 225 226 static const u16 mas_jpeg_links[] = { 227 MSM8939_SNOC_MM_INT_0, 228 MSM8939_SNOC_MM_INT_2 229 }; 230 231 static struct qcom_icc_node mas_jpeg = { 232 .name = "mas_jpeg", 233 .id = MSM8939_MASTER_JPEG, 234 .buswidth = 16, 235 .mas_rpm_id = -1, 236 .slv_rpm_id = -1, 237 .qos.ap_owned = true, 238 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 239 .qos.areq_prio = 0, 240 .qos.prio_level = 0, 241 .qos.qos_port = 6, 242 .num_links = ARRAY_SIZE(mas_jpeg_links), 243 .links = mas_jpeg_links, 244 }; 245 246 static const u16 mas_mdp0_links[] = { 247 MSM8939_SNOC_MM_INT_1, 248 MSM8939_SNOC_MM_INT_2 249 }; 250 251 static struct qcom_icc_node mas_mdp0 = { 252 .name = "mas_mdp0", 253 .id = MSM8939_MASTER_MDP_PORT0, 254 .buswidth = 16, 255 .mas_rpm_id = -1, 256 .slv_rpm_id = -1, 257 .qos.ap_owned = true, 258 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 259 .qos.areq_prio = 0, 260 .qos.prio_level = 0, 261 .qos.qos_port = 7, 262 .num_links = ARRAY_SIZE(mas_mdp0_links), 263 .links = mas_mdp0_links, 264 }; 265 266 static const u16 mas_mdp1_links[] = { 267 MSM8939_SNOC_MM_INT_0, 268 MSM8939_SNOC_MM_INT_2 269 }; 270 271 static struct qcom_icc_node mas_mdp1 = { 272 .name = "mas_mdp1", 273 .id = MSM8939_MASTER_MDP_PORT1, 274 .buswidth = 16, 275 .mas_rpm_id = -1, 276 .slv_rpm_id = -1, 277 .qos.ap_owned = true, 278 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 279 .qos.areq_prio = 0, 280 .qos.prio_level = 0, 281 .qos.qos_port = 13, 282 .num_links = ARRAY_SIZE(mas_mdp1_links), 283 .links = mas_mdp1_links, 284 }; 285 286 static const u16 mas_cpp_links[] = { 287 MSM8939_SNOC_MM_INT_0, 288 MSM8939_SNOC_MM_INT_2 289 }; 290 291 static struct qcom_icc_node mas_cpp = { 292 .name = "mas_cpp", 293 .id = MSM8939_MASTER_CPP, 294 .buswidth = 16, 295 .mas_rpm_id = -1, 296 .slv_rpm_id = -1, 297 .qos.ap_owned = true, 298 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 299 .qos.areq_prio = 0, 300 .qos.prio_level = 0, 301 .qos.qos_port = 12, 302 .num_links = ARRAY_SIZE(mas_cpp_links), 303 .links = mas_cpp_links, 304 }; 305 306 static const u16 mas_pcnoc_crypto_0_links[] = { 307 MSM8939_PNOC_INT_1 308 }; 309 310 static struct qcom_icc_node mas_pcnoc_crypto_0 = { 311 .name = "mas_pcnoc_crypto_0", 312 .id = MSM8939_MASTER_CRYPTO_CORE0, 313 .buswidth = 8, 314 .mas_rpm_id = -1, 315 .slv_rpm_id = -1, 316 .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links), 317 .links = mas_pcnoc_crypto_0_links, 318 }; 319 320 static const u16 mas_pcnoc_sdcc_1_links[] = { 321 MSM8939_PNOC_INT_1 322 }; 323 324 static struct qcom_icc_node mas_pcnoc_sdcc_1 = { 325 .name = "mas_pcnoc_sdcc_1", 326 .id = MSM8939_MASTER_SDCC_1, 327 .buswidth = 8, 328 .mas_rpm_id = -1, 329 .slv_rpm_id = -1, 330 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links), 331 .links = mas_pcnoc_sdcc_1_links, 332 }; 333 334 static const u16 mas_pcnoc_sdcc_2_links[] = { 335 MSM8939_PNOC_INT_1 336 }; 337 338 static struct qcom_icc_node mas_pcnoc_sdcc_2 = { 339 .name = "mas_pcnoc_sdcc_2", 340 .id = MSM8939_MASTER_SDCC_2, 341 .buswidth = 8, 342 .mas_rpm_id = -1, 343 .slv_rpm_id = -1, 344 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links), 345 .links = mas_pcnoc_sdcc_2_links, 346 }; 347 348 static const u16 mas_qdss_bam_links[] = { 349 MSM8939_SNOC_QDSS_INT 350 }; 351 352 static struct qcom_icc_node mas_qdss_bam = { 353 .name = "mas_qdss_bam", 354 .id = MSM8939_MASTER_QDSS_BAM, 355 .buswidth = 8, 356 .mas_rpm_id = -1, 357 .slv_rpm_id = -1, 358 .qos.ap_owned = true, 359 .qos.qos_mode = NOC_QOS_MODE_FIXED, 360 .qos.areq_prio = 1, 361 .qos.prio_level = 1, 362 .qos.qos_port = 11, 363 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 364 .links = mas_qdss_bam_links, 365 }; 366 367 static const u16 mas_qdss_etr_links[] = { 368 MSM8939_SNOC_QDSS_INT 369 }; 370 371 static struct qcom_icc_node mas_qdss_etr = { 372 .name = "mas_qdss_etr", 373 .id = MSM8939_MASTER_QDSS_ETR, 374 .buswidth = 8, 375 .mas_rpm_id = -1, 376 .slv_rpm_id = -1, 377 .qos.ap_owned = true, 378 .qos.qos_mode = NOC_QOS_MODE_FIXED, 379 .qos.areq_prio = 1, 380 .qos.prio_level = 1, 381 .qos.qos_port = 10, 382 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 383 .links = mas_qdss_etr_links, 384 }; 385 386 static const u16 mas_snoc_cfg_links[] = { 387 MSM8939_SLAVE_SRVC_SNOC 388 }; 389 390 static struct qcom_icc_node mas_snoc_cfg = { 391 .name = "mas_snoc_cfg", 392 .id = MSM8939_MASTER_SNOC_CFG, 393 .buswidth = 4, 394 .mas_rpm_id = -1, 395 .slv_rpm_id = -1, 396 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 397 .links = mas_snoc_cfg_links, 398 }; 399 400 static const u16 mas_spdm_links[] = { 401 MSM8939_PNOC_MAS_0 402 }; 403 404 static struct qcom_icc_node mas_spdm = { 405 .name = "mas_spdm", 406 .id = MSM8939_MASTER_SPDM, 407 .buswidth = 4, 408 .mas_rpm_id = -1, 409 .slv_rpm_id = -1, 410 .num_links = ARRAY_SIZE(mas_spdm_links), 411 .links = mas_spdm_links, 412 }; 413 414 static const u16 mas_tcu0_links[] = { 415 MSM8939_SLAVE_EBI_CH0, 416 MSM8939_BIMC_SNOC_MAS, 417 MSM8939_SLAVE_AMPSS_L2 418 }; 419 420 static struct qcom_icc_node mas_tcu0 = { 421 .name = "mas_tcu0", 422 .id = MSM8939_MASTER_TCU0, 423 .buswidth = 16, 424 .mas_rpm_id = -1, 425 .slv_rpm_id = -1, 426 .qos.ap_owned = true, 427 .qos.qos_mode = NOC_QOS_MODE_FIXED, 428 .qos.areq_prio = 2, 429 .qos.prio_level = 2, 430 .qos.qos_port = 6, 431 .num_links = ARRAY_SIZE(mas_tcu0_links), 432 .links = mas_tcu0_links, 433 }; 434 435 static const u16 mas_usb_hs1_links[] = { 436 MSM8939_PNOC_MAS_1 437 }; 438 439 static struct qcom_icc_node mas_usb_hs1 = { 440 .name = "mas_usb_hs1", 441 .id = MSM8939_MASTER_USB_HS1, 442 .buswidth = 4, 443 .mas_rpm_id = -1, 444 .slv_rpm_id = -1, 445 .num_links = ARRAY_SIZE(mas_usb_hs1_links), 446 .links = mas_usb_hs1_links, 447 }; 448 449 static const u16 mas_usb_hs2_links[] = { 450 MSM8939_PNOC_MAS_1 451 }; 452 453 static struct qcom_icc_node mas_usb_hs2 = { 454 .name = "mas_usb_hs2", 455 .id = MSM8939_MASTER_USB_HS2, 456 .buswidth = 4, 457 .mas_rpm_id = -1, 458 .slv_rpm_id = -1, 459 .num_links = ARRAY_SIZE(mas_usb_hs2_links), 460 .links = mas_usb_hs2_links, 461 }; 462 463 static const u16 mas_vfe_links[] = { 464 MSM8939_SNOC_MM_INT_1, 465 MSM8939_SNOC_MM_INT_2 466 }; 467 468 static struct qcom_icc_node mas_vfe = { 469 .name = "mas_vfe", 470 .id = MSM8939_MASTER_VFE, 471 .buswidth = 16, 472 .mas_rpm_id = -1, 473 .slv_rpm_id = -1, 474 .qos.ap_owned = true, 475 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 476 .qos.areq_prio = 0, 477 .qos.prio_level = 0, 478 .qos.qos_port = 9, 479 .num_links = ARRAY_SIZE(mas_vfe_links), 480 .links = mas_vfe_links, 481 }; 482 483 static const u16 mas_video_links[] = { 484 MSM8939_SNOC_MM_INT_0, 485 MSM8939_SNOC_MM_INT_2 486 }; 487 488 static struct qcom_icc_node mas_video = { 489 .name = "mas_video", 490 .id = MSM8939_MASTER_VIDEO_P0, 491 .buswidth = 16, 492 .mas_rpm_id = -1, 493 .slv_rpm_id = -1, 494 .qos.ap_owned = true, 495 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 496 .qos.areq_prio = 0, 497 .qos.prio_level = 0, 498 .qos.qos_port = 8, 499 .num_links = ARRAY_SIZE(mas_video_links), 500 .links = mas_video_links, 501 }; 502 503 static const u16 mm_int_0_links[] = { 504 MSM8939_SNOC_BIMC_2_MAS 505 }; 506 507 static struct qcom_icc_node mm_int_0 = { 508 .name = "mm_int_0", 509 .id = MSM8939_SNOC_MM_INT_0, 510 .buswidth = 16, 511 .mas_rpm_id = -1, 512 .slv_rpm_id = -1, 513 .qos.ap_owned = true, 514 .qos.qos_mode = NOC_QOS_MODE_INVALID, 515 .num_links = ARRAY_SIZE(mm_int_0_links), 516 .links = mm_int_0_links, 517 }; 518 519 static const u16 mm_int_1_links[] = { 520 MSM8939_SNOC_BIMC_1_MAS 521 }; 522 523 static struct qcom_icc_node mm_int_1 = { 524 .name = "mm_int_1", 525 .id = MSM8939_SNOC_MM_INT_1, 526 .buswidth = 16, 527 .mas_rpm_id = -1, 528 .slv_rpm_id = -1, 529 .qos.ap_owned = true, 530 .qos.qos_mode = NOC_QOS_MODE_INVALID, 531 .num_links = ARRAY_SIZE(mm_int_1_links), 532 .links = mm_int_1_links, 533 }; 534 535 static const u16 mm_int_2_links[] = { 536 MSM8939_SNOC_INT_0 537 }; 538 539 static struct qcom_icc_node mm_int_2 = { 540 .name = "mm_int_2", 541 .id = MSM8939_SNOC_MM_INT_2, 542 .buswidth = 16, 543 .mas_rpm_id = -1, 544 .slv_rpm_id = -1, 545 .qos.ap_owned = true, 546 .qos.qos_mode = NOC_QOS_MODE_INVALID, 547 .num_links = ARRAY_SIZE(mm_int_2_links), 548 .links = mm_int_2_links, 549 }; 550 551 static const u16 pcnoc_int_0_links[] = { 552 MSM8939_PNOC_SNOC_MAS, 553 MSM8939_PNOC_SLV_0, 554 MSM8939_PNOC_SLV_1, 555 MSM8939_PNOC_SLV_2, 556 MSM8939_PNOC_SLV_3, 557 MSM8939_PNOC_SLV_4, 558 MSM8939_PNOC_SLV_8, 559 MSM8939_PNOC_SLV_9 560 }; 561 562 static struct qcom_icc_node pcnoc_int_0 = { 563 .name = "pcnoc_int_0", 564 .id = MSM8939_PNOC_INT_0, 565 .buswidth = 8, 566 .mas_rpm_id = -1, 567 .slv_rpm_id = -1, 568 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 569 .links = pcnoc_int_0_links, 570 }; 571 572 static const u16 pcnoc_int_1_links[] = { 573 MSM8939_PNOC_SNOC_MAS 574 }; 575 576 static struct qcom_icc_node pcnoc_int_1 = { 577 .name = "pcnoc_int_1", 578 .id = MSM8939_PNOC_INT_1, 579 .buswidth = 8, 580 .mas_rpm_id = -1, 581 .slv_rpm_id = -1, 582 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 583 .links = pcnoc_int_1_links, 584 }; 585 586 static const u16 pcnoc_m_0_links[] = { 587 MSM8939_PNOC_INT_0 588 }; 589 590 static struct qcom_icc_node pcnoc_m_0 = { 591 .name = "pcnoc_m_0", 592 .id = MSM8939_PNOC_MAS_0, 593 .buswidth = 8, 594 .mas_rpm_id = -1, 595 .slv_rpm_id = -1, 596 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 597 .links = pcnoc_m_0_links, 598 }; 599 600 static const u16 pcnoc_m_1_links[] = { 601 MSM8939_PNOC_SNOC_MAS 602 }; 603 604 static struct qcom_icc_node pcnoc_m_1 = { 605 .name = "pcnoc_m_1", 606 .id = MSM8939_PNOC_MAS_1, 607 .buswidth = 8, 608 .mas_rpm_id = -1, 609 .slv_rpm_id = -1, 610 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 611 .links = pcnoc_m_1_links, 612 }; 613 614 static const u16 pcnoc_s_0_links[] = { 615 MSM8939_SLAVE_CLK_CTL, 616 MSM8939_SLAVE_TLMM, 617 MSM8939_SLAVE_TCSR, 618 MSM8939_SLAVE_SECURITY, 619 MSM8939_SLAVE_MSS 620 }; 621 622 static struct qcom_icc_node pcnoc_s_0 = { 623 .name = "pcnoc_s_0", 624 .id = MSM8939_PNOC_SLV_0, 625 .buswidth = 4, 626 .mas_rpm_id = -1, 627 .slv_rpm_id = -1, 628 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 629 .links = pcnoc_s_0_links, 630 }; 631 632 static const u16 pcnoc_s_1_links[] = { 633 MSM8939_SLAVE_IMEM_CFG, 634 MSM8939_SLAVE_CRYPTO_0_CFG, 635 MSM8939_SLAVE_MSG_RAM, 636 MSM8939_SLAVE_PDM, 637 MSM8939_SLAVE_PRNG 638 }; 639 640 static struct qcom_icc_node pcnoc_s_1 = { 641 .name = "pcnoc_s_1", 642 .id = MSM8939_PNOC_SLV_1, 643 .buswidth = 4, 644 .mas_rpm_id = -1, 645 .slv_rpm_id = -1, 646 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 647 .links = pcnoc_s_1_links, 648 }; 649 650 static const u16 pcnoc_s_2_links[] = { 651 MSM8939_SLAVE_SPDM, 652 MSM8939_SLAVE_BOOT_ROM, 653 MSM8939_SLAVE_BIMC_CFG, 654 MSM8939_SLAVE_PNOC_CFG, 655 MSM8939_SLAVE_PMIC_ARB 656 }; 657 658 static struct qcom_icc_node pcnoc_s_2 = { 659 .name = "pcnoc_s_2", 660 .id = MSM8939_PNOC_SLV_2, 661 .buswidth = 4, 662 .mas_rpm_id = -1, 663 .slv_rpm_id = -1, 664 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 665 .links = pcnoc_s_2_links, 666 }; 667 668 static const u16 pcnoc_s_3_links[] = { 669 MSM8939_SLAVE_MPM, 670 MSM8939_SLAVE_SNOC_CFG, 671 MSM8939_SLAVE_RBCPR_CFG, 672 MSM8939_SLAVE_QDSS_CFG, 673 MSM8939_SLAVE_DEHR_CFG 674 }; 675 676 static struct qcom_icc_node pcnoc_s_3 = { 677 .name = "pcnoc_s_3", 678 .id = MSM8939_PNOC_SLV_3, 679 .buswidth = 4, 680 .mas_rpm_id = -1, 681 .slv_rpm_id = -1, 682 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 683 .links = pcnoc_s_3_links, 684 }; 685 686 static const u16 pcnoc_s_4_links[] = { 687 MSM8939_SLAVE_VENUS_CFG, 688 MSM8939_SLAVE_CAMERA_CFG, 689 MSM8939_SLAVE_DISPLAY_CFG 690 }; 691 692 static struct qcom_icc_node pcnoc_s_4 = { 693 .name = "pcnoc_s_4", 694 .id = MSM8939_PNOC_SLV_4, 695 .buswidth = 4, 696 .mas_rpm_id = -1, 697 .slv_rpm_id = -1, 698 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 699 .links = pcnoc_s_4_links, 700 }; 701 702 static const u16 pcnoc_s_8_links[] = { 703 MSM8939_SLAVE_USB_HS1, 704 MSM8939_SLAVE_SDCC_1, 705 MSM8939_SLAVE_BLSP_1 706 }; 707 708 static struct qcom_icc_node pcnoc_s_8 = { 709 .name = "pcnoc_s_8", 710 .id = MSM8939_PNOC_SLV_8, 711 .buswidth = 4, 712 .mas_rpm_id = -1, 713 .slv_rpm_id = -1, 714 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 715 .links = pcnoc_s_8_links, 716 }; 717 718 static const u16 pcnoc_s_9_links[] = { 719 MSM8939_SLAVE_SDCC_2, 720 MSM8939_SLAVE_LPASS, 721 MSM8939_SLAVE_USB_HS2 722 }; 723 724 static struct qcom_icc_node pcnoc_s_9 = { 725 .name = "pcnoc_s_9", 726 .id = MSM8939_PNOC_SLV_9, 727 .buswidth = 4, 728 .mas_rpm_id = -1, 729 .slv_rpm_id = -1, 730 .num_links = ARRAY_SIZE(pcnoc_s_9_links), 731 .links = pcnoc_s_9_links, 732 }; 733 734 static const u16 pcnoc_snoc_mas_links[] = { 735 MSM8939_PNOC_SNOC_SLV 736 }; 737 738 static struct qcom_icc_node pcnoc_snoc_mas = { 739 .name = "pcnoc_snoc_mas", 740 .id = MSM8939_PNOC_SNOC_MAS, 741 .buswidth = 8, 742 .mas_rpm_id = 29, 743 .slv_rpm_id = -1, 744 .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links), 745 .links = pcnoc_snoc_mas_links, 746 }; 747 748 static const u16 pcnoc_snoc_slv_links[] = { 749 MSM8939_SNOC_INT_0, 750 MSM8939_SNOC_INT_BIMC, 751 MSM8939_SNOC_INT_1 752 }; 753 754 static struct qcom_icc_node pcnoc_snoc_slv = { 755 .name = "pcnoc_snoc_slv", 756 .id = MSM8939_PNOC_SNOC_SLV, 757 .buswidth = 8, 758 .mas_rpm_id = -1, 759 .slv_rpm_id = 45, 760 .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links), 761 .links = pcnoc_snoc_slv_links, 762 }; 763 764 static const u16 qdss_int_links[] = { 765 MSM8939_SNOC_INT_0, 766 MSM8939_SNOC_INT_BIMC 767 }; 768 769 static struct qcom_icc_node qdss_int = { 770 .name = "qdss_int", 771 .id = MSM8939_SNOC_QDSS_INT, 772 .buswidth = 8, 773 .mas_rpm_id = -1, 774 .slv_rpm_id = -1, 775 .qos.ap_owned = true, 776 .qos.qos_mode = NOC_QOS_MODE_INVALID, 777 .num_links = ARRAY_SIZE(qdss_int_links), 778 .links = qdss_int_links, 779 }; 780 781 static struct qcom_icc_node slv_apps_l2 = { 782 .name = "slv_apps_l2", 783 .id = MSM8939_SLAVE_AMPSS_L2, 784 .buswidth = 16, 785 .mas_rpm_id = -1, 786 .slv_rpm_id = -1, 787 }; 788 789 static struct qcom_icc_node slv_apss = { 790 .name = "slv_apss", 791 .id = MSM8939_SLAVE_APSS, 792 .buswidth = 4, 793 .mas_rpm_id = -1, 794 .slv_rpm_id = -1, 795 }; 796 797 static struct qcom_icc_node slv_audio = { 798 .name = "slv_audio", 799 .id = MSM8939_SLAVE_LPASS, 800 .buswidth = 4, 801 .mas_rpm_id = -1, 802 .slv_rpm_id = -1, 803 }; 804 805 static struct qcom_icc_node slv_bimc_cfg = { 806 .name = "slv_bimc_cfg", 807 .id = MSM8939_SLAVE_BIMC_CFG, 808 .buswidth = 4, 809 .mas_rpm_id = -1, 810 .slv_rpm_id = -1, 811 }; 812 813 static struct qcom_icc_node slv_blsp_1 = { 814 .name = "slv_blsp_1", 815 .id = MSM8939_SLAVE_BLSP_1, 816 .buswidth = 4, 817 .mas_rpm_id = -1, 818 .slv_rpm_id = -1, 819 }; 820 821 static struct qcom_icc_node slv_boot_rom = { 822 .name = "slv_boot_rom", 823 .id = MSM8939_SLAVE_BOOT_ROM, 824 .buswidth = 4, 825 .mas_rpm_id = -1, 826 .slv_rpm_id = -1, 827 }; 828 829 static struct qcom_icc_node slv_camera_cfg = { 830 .name = "slv_camera_cfg", 831 .id = MSM8939_SLAVE_CAMERA_CFG, 832 .buswidth = 4, 833 .mas_rpm_id = -1, 834 .slv_rpm_id = -1, 835 }; 836 837 static struct qcom_icc_node slv_cats_0 = { 838 .name = "slv_cats_0", 839 .id = MSM8939_SLAVE_CATS_128, 840 .buswidth = 16, 841 .mas_rpm_id = -1, 842 .slv_rpm_id = -1, 843 }; 844 845 static struct qcom_icc_node slv_cats_1 = { 846 .name = "slv_cats_1", 847 .id = MSM8939_SLAVE_OCMEM_64, 848 .buswidth = 8, 849 .mas_rpm_id = -1, 850 .slv_rpm_id = -1, 851 }; 852 853 static struct qcom_icc_node slv_clk_ctl = { 854 .name = "slv_clk_ctl", 855 .id = MSM8939_SLAVE_CLK_CTL, 856 .buswidth = 4, 857 .mas_rpm_id = -1, 858 .slv_rpm_id = -1, 859 }; 860 861 static struct qcom_icc_node slv_crypto_0_cfg = { 862 .name = "slv_crypto_0_cfg", 863 .id = MSM8939_SLAVE_CRYPTO_0_CFG, 864 .buswidth = 4, 865 .mas_rpm_id = -1, 866 .slv_rpm_id = -1, 867 }; 868 869 static struct qcom_icc_node slv_dehr_cfg = { 870 .name = "slv_dehr_cfg", 871 .id = MSM8939_SLAVE_DEHR_CFG, 872 .buswidth = 4, 873 .mas_rpm_id = -1, 874 .slv_rpm_id = -1, 875 }; 876 877 static struct qcom_icc_node slv_display_cfg = { 878 .name = "slv_display_cfg", 879 .id = MSM8939_SLAVE_DISPLAY_CFG, 880 .buswidth = 4, 881 .mas_rpm_id = -1, 882 .slv_rpm_id = -1, 883 }; 884 885 static struct qcom_icc_node slv_ebi_ch0 = { 886 .name = "slv_ebi_ch0", 887 .id = MSM8939_SLAVE_EBI_CH0, 888 .buswidth = 16, 889 .mas_rpm_id = -1, 890 .slv_rpm_id = 0, 891 }; 892 893 static struct qcom_icc_node slv_gfx_cfg = { 894 .name = "slv_gfx_cfg", 895 .id = MSM8939_SLAVE_GRAPHICS_3D_CFG, 896 .buswidth = 4, 897 .mas_rpm_id = -1, 898 .slv_rpm_id = -1, 899 }; 900 901 static struct qcom_icc_node slv_imem_cfg = { 902 .name = "slv_imem_cfg", 903 .id = MSM8939_SLAVE_IMEM_CFG, 904 .buswidth = 4, 905 .mas_rpm_id = -1, 906 .slv_rpm_id = -1, 907 }; 908 909 static struct qcom_icc_node slv_imem = { 910 .name = "slv_imem", 911 .id = MSM8939_SLAVE_IMEM, 912 .buswidth = 8, 913 .mas_rpm_id = -1, 914 .slv_rpm_id = 26, 915 }; 916 917 static struct qcom_icc_node slv_mpm = { 918 .name = "slv_mpm", 919 .id = MSM8939_SLAVE_MPM, 920 .buswidth = 4, 921 .mas_rpm_id = -1, 922 .slv_rpm_id = -1, 923 }; 924 925 static struct qcom_icc_node slv_msg_ram = { 926 .name = "slv_msg_ram", 927 .id = MSM8939_SLAVE_MSG_RAM, 928 .buswidth = 4, 929 .mas_rpm_id = -1, 930 .slv_rpm_id = -1, 931 }; 932 933 static struct qcom_icc_node slv_mss = { 934 .name = "slv_mss", 935 .id = MSM8939_SLAVE_MSS, 936 .buswidth = 4, 937 .mas_rpm_id = -1, 938 .slv_rpm_id = -1, 939 }; 940 941 static struct qcom_icc_node slv_pdm = { 942 .name = "slv_pdm", 943 .id = MSM8939_SLAVE_PDM, 944 .buswidth = 4, 945 .mas_rpm_id = -1, 946 .slv_rpm_id = -1, 947 }; 948 949 static struct qcom_icc_node slv_pmic_arb = { 950 .name = "slv_pmic_arb", 951 .id = MSM8939_SLAVE_PMIC_ARB, 952 .buswidth = 4, 953 .mas_rpm_id = -1, 954 .slv_rpm_id = -1, 955 }; 956 957 static struct qcom_icc_node slv_pcnoc_cfg = { 958 .name = "slv_pcnoc_cfg", 959 .id = MSM8939_SLAVE_PNOC_CFG, 960 .buswidth = 4, 961 .mas_rpm_id = -1, 962 .slv_rpm_id = -1, 963 }; 964 965 static struct qcom_icc_node slv_prng = { 966 .name = "slv_prng", 967 .id = MSM8939_SLAVE_PRNG, 968 .buswidth = 4, 969 .mas_rpm_id = -1, 970 .slv_rpm_id = -1, 971 }; 972 973 static struct qcom_icc_node slv_qdss_cfg = { 974 .name = "slv_qdss_cfg", 975 .id = MSM8939_SLAVE_QDSS_CFG, 976 .buswidth = 4, 977 .mas_rpm_id = -1, 978 .slv_rpm_id = -1, 979 }; 980 981 static struct qcom_icc_node slv_qdss_stm = { 982 .name = "slv_qdss_stm", 983 .id = MSM8939_SLAVE_QDSS_STM, 984 .buswidth = 4, 985 .mas_rpm_id = -1, 986 .slv_rpm_id = 30, 987 }; 988 989 static struct qcom_icc_node slv_rbcpr_cfg = { 990 .name = "slv_rbcpr_cfg", 991 .id = MSM8939_SLAVE_RBCPR_CFG, 992 .buswidth = 4, 993 .mas_rpm_id = -1, 994 .slv_rpm_id = -1, 995 }; 996 997 static struct qcom_icc_node slv_sdcc_1 = { 998 .name = "slv_sdcc_1", 999 .id = MSM8939_SLAVE_SDCC_1, 1000 .buswidth = 4, 1001 .mas_rpm_id = -1, 1002 .slv_rpm_id = -1, 1003 }; 1004 1005 static struct qcom_icc_node slv_sdcc_2 = { 1006 .name = "slv_sdcc_2", 1007 .id = MSM8939_SLAVE_SDCC_2, 1008 .buswidth = 4, 1009 .mas_rpm_id = -1, 1010 .slv_rpm_id = -1, 1011 }; 1012 1013 static struct qcom_icc_node slv_security = { 1014 .name = "slv_security", 1015 .id = MSM8939_SLAVE_SECURITY, 1016 .buswidth = 4, 1017 .mas_rpm_id = -1, 1018 .slv_rpm_id = -1, 1019 }; 1020 1021 static struct qcom_icc_node slv_snoc_cfg = { 1022 .name = "slv_snoc_cfg", 1023 .id = MSM8939_SLAVE_SNOC_CFG, 1024 .buswidth = 4, 1025 .mas_rpm_id = -1, 1026 .slv_rpm_id = -1, 1027 }; 1028 1029 static struct qcom_icc_node slv_spdm = { 1030 .name = "slv_spdm", 1031 .id = MSM8939_SLAVE_SPDM, 1032 .buswidth = 4, 1033 .mas_rpm_id = -1, 1034 .slv_rpm_id = -1, 1035 }; 1036 1037 static struct qcom_icc_node slv_srvc_snoc = { 1038 .name = "slv_srvc_snoc", 1039 .id = MSM8939_SLAVE_SRVC_SNOC, 1040 .buswidth = 8, 1041 .mas_rpm_id = -1, 1042 .slv_rpm_id = -1, 1043 }; 1044 1045 static struct qcom_icc_node slv_tcsr = { 1046 .name = "slv_tcsr", 1047 .id = MSM8939_SLAVE_TCSR, 1048 .buswidth = 4, 1049 .mas_rpm_id = -1, 1050 .slv_rpm_id = -1, 1051 }; 1052 1053 static struct qcom_icc_node slv_tlmm = { 1054 .name = "slv_tlmm", 1055 .id = MSM8939_SLAVE_TLMM, 1056 .buswidth = 4, 1057 .mas_rpm_id = -1, 1058 .slv_rpm_id = -1, 1059 }; 1060 1061 static struct qcom_icc_node slv_usb_hs1 = { 1062 .name = "slv_usb_hs1", 1063 .id = MSM8939_SLAVE_USB_HS1, 1064 .buswidth = 4, 1065 .mas_rpm_id = -1, 1066 .slv_rpm_id = -1, 1067 }; 1068 1069 static struct qcom_icc_node slv_usb_hs2 = { 1070 .name = "slv_usb_hs2", 1071 .id = MSM8939_SLAVE_USB_HS2, 1072 .buswidth = 4, 1073 .mas_rpm_id = -1, 1074 .slv_rpm_id = -1, 1075 }; 1076 1077 static struct qcom_icc_node slv_venus_cfg = { 1078 .name = "slv_venus_cfg", 1079 .id = MSM8939_SLAVE_VENUS_CFG, 1080 .buswidth = 4, 1081 .mas_rpm_id = -1, 1082 .slv_rpm_id = -1, 1083 }; 1084 1085 static const u16 snoc_bimc_0_mas_links[] = { 1086 MSM8939_SNOC_BIMC_0_SLV 1087 }; 1088 1089 static struct qcom_icc_node snoc_bimc_0_mas = { 1090 .name = "snoc_bimc_0_mas", 1091 .id = MSM8939_SNOC_BIMC_0_MAS, 1092 .buswidth = 16, 1093 .mas_rpm_id = -1, 1094 .slv_rpm_id = -1, 1095 .qos.ap_owned = true, 1096 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1097 .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links), 1098 .links = snoc_bimc_0_mas_links, 1099 }; 1100 1101 static const u16 snoc_bimc_0_slv_links[] = { 1102 MSM8939_SLAVE_EBI_CH0 1103 }; 1104 1105 static struct qcom_icc_node snoc_bimc_0_slv = { 1106 .name = "snoc_bimc_0_slv", 1107 .id = MSM8939_SNOC_BIMC_0_SLV, 1108 .buswidth = 16, 1109 .mas_rpm_id = -1, 1110 .slv_rpm_id = -1, 1111 .qos.ap_owned = true, 1112 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1113 .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links), 1114 .links = snoc_bimc_0_slv_links, 1115 }; 1116 1117 static const u16 snoc_bimc_1_mas_links[] = { 1118 MSM8939_SNOC_BIMC_1_SLV 1119 }; 1120 1121 static struct qcom_icc_node snoc_bimc_1_mas = { 1122 .name = "snoc_bimc_1_mas", 1123 .id = MSM8939_SNOC_BIMC_1_MAS, 1124 .buswidth = 16, 1125 .mas_rpm_id = 76, 1126 .slv_rpm_id = -1, 1127 .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links), 1128 .links = snoc_bimc_1_mas_links, 1129 }; 1130 1131 static const u16 snoc_bimc_1_slv_links[] = { 1132 MSM8939_SLAVE_EBI_CH0 1133 }; 1134 1135 static struct qcom_icc_node snoc_bimc_1_slv = { 1136 .name = "snoc_bimc_1_slv", 1137 .id = MSM8939_SNOC_BIMC_1_SLV, 1138 .buswidth = 16, 1139 .mas_rpm_id = -1, 1140 .slv_rpm_id = 104, 1141 .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links), 1142 .links = snoc_bimc_1_slv_links, 1143 }; 1144 1145 static const u16 snoc_bimc_2_mas_links[] = { 1146 MSM8939_SNOC_BIMC_2_SLV 1147 }; 1148 1149 static struct qcom_icc_node snoc_bimc_2_mas = { 1150 .name = "snoc_bimc_2_mas", 1151 .id = MSM8939_SNOC_BIMC_2_MAS, 1152 .buswidth = 16, 1153 .mas_rpm_id = -1, 1154 .slv_rpm_id = -1, 1155 .qos.ap_owned = true, 1156 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1157 .num_links = ARRAY_SIZE(snoc_bimc_2_mas_links), 1158 .links = snoc_bimc_2_mas_links, 1159 }; 1160 1161 static const u16 snoc_bimc_2_slv_links[] = { 1162 MSM8939_SLAVE_EBI_CH0 1163 }; 1164 1165 static struct qcom_icc_node snoc_bimc_2_slv = { 1166 .name = "snoc_bimc_2_slv", 1167 .id = MSM8939_SNOC_BIMC_2_SLV, 1168 .buswidth = 16, 1169 .mas_rpm_id = -1, 1170 .slv_rpm_id = -1, 1171 .qos.ap_owned = true, 1172 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1173 .num_links = ARRAY_SIZE(snoc_bimc_2_slv_links), 1174 .links = snoc_bimc_2_slv_links, 1175 }; 1176 1177 static const u16 snoc_int_0_links[] = { 1178 MSM8939_SLAVE_QDSS_STM, 1179 MSM8939_SLAVE_IMEM, 1180 MSM8939_SNOC_PNOC_MAS 1181 }; 1182 1183 static struct qcom_icc_node snoc_int_0 = { 1184 .name = "snoc_int_0", 1185 .id = MSM8939_SNOC_INT_0, 1186 .buswidth = 8, 1187 .mas_rpm_id = 99, 1188 .slv_rpm_id = 130, 1189 .num_links = ARRAY_SIZE(snoc_int_0_links), 1190 .links = snoc_int_0_links, 1191 }; 1192 1193 static const u16 snoc_int_1_links[] = { 1194 MSM8939_SLAVE_APSS, 1195 MSM8939_SLAVE_CATS_128, 1196 MSM8939_SLAVE_OCMEM_64 1197 }; 1198 1199 static struct qcom_icc_node snoc_int_1 = { 1200 .name = "snoc_int_1", 1201 .id = MSM8939_SNOC_INT_1, 1202 .buswidth = 8, 1203 .mas_rpm_id = -1, 1204 .slv_rpm_id = -1, 1205 .num_links = ARRAY_SIZE(snoc_int_1_links), 1206 .links = snoc_int_1_links, 1207 }; 1208 1209 static const u16 snoc_int_bimc_links[] = { 1210 MSM8939_SNOC_BIMC_1_MAS 1211 }; 1212 1213 static struct qcom_icc_node snoc_int_bimc = { 1214 .name = "snoc_int_bimc", 1215 .id = MSM8939_SNOC_INT_BIMC, 1216 .buswidth = 8, 1217 .mas_rpm_id = 101, 1218 .slv_rpm_id = 132, 1219 .num_links = ARRAY_SIZE(snoc_int_bimc_links), 1220 .links = snoc_int_bimc_links, 1221 }; 1222 1223 static const u16 snoc_pcnoc_mas_links[] = { 1224 MSM8939_SNOC_PNOC_SLV 1225 }; 1226 1227 static struct qcom_icc_node snoc_pcnoc_mas = { 1228 .name = "snoc_pcnoc_mas", 1229 .id = MSM8939_SNOC_PNOC_MAS, 1230 .buswidth = 8, 1231 .mas_rpm_id = -1, 1232 .slv_rpm_id = -1, 1233 .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links), 1234 .links = snoc_pcnoc_mas_links, 1235 }; 1236 1237 static const u16 snoc_pcnoc_slv_links[] = { 1238 MSM8939_PNOC_INT_0 1239 }; 1240 1241 static struct qcom_icc_node snoc_pcnoc_slv = { 1242 .name = "snoc_pcnoc_slv", 1243 .id = MSM8939_SNOC_PNOC_SLV, 1244 .buswidth = 8, 1245 .mas_rpm_id = -1, 1246 .slv_rpm_id = -1, 1247 .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links), 1248 .links = snoc_pcnoc_slv_links, 1249 }; 1250 1251 static struct qcom_icc_node * const msm8939_snoc_nodes[] = { 1252 [BIMC_SNOC_SLV] = &bimc_snoc_slv, 1253 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1254 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1255 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1256 [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv, 1257 [SLAVE_APSS] = &slv_apss, 1258 [SLAVE_CATS_128] = &slv_cats_0, 1259 [SLAVE_OCMEM_64] = &slv_cats_1, 1260 [SLAVE_IMEM] = &slv_imem, 1261 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1262 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, 1263 [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas, 1264 [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas, 1265 [SNOC_BIMC_2_MAS] = &snoc_bimc_2_mas, 1266 [SNOC_INT_0] = &snoc_int_0, 1267 [SNOC_INT_1] = &snoc_int_1, 1268 [SNOC_INT_BIMC] = &snoc_int_bimc, 1269 [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas, 1270 [SNOC_QDSS_INT] = &qdss_int, 1271 }; 1272 1273 static const struct regmap_config msm8939_snoc_regmap_config = { 1274 .reg_bits = 32, 1275 .reg_stride = 4, 1276 .val_bits = 32, 1277 .max_register = 0x14080, 1278 .fast_io = true, 1279 }; 1280 1281 static const struct qcom_icc_desc msm8939_snoc = { 1282 .type = QCOM_ICC_NOC, 1283 .nodes = msm8939_snoc_nodes, 1284 .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), 1285 .bus_clk_desc = &bus_1_clk, 1286 .regmap_cfg = &msm8939_snoc_regmap_config, 1287 .qos_offset = 0x7000, 1288 }; 1289 1290 static struct qcom_icc_node * const msm8939_snoc_mm_nodes[] = { 1291 [MASTER_VIDEO_P0] = &mas_video, 1292 [MASTER_JPEG] = &mas_jpeg, 1293 [MASTER_VFE] = &mas_vfe, 1294 [MASTER_MDP_PORT0] = &mas_mdp0, 1295 [MASTER_MDP_PORT1] = &mas_mdp1, 1296 [MASTER_CPP] = &mas_cpp, 1297 [SNOC_MM_INT_0] = &mm_int_0, 1298 [SNOC_MM_INT_1] = &mm_int_1, 1299 [SNOC_MM_INT_2] = &mm_int_2, 1300 }; 1301 1302 static const struct qcom_icc_desc msm8939_snoc_mm = { 1303 .type = QCOM_ICC_NOC, 1304 .nodes = msm8939_snoc_mm_nodes, 1305 .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), 1306 .bus_clk_desc = &bus_2_clk, 1307 .regmap_cfg = &msm8939_snoc_regmap_config, 1308 .qos_offset = 0x7000, 1309 }; 1310 1311 static struct qcom_icc_node * const msm8939_bimc_nodes[] = { 1312 [BIMC_SNOC_MAS] = &bimc_snoc_mas, 1313 [MASTER_AMPSS_M0] = &mas_apss, 1314 [MASTER_GRAPHICS_3D] = &mas_gfx, 1315 [MASTER_TCU0] = &mas_tcu0, 1316 [SLAVE_AMPSS_L2] = &slv_apps_l2, 1317 [SLAVE_EBI_CH0] = &slv_ebi_ch0, 1318 [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv, 1319 [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv, 1320 [SNOC_BIMC_2_SLV] = &snoc_bimc_2_slv, 1321 }; 1322 1323 static const struct regmap_config msm8939_bimc_regmap_config = { 1324 .reg_bits = 32, 1325 .reg_stride = 4, 1326 .val_bits = 32, 1327 .max_register = 0x62000, 1328 .fast_io = true, 1329 }; 1330 1331 static const struct qcom_icc_desc msm8939_bimc = { 1332 .type = QCOM_ICC_BIMC, 1333 .nodes = msm8939_bimc_nodes, 1334 .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), 1335 .bus_clk_desc = &bimc_clk, 1336 .regmap_cfg = &msm8939_bimc_regmap_config, 1337 .qos_offset = 0x8000, 1338 }; 1339 1340 static struct qcom_icc_node * const msm8939_pcnoc_nodes[] = { 1341 [MASTER_BLSP_1] = &mas_blsp_1, 1342 [MASTER_DEHR] = &mas_dehr, 1343 [MASTER_LPASS] = &mas_audio, 1344 [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0, 1345 [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1, 1346 [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2, 1347 [MASTER_SPDM] = &mas_spdm, 1348 [MASTER_USB_HS1] = &mas_usb_hs1, 1349 [MASTER_USB_HS2] = &mas_usb_hs2, 1350 [PCNOC_INT_0] = &pcnoc_int_0, 1351 [PCNOC_INT_1] = &pcnoc_int_1, 1352 [PCNOC_MAS_0] = &pcnoc_m_0, 1353 [PCNOC_MAS_1] = &pcnoc_m_1, 1354 [PCNOC_SLV_0] = &pcnoc_s_0, 1355 [PCNOC_SLV_1] = &pcnoc_s_1, 1356 [PCNOC_SLV_2] = &pcnoc_s_2, 1357 [PCNOC_SLV_3] = &pcnoc_s_3, 1358 [PCNOC_SLV_4] = &pcnoc_s_4, 1359 [PCNOC_SLV_8] = &pcnoc_s_8, 1360 [PCNOC_SLV_9] = &pcnoc_s_9, 1361 [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas, 1362 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1363 [SLAVE_BLSP_1] = &slv_blsp_1, 1364 [SLAVE_BOOT_ROM] = &slv_boot_rom, 1365 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1366 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1367 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1368 [SLAVE_DEHR_CFG] = &slv_dehr_cfg, 1369 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1370 [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg, 1371 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1372 [SLAVE_LPASS] = &slv_audio, 1373 [SLAVE_MPM] = &slv_mpm, 1374 [SLAVE_MSG_RAM] = &slv_msg_ram, 1375 [SLAVE_MSS] = &slv_mss, 1376 [SLAVE_PDM] = &slv_pdm, 1377 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1378 [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg, 1379 [SLAVE_PRNG] = &slv_prng, 1380 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1381 [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg, 1382 [SLAVE_SDCC_1] = &slv_sdcc_1, 1383 [SLAVE_SDCC_2] = &slv_sdcc_2, 1384 [SLAVE_SECURITY] = &slv_security, 1385 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1386 [SLAVE_SPDM] = &slv_spdm, 1387 [SLAVE_TCSR] = &slv_tcsr, 1388 [SLAVE_TLMM] = &slv_tlmm, 1389 [SLAVE_USB_HS1] = &slv_usb_hs1, 1390 [SLAVE_USB_HS2] = &slv_usb_hs2, 1391 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1392 [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, 1393 }; 1394 1395 static const struct regmap_config msm8939_pcnoc_regmap_config = { 1396 .reg_bits = 32, 1397 .reg_stride = 4, 1398 .val_bits = 32, 1399 .max_register = 0x11000, 1400 .fast_io = true, 1401 }; 1402 1403 static const struct qcom_icc_desc msm8939_pcnoc = { 1404 .type = QCOM_ICC_NOC, 1405 .nodes = msm8939_pcnoc_nodes, 1406 .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), 1407 .bus_clk_desc = &bus_0_clk, 1408 .regmap_cfg = &msm8939_pcnoc_regmap_config, 1409 .qos_offset = 0x7000, 1410 }; 1411 1412 static const struct of_device_id msm8939_noc_of_match[] = { 1413 { .compatible = "qcom,msm8939-bimc", .data = &msm8939_bimc }, 1414 { .compatible = "qcom,msm8939-pcnoc", .data = &msm8939_pcnoc }, 1415 { .compatible = "qcom,msm8939-snoc", .data = &msm8939_snoc }, 1416 { .compatible = "qcom,msm8939-snoc-mm", .data = &msm8939_snoc_mm }, 1417 { } 1418 }; 1419 MODULE_DEVICE_TABLE(of, msm8939_noc_of_match); 1420 1421 static struct platform_driver msm8939_noc_driver = { 1422 .probe = qnoc_probe, 1423 .remove = qnoc_remove, 1424 .driver = { 1425 .name = "qnoc-msm8939", 1426 .of_match_table = msm8939_noc_of_match, 1427 .sync_state = icc_sync_state, 1428 }, 1429 }; 1430 module_platform_driver(msm8939_noc_driver); 1431 MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>"); 1432 MODULE_DESCRIPTION("Qualcomm MSM8939 NoC driver"); 1433 MODULE_LICENSE("GPL v2"); 1434