1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020 Linaro Ltd. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/seq_file.h> 14 #include <linux/cleanup.h> 15 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pm_clock.h> 20 #include <linux/pm_runtime.h> 21 22 #include "../pinctrl-utils.h" 23 24 #include "pinctrl-lpass-lpi.h" 25 26 #define MAX_NR_GPIO 32 27 #define GPIO_FUNC 0 28 29 struct lpi_pinctrl { 30 struct device *dev; 31 struct pinctrl_dev *ctrl; 32 struct gpio_chip chip; 33 struct pinctrl_desc desc; 34 char __iomem *tlmm_base; 35 char __iomem *slew_base; 36 /* Protects from concurrent register updates */ 37 struct mutex lock; 38 DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); 39 const struct lpi_pinctrl_variant_data *data; 40 }; 41 42 static void __iomem *lpi_gpio_reg(struct lpi_pinctrl *state, 43 unsigned int pin, unsigned int addr) 44 { 45 u32 pin_offset; 46 47 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) 48 pin_offset = state->data->groups[pin].pin_offset; 49 else 50 pin_offset = LPI_TLMM_REG_OFFSET * pin; 51 52 return state->tlmm_base + pin_offset + addr; 53 } 54 55 static void lpi_gpio_read_reg(struct lpi_pinctrl *state, 56 unsigned int pin, unsigned int addr, u32 *val) 57 { 58 *val = ioread32(lpi_gpio_reg(state, pin, addr)); 59 } 60 61 static void lpi_gpio_write_reg(struct lpi_pinctrl *state, 62 unsigned int pin, unsigned int addr, 63 unsigned int val) 64 { 65 iowrite32(val, lpi_gpio_reg(state, pin, addr)); 66 } 67 68 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, 69 unsigned int addr, u32 *val) 70 { 71 int ret; 72 73 ret = pm_runtime_resume_and_get(state->dev); 74 if (ret < 0) 75 return ret; 76 77 lpi_gpio_read_reg(state, pin, addr, val); 78 79 return pm_runtime_put_autosuspend(state->dev); 80 } 81 82 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { 83 .get_groups_count = pinctrl_generic_get_group_count, 84 .get_group_name = pinctrl_generic_get_group_name, 85 .get_group_pins = pinctrl_generic_get_group_pins, 86 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 87 .dt_free_map = pinctrl_utils_free_map, 88 }; 89 90 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev) 91 { 92 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 93 94 return pctrl->data->nfunctions; 95 } 96 97 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev, 98 unsigned int function) 99 { 100 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 101 102 return pctrl->data->functions[function].name; 103 } 104 105 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, 106 unsigned int function, 107 const char *const **groups, 108 unsigned *const num_qgroups) 109 { 110 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 111 112 *groups = pctrl->data->functions[function].groups; 113 *num_qgroups = pctrl->data->functions[function].ngroups; 114 115 return 0; 116 } 117 118 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, 119 unsigned int group) 120 { 121 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 122 const struct lpi_pingroup *g = &pctrl->data->groups[group]; 123 u32 io_val, val; 124 int i, pin = g->pin, ret; 125 126 for (i = 0; i < g->nfuncs; i++) { 127 if (g->funcs[i] == function) 128 break; 129 } 130 131 if (WARN_ON(i == g->nfuncs)) 132 return -EINVAL; 133 134 ret = pm_runtime_resume_and_get(pctrl->dev); 135 if (ret < 0) 136 return ret; 137 138 guard(mutex)(&pctrl->lock); 139 lpi_gpio_read_reg(pctrl, pin, LPI_GPIO_CFG_REG, &val); 140 141 /* 142 * If this is the first time muxing to GPIO and the direction is 143 * output, make sure that we're not going to be glitching the pin 144 * by reading the current state of the pin and setting it as the 145 * output. 146 */ 147 if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && 148 !test_and_set_bit(group, pctrl->ever_gpio)) { 149 lpi_gpio_read_reg(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); 150 151 if (io_val & LPI_GPIO_VALUE_IN_MASK) { 152 if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) 153 lpi_gpio_write_reg(pctrl, group, 154 LPI_GPIO_VALUE_REG, 155 io_val | LPI_GPIO_VALUE_OUT_MASK); 156 } else { 157 if (io_val & LPI_GPIO_VALUE_OUT_MASK) 158 lpi_gpio_write_reg(pctrl, group, 159 LPI_GPIO_VALUE_REG, 160 io_val & ~LPI_GPIO_VALUE_OUT_MASK); 161 } 162 } 163 164 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); 165 lpi_gpio_write_reg(pctrl, pin, LPI_GPIO_CFG_REG, val); 166 167 return pm_runtime_put_autosuspend(pctrl->dev); 168 } 169 170 static const struct pinmux_ops lpi_gpio_pinmux_ops = { 171 .get_functions_count = lpi_gpio_get_functions_count, 172 .get_function_name = lpi_gpio_get_function_name, 173 .get_function_groups = lpi_gpio_get_function_groups, 174 .set_mux = lpi_gpio_set_mux, 175 }; 176 177 static int lpi_config_get(struct pinctrl_dev *pctldev, 178 unsigned int pin, unsigned long *config) 179 { 180 unsigned int param = pinconf_to_config_param(*config); 181 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); 182 unsigned int arg = 0; 183 u32 ctl_reg; 184 int is_out; 185 int pull; 186 int ret; 187 188 ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); 189 if (ret) 190 return ret; 191 192 is_out = ctl_reg & LPI_GPIO_OE_MASK; 193 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); 194 195 switch (param) { 196 case PIN_CONFIG_BIAS_DISABLE: 197 if (pull == LPI_GPIO_BIAS_DISABLE) 198 arg = 1; 199 break; 200 case PIN_CONFIG_BIAS_PULL_DOWN: 201 if (pull == LPI_GPIO_PULL_DOWN) 202 arg = 1; 203 break; 204 case PIN_CONFIG_BIAS_BUS_HOLD: 205 if (pull == LPI_GPIO_KEEPER) 206 arg = 1; 207 break; 208 case PIN_CONFIG_BIAS_PULL_UP: 209 if (pull == LPI_GPIO_PULL_UP) 210 arg = 1; 211 break; 212 case PIN_CONFIG_INPUT_ENABLE: 213 case PIN_CONFIG_LEVEL: 214 if (is_out) 215 arg = 1; 216 break; 217 default: 218 return -EINVAL; 219 } 220 221 *config = pinconf_to_config_packed(param, arg); 222 223 return 0; 224 } 225 226 static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, 227 const struct lpi_pingroup *g, 228 unsigned int group, unsigned int slew) 229 { 230 unsigned long sval; 231 void __iomem *reg; 232 int slew_offset, ret; 233 234 if (slew > LPI_SLEW_RATE_MAX) { 235 dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", 236 slew, group); 237 return -EINVAL; 238 } 239 240 slew_offset = g->slew_offset; 241 if (slew_offset == LPI_NO_SLEW) 242 return 0; 243 244 if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) 245 reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; 246 else if (g->slew_base_spare_1) 247 reg = pctrl->slew_base + LPI_SPARE_1_REG; 248 else 249 reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; 250 251 ret = pm_runtime_resume_and_get(pctrl->dev); 252 if (ret < 0) 253 return ret; 254 255 mutex_lock(&pctrl->lock); 256 257 sval = ioread32(reg); 258 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); 259 sval |= slew << slew_offset; 260 iowrite32(sval, reg); 261 262 mutex_unlock(&pctrl->lock); 263 264 return pm_runtime_put_autosuspend(pctrl->dev); 265 } 266 267 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, 268 unsigned long *configs, unsigned int nconfs) 269 { 270 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev); 271 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; 272 bool value, output_enabled = false; 273 const struct lpi_pingroup *g; 274 u32 val; 275 int i, ret; 276 277 g = &pctrl->data->groups[group]; 278 for (i = 0; i < nconfs; i++) { 279 param = pinconf_to_config_param(configs[i]); 280 arg = pinconf_to_config_argument(configs[i]); 281 282 switch (param) { 283 case PIN_CONFIG_BIAS_DISABLE: 284 pullup = LPI_GPIO_BIAS_DISABLE; 285 break; 286 case PIN_CONFIG_BIAS_PULL_DOWN: 287 pullup = LPI_GPIO_PULL_DOWN; 288 break; 289 case PIN_CONFIG_BIAS_BUS_HOLD: 290 pullup = LPI_GPIO_KEEPER; 291 break; 292 case PIN_CONFIG_BIAS_PULL_UP: 293 pullup = LPI_GPIO_PULL_UP; 294 break; 295 case PIN_CONFIG_INPUT_ENABLE: 296 output_enabled = false; 297 break; 298 case PIN_CONFIG_LEVEL: 299 output_enabled = true; 300 value = arg; 301 break; 302 case PIN_CONFIG_DRIVE_STRENGTH: 303 strength = arg; 304 break; 305 case PIN_CONFIG_SLEW_RATE: 306 ret = lpi_config_set_slew_rate(pctrl, g, group, arg); 307 if (ret) 308 return ret; 309 break; 310 default: 311 return -EINVAL; 312 } 313 } 314 315 /* 316 * As per Hardware Programming Guide, when configuring pin as output, 317 * set the pin value before setting output-enable (OE). 318 */ 319 ret = pm_runtime_resume_and_get(pctrl->dev); 320 if (ret < 0) 321 return ret; 322 323 guard(mutex)(&pctrl->lock); 324 if (output_enabled) { 325 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); 326 lpi_gpio_write_reg(pctrl, group, LPI_GPIO_VALUE_REG, val); 327 } 328 329 lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val); 330 331 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); 332 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), 333 LPI_GPIO_OUT_STRENGTH_MASK); 334 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); 335 336 lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val); 337 338 return pm_runtime_put_autosuspend(pctrl->dev); 339 } 340 341 static const struct pinconf_ops lpi_gpio_pinconf_ops = { 342 .is_generic = true, 343 .pin_config_group_get = lpi_config_get, 344 .pin_config_group_set = lpi_config_set, 345 }; 346 347 static int lpi_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 348 { 349 unsigned long config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, 0); 350 struct lpi_pinctrl *state = gpiochip_get_data(chip); 351 unsigned long arg; 352 int ret; 353 354 ret = lpi_config_get(state->ctrl, pin, &config); 355 if (ret) 356 return ret; 357 358 arg = pinconf_to_config_argument(config); 359 360 return arg ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 361 } 362 363 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 364 { 365 struct lpi_pinctrl *state = gpiochip_get_data(chip); 366 unsigned long config; 367 368 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 369 370 return lpi_config_set(state->ctrl, pin, &config, 1); 371 } 372 373 static int lpi_gpio_direction_output(struct gpio_chip *chip, 374 unsigned int pin, int val) 375 { 376 struct lpi_pinctrl *state = gpiochip_get_data(chip); 377 unsigned long config; 378 379 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val); 380 381 return lpi_config_set(state->ctrl, pin, &config, 1); 382 } 383 384 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) 385 { 386 struct lpi_pinctrl *state = gpiochip_get_data(chip); 387 u32 val; 388 int ret; 389 390 ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); 391 if (ret) 392 return ret; 393 394 return val & LPI_GPIO_VALUE_IN_MASK; 395 } 396 397 static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 398 { 399 struct lpi_pinctrl *state = gpiochip_get_data(chip); 400 unsigned long config; 401 402 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value); 403 404 return lpi_config_set(state->ctrl, pin, &config, 1); 405 } 406 407 #ifdef CONFIG_DEBUG_FS 408 409 static unsigned int lpi_regval_to_drive(u32 val) 410 { 411 return (val + 1) * 2; 412 } 413 414 static void lpi_gpio_dbg_show_one(struct seq_file *s, 415 struct pinctrl_dev *pctldev, 416 struct gpio_chip *chip, 417 unsigned int offset, 418 unsigned int gpio) 419 { 420 struct lpi_pinctrl *state = gpiochip_get_data(chip); 421 struct pinctrl_pin_desc pindesc; 422 unsigned int func; 423 int is_out; 424 int drive; 425 int pull; 426 u32 ctl_reg; 427 428 static const char * const pulls[] = { 429 "no pull", 430 "pull down", 431 "keeper", 432 "pull up" 433 }; 434 435 pctldev = pctldev ? : state->ctrl; 436 pindesc = pctldev->desc->pins[offset]; 437 if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) 438 return; 439 440 is_out = ctl_reg & LPI_GPIO_OE_MASK; 441 442 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); 443 drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg); 444 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); 445 446 seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func); 447 seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); 448 seq_printf(s, " %s", pulls[pull]); 449 } 450 451 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 452 { 453 unsigned int gpio = chip->base; 454 unsigned int i; 455 456 for (i = 0; i < chip->ngpio; i++, gpio++) { 457 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); 458 seq_puts(s, "\n"); 459 } 460 } 461 462 #else 463 #define lpi_gpio_dbg_show NULL 464 #endif 465 466 static const struct gpio_chip lpi_gpio_template = { 467 .get_direction = lpi_gpio_get_direction, 468 .direction_input = lpi_gpio_direction_input, 469 .direction_output = lpi_gpio_direction_output, 470 .get = lpi_gpio_get, 471 .set = lpi_gpio_set, 472 .request = gpiochip_generic_request, 473 .free = gpiochip_generic_free, 474 .dbg_show = lpi_gpio_dbg_show, 475 }; 476 477 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl) 478 { 479 int i, ret; 480 481 for (i = 0; i < pctrl->data->npins; i++) { 482 const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i; 483 484 ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name, 485 (int *)&pin_info->number, 1, NULL); 486 if (ret < 0) 487 goto err_pinctrl; 488 } 489 490 return 0; 491 492 err_pinctrl: 493 for (; i > 0; i--) 494 pinctrl_generic_remove_group(pctrl->ctrl, i - 1); 495 496 return ret; 497 } 498 499 int lpi_pinctrl_probe(struct platform_device *pdev) 500 { 501 const struct lpi_pinctrl_variant_data *data; 502 struct device *dev = &pdev->dev; 503 struct lpi_pinctrl *pctrl; 504 int ret; 505 506 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 507 if (!pctrl) 508 return -ENOMEM; 509 510 platform_set_drvdata(pdev, pctrl); 511 512 data = of_device_get_match_data(dev); 513 if (!data) 514 return -EINVAL; 515 516 if (WARN_ON(data->npins > MAX_NR_GPIO)) 517 return -EINVAL; 518 519 pctrl->data = data; 520 pctrl->dev = &pdev->dev; 521 522 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); 523 if (IS_ERR(pctrl->tlmm_base)) 524 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), 525 "TLMM resource not provided\n"); 526 527 if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) { 528 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); 529 if (IS_ERR(pctrl->slew_base)) 530 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), 531 "Slew resource not provided\n"); 532 } 533 534 ret = devm_pm_clk_create(dev); 535 if (ret) 536 return ret; 537 538 ret = of_pm_clk_add_clks(dev); 539 if (ret < 0 && ret != -ENODEV) 540 return ret; 541 542 pm_runtime_set_autosuspend_delay(dev, 100); 543 pm_runtime_use_autosuspend(dev); 544 ret = devm_pm_runtime_enable(dev); 545 if (ret) 546 return ret; 547 548 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; 549 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; 550 pctrl->desc.confops = &lpi_gpio_pinconf_ops; 551 pctrl->desc.owner = THIS_MODULE; 552 pctrl->desc.name = dev_name(dev); 553 pctrl->desc.pins = data->pins; 554 pctrl->desc.npins = data->npins; 555 pctrl->chip = lpi_gpio_template; 556 pctrl->chip.parent = dev; 557 pctrl->chip.base = -1; 558 pctrl->chip.ngpio = data->npins; 559 pctrl->chip.label = dev_name(dev); 560 pctrl->chip.can_sleep = true; 561 562 mutex_init(&pctrl->lock); 563 564 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl); 565 if (IS_ERR(pctrl->ctrl)) { 566 ret = PTR_ERR(pctrl->ctrl); 567 dev_err(dev, "failed to add pin controller\n"); 568 goto err_pinctrl; 569 } 570 571 ret = lpi_build_pin_desc_groups(pctrl); 572 if (ret) 573 goto err_pinctrl; 574 575 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); 576 if (ret) { 577 dev_err(pctrl->dev, "can't add gpio chip\n"); 578 goto err_pinctrl; 579 } 580 581 return 0; 582 583 err_pinctrl: 584 mutex_destroy(&pctrl->lock); 585 586 return ret; 587 } 588 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe); 589 590 void lpi_pinctrl_remove(struct platform_device *pdev) 591 { 592 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); 593 int i; 594 595 mutex_destroy(&pctrl->lock); 596 597 for (i = 0; i < pctrl->data->npins; i++) 598 pinctrl_generic_remove_group(pctrl->ctrl, i); 599 } 600 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove); 601 602 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); 603 MODULE_LICENSE("GPL"); 604