xref: /linux/drivers/tty/serial/8250/8250_fintek.c (revision c8f3ac729f827b655e0a239a3967b47c9dfce606) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Probe for F81216A LPC to 4 UART and F81214E LPC/eSPI to 2 UART
4  *
5  *  Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
6  */
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/pnp.h>
10 #include <linux/kernel.h>
11 #include <linux/serial_core.h>
12 #include <linux/irq.h>
13 #include  "8250.h"
14 
15 #define ADDR_PORT 0
16 #define DATA_PORT 1
17 #define EXIT_KEY 0xAA
18 #define CHIP_ID1  0x20
19 #define CHIP_ID2  0x21
20 #define CHIP_ID_F81865 0x0407
21 #define CHIP_ID_F81866 0x1010
22 #define CHIP_ID_F81966 0x0215
23 #define CHIP_ID_F81216AD 0x1602
24 #define CHIP_ID_F81216E 0x1617
25 #define CHIP_ID_F81216H 0x0501
26 #define CHIP_ID_F81214E 0x1417
27 #define CHIP_ID_F81216 0x0802
28 #define VENDOR_ID1 0x23
29 #define VENDOR_ID1_VAL 0x19
30 #define VENDOR_ID2 0x24
31 #define VENDOR_ID2_VAL 0x34
32 #define IO_ADDR1 0x61
33 #define IO_ADDR2 0x60
34 #define LDN 0x7
35 
36 #define FINTEK_IRQ_MODE	0x70
37 #define IRQ_SHARE	BIT(4)
38 #define IRQ_MODE_MASK	(BIT(6) | BIT(5))
39 #define IRQ_LEVEL_LOW	0
40 #define IRQ_EDGE_HIGH	BIT(5)
41 
42 /*
43  * F81216H clock source register, the value and mask is the same with F81866,
44  * but it's on F0h.
45  *
46  * Clock speeds for UART (register F0h)
47  * 00: 1.8432MHz.
48  * 01: 18.432MHz.
49  * 10: 24MHz.
50  * 11: 14.769MHz.
51  */
52 #define RS485  0xF0
53 #define RTS_INVERT BIT(5)
54 #define RS485_URA BIT(4)
55 #define RXW4C_IRA BIT(3)
56 #define TXW4C_IRA BIT(2)
57 
58 #define FIFO_CTRL		0xF6
59 #define FIFO_MODE_MASK		(BIT(1) | BIT(0))
60 #define FIFO_MODE_128		(BIT(1) | BIT(0))
61 #define RXFTHR_MODE_MASK	(BIT(5) | BIT(4))
62 #define RXFTHR_MODE_4X		BIT(5)
63 
64 #define F81216_LDN_LOW	0x0
65 #define F81216_LDN_HIGH	0x4
66 
67 /*
68  * F81866/966 registers
69  *
70  * The IRQ setting mode of F81866/966 is not the same with F81216 series.
71  *	Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
72  *	Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
73  *
74  * Clock speeds for UART (register F2h)
75  * 00: 1.8432MHz.
76  * 01: 18.432MHz.
77  * 10: 24MHz.
78  * 11: 14.769MHz.
79  */
80 #define F81866_IRQ_MODE		0xf0
81 #define F81866_IRQ_SHARE	BIT(0)
82 #define F81866_IRQ_MODE0	BIT(1)
83 
84 #define F81866_FIFO_CTRL	FIFO_CTRL
85 #define F81866_IRQ_MODE1	BIT(3)
86 
87 #define F81866_LDN_LOW		0x10
88 #define F81866_LDN_HIGH		0x16
89 
90 #define F81866_UART_CLK 0xF2
91 #define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
92 #define F81866_UART_CLK_1_8432MHZ 0
93 #define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
94 #define F81866_UART_CLK_18_432MHZ BIT(0)
95 #define F81866_UART_CLK_24MHZ BIT(1)
96 
97 struct fintek_8250 {
98 	u16 pid;
99 	u16 base_port;
100 	u8 index;
101 	u8 key;
102 };
103 
104 static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
105 {
106 	outb(reg, pdata->base_port + ADDR_PORT);
107 	return inb(pdata->base_port + DATA_PORT);
108 }
109 
110 static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
111 {
112 	outb(reg, pdata->base_port + ADDR_PORT);
113 	outb(data, pdata->base_port + DATA_PORT);
114 }
115 
116 static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
117 			       u8 data)
118 {
119 	u8 tmp;
120 
121 	tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
122 	sio_write_reg(pdata, reg, tmp);
123 }
124 
125 static int fintek_8250_enter_key(u16 base_port, u8 key)
126 {
127 	if (!request_muxed_region(base_port, 2, "8250_fintek"))
128 		return -EBUSY;
129 
130 	/* Force to deactivate all SuperIO in this base_port */
131 	outb(EXIT_KEY, base_port + ADDR_PORT);
132 
133 	outb(key, base_port + ADDR_PORT);
134 	outb(key, base_port + ADDR_PORT);
135 	return 0;
136 }
137 
138 static void fintek_8250_exit_key(u16 base_port)
139 {
140 
141 	outb(EXIT_KEY, base_port + ADDR_PORT);
142 	release_region(base_port + ADDR_PORT, 2);
143 }
144 
145 static int fintek_8250_check_id(struct fintek_8250 *pdata)
146 {
147 	u16 chip;
148 
149 	if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
150 		return -ENODEV;
151 
152 	if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
153 		return -ENODEV;
154 
155 	chip = sio_read_reg(pdata, CHIP_ID1);
156 	chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
157 
158 	switch (chip) {
159 	case CHIP_ID_F81865:
160 	case CHIP_ID_F81866:
161 	case CHIP_ID_F81966:
162 	case CHIP_ID_F81216AD:
163 	case CHIP_ID_F81216E:
164 	case CHIP_ID_F81216H:
165 	case CHIP_ID_F81214E:
166 	case CHIP_ID_F81216:
167 		break;
168 	default:
169 		return -ENODEV;
170 	}
171 
172 	pdata->pid = chip;
173 	return 0;
174 }
175 
176 static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
177 				     int *max)
178 {
179 	switch (pdata->pid) {
180 	case CHIP_ID_F81966:
181 	case CHIP_ID_F81865:
182 	case CHIP_ID_F81866:
183 		*min = F81866_LDN_LOW;
184 		*max = F81866_LDN_HIGH;
185 		return 0;
186 
187 	case CHIP_ID_F81216AD:
188 	case CHIP_ID_F81216E:
189 	case CHIP_ID_F81216H:
190 	case CHIP_ID_F81214E:
191 	case CHIP_ID_F81216:
192 		*min = F81216_LDN_LOW;
193 		*max = F81216_LDN_HIGH;
194 		return 0;
195 	}
196 
197 	return -ENODEV;
198 }
199 
200 static int fintek_8250_rs485_config(struct uart_port *port, struct ktermios *termios,
201 			      struct serial_rs485 *rs485)
202 {
203 	uint8_t config = 0;
204 	struct fintek_8250 *pdata = port->private_data;
205 
206 	if (!pdata)
207 		return -EINVAL;
208 
209 
210 	if (rs485->flags & SER_RS485_ENABLED) {
211 		/* Hardware do not support same RTS level on send and receive */
212 		if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
213 		    !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
214 			return -EINVAL;
215 		config |= RS485_URA;
216 	}
217 
218 	if (rs485->delay_rts_before_send) {
219 		rs485->delay_rts_before_send = 1;
220 		config |= TXW4C_IRA;
221 	}
222 
223 	if (rs485->delay_rts_after_send) {
224 		rs485->delay_rts_after_send = 1;
225 		config |= RXW4C_IRA;
226 	}
227 
228 	if (rs485->flags & SER_RS485_RTS_ON_SEND)
229 		config |= RTS_INVERT;
230 
231 	if (fintek_8250_enter_key(pdata->base_port, pdata->key))
232 		return -EBUSY;
233 
234 	sio_write_reg(pdata, LDN, pdata->index);
235 	sio_write_reg(pdata, RS485, config);
236 	fintek_8250_exit_key(pdata->base_port);
237 
238 	return 0;
239 }
240 
241 static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
242 {
243 	sio_write_reg(pdata, LDN, pdata->index);
244 
245 	switch (pdata->pid) {
246 	case CHIP_ID_F81966:
247 	case CHIP_ID_F81866:
248 		sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
249 				   0);
250 		fallthrough;
251 	case CHIP_ID_F81865:
252 		sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
253 				   F81866_IRQ_SHARE);
254 		sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
255 				   is_level ? 0 : F81866_IRQ_MODE0);
256 		break;
257 
258 	case CHIP_ID_F81216AD:
259 	case CHIP_ID_F81216E:
260 	case CHIP_ID_F81216H:
261 	case CHIP_ID_F81214E:
262 	case CHIP_ID_F81216:
263 		sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
264 				   IRQ_SHARE);
265 		sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
266 				   is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
267 		break;
268 	}
269 }
270 
271 static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
272 {
273 	switch (pdata->pid) {
274 	case CHIP_ID_F81216E: /* 128Bytes FIFO */
275 	case CHIP_ID_F81216H:
276 	case CHIP_ID_F81214E:
277 	case CHIP_ID_F81966:
278 	case CHIP_ID_F81866:
279 		sio_write_mask_reg(pdata, FIFO_CTRL,
280 				   FIFO_MODE_MASK | RXFTHR_MODE_MASK,
281 				   FIFO_MODE_128 | RXFTHR_MODE_4X);
282 		break;
283 
284 	default: /* Default 16Bytes FIFO */
285 		break;
286 	}
287 }
288 
289 static void fintek_8250_set_termios(struct uart_port *port,
290 				    struct ktermios *termios,
291 				    const struct ktermios *old)
292 {
293 	struct fintek_8250 *pdata = port->private_data;
294 	unsigned int baud = tty_termios_baud_rate(termios);
295 	int i;
296 	u8 reg;
297 	static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
298 	static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
299 			F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
300 			F81866_UART_CLK_24MHZ };
301 
302 	/*
303 	 * We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
304 	 * crash on baudrate_table[i] % baud with "division by zero".
305 	 */
306 	if (!baud)
307 		goto exit;
308 
309 	switch (pdata->pid) {
310 	case CHIP_ID_F81216E:
311 	case CHIP_ID_F81216H:
312 	case CHIP_ID_F81214E:
313 		reg = RS485;
314 		break;
315 	case CHIP_ID_F81966:
316 	case CHIP_ID_F81866:
317 		reg = F81866_UART_CLK;
318 		break;
319 	default:
320 		/* Don't change clocksource with unknown PID */
321 		dev_warn(port->dev,
322 			"%s: pid: %x Not support. use default set_termios.\n",
323 			__func__, pdata->pid);
324 		goto exit;
325 	}
326 
327 	for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
328 		if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
329 			continue;
330 
331 		if (port->uartclk == baudrate_table[i] * 16)
332 			break;
333 
334 		if (fintek_8250_enter_key(pdata->base_port, pdata->key))
335 			continue;
336 
337 		port->uartclk = baudrate_table[i] * 16;
338 
339 		sio_write_reg(pdata, LDN, pdata->index);
340 		sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
341 				clock_table[i]);
342 
343 		fintek_8250_exit_key(pdata->base_port);
344 		break;
345 	}
346 
347 	if (i == ARRAY_SIZE(baudrate_table)) {
348 		baud = tty_termios_baud_rate(old);
349 		tty_termios_encode_baud_rate(termios, baud, baud);
350 	}
351 
352 exit:
353 	serial8250_do_set_termios(port, termios, old);
354 }
355 
356 static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
357 {
358 	struct fintek_8250 *pdata = uart->port.private_data;
359 
360 	switch (pdata->pid) {
361 	case CHIP_ID_F81216E:
362 	case CHIP_ID_F81216H:
363 	case CHIP_ID_F81214E:
364 	case CHIP_ID_F81966:
365 	case CHIP_ID_F81866:
366 		uart->port.set_termios = fintek_8250_set_termios;
367 		break;
368 
369 	default:
370 		break;
371 	}
372 }
373 
374 static int probe_setup_port(struct fintek_8250 *pdata,
375 					struct uart_8250_port *uart)
376 {
377 	static const u16 addr[] = {0x4e, 0x2e};
378 	static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
379 	struct irq_data *irq_data;
380 	bool level_mode = false;
381 	int i, j, k, min, max;
382 
383 	for (i = 0; i < ARRAY_SIZE(addr); i++) {
384 		for (j = 0; j < ARRAY_SIZE(keys); j++) {
385 			pdata->base_port = addr[i];
386 			pdata->key = keys[j];
387 
388 			if (fintek_8250_enter_key(addr[i], keys[j]))
389 				continue;
390 			if (fintek_8250_check_id(pdata) ||
391 			    fintek_8250_get_ldn_range(pdata, &min, &max)) {
392 				fintek_8250_exit_key(addr[i]);
393 				continue;
394 			}
395 
396 			for (k = min; k < max; k++) {
397 				u16 aux;
398 
399 				sio_write_reg(pdata, LDN, k);
400 				aux = sio_read_reg(pdata, IO_ADDR1);
401 				aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
402 				if (aux != uart->port.iobase)
403 					continue;
404 
405 				pdata->index = k;
406 
407 				irq_data = irq_get_irq_data(uart->port.irq);
408 				if (irq_data)
409 					level_mode =
410 						irqd_is_level_type(irq_data);
411 
412 				fintek_8250_set_irq_mode(pdata, level_mode);
413 				fintek_8250_set_max_fifo(pdata);
414 
415 				fintek_8250_exit_key(addr[i]);
416 
417 				return 0;
418 			}
419 
420 			fintek_8250_exit_key(addr[i]);
421 		}
422 	}
423 
424 	return -ENODEV;
425 }
426 
427 /* Only the first port supports delays */
428 static const struct serial_rs485 fintek_8250_rs485_supported_port0 = {
429 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
430 	.delay_rts_before_send = 1,
431 	.delay_rts_after_send = 1,
432 };
433 
434 static const struct serial_rs485 fintek_8250_rs485_supported = {
435 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
436 };
437 
438 static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
439 {
440 	struct fintek_8250 *pdata = uart->port.private_data;
441 
442 	switch (pdata->pid) {
443 	case CHIP_ID_F81216AD:
444 	case CHIP_ID_F81216H:
445 	case CHIP_ID_F81966:
446 	case CHIP_ID_F81866:
447 	case CHIP_ID_F81865:
448 		uart->port.rs485_config = fintek_8250_rs485_config;
449 		if (!pdata->index)
450 			uart->port.rs485_supported = fintek_8250_rs485_supported_port0;
451 		else
452 			uart->port.rs485_supported = fintek_8250_rs485_supported;
453 		break;
454 
455 	case CHIP_ID_F81216E: /* F81216E does not support RS485 delays */
456 	case CHIP_ID_F81214E: /* F81214E does not support RS485 delays */
457 		uart->port.rs485_config = fintek_8250_rs485_config;
458 		uart->port.rs485_supported = fintek_8250_rs485_supported;
459 		break;
460 
461 	default: /* No RS485 Auto direction functional */
462 		break;
463 	}
464 }
465 
466 int fintek_8250_probe(struct uart_8250_port *uart)
467 {
468 	struct fintek_8250 *pdata;
469 	struct fintek_8250 probe_data;
470 
471 	if (probe_setup_port(&probe_data, uart))
472 		return -ENODEV;
473 
474 	pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
475 	if (!pdata)
476 		return -ENOMEM;
477 
478 	memcpy(pdata, &probe_data, sizeof(probe_data));
479 	uart->port.private_data = pdata;
480 	fintek_8250_set_rs485_handler(uart);
481 	fintek_8250_set_termios_handler(uart);
482 
483 	return 0;
484 }
485