1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dp_h__ 2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dp_h__ 3 #include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h> 4 5 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 6 7 /* 8 * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 9 * SPDX-License-Identifier: MIT 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 26 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 27 * DEALINGS IN THE SOFTWARE. 28 */ 29 30 #define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */ 31 32 #define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U 33 34 typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS { 35 NvU32 subDeviceInstance; 36 NvU32 displayId; 37 NvBool bAddrOnly; 38 NvU32 cmd; 39 NvU32 addr; 40 NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE]; 41 NvU32 size; 42 NvU32 replyType; 43 NvU32 retryTimeMs; 44 } NV0073_CTRL_DP_AUXCH_CTRL_PARAMS; 45 46 #define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3 47 #define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U) 48 #define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U) 49 #define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2 50 #define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U) 51 #define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U) 52 #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0 53 #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U) 54 #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U) 55 #define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U) 56 57 #define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */ 58 59 typedef struct NV0073_CTRL_DP_CTRL_PARAMS { 60 NvU32 subDeviceInstance; 61 NvU32 displayId; 62 NvU32 cmd; 63 NvU32 data; 64 NvU32 err; 65 NvU32 retryTimeMs; 66 NvU32 eightLaneDpcdBaseAddr; 67 } NV0073_CTRL_DP_CTRL_PARAMS; 68 69 #define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0 70 #define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U) 71 #define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U) 72 #define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1 73 #define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U) 74 #define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U) 75 #define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2 76 #define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U) 77 #define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U) 78 #define NV0073_CTRL_DP_CMD_UNUSED 3:3 79 #define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4 80 #define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U) 81 #define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U) 82 #define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5 83 #define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U) 84 #define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U) 85 #define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6 86 #define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U) 87 #define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U) 88 #define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7 89 #define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U) 90 #define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U) 91 #define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8 92 #define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U) 93 #define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U) 94 #define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9 95 #define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) 96 #define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) 97 #define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10 98 #define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U) 99 #define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U) 100 #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11 101 #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) 102 #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) 103 #define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) 104 #define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13 105 #define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U) 106 #define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U) 107 #define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14 108 #define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) 109 #define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) 110 #define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15 111 #define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U) 112 #define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U) 113 114 #define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29 115 #define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U) 116 #define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U) 117 #define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30 118 #define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U) 119 #define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U) 120 #define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31 121 #define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U) 122 #define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U) 123 124 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0 125 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U) 126 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U) 127 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U) 128 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U) 129 #define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U) 130 #define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8 131 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U) 132 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U) 133 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U) 134 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU) 135 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU) 136 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U) 137 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U) 138 #define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU) 139 #define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18 140 #define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U) 141 #define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U) 142 #define NV0073_CTRL_DP_DATA_TARGET 22:19 143 #define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U) 144 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U) 145 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U) 146 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U) 147 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U) 148 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U) 149 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U) 150 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U) 151 #define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U) 152 153 #define NV0073_CTRL_MAX_LANES 8U 154 155 typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS { 156 NvU32 subDeviceInstance; 157 NvU32 displayId; 158 NvU32 numLanes; 159 NvU32 data[NV0073_CTRL_MAX_LANES]; 160 } NV0073_CTRL_DP_LANE_DATA_PARAMS; 161 162 #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0 163 #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U) 164 #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U) 165 #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U) 166 #define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U) 167 #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2 168 #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U) 169 #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U) 170 #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U) 171 #define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U) 172 173 #define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */ 174 175 #define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */ 176 177 typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS { 178 NvU32 subDeviceInstance; 179 NvU32 displayId; 180 NvU32 mute; 181 } NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS; 182 183 #define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */ 184 185 typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS { 186 NvU32 subDeviceInstance; 187 NvU32 displayId; 188 NvU32 preferredDisplayId; 189 190 NvBool force; 191 NvBool useBFM; 192 193 NvU32 displayIdAssigned; 194 NvU32 allDisplayMask; 195 } NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS; 196 197 #define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */ 198 199 typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { 200 NvU32 subDeviceInstance; 201 NvU32 displayId; 202 } NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS; 203 204 #define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */ 205 206 typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS { 207 NvU32 subDeviceInstance; 208 NvU32 head; 209 NvU32 sorIndex; 210 NvU32 dpLink; 211 212 NvBool bEnableOverride; 213 NvBool bMST; 214 NvU32 singleHeadMultistreamMode; 215 NvU32 hBlankSym; 216 NvU32 vBlankSym; 217 NvU32 colorFormat; 218 NvBool bEnableTwoHeadOneOr; 219 220 struct { 221 NvU32 slotStart; 222 NvU32 slotEnd; 223 NvU32 PBN; 224 NvU32 Timeslice; 225 NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT 226 NvU32 singleHeadMSTPipeline; 227 NvBool bEnableAudioOverRightPanel; 228 } MST; 229 230 struct { 231 NvBool bEnhancedFraming; 232 NvU32 tuSize; 233 NvU32 waterMark; 234 NvU32 actualPclkHz; // deprecated -Use MvidWarParams 235 NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams 236 NvBool bEnableAudioOverRightPanel; 237 struct { 238 NvU32 activeCnt; 239 NvU32 activeFrac; 240 NvU32 activePolarity; 241 NvBool mvidWarEnabled; 242 struct { 243 NvU32 actualPclkHz; 244 NvU32 linkClkFreqHz; 245 } MvidWarParams; 246 } Legacy; 247 } SST; 248 } NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS; 249 250 #define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */ 251 252 typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS { 253 NvU32 subDeviceInstance; 254 } NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS; 255 256 #define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ 257 258 #define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) 259 260 typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { 261 NvU32 subDeviceInstance; 262 NvU32 sorIndex; 263 NvU32 maxLinkRate; 264 NvU32 dpVersionsSupported; 265 NvU32 UHBRSupported; 266 NvBool bIsMultistreamSupported; 267 NvBool bIsSCEnabled; 268 NvBool bHasIncreasedWatermarkLimits; 269 NvBool bIsPC2Disabled; 270 NvBool isSingleHeadMSTSupported; 271 NvBool bFECSupported; 272 NvBool bIsTrainPhyRepeater; 273 NvBool bOverrideLinkBw; 274 NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; 275 } NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; 276 277 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 278 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) 279 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) 280 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 281 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) 282 #define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) 283 284 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 285 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) 286 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) 287 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U) 288 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U) 289 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U) 290 291 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U) 292 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U) 293 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U) 294 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U) 295 296 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U) 297 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U) 298 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U) 299 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U) 300 #define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U) 301 302 #define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */ 303 304 #define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U 305 306 typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { 307 // In 308 NvU32 subDeviceInstance; 309 NvU32 displayId; 310 NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; 311 312 // Out 313 NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; 314 NvU8 linkBwCount; 315 } NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; 316 317 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0 318 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U) 319 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U) 320 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U) 321 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U) 322 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U) 323 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U) 324 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U) 325 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U) 326 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U) 327 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U) 328 329 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U) 330 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U) 331 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U) 332 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U) 333 #define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U) 334 335 #endif 336