1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/pci.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_atombios.h"
31 #include "amdgpu_dpm_internal.h"
32 #include "amd_pcie.h"
33 #include "atom.h"
34 #include "gfx_v6_0.h"
35 #include "r600_dpm.h"
36 #include "sid.h"
37 #include "si_dpm.h"
38 #include "../include/pptable.h"
39 #include <linux/math64.h>
40 #include <linux/seq_file.h>
41 #include <linux/firmware.h>
42 #include <legacy_dpm.h>
43
44 #include "bif/bif_3_0_d.h"
45 #include "bif/bif_3_0_sh_mask.h"
46
47 #include "dce/dce_6_0_d.h"
48 #include "dce/dce_6_0_sh_mask.h"
49
50 #include "gca/gfx_6_0_d.h"
51 #include "gca/gfx_6_0_sh_mask.h"
52
53 #include"gmc/gmc_6_0_d.h"
54 #include"gmc/gmc_6_0_sh_mask.h"
55
56 #include "smu/smu_6_0_d.h"
57 #include "smu/smu_6_0_sh_mask.h"
58
59 #define MC_CG_ARB_FREQ_F0 0x0a
60 #define MC_CG_ARB_FREQ_F1 0x0b
61 #define MC_CG_ARB_FREQ_F2 0x0c
62 #define MC_CG_ARB_FREQ_F3 0x0d
63
64 #define SMC_RAM_END 0x20000
65
66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
67
68
69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
76
77 #define BIOS_SCRATCH_4 0x5cd
78
79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
82 MODULE_FIRMWARE("amdgpu/verde_smc.bin");
83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
84 MODULE_FIRMWARE("amdgpu/oland_smc.bin");
85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
89
90 static const struct amd_pm_funcs si_dpm_funcs;
91
92 union power_info {
93 struct _ATOM_POWERPLAY_INFO info;
94 struct _ATOM_POWERPLAY_INFO_V2 info_2;
95 struct _ATOM_POWERPLAY_INFO_V3 info_3;
96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
101 };
102
103 union fan_info {
104 struct _ATOM_PPLIB_FANTABLE fan;
105 struct _ATOM_PPLIB_FANTABLE2 fan2;
106 struct _ATOM_PPLIB_FANTABLE3 fan3;
107 };
108
109 union pplib_clock_info {
110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
114 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
115 };
116
117 enum si_dpm_auto_throttle_src {
118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL,
119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL
120 };
121
122 enum si_dpm_event_src {
123 SI_DPM_EVENT_SRC_ANALOG = 0,
124 SI_DPM_EVENT_SRC_EXTERNAL = 1,
125 SI_DPM_EVENT_SRC_DIGITAL = 2,
126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
128 };
129
130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
131 {
132 R600_UTC_DFLT_00,
133 R600_UTC_DFLT_01,
134 R600_UTC_DFLT_02,
135 R600_UTC_DFLT_03,
136 R600_UTC_DFLT_04,
137 R600_UTC_DFLT_05,
138 R600_UTC_DFLT_06,
139 R600_UTC_DFLT_07,
140 R600_UTC_DFLT_08,
141 R600_UTC_DFLT_09,
142 R600_UTC_DFLT_10,
143 R600_UTC_DFLT_11,
144 R600_UTC_DFLT_12,
145 R600_UTC_DFLT_13,
146 R600_UTC_DFLT_14,
147 };
148
149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
150 {
151 R600_DTC_DFLT_00,
152 R600_DTC_DFLT_01,
153 R600_DTC_DFLT_02,
154 R600_DTC_DFLT_03,
155 R600_DTC_DFLT_04,
156 R600_DTC_DFLT_05,
157 R600_DTC_DFLT_06,
158 R600_DTC_DFLT_07,
159 R600_DTC_DFLT_08,
160 R600_DTC_DFLT_09,
161 R600_DTC_DFLT_10,
162 R600_DTC_DFLT_11,
163 R600_DTC_DFLT_12,
164 R600_DTC_DFLT_13,
165 R600_DTC_DFLT_14,
166 };
167
168 static const struct si_cac_config_reg cac_weights_tahiti[] =
169 {
170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
230 { 0xFFFFFFFF }
231 };
232
233 static const struct si_cac_config_reg lcac_tahiti[] =
234 {
235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
321 { 0xFFFFFFFF }
322
323 };
324
325 static const struct si_cac_config_reg cac_override_tahiti[] =
326 {
327 { 0xFFFFFFFF }
328 };
329
330 static const struct si_powertune_data powertune_data_tahiti =
331 {
332 ((1 << 16) | 27027),
333 6,
334 0,
335 4,
336 95,
337 {
338 0UL,
339 0UL,
340 4521550UL,
341 309631529UL,
342 -1270850L,
343 4513710L,
344 40
345 },
346 595000000UL,
347 12,
348 {
349 0,
350 0,
351 0,
352 0,
353 0,
354 0,
355 0,
356 0
357 },
358 true
359 };
360
361 static const struct si_dte_data dte_data_tahiti =
362 {
363 { 1159409, 0, 0, 0, 0 },
364 { 777, 0, 0, 0, 0 },
365 2,
366 54000,
367 127000,
368 25,
369 2,
370 10,
371 13,
372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
375 85,
376 false
377 };
378
379 static const struct si_dte_data dte_data_tahiti_pro =
380 {
381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
382 { 0x0, 0x0, 0x0, 0x0, 0x0 },
383 5,
384 45000,
385 100,
386 0xA,
387 1,
388 0,
389 0x10,
390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
393 90,
394 true
395 };
396
397 static const struct si_dte_data dte_data_new_zealand =
398 {
399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
401 0x5,
402 0xAFC8,
403 0x69,
404 0x32,
405 1,
406 0,
407 0x10,
408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
411 85,
412 true
413 };
414
415 static const struct si_dte_data dte_data_aruba_pro =
416 {
417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
418 { 0x0, 0x0, 0x0, 0x0, 0x0 },
419 5,
420 45000,
421 100,
422 0xA,
423 1,
424 0,
425 0x10,
426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
429 90,
430 true
431 };
432
433 static const struct si_dte_data dte_data_malta =
434 {
435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
436 { 0x0, 0x0, 0x0, 0x0, 0x0 },
437 5,
438 45000,
439 100,
440 0xA,
441 1,
442 0,
443 0x10,
444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
447 90,
448 true
449 };
450
451 static const struct si_cac_config_reg cac_weights_pitcairn[] =
452 {
453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
513 { 0xFFFFFFFF }
514 };
515
516 static const struct si_cac_config_reg lcac_pitcairn[] =
517 {
518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
604 { 0xFFFFFFFF }
605 };
606
607 static const struct si_cac_config_reg cac_override_pitcairn[] =
608 {
609 { 0xFFFFFFFF }
610 };
611
612 static const struct si_powertune_data powertune_data_pitcairn =
613 {
614 ((1 << 16) | 27027),
615 5,
616 0,
617 6,
618 100,
619 {
620 51600000UL,
621 1800000UL,
622 7194395UL,
623 309631529UL,
624 -1270850L,
625 4513710L,
626 100
627 },
628 117830498UL,
629 12,
630 {
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 0
639 },
640 true
641 };
642
643 static const struct si_dte_data dte_data_pitcairn =
644 {
645 { 0, 0, 0, 0, 0 },
646 { 0, 0, 0, 0, 0 },
647 0,
648 0,
649 0,
650 0,
651 0,
652 0,
653 0,
654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
657 0,
658 false
659 };
660
661 static const struct si_dte_data dte_data_curacao_xt =
662 {
663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
664 { 0x0, 0x0, 0x0, 0x0, 0x0 },
665 5,
666 45000,
667 100,
668 0xA,
669 1,
670 0,
671 0x10,
672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
675 90,
676 true
677 };
678
679 static const struct si_dte_data dte_data_curacao_pro =
680 {
681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
682 { 0x0, 0x0, 0x0, 0x0, 0x0 },
683 5,
684 45000,
685 100,
686 0xA,
687 1,
688 0,
689 0x10,
690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
693 90,
694 true
695 };
696
697 static const struct si_dte_data dte_data_neptune_xt =
698 {
699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
700 { 0x0, 0x0, 0x0, 0x0, 0x0 },
701 5,
702 45000,
703 100,
704 0xA,
705 1,
706 0,
707 0x10,
708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
711 90,
712 true
713 };
714
715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
716 {
717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
777 { 0xFFFFFFFF }
778 };
779
780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
781 {
782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
842 { 0xFFFFFFFF }
843 };
844
845 static const struct si_cac_config_reg cac_weights_heathrow[] =
846 {
847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
907 { 0xFFFFFFFF }
908 };
909
910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
911 {
912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
972 { 0xFFFFFFFF }
973 };
974
975 static const struct si_cac_config_reg cac_weights_cape_verde[] =
976 {
977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1037 { 0xFFFFFFFF }
1038 };
1039
1040 static const struct si_cac_config_reg lcac_cape_verde[] =
1041 {
1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1096 { 0xFFFFFFFF }
1097 };
1098
1099 static const struct si_cac_config_reg cac_override_cape_verde[] =
1100 {
1101 { 0xFFFFFFFF }
1102 };
1103
1104 static const struct si_powertune_data powertune_data_cape_verde =
1105 {
1106 ((1 << 16) | 0x6993),
1107 5,
1108 0,
1109 7,
1110 105,
1111 {
1112 0UL,
1113 0UL,
1114 7194395UL,
1115 309631529UL,
1116 -1270850L,
1117 4513710L,
1118 100
1119 },
1120 117830498UL,
1121 12,
1122 {
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 0
1131 },
1132 true
1133 };
1134
1135 static const struct si_dte_data dte_data_cape_verde =
1136 {
1137 { 0, 0, 0, 0, 0 },
1138 { 0, 0, 0, 0, 0 },
1139 0,
1140 0,
1141 0,
1142 0,
1143 0,
1144 0,
1145 0,
1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1149 0,
1150 false
1151 };
1152
1153 static const struct si_dte_data dte_data_venus_xtx =
1154 {
1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1157 5,
1158 55000,
1159 0x69,
1160 0xA,
1161 1,
1162 0,
1163 0x3,
1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 90,
1168 true
1169 };
1170
1171 static const struct si_dte_data dte_data_venus_xt =
1172 {
1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1175 5,
1176 55000,
1177 0x69,
1178 0xA,
1179 1,
1180 0,
1181 0x3,
1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 90,
1186 true
1187 };
1188
1189 static const struct si_dte_data dte_data_venus_pro =
1190 {
1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1193 5,
1194 55000,
1195 0x69,
1196 0xA,
1197 1,
1198 0,
1199 0x3,
1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1203 90,
1204 true
1205 };
1206
1207 static const struct si_cac_config_reg cac_weights_oland[] =
1208 {
1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1269 { 0xFFFFFFFF }
1270 };
1271
1272 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1273 {
1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1334 { 0xFFFFFFFF }
1335 };
1336
1337 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1338 {
1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1399 { 0xFFFFFFFF }
1400 };
1401
1402 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1403 {
1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1464 { 0xFFFFFFFF }
1465 };
1466
1467 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1468 {
1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1529 { 0xFFFFFFFF }
1530 };
1531
1532 static const struct si_cac_config_reg lcac_oland[] =
1533 {
1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0xFFFFFFFF }
1577 };
1578
1579 static const struct si_cac_config_reg lcac_mars_pro[] =
1580 {
1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1623 { 0xFFFFFFFF }
1624 };
1625
1626 static const struct si_cac_config_reg cac_override_oland[] =
1627 {
1628 { 0xFFFFFFFF }
1629 };
1630
1631 static const struct si_powertune_data powertune_data_oland =
1632 {
1633 ((1 << 16) | 0x6993),
1634 5,
1635 0,
1636 7,
1637 105,
1638 {
1639 0UL,
1640 0UL,
1641 7194395UL,
1642 309631529UL,
1643 -1270850L,
1644 4513710L,
1645 100
1646 },
1647 117830498UL,
1648 12,
1649 {
1650 0,
1651 0,
1652 0,
1653 0,
1654 0,
1655 0,
1656 0,
1657 0
1658 },
1659 true
1660 };
1661
1662 static const struct si_powertune_data powertune_data_mars_pro =
1663 {
1664 ((1 << 16) | 0x6993),
1665 5,
1666 0,
1667 7,
1668 105,
1669 {
1670 0UL,
1671 0UL,
1672 7194395UL,
1673 309631529UL,
1674 -1270850L,
1675 4513710L,
1676 100
1677 },
1678 117830498UL,
1679 12,
1680 {
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 0
1689 },
1690 true
1691 };
1692
1693 static const struct si_dte_data dte_data_oland =
1694 {
1695 { 0, 0, 0, 0, 0 },
1696 { 0, 0, 0, 0, 0 },
1697 0,
1698 0,
1699 0,
1700 0,
1701 0,
1702 0,
1703 0,
1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1707 0,
1708 false
1709 };
1710
1711 static const struct si_dte_data dte_data_mars_pro =
1712 {
1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1714 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1715 5,
1716 55000,
1717 105,
1718 0xA,
1719 1,
1720 0,
1721 0x10,
1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1725 90,
1726 true
1727 };
1728
1729 static const struct si_dte_data dte_data_sun_xt =
1730 {
1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1732 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1733 5,
1734 55000,
1735 105,
1736 0xA,
1737 1,
1738 0,
1739 0x10,
1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1743 90,
1744 true
1745 };
1746
1747
1748 static const struct si_cac_config_reg cac_weights_hainan[] =
1749 {
1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1810 { 0xFFFFFFFF }
1811 };
1812
1813 static const struct si_powertune_data powertune_data_hainan =
1814 {
1815 ((1 << 16) | 0x6993),
1816 5,
1817 0,
1818 9,
1819 105,
1820 {
1821 0UL,
1822 0UL,
1823 7194395UL,
1824 309631529UL,
1825 -1270850L,
1826 4513710L,
1827 100
1828 },
1829 117830498UL,
1830 12,
1831 {
1832 0,
1833 0,
1834 0,
1835 0,
1836 0,
1837 0,
1838 0,
1839 0
1840 },
1841 true
1842 };
1843
1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1848
1849 static int si_populate_voltage_value(struct amdgpu_device *adev,
1850 const struct atom_voltage_table *table,
1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1852 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1854 u16 *std_voltage);
1855 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1856 u16 reg_offset, u32 value);
1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1858 struct rv7xx_pl *pl,
1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1860 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1861 u32 engine_clock,
1862 SISLANDS_SMC_SCLK_VALUE *sclk);
1863
1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1867
si_get_pi(struct amdgpu_device * adev)1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1869 {
1870 struct si_power_info *pi = adev->pm.dpm.priv;
1871 return pi;
1872 }
1873
si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 ileakage,u32 * leakage)1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1875 u16 v, s32 t, u32 ileakage, u32 *leakage)
1876 {
1877 s64 kt, kv, leakage_w, i_leakage, vddc;
1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1879 s64 tmp;
1880
1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1882 vddc = div64_s64(drm_int2fixp(v), 1000);
1883 temperature = div64_s64(drm_int2fixp(t), 1000);
1884
1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1889 t_ref = drm_int2fixp(coeff->t_ref);
1890
1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1895
1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1897
1898 *leakage = drm_fixp2int(leakage_w * 1000);
1899 }
1900
si_calculate_leakage_for_v_and_t(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 i_leakage,u32 * leakage)1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1902 const struct ni_leakage_coeffients *coeff,
1903 u16 v,
1904 s32 t,
1905 u32 i_leakage,
1906 u32 *leakage)
1907 {
1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1909 }
1910
si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 ileakage,u32 * leakage)1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1912 const u32 fixed_kt, u16 v,
1913 u32 ileakage, u32 *leakage)
1914 {
1915 s64 kt, kv, leakage_w, i_leakage, vddc;
1916
1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1918 vddc = div64_s64(drm_int2fixp(v), 1000);
1919
1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1923
1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1925
1926 *leakage = drm_fixp2int(leakage_w * 1000);
1927 }
1928
si_calculate_leakage_for_v(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 i_leakage,u32 * leakage)1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1930 const struct ni_leakage_coeffients *coeff,
1931 const u32 fixed_kt,
1932 u16 v,
1933 u32 i_leakage,
1934 u32 *leakage)
1935 {
1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1937 }
1938
1939
si_update_dte_from_pl2(struct amdgpu_device * adev,struct si_dte_data * dte_data)1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1941 struct si_dte_data *dte_data)
1942 {
1943 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1945 u32 k = dte_data->k;
1946 u32 t_max = dte_data->max_t;
1947 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1948 u32 t_0 = dte_data->t0;
1949 u32 i;
1950
1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1952 dte_data->tdep_count = 3;
1953
1954 for (i = 0; i < k; i++) {
1955 dte_data->r[i] =
1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1957 (p_limit2 * (u32)100);
1958 }
1959
1960 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1961
1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1963 dte_data->tdep_r[i] = dte_data->r[4];
1964 }
1965 } else {
1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1967 }
1968 }
1969
rv770_get_pi(struct amdgpu_device * adev)1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1971 {
1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1973
1974 return pi;
1975 }
1976
ni_get_pi(struct amdgpu_device * adev)1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1978 {
1979 struct ni_power_info *pi = adev->pm.dpm.priv;
1980
1981 return pi;
1982 }
1983
si_get_ps(struct amdgpu_ps * aps)1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1985 {
1986 struct si_ps *ps = aps->ps_priv;
1987
1988 return ps;
1989 }
1990
si_initialize_powertune_defaults(struct amdgpu_device * adev)1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1992 {
1993 struct ni_power_info *ni_pi = ni_get_pi(adev);
1994 struct si_power_info *si_pi = si_get_pi(adev);
1995 bool update_dte_from_pl2 = false;
1996
1997 if (adev->asic_type == CHIP_TAHITI) {
1998 si_pi->cac_weights = cac_weights_tahiti;
1999 si_pi->lcac_config = lcac_tahiti;
2000 si_pi->cac_override = cac_override_tahiti;
2001 si_pi->powertune_data = &powertune_data_tahiti;
2002 si_pi->dte_data = dte_data_tahiti;
2003
2004 switch (adev->pdev->device) {
2005 case 0x6798:
2006 si_pi->dte_data.enable_dte_by_default = true;
2007 break;
2008 case 0x6799:
2009 si_pi->dte_data = dte_data_new_zealand;
2010 break;
2011 case 0x6790:
2012 case 0x6791:
2013 case 0x6792:
2014 case 0x679E:
2015 si_pi->dte_data = dte_data_aruba_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x679B:
2019 si_pi->dte_data = dte_data_malta;
2020 update_dte_from_pl2 = true;
2021 break;
2022 case 0x679A:
2023 si_pi->dte_data = dte_data_tahiti_pro;
2024 update_dte_from_pl2 = true;
2025 break;
2026 default:
2027 if (si_pi->dte_data.enable_dte_by_default == true)
2028 DRM_ERROR("DTE is not enabled!\n");
2029 break;
2030 }
2031 } else if (adev->asic_type == CHIP_PITCAIRN) {
2032 si_pi->cac_weights = cac_weights_pitcairn;
2033 si_pi->lcac_config = lcac_pitcairn;
2034 si_pi->cac_override = cac_override_pitcairn;
2035 si_pi->powertune_data = &powertune_data_pitcairn;
2036
2037 switch (adev->pdev->device) {
2038 case 0x6810:
2039 case 0x6818:
2040 si_pi->dte_data = dte_data_curacao_xt;
2041 update_dte_from_pl2 = true;
2042 break;
2043 case 0x6819:
2044 case 0x6811:
2045 si_pi->dte_data = dte_data_curacao_pro;
2046 update_dte_from_pl2 = true;
2047 break;
2048 case 0x6800:
2049 case 0x6806:
2050 si_pi->dte_data = dte_data_neptune_xt;
2051 update_dte_from_pl2 = true;
2052 break;
2053 default:
2054 si_pi->dte_data = dte_data_pitcairn;
2055 break;
2056 }
2057 } else if (adev->asic_type == CHIP_VERDE) {
2058 si_pi->lcac_config = lcac_cape_verde;
2059 si_pi->cac_override = cac_override_cape_verde;
2060 si_pi->powertune_data = &powertune_data_cape_verde;
2061
2062 switch (adev->pdev->device) {
2063 case 0x683B:
2064 case 0x683F:
2065 case 0x6829:
2066 case 0x6835:
2067 si_pi->cac_weights = cac_weights_cape_verde_pro;
2068 si_pi->dte_data = dte_data_cape_verde;
2069 break;
2070 case 0x682C:
2071 si_pi->cac_weights = cac_weights_cape_verde_pro;
2072 si_pi->dte_data = dte_data_sun_xt;
2073 update_dte_from_pl2 = true;
2074 break;
2075 case 0x6825:
2076 case 0x6827:
2077 si_pi->cac_weights = cac_weights_heathrow;
2078 si_pi->dte_data = dte_data_cape_verde;
2079 break;
2080 case 0x6824:
2081 case 0x682D:
2082 si_pi->cac_weights = cac_weights_chelsea_xt;
2083 si_pi->dte_data = dte_data_cape_verde;
2084 break;
2085 case 0x682F:
2086 si_pi->cac_weights = cac_weights_chelsea_pro;
2087 si_pi->dte_data = dte_data_cape_verde;
2088 break;
2089 case 0x6820:
2090 si_pi->cac_weights = cac_weights_heathrow;
2091 si_pi->dte_data = dte_data_venus_xtx;
2092 break;
2093 case 0x6821:
2094 si_pi->cac_weights = cac_weights_heathrow;
2095 si_pi->dte_data = dte_data_venus_xt;
2096 break;
2097 case 0x6823:
2098 case 0x682B:
2099 case 0x6822:
2100 case 0x682A:
2101 si_pi->cac_weights = cac_weights_chelsea_pro;
2102 si_pi->dte_data = dte_data_venus_pro;
2103 break;
2104 default:
2105 si_pi->cac_weights = cac_weights_cape_verde;
2106 si_pi->dte_data = dte_data_cape_verde;
2107 break;
2108 }
2109 } else if (adev->asic_type == CHIP_OLAND) {
2110 si_pi->lcac_config = lcac_mars_pro;
2111 si_pi->cac_override = cac_override_oland;
2112 si_pi->powertune_data = &powertune_data_mars_pro;
2113 si_pi->dte_data = dte_data_mars_pro;
2114
2115 switch (adev->pdev->device) {
2116 case 0x6601:
2117 case 0x6621:
2118 case 0x6603:
2119 case 0x6605:
2120 si_pi->cac_weights = cac_weights_mars_pro;
2121 update_dte_from_pl2 = true;
2122 break;
2123 case 0x6600:
2124 case 0x6606:
2125 case 0x6620:
2126 case 0x6604:
2127 si_pi->cac_weights = cac_weights_mars_xt;
2128 update_dte_from_pl2 = true;
2129 break;
2130 case 0x6611:
2131 case 0x6613:
2132 case 0x6608:
2133 si_pi->cac_weights = cac_weights_oland_pro;
2134 update_dte_from_pl2 = true;
2135 break;
2136 case 0x6610:
2137 si_pi->cac_weights = cac_weights_oland_xt;
2138 update_dte_from_pl2 = true;
2139 break;
2140 default:
2141 si_pi->cac_weights = cac_weights_oland;
2142 si_pi->lcac_config = lcac_oland;
2143 si_pi->cac_override = cac_override_oland;
2144 si_pi->powertune_data = &powertune_data_oland;
2145 si_pi->dte_data = dte_data_oland;
2146 break;
2147 }
2148 } else if (adev->asic_type == CHIP_HAINAN) {
2149 si_pi->cac_weights = cac_weights_hainan;
2150 si_pi->lcac_config = lcac_oland;
2151 si_pi->cac_override = cac_override_oland;
2152 si_pi->powertune_data = &powertune_data_hainan;
2153 si_pi->dte_data = dte_data_sun_xt;
2154 update_dte_from_pl2 = true;
2155 } else {
2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2157 return;
2158 }
2159
2160 ni_pi->enable_power_containment = false;
2161 ni_pi->enable_cac = false;
2162 ni_pi->enable_sq_ramping = false;
2163 si_pi->enable_dte = false;
2164
2165 if (si_pi->powertune_data->enable_powertune_by_default) {
2166 ni_pi->enable_power_containment = true;
2167 ni_pi->enable_cac = true;
2168 if (si_pi->dte_data.enable_dte_by_default) {
2169 si_pi->enable_dte = true;
2170 if (update_dte_from_pl2)
2171 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2172
2173 }
2174 ni_pi->enable_sq_ramping = true;
2175 }
2176
2177 ni_pi->driver_calculate_cac_leakage = true;
2178 ni_pi->cac_configuration_required = true;
2179
2180 if (ni_pi->cac_configuration_required) {
2181 ni_pi->support_cac_long_term_average = true;
2182 si_pi->dyn_powertune_data.l2_lta_window_size =
2183 si_pi->powertune_data->l2_lta_window_size_default;
2184 si_pi->dyn_powertune_data.lts_truncate =
2185 si_pi->powertune_data->lts_truncate_default;
2186 } else {
2187 ni_pi->support_cac_long_term_average = false;
2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2189 si_pi->dyn_powertune_data.lts_truncate = 0;
2190 }
2191
2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2193 }
2194
si_get_smc_power_scaling_factor(struct amdgpu_device * adev)2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2196 {
2197 return 1;
2198 }
2199
si_calculate_cac_wintime(struct amdgpu_device * adev)2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2201 {
2202 u32 xclk;
2203 u32 wintime;
2204 u32 cac_window;
2205 u32 cac_window_size;
2206
2207 xclk = amdgpu_asic_get_xclk(adev);
2208
2209 if (xclk == 0)
2210 return 0;
2211
2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK;
2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2214
2215 wintime = (cac_window_size * 100) / xclk;
2216
2217 return wintime;
2218 }
2219
si_scale_power_for_smc(u32 power_in_watts,u32 scaling_factor)2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2221 {
2222 return power_in_watts;
2223 }
2224
si_calculate_adjusted_tdp_limits(struct amdgpu_device * adev,bool adjust_polarity,u32 tdp_adjustment,u32 * tdp_limit,u32 * near_tdp_limit)2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2226 bool adjust_polarity,
2227 u32 tdp_adjustment,
2228 u32 *tdp_limit,
2229 u32 *near_tdp_limit)
2230 {
2231 u32 adjustment_delta, max_tdp_limit;
2232
2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2234 return -EINVAL;
2235
2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2237
2238 if (adjust_polarity) {
2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2241 } else {
2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2246 else
2247 *near_tdp_limit = 0;
2248 }
2249
2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2251 return -EINVAL;
2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2253 return -EINVAL;
2254
2255 return 0;
2256 }
2257
si_populate_smc_tdp_limits(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2259 struct amdgpu_ps *amdgpu_state)
2260 {
2261 struct ni_power_info *ni_pi = ni_get_pi(adev);
2262 struct si_power_info *si_pi = si_get_pi(adev);
2263
2264 if (ni_pi->enable_power_containment) {
2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2266 PP_SIslands_PAPMParameters *papm_parm;
2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2269 u32 tdp_limit;
2270 u32 near_tdp_limit;
2271 int ret;
2272
2273 if (scaling_factor == 0)
2274 return -EINVAL;
2275
2276 ret = si_calculate_adjusted_tdp_limits(adev,
2277 false, /* ??? */
2278 adev->pm.dpm.tdp_adjustment,
2279 &tdp_limit,
2280 &near_tdp_limit);
2281 if (ret)
2282 return ret;
2283
2284 if (adev->pdev->device == 0x6611 && adev->pdev->revision == 0x87) {
2285 /* Workaround buggy powertune on Radeon 430 and 520. */
2286 tdp_limit = 32;
2287 near_tdp_limit = 28;
2288 }
2289
2290 smc_table->dpm2Params.TDPLimit =
2291 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2292 smc_table->dpm2Params.NearTDPLimit =
2293 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2294 smc_table->dpm2Params.SafePowerLimit =
2295 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2296
2297 ret = amdgpu_si_copy_bytes_to_smc(adev,
2298 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2299 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2300 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2301 sizeof(u32) * 3,
2302 si_pi->sram_end);
2303 if (ret)
2304 return ret;
2305
2306 if (si_pi->enable_ppm) {
2307 papm_parm = &si_pi->papm_parm;
2308 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2309 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2310 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2311 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2312 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2313 papm_parm->PlatformPowerLimit = 0xffffffff;
2314 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2315
2316 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2317 (u8 *)papm_parm,
2318 sizeof(PP_SIslands_PAPMParameters),
2319 si_pi->sram_end);
2320 if (ret)
2321 return ret;
2322 }
2323 }
2324 return 0;
2325 }
2326
si_populate_smc_tdp_limits_2(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2327 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2328 struct amdgpu_ps *amdgpu_state)
2329 {
2330 struct ni_power_info *ni_pi = ni_get_pi(adev);
2331 struct si_power_info *si_pi = si_get_pi(adev);
2332
2333 if (ni_pi->enable_power_containment) {
2334 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2335 int ret;
2336
2337 ret = amdgpu_si_copy_bytes_to_smc(adev,
2338 (si_pi->state_table_start +
2339 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2340 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2341 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2342 sizeof(u32) * 2,
2343 si_pi->sram_end);
2344 if (ret)
2345 return ret;
2346 }
2347
2348 return 0;
2349 }
2350
si_calculate_power_efficiency_ratio(struct amdgpu_device * adev,const u16 prev_std_vddc,const u16 curr_std_vddc)2351 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2352 const u16 prev_std_vddc,
2353 const u16 curr_std_vddc)
2354 {
2355 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2356 u64 prev_vddc = (u64)prev_std_vddc;
2357 u64 curr_vddc = (u64)curr_std_vddc;
2358 u64 pwr_efficiency_ratio, n, d;
2359
2360 if ((prev_vddc == 0) || (curr_vddc == 0))
2361 return 0;
2362
2363 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2364 d = prev_vddc * prev_vddc;
2365 pwr_efficiency_ratio = div64_u64(n, d);
2366
2367 if (pwr_efficiency_ratio > (u64)0xFFFF)
2368 return 0;
2369
2370 return (u16)pwr_efficiency_ratio;
2371 }
2372
si_should_disable_uvd_powertune(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2373 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2374 struct amdgpu_ps *amdgpu_state)
2375 {
2376 struct si_power_info *si_pi = si_get_pi(adev);
2377
2378 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2379 amdgpu_state->vclk && amdgpu_state->dclk)
2380 return true;
2381
2382 return false;
2383 }
2384
evergreen_get_pi(struct amdgpu_device * adev)2385 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2386 {
2387 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2388
2389 return pi;
2390 }
2391
si_populate_power_containment_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2392 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2393 struct amdgpu_ps *amdgpu_state,
2394 SISLANDS_SMC_SWSTATE *smc_state)
2395 {
2396 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2397 struct ni_power_info *ni_pi = ni_get_pi(adev);
2398 struct si_ps *state = si_get_ps(amdgpu_state);
2399 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2400 u32 prev_sclk;
2401 u32 max_sclk;
2402 u32 min_sclk;
2403 u16 prev_std_vddc;
2404 u16 curr_std_vddc;
2405 int i;
2406 u16 pwr_efficiency_ratio;
2407 u8 max_ps_percent;
2408 bool disable_uvd_power_tune;
2409 int ret;
2410
2411 if (ni_pi->enable_power_containment == false)
2412 return 0;
2413
2414 if (state->performance_level_count == 0)
2415 return -EINVAL;
2416
2417 if (smc_state->levelCount != state->performance_level_count)
2418 return -EINVAL;
2419
2420 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2421
2422 smc_state->levels[0].dpm2.MaxPS = 0;
2423 smc_state->levels[0].dpm2.NearTDPDec = 0;
2424 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2425 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2426 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2427
2428 for (i = 1; i < state->performance_level_count; i++) {
2429 prev_sclk = state->performance_levels[i-1].sclk;
2430 max_sclk = state->performance_levels[i].sclk;
2431 if (i == 1)
2432 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2433 else
2434 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2435
2436 if (prev_sclk > max_sclk)
2437 return -EINVAL;
2438
2439 if ((max_ps_percent == 0) ||
2440 (prev_sclk == max_sclk) ||
2441 disable_uvd_power_tune)
2442 min_sclk = max_sclk;
2443 else if (i == 1)
2444 min_sclk = prev_sclk;
2445 else
2446 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2447
2448 if (min_sclk < state->performance_levels[0].sclk)
2449 min_sclk = state->performance_levels[0].sclk;
2450
2451 if (min_sclk == 0)
2452 return -EINVAL;
2453
2454 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2455 state->performance_levels[i-1].vddc, &vddc);
2456 if (ret)
2457 return ret;
2458
2459 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2460 if (ret)
2461 return ret;
2462
2463 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2464 state->performance_levels[i].vddc, &vddc);
2465 if (ret)
2466 return ret;
2467
2468 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2469 if (ret)
2470 return ret;
2471
2472 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2473 prev_std_vddc, curr_std_vddc);
2474
2475 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2476 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2477 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2478 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2479 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2480 }
2481
2482 return 0;
2483 }
2484
si_populate_sq_ramping_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2485 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2486 struct amdgpu_ps *amdgpu_state,
2487 SISLANDS_SMC_SWSTATE *smc_state)
2488 {
2489 struct ni_power_info *ni_pi = ni_get_pi(adev);
2490 struct si_ps *state = si_get_ps(amdgpu_state);
2491 u32 sq_power_throttle, sq_power_throttle2;
2492 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2493 int i;
2494
2495 if (state->performance_level_count == 0)
2496 return -EINVAL;
2497
2498 if (smc_state->levelCount != state->performance_level_count)
2499 return -EINVAL;
2500
2501 if (adev->pm.dpm.sq_ramping_threshold == 0)
2502 return -EINVAL;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT))
2505 enable_sq_ramping = false;
2506
2507 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT))
2508 enable_sq_ramping = false;
2509
2510 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT))
2511 enable_sq_ramping = false;
2512
2513 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT))
2514 enable_sq_ramping = false;
2515
2516 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT))
2517 enable_sq_ramping = false;
2518
2519 for (i = 0; i < state->performance_level_count; i++) {
2520 sq_power_throttle = 0;
2521 sq_power_throttle2 = 0;
2522
2523 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2524 enable_sq_ramping) {
2525 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT;
2526 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT;
2527 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT;
2528 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT;
2529 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT;
2530 } else {
2531 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK |
2532 SQ_POWER_THROTTLE__MIN_POWER_MASK;
2533 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
2534 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
2535 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
2536 }
2537
2538 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2539 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2540 }
2541
2542 return 0;
2543 }
2544
si_enable_power_containment(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2545 static int si_enable_power_containment(struct amdgpu_device *adev,
2546 struct amdgpu_ps *amdgpu_new_state,
2547 bool enable)
2548 {
2549 struct ni_power_info *ni_pi = ni_get_pi(adev);
2550 PPSMC_Result smc_result;
2551 int ret = 0;
2552
2553 if (ni_pi->enable_power_containment) {
2554 if (enable) {
2555 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2556 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2557 if (smc_result != PPSMC_Result_OK)
2558 ret = -EINVAL;
2559 }
2560 } else {
2561 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2562 if (smc_result != PPSMC_Result_OK)
2563 ret = -EINVAL;
2564 }
2565 }
2566
2567 return ret;
2568 }
2569
si_initialize_smc_dte_tables(struct amdgpu_device * adev)2570 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2571 {
2572 struct si_power_info *si_pi = si_get_pi(adev);
2573 int ret = 0;
2574 struct si_dte_data *dte_data = &si_pi->dte_data;
2575 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2576 u32 table_size;
2577 u8 tdep_count;
2578 u32 i;
2579
2580 if (dte_data == NULL)
2581 si_pi->enable_dte = false;
2582
2583 if (si_pi->enable_dte == false)
2584 return 0;
2585
2586 if (dte_data->k <= 0)
2587 return -EINVAL;
2588
2589 dte_tables = kzalloc_obj(Smc_SIslands_DTE_Configuration);
2590 if (dte_tables == NULL) {
2591 si_pi->enable_dte = false;
2592 return -ENOMEM;
2593 }
2594
2595 table_size = dte_data->k;
2596
2597 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2598 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2599
2600 tdep_count = dte_data->tdep_count;
2601 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2602 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2603
2604 dte_tables->K = cpu_to_be32(table_size);
2605 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2606 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2607 dte_tables->WindowSize = dte_data->window_size;
2608 dte_tables->temp_select = dte_data->temp_select;
2609 dte_tables->DTE_mode = dte_data->dte_mode;
2610 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2611
2612 if (tdep_count > 0)
2613 table_size--;
2614
2615 for (i = 0; i < table_size; i++) {
2616 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2617 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2618 }
2619
2620 dte_tables->Tdep_count = tdep_count;
2621
2622 for (i = 0; i < (u32)tdep_count; i++) {
2623 dte_tables->T_limits[i] = dte_data->t_limits[i];
2624 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2625 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2626 }
2627
2628 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2629 (u8 *)dte_tables,
2630 sizeof(Smc_SIslands_DTE_Configuration),
2631 si_pi->sram_end);
2632 kfree(dte_tables);
2633
2634 return ret;
2635 }
2636
si_get_cac_std_voltage_max_min(struct amdgpu_device * adev,u16 * max,u16 * min)2637 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2638 u16 *max, u16 *min)
2639 {
2640 struct si_power_info *si_pi = si_get_pi(adev);
2641 struct amdgpu_cac_leakage_table *table =
2642 &adev->pm.dpm.dyn_state.cac_leakage_table;
2643 u32 i;
2644 u32 v0_loadline;
2645
2646 if (table == NULL)
2647 return -EINVAL;
2648
2649 *max = 0;
2650 *min = 0xFFFF;
2651
2652 for (i = 0; i < table->count; i++) {
2653 if (table->entries[i].vddc > *max)
2654 *max = table->entries[i].vddc;
2655 if (table->entries[i].vddc < *min)
2656 *min = table->entries[i].vddc;
2657 }
2658
2659 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2660 return -EINVAL;
2661
2662 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2663
2664 if (v0_loadline > 0xFFFFUL)
2665 return -EINVAL;
2666
2667 *min = (u16)v0_loadline;
2668
2669 if ((*min > *max) || (*max == 0) || (*min == 0))
2670 return -EINVAL;
2671
2672 return 0;
2673 }
2674
si_get_cac_std_voltage_step(u16 max,u16 min)2675 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2676 {
2677 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2678 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2679 }
2680
si_init_dte_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step,u16 t0,u16 t_step)2681 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2682 PP_SIslands_CacConfig *cac_tables,
2683 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2684 u16 t0, u16 t_step)
2685 {
2686 struct si_power_info *si_pi = si_get_pi(adev);
2687 u32 leakage;
2688 unsigned int i, j;
2689 s32 t;
2690 u32 smc_leakage;
2691 u32 scaling_factor;
2692 u16 voltage;
2693
2694 scaling_factor = si_get_smc_power_scaling_factor(adev);
2695
2696 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2697 t = (1000 * (i * t_step + t0));
2698
2699 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2700 voltage = vddc_max - (vddc_step * j);
2701
2702 si_calculate_leakage_for_v_and_t(adev,
2703 &si_pi->powertune_data->leakage_coefficients,
2704 voltage,
2705 t,
2706 si_pi->dyn_powertune_data.cac_leakage,
2707 &leakage);
2708
2709 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2710
2711 if (smc_leakage > 0xFFFF)
2712 smc_leakage = 0xFFFF;
2713
2714 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2715 cpu_to_be16((u16)smc_leakage);
2716 }
2717 }
2718 return 0;
2719 }
2720
si_init_simplified_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step)2721 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2722 PP_SIslands_CacConfig *cac_tables,
2723 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2724 {
2725 struct si_power_info *si_pi = si_get_pi(adev);
2726 u32 leakage;
2727 unsigned int i, j;
2728 u32 smc_leakage;
2729 u32 scaling_factor;
2730 u16 voltage;
2731
2732 scaling_factor = si_get_smc_power_scaling_factor(adev);
2733
2734 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2735 voltage = vddc_max - (vddc_step * j);
2736
2737 si_calculate_leakage_for_v(adev,
2738 &si_pi->powertune_data->leakage_coefficients,
2739 si_pi->powertune_data->fixed_kt,
2740 voltage,
2741 si_pi->dyn_powertune_data.cac_leakage,
2742 &leakage);
2743
2744 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2745
2746 if (smc_leakage > 0xFFFF)
2747 smc_leakage = 0xFFFF;
2748
2749 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2750 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2751 cpu_to_be16((u16)smc_leakage);
2752 }
2753 return 0;
2754 }
2755
si_initialize_smc_cac_tables(struct amdgpu_device * adev)2756 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2757 {
2758 struct ni_power_info *ni_pi = ni_get_pi(adev);
2759 struct si_power_info *si_pi = si_get_pi(adev);
2760 PP_SIslands_CacConfig *cac_tables = NULL;
2761 u16 vddc_max, vddc_min, vddc_step;
2762 u16 t0, t_step;
2763 u32 load_line_slope, reg;
2764 int ret = 0;
2765 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2766
2767 if (ni_pi->enable_cac == false)
2768 return 0;
2769
2770 cac_tables = kzalloc_obj(PP_SIslands_CacConfig);
2771 if (!cac_tables)
2772 return -ENOMEM;
2773
2774 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;
2775 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT);
2776 WREG32(mmCG_CAC_CTRL, reg);
2777
2778 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2779 si_pi->dyn_powertune_data.dc_pwr_value =
2780 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2781 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2782 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2783
2784 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2785
2786 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2787 if (ret)
2788 goto done_free;
2789
2790 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2791 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2792 t_step = 4;
2793 t0 = 60;
2794
2795 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2796 ret = si_init_dte_leakage_table(adev, cac_tables,
2797 vddc_max, vddc_min, vddc_step,
2798 t0, t_step);
2799 else
2800 ret = si_init_simplified_leakage_table(adev, cac_tables,
2801 vddc_max, vddc_min, vddc_step);
2802 if (ret)
2803 goto done_free;
2804
2805 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2806
2807 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2808 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2809 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2810 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2811 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2812 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2813 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2814 cac_tables->calculation_repeats = cpu_to_be32(2);
2815 cac_tables->dc_cac = cpu_to_be32(0);
2816 cac_tables->log2_PG_LKG_SCALE = 12;
2817 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2818 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2819 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2820
2821 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2822 (u8 *)cac_tables,
2823 sizeof(PP_SIslands_CacConfig),
2824 si_pi->sram_end);
2825
2826 if (ret)
2827 goto done_free;
2828
2829 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2830
2831 done_free:
2832 if (ret) {
2833 ni_pi->enable_cac = false;
2834 ni_pi->enable_power_containment = false;
2835 }
2836
2837 kfree(cac_tables);
2838
2839 return ret;
2840 }
2841
si_program_cac_config_registers(struct amdgpu_device * adev,const struct si_cac_config_reg * cac_config_regs)2842 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2843 const struct si_cac_config_reg *cac_config_regs)
2844 {
2845 const struct si_cac_config_reg *config_regs = cac_config_regs;
2846 u32 data = 0, offset;
2847
2848 if (!config_regs)
2849 return -EINVAL;
2850
2851 while (config_regs->offset != 0xFFFFFFFF) {
2852 switch (config_regs->type) {
2853 case SISLANDS_CACCONFIG_CGIND:
2854 offset = SMC_CG_IND_START + config_regs->offset;
2855 if (offset < SMC_CG_IND_END)
2856 data = RREG32_SMC(offset);
2857 break;
2858 default:
2859 data = RREG32(config_regs->offset);
2860 break;
2861 }
2862
2863 data &= ~config_regs->mask;
2864 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2865
2866 switch (config_regs->type) {
2867 case SISLANDS_CACCONFIG_CGIND:
2868 offset = SMC_CG_IND_START + config_regs->offset;
2869 if (offset < SMC_CG_IND_END)
2870 WREG32_SMC(offset, data);
2871 break;
2872 default:
2873 WREG32(config_regs->offset, data);
2874 break;
2875 }
2876 config_regs++;
2877 }
2878 return 0;
2879 }
2880
si_initialize_hardware_cac_manager(struct amdgpu_device * adev)2881 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2882 {
2883 struct ni_power_info *ni_pi = ni_get_pi(adev);
2884 struct si_power_info *si_pi = si_get_pi(adev);
2885 int ret;
2886
2887 if ((ni_pi->enable_cac == false) ||
2888 (ni_pi->cac_configuration_required == false))
2889 return 0;
2890
2891 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2892 if (ret)
2893 return ret;
2894 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2895 if (ret)
2896 return ret;
2897 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2898 if (ret)
2899 return ret;
2900
2901 return 0;
2902 }
2903
si_enable_smc_cac(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2904 static int si_enable_smc_cac(struct amdgpu_device *adev,
2905 struct amdgpu_ps *amdgpu_new_state,
2906 bool enable)
2907 {
2908 struct ni_power_info *ni_pi = ni_get_pi(adev);
2909 struct si_power_info *si_pi = si_get_pi(adev);
2910 PPSMC_Result smc_result;
2911 int ret = 0;
2912
2913 if (ni_pi->enable_cac) {
2914 if (enable) {
2915 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2916 if (ni_pi->support_cac_long_term_average) {
2917 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2918 if (smc_result != PPSMC_Result_OK)
2919 ni_pi->support_cac_long_term_average = false;
2920 }
2921
2922 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2923 if (smc_result != PPSMC_Result_OK) {
2924 ret = -EINVAL;
2925 ni_pi->cac_enabled = false;
2926 } else {
2927 ni_pi->cac_enabled = true;
2928 }
2929
2930 if (si_pi->enable_dte) {
2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2932 if (smc_result != PPSMC_Result_OK)
2933 ret = -EINVAL;
2934 }
2935 }
2936 } else if (ni_pi->cac_enabled) {
2937 if (si_pi->enable_dte)
2938 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2939
2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2941
2942 ni_pi->cac_enabled = false;
2943
2944 if (ni_pi->support_cac_long_term_average)
2945 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2946 }
2947 }
2948 return ret;
2949 }
2950
si_init_smc_spll_table(struct amdgpu_device * adev)2951 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2952 {
2953 struct ni_power_info *ni_pi = ni_get_pi(adev);
2954 struct si_power_info *si_pi = si_get_pi(adev);
2955 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2956 SISLANDS_SMC_SCLK_VALUE sclk_params;
2957 u32 fb_div, p_div;
2958 u32 clk_s, clk_v;
2959 u32 sclk = 0;
2960 int ret = 0;
2961 u32 tmp;
2962 int i;
2963
2964 if (si_pi->spll_table_start == 0)
2965 return -EINVAL;
2966
2967 spll_table = kzalloc_obj(SMC_SISLANDS_SPLL_DIV_TABLE);
2968 if (spll_table == NULL)
2969 return -ENOMEM;
2970
2971 for (i = 0; i < 256; i++) {
2972 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2973 if (ret)
2974 break;
2975 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
2977 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
2978 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
2979
2980 fb_div &= ~0x00001FFF;
2981 fb_div >>= 1;
2982 clk_v >>= 6;
2983
2984 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2985 ret = -EINVAL;
2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2987 ret = -EINVAL;
2988 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2989 ret = -EINVAL;
2990 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2991 ret = -EINVAL;
2992
2993 if (ret)
2994 break;
2995
2996 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2997 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2998 spll_table->freq[i] = cpu_to_be32(tmp);
2999
3000 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
3001 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
3002 spll_table->ss[i] = cpu_to_be32(tmp);
3003
3004 sclk += 512;
3005 }
3006
3007
3008 if (!ret)
3009 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3010 (u8 *)spll_table,
3011 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3012 si_pi->sram_end);
3013
3014 if (ret)
3015 ni_pi->enable_power_containment = false;
3016
3017 kfree(spll_table);
3018
3019 return ret;
3020 }
3021
si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device * adev,u16 vce_voltage)3022 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3023 u16 vce_voltage)
3024 {
3025 u16 highest_leakage = 0;
3026 struct si_power_info *si_pi = si_get_pi(adev);
3027 int i;
3028
3029 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3030 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3031 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3032 }
3033
3034 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3035 return highest_leakage;
3036
3037 return vce_voltage;
3038 }
3039
si_get_vce_clock_voltage(struct amdgpu_device * adev,u32 evclk,u32 ecclk,u16 * voltage)3040 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3041 u32 evclk, u32 ecclk, u16 *voltage)
3042 {
3043 u32 i;
3044 int ret = -EINVAL;
3045 struct amdgpu_vce_clock_voltage_dependency_table *table =
3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3047
3048 if (((evclk == 0) && (ecclk == 0)) ||
3049 (table && (table->count == 0))) {
3050 *voltage = 0;
3051 return 0;
3052 }
3053
3054 for (i = 0; i < table->count; i++) {
3055 if ((evclk <= table->entries[i].evclk) &&
3056 (ecclk <= table->entries[i].ecclk)) {
3057 *voltage = table->entries[i].v;
3058 ret = 0;
3059 break;
3060 }
3061 }
3062
3063 /* if no match return the highest voltage */
3064 if (ret)
3065 *voltage = table->entries[table->count - 1].v;
3066
3067 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3068
3069 return ret;
3070 }
3071
si_dpm_vblank_too_short(void * handle)3072 static bool si_dpm_vblank_too_short(void *handle)
3073 {
3074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3075 u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time;
3076 /* we never hit the non-gddr5 limit so disable it */
3077 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3078
3079 /* Disregard vblank time when there are no displays connected */
3080 if (!adev->pm.pm_display_cfg.num_display)
3081 return false;
3082
3083 /* Consider zero vblank time too short and disable MCLK switching.
3084 * Note that the vblank time is set to maximum when no displays are attached,
3085 * so we'll still enable MCLK switching in that case.
3086 */
3087 if (vblank_time == 0)
3088 return true;
3089 else if (vblank_time < switch_limit)
3090 return true;
3091 else
3092 return false;
3093
3094 }
3095
ni_copy_and_switch_arb_sets(struct amdgpu_device * adev,u32 arb_freq_src,u32 arb_freq_dest)3096 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3097 u32 arb_freq_src, u32 arb_freq_dest)
3098 {
3099 u32 mc_arb_dram_timing;
3100 u32 mc_arb_dram_timing2;
3101 u32 burst_time;
3102 u32 mc_cg_config;
3103
3104 switch (arb_freq_src) {
3105 case MC_CG_ARB_FREQ_F0:
3106 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3107 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3108 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3109 break;
3110 case MC_CG_ARB_FREQ_F1:
3111 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3113 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3114 break;
3115 case MC_CG_ARB_FREQ_F2:
3116 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3117 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3118 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3119 break;
3120 case MC_CG_ARB_FREQ_F3:
3121 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3122 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3123 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3124 break;
3125 default:
3126 return -EINVAL;
3127 }
3128
3129 switch (arb_freq_dest) {
3130 case MC_CG_ARB_FREQ_F0:
3131 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3132 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3133 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3134 break;
3135 case MC_CG_ARB_FREQ_F1:
3136 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3137 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3138 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3139 break;
3140 case MC_CG_ARB_FREQ_F2:
3141 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3142 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3143 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3144 break;
3145 case MC_CG_ARB_FREQ_F3:
3146 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3147 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3148 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3149 break;
3150 default:
3151 return -EINVAL;
3152 }
3153
3154 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3155 WREG32(MC_CG_CONFIG, mc_cg_config);
3156 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3157
3158 return 0;
3159 }
3160
ni_update_current_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3161 static void ni_update_current_ps(struct amdgpu_device *adev,
3162 struct amdgpu_ps *rps)
3163 {
3164 struct si_ps *new_ps = si_get_ps(rps);
3165 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3166 struct ni_power_info *ni_pi = ni_get_pi(adev);
3167
3168 eg_pi->current_rps = *rps;
3169 ni_pi->current_ps = *new_ps;
3170 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3171 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3172 }
3173
ni_update_requested_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3174 static void ni_update_requested_ps(struct amdgpu_device *adev,
3175 struct amdgpu_ps *rps)
3176 {
3177 struct si_ps *new_ps = si_get_ps(rps);
3178 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3179 struct ni_power_info *ni_pi = ni_get_pi(adev);
3180
3181 eg_pi->requested_rps = *rps;
3182 ni_pi->requested_ps = *new_ps;
3183 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3184 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3185 }
3186
ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3187 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3188 struct amdgpu_ps *new_ps,
3189 struct amdgpu_ps *old_ps)
3190 {
3191 struct si_ps *new_state = si_get_ps(new_ps);
3192 struct si_ps *current_state = si_get_ps(old_ps);
3193
3194 if ((new_ps->vclk == old_ps->vclk) &&
3195 (new_ps->dclk == old_ps->dclk))
3196 return;
3197
3198 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3199 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3200 return;
3201
3202 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3203 }
3204
ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3205 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3206 struct amdgpu_ps *new_ps,
3207 struct amdgpu_ps *old_ps)
3208 {
3209 struct si_ps *new_state = si_get_ps(new_ps);
3210 struct si_ps *current_state = si_get_ps(old_ps);
3211
3212 if ((new_ps->vclk == old_ps->vclk) &&
3213 (new_ps->dclk == old_ps->dclk))
3214 return;
3215
3216 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3217 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3218 return;
3219
3220 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3221 }
3222
btc_find_voltage(struct atom_voltage_table * table,u16 voltage)3223 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3224 {
3225 unsigned int i;
3226
3227 for (i = 0; i < table->count; i++)
3228 if (voltage <= table->entries[i].value)
3229 return table->entries[i].value;
3230
3231 return table->entries[table->count - 1].value;
3232 }
3233
btc_find_valid_clock(struct amdgpu_clock_array * clocks,u32 max_clock,u32 requested_clock)3234 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3235 u32 max_clock, u32 requested_clock)
3236 {
3237 unsigned int i;
3238
3239 if ((clocks == NULL) || (clocks->count == 0))
3240 return (requested_clock < max_clock) ? requested_clock : max_clock;
3241
3242 for (i = 0; i < clocks->count; i++) {
3243 if (clocks->values[i] >= requested_clock)
3244 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3245 }
3246
3247 return (clocks->values[clocks->count - 1] < max_clock) ?
3248 clocks->values[clocks->count - 1] : max_clock;
3249 }
3250
btc_get_valid_mclk(struct amdgpu_device * adev,u32 max_mclk,u32 requested_mclk)3251 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3252 u32 max_mclk, u32 requested_mclk)
3253 {
3254 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3255 max_mclk, requested_mclk);
3256 }
3257
btc_get_valid_sclk(struct amdgpu_device * adev,u32 max_sclk,u32 requested_sclk)3258 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3259 u32 max_sclk, u32 requested_sclk)
3260 {
3261 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3262 max_sclk, requested_sclk);
3263 }
3264
btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table * table,u32 * max_clock)3265 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3266 u32 *max_clock)
3267 {
3268 u32 i, clock = 0;
3269
3270 if ((table == NULL) || (table->count == 0)) {
3271 *max_clock = clock;
3272 return;
3273 }
3274
3275 for (i = 0; i < table->count; i++) {
3276 if (clock < table->entries[i].clk)
3277 clock = table->entries[i].clk;
3278 }
3279 *max_clock = clock;
3280 }
3281
btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table * table,u32 clock,u16 max_voltage,u16 * voltage)3282 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3283 u32 clock, u16 max_voltage, u16 *voltage)
3284 {
3285 u32 i;
3286
3287 if ((table == NULL) || (table->count == 0))
3288 return;
3289
3290 for (i= 0; i < table->count; i++) {
3291 if (clock <= table->entries[i].clk) {
3292 if (*voltage < table->entries[i].v)
3293 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3294 table->entries[i].v : max_voltage);
3295 return;
3296 }
3297 }
3298
3299 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3300 }
3301
btc_adjust_clock_combinations(struct amdgpu_device * adev,const struct amdgpu_clock_and_voltage_limits * max_limits,struct rv7xx_pl * pl)3302 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3303 const struct amdgpu_clock_and_voltage_limits *max_limits,
3304 struct rv7xx_pl *pl)
3305 {
3306
3307 if ((pl->mclk == 0) || (pl->sclk == 0))
3308 return;
3309
3310 if (pl->mclk == pl->sclk)
3311 return;
3312
3313 if (pl->mclk > pl->sclk) {
3314 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3315 pl->sclk = btc_get_valid_sclk(adev,
3316 max_limits->sclk,
3317 (pl->mclk +
3318 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3319 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3320 } else {
3321 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3322 pl->mclk = btc_get_valid_mclk(adev,
3323 max_limits->mclk,
3324 pl->sclk -
3325 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3326 }
3327 }
3328
btc_apply_voltage_delta_rules(struct amdgpu_device * adev,u16 max_vddc,u16 max_vddci,u16 * vddc,u16 * vddci)3329 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3330 u16 max_vddc, u16 max_vddci,
3331 u16 *vddc, u16 *vddci)
3332 {
3333 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3334 u16 new_voltage;
3335
3336 if ((0 == *vddc) || (0 == *vddci))
3337 return;
3338
3339 if (*vddc > *vddci) {
3340 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3341 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3342 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3343 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3344 }
3345 } else {
3346 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3347 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3348 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3349 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3350 }
3351 }
3352 }
3353
r600_calculate_u_and_p(u32 i,u32 r_c,u32 p_b,u32 * p,u32 * u)3354 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3355 u32 *p, u32 *u)
3356 {
3357 u32 b_c = 0;
3358 u32 i_c;
3359 u32 tmp;
3360
3361 i_c = (i * r_c) / 100;
3362 tmp = i_c >> p_b;
3363
3364 while (tmp) {
3365 b_c++;
3366 tmp >>= 1;
3367 }
3368
3369 *u = (b_c + 1) / 2;
3370 *p = i_c / (1 << (2 * (*u)));
3371 }
3372
r600_calculate_at(u32 t,u32 h,u32 fh,u32 fl,u32 * tl,u32 * th)3373 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3374 {
3375 u32 k, a, ah, al;
3376 u32 t1;
3377
3378 if ((fl == 0) || (fh == 0) || (fl > fh))
3379 return -EINVAL;
3380
3381 k = (100 * fh) / fl;
3382 t1 = (t * (k - 100));
3383 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3384 a = (a + 5) / 10;
3385 ah = ((a * t) + 5000) / 10000;
3386 al = a - ah;
3387
3388 *th = t - ah;
3389 *tl = t + al;
3390
3391 return 0;
3392 }
3393
r600_is_uvd_state(u32 class,u32 class2)3394 static bool r600_is_uvd_state(u32 class, u32 class2)
3395 {
3396 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3397 return true;
3398 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3399 return true;
3400 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3401 return true;
3402 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3403 return true;
3404 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3405 return true;
3406 return false;
3407 }
3408
rv770_get_memory_module_index(struct amdgpu_device * adev)3409 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3410 {
3411 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3412 }
3413
rv770_get_max_vddc(struct amdgpu_device * adev)3414 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3415 {
3416 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3417 u16 vddc;
3418
3419 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3420 pi->max_vddc = 0;
3421 else
3422 pi->max_vddc = vddc;
3423 }
3424
rv770_get_engine_memory_ss(struct amdgpu_device * adev)3425 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3426 {
3427 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3428 struct amdgpu_atom_ss ss;
3429
3430 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3431 ASIC_INTERNAL_ENGINE_SS, 0);
3432 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3433 ASIC_INTERNAL_MEMORY_SS, 0);
3434
3435 if (pi->sclk_ss || pi->mclk_ss)
3436 pi->dynamic_ss = true;
3437 else
3438 pi->dynamic_ss = false;
3439 }
3440
3441
si_apply_state_adjust_rules(struct amdgpu_device * adev,struct amdgpu_ps * rps)3442 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3443 struct amdgpu_ps *rps)
3444 {
3445 const struct amd_pp_display_configuration *display_cfg =
3446 &adev->pm.pm_display_cfg;
3447 struct si_ps *ps = si_get_ps(rps);
3448 struct amdgpu_clock_and_voltage_limits *max_limits;
3449 bool disable_mclk_switching = false;
3450 bool disable_sclk_switching = false;
3451 u32 mclk, sclk;
3452 u16 vddc, vddci, min_vce_voltage = 0;
3453 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3454 u32 max_sclk = 0, max_mclk = 0;
3455 u32 high_pixelclock_count = 0;
3456 int i;
3457
3458 if (adev->asic_type == CHIP_HAINAN) {
3459 if ((adev->pdev->revision == 0x81) ||
3460 (adev->pdev->revision == 0xC3) ||
3461 (adev->pdev->device == 0x6660) ||
3462 (adev->pdev->device == 0x6664) ||
3463 (adev->pdev->device == 0x6665) ||
3464 (adev->pdev->device == 0x6667) ||
3465 (adev->pdev->device == 0x666F)) {
3466 max_sclk = 75000;
3467 }
3468 if ((adev->pdev->revision == 0xC3) ||
3469 (adev->pdev->device == 0x6665)) {
3470 max_sclk = 60000;
3471 max_mclk = 80000;
3472 }
3473 if ((adev->pdev->device == 0x666f) &&
3474 (adev->pdev->revision == 0x00)) {
3475 max_sclk = 80000;
3476 max_mclk = 95000;
3477 }
3478 } else if (adev->asic_type == CHIP_OLAND) {
3479 if ((adev->pdev->revision == 0xC7) ||
3480 (adev->pdev->revision == 0x80) ||
3481 (adev->pdev->revision == 0x81) ||
3482 (adev->pdev->revision == 0x83) ||
3483 (adev->pdev->revision == 0x87 &&
3484 adev->pdev->device != 0x6611) ||
3485 (adev->pdev->device == 0x6604) ||
3486 (adev->pdev->device == 0x6605)) {
3487 max_sclk = 75000;
3488 } else if (adev->pdev->revision == 0x87 &&
3489 adev->pdev->device == 0x6611) {
3490 /* Radeon 430 and 520 */
3491 max_sclk = 78000;
3492 }
3493 }
3494
3495 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz.
3496 * For example, 4K 60Hz and 1080p 144Hz fall into this category.
3497 * Find number of such displays connected.
3498 */
3499 for (i = 0; i < display_cfg->num_display; i++) {
3500 /* The array only contains active displays. */
3501 if (display_cfg->displays[i].pixel_clock > 297000)
3502 high_pixelclock_count++;
3503 }
3504
3505 /* These are some ad-hoc fixes to some issues observed with SI GPUs.
3506 * They are necessary because we don't have something like dce_calcs
3507 * for these GPUs to calculate bandwidth requirements.
3508 */
3509 if (high_pixelclock_count) {
3510 /* Work around flickering lines at the bottom edge
3511 * of the screen when using a single 4K 60Hz monitor.
3512 */
3513 disable_mclk_switching = true;
3514
3515 /* On Oland, we observe some flickering when two 4K 60Hz
3516 * displays are connected, possibly because voltage is too low.
3517 * Raise the voltage by requiring a higher SCLK.
3518 * (Voltage cannot be adjusted independently without also SCLK.)
3519 */
3520 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND)
3521 disable_sclk_switching = true;
3522 }
3523
3524 if (rps->vce_active) {
3525 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3526 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3527 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3528 &min_vce_voltage);
3529 } else {
3530 rps->evclk = 0;
3531 rps->ecclk = 0;
3532 }
3533
3534 if ((adev->pm.pm_display_cfg.num_display > 1) ||
3535 si_dpm_vblank_too_short(adev))
3536 disable_mclk_switching = true;
3537
3538 if (rps->vclk || rps->dclk) {
3539 disable_mclk_switching = true;
3540 disable_sclk_switching = true;
3541 }
3542
3543 if (adev->pm.ac_power)
3544 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3545 else
3546 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3547
3548 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3549 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3550 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3551 }
3552 if (adev->pm.ac_power == false) {
3553 for (i = 0; i < ps->performance_level_count; i++) {
3554 if (ps->performance_levels[i].mclk > max_limits->mclk)
3555 ps->performance_levels[i].mclk = max_limits->mclk;
3556 if (ps->performance_levels[i].sclk > max_limits->sclk)
3557 ps->performance_levels[i].sclk = max_limits->sclk;
3558 if (ps->performance_levels[i].vddc > max_limits->vddc)
3559 ps->performance_levels[i].vddc = max_limits->vddc;
3560 if (ps->performance_levels[i].vddci > max_limits->vddci)
3561 ps->performance_levels[i].vddci = max_limits->vddci;
3562 }
3563 }
3564
3565 /* limit clocks to max supported clocks based on voltage dependency tables */
3566 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3567 &max_sclk_vddc);
3568 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3569 &max_mclk_vddci);
3570 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3571 &max_mclk_vddc);
3572
3573 for (i = 0; i < ps->performance_level_count; i++) {
3574 if (max_sclk_vddc) {
3575 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3576 ps->performance_levels[i].sclk = max_sclk_vddc;
3577 }
3578 if (max_mclk_vddci) {
3579 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3580 ps->performance_levels[i].mclk = max_mclk_vddci;
3581 }
3582 if (max_mclk_vddc) {
3583 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3584 ps->performance_levels[i].mclk = max_mclk_vddc;
3585 }
3586 if (max_mclk) {
3587 if (ps->performance_levels[i].mclk > max_mclk)
3588 ps->performance_levels[i].mclk = max_mclk;
3589 }
3590 if (max_sclk) {
3591 if (ps->performance_levels[i].sclk > max_sclk)
3592 ps->performance_levels[i].sclk = max_sclk;
3593 }
3594 }
3595
3596 /* XXX validate the min clocks required for display */
3597
3598 if (disable_mclk_switching) {
3599 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3600 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3601 } else {
3602 mclk = ps->performance_levels[0].mclk;
3603 vddci = ps->performance_levels[0].vddci;
3604 }
3605
3606 if (disable_sclk_switching) {
3607 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3608 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3609 } else {
3610 sclk = ps->performance_levels[0].sclk;
3611 vddc = ps->performance_levels[0].vddc;
3612 }
3613
3614 if (rps->vce_active) {
3615 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3616 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3617 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3618 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3619 }
3620
3621 /* adjusted low state */
3622 ps->performance_levels[0].sclk = sclk;
3623 ps->performance_levels[0].mclk = mclk;
3624 ps->performance_levels[0].vddc = vddc;
3625 ps->performance_levels[0].vddci = vddci;
3626
3627 if (disable_sclk_switching) {
3628 sclk = ps->performance_levels[0].sclk;
3629 for (i = 1; i < ps->performance_level_count; i++) {
3630 if (sclk < ps->performance_levels[i].sclk)
3631 sclk = ps->performance_levels[i].sclk;
3632 }
3633 for (i = 0; i < ps->performance_level_count; i++) {
3634 ps->performance_levels[i].sclk = sclk;
3635 ps->performance_levels[i].vddc = vddc;
3636 }
3637 } else {
3638 for (i = 1; i < ps->performance_level_count; i++) {
3639 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3640 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3641 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3642 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3643 }
3644 }
3645
3646 if (disable_mclk_switching) {
3647 mclk = ps->performance_levels[0].mclk;
3648 for (i = 1; i < ps->performance_level_count; i++) {
3649 if (mclk < ps->performance_levels[i].mclk)
3650 mclk = ps->performance_levels[i].mclk;
3651 }
3652 for (i = 0; i < ps->performance_level_count; i++) {
3653 ps->performance_levels[i].mclk = mclk;
3654 ps->performance_levels[i].vddci = vddci;
3655 }
3656 } else {
3657 for (i = 1; i < ps->performance_level_count; i++) {
3658 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3659 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3660 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3661 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3662 }
3663 }
3664
3665 for (i = 0; i < ps->performance_level_count; i++)
3666 btc_adjust_clock_combinations(adev, max_limits,
3667 &ps->performance_levels[i]);
3668
3669 for (i = 0; i < ps->performance_level_count; i++) {
3670 if (ps->performance_levels[i].vddc < min_vce_voltage)
3671 ps->performance_levels[i].vddc = min_vce_voltage;
3672 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3673 ps->performance_levels[i].sclk,
3674 max_limits->vddc, &ps->performance_levels[i].vddc);
3675 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3676 ps->performance_levels[i].mclk,
3677 max_limits->vddci, &ps->performance_levels[i].vddci);
3678 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3679 ps->performance_levels[i].mclk,
3680 max_limits->vddc, &ps->performance_levels[i].vddc);
3681 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3682 display_cfg->display_clk,
3683 max_limits->vddc, &ps->performance_levels[i].vddc);
3684 }
3685
3686 for (i = 0; i < ps->performance_level_count; i++) {
3687 btc_apply_voltage_delta_rules(adev,
3688 max_limits->vddc, max_limits->vddci,
3689 &ps->performance_levels[i].vddc,
3690 &ps->performance_levels[i].vddci);
3691 }
3692
3693 ps->dc_compatible = true;
3694 for (i = 0; i < ps->performance_level_count; i++) {
3695 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3696 ps->dc_compatible = false;
3697 }
3698 }
3699
3700 #if 0
3701 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3702 u16 reg_offset, u32 *value)
3703 {
3704 struct si_power_info *si_pi = si_get_pi(adev);
3705
3706 return amdgpu_si_read_smc_sram_dword(adev,
3707 si_pi->soft_regs_start + reg_offset, value,
3708 si_pi->sram_end);
3709 }
3710 #endif
3711
si_write_smc_soft_register(struct amdgpu_device * adev,u16 reg_offset,u32 value)3712 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3713 u16 reg_offset, u32 value)
3714 {
3715 struct si_power_info *si_pi = si_get_pi(adev);
3716
3717 return amdgpu_si_write_smc_sram_dword(adev,
3718 si_pi->soft_regs_start + reg_offset,
3719 value, si_pi->sram_end);
3720 }
3721
si_is_special_1gb_platform(struct amdgpu_device * adev)3722 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3723 {
3724 bool ret = false;
3725 u32 tmp, width, row, column, bank, density;
3726 bool is_memory_gddr5, is_special;
3727
3728 tmp = RREG32(MC_SEQ_MISC0);
3729 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3730 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3731 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3732
3733 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3734 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3735
3736 tmp = RREG32(mmMC_ARB_RAMCFG);
3737 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10;
3738 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8;
3739 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2;
3740
3741 density = (1 << (row + column - 20 + bank)) * width;
3742
3743 if ((adev->pdev->device == 0x6819) &&
3744 is_memory_gddr5 && is_special && (density == 0x400))
3745 ret = true;
3746
3747 return ret;
3748 }
3749
si_get_leakage_vddc(struct amdgpu_device * adev)3750 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3751 {
3752 struct si_power_info *si_pi = si_get_pi(adev);
3753 u16 vddc, count = 0;
3754 int i, ret;
3755
3756 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3757 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3758
3759 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3760 si_pi->leakage_voltage.entries[count].voltage = vddc;
3761 si_pi->leakage_voltage.entries[count].leakage_index =
3762 SISLANDS_LEAKAGE_INDEX0 + i;
3763 count++;
3764 }
3765 }
3766 si_pi->leakage_voltage.count = count;
3767 }
3768
si_get_leakage_voltage_from_leakage_index(struct amdgpu_device * adev,u32 index,u16 * leakage_voltage)3769 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3770 u32 index, u16 *leakage_voltage)
3771 {
3772 struct si_power_info *si_pi = si_get_pi(adev);
3773 int i;
3774
3775 if (leakage_voltage == NULL)
3776 return -EINVAL;
3777
3778 if ((index & 0xff00) != 0xff00)
3779 return -EINVAL;
3780
3781 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3782 return -EINVAL;
3783
3784 if (index < SISLANDS_LEAKAGE_INDEX0)
3785 return -EINVAL;
3786
3787 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3788 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3789 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3790 return 0;
3791 }
3792 }
3793 return -EAGAIN;
3794 }
3795
si_set_dpm_event_sources(struct amdgpu_device * adev,u32 sources)3796 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3797 {
3798 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3799 bool want_thermal_protection;
3800 enum si_dpm_event_src dpm_event_src;
3801
3802 switch (sources) {
3803 case 0:
3804 default:
3805 want_thermal_protection = false;
3806 break;
3807 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL):
3808 want_thermal_protection = true;
3809 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL;
3810 break;
3811 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3812 want_thermal_protection = true;
3813 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL;
3814 break;
3815 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3816 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3817 want_thermal_protection = true;
3818 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3819 break;
3820 }
3821
3822 if (want_thermal_protection) {
3823 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK);
3824 if (pi->thermal_protection)
3825 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3826 } else {
3827 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3828 }
3829 }
3830
si_enable_auto_throttle_source(struct amdgpu_device * adev,enum si_dpm_auto_throttle_src source,bool enable)3831 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3832 enum si_dpm_auto_throttle_src source,
3833 bool enable)
3834 {
3835 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3836
3837 if (enable) {
3838 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3839 pi->active_auto_throttle_sources |= 1 << source;
3840 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3841 }
3842 } else {
3843 if (pi->active_auto_throttle_sources & (1 << source)) {
3844 pi->active_auto_throttle_sources &= ~(1 << source);
3845 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3846 }
3847 }
3848 }
3849
si_start_dpm(struct amdgpu_device * adev)3850 static void si_start_dpm(struct amdgpu_device *adev)
3851 {
3852 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3853 }
3854
si_stop_dpm(struct amdgpu_device * adev)3855 static void si_stop_dpm(struct amdgpu_device *adev)
3856 {
3857 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3858 }
3859
si_enable_sclk_control(struct amdgpu_device * adev,bool enable)3860 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3861 {
3862 if (enable)
3863 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3864 else
3865 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3866
3867 }
3868
3869 #if 0
3870 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3871 u32 thermal_level)
3872 {
3873 PPSMC_Result ret;
3874
3875 if (thermal_level == 0) {
3876 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3877 if (ret == PPSMC_Result_OK)
3878 return 0;
3879 else
3880 return -EINVAL;
3881 }
3882 return 0;
3883 }
3884
3885 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3886 {
3887 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3888 }
3889 #endif
3890
3891 #if 0
3892 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3893 {
3894 if (ac_power)
3895 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3896 0 : -EINVAL;
3897
3898 return 0;
3899 }
3900 #endif
3901
si_send_msg_to_smc_with_parameter(struct amdgpu_device * adev,PPSMC_Msg msg,u32 parameter)3902 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3903 PPSMC_Msg msg, u32 parameter)
3904 {
3905 WREG32(mmSMC_SCRATCH0, parameter);
3906 return amdgpu_si_send_msg_to_smc(adev, msg);
3907 }
3908
si_restrict_performance_levels_before_switch(struct amdgpu_device * adev)3909 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3910 {
3911 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3912 return -EINVAL;
3913
3914 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3915 0 : -EINVAL;
3916 }
3917
si_dpm_force_performance_level(void * handle,enum amd_dpm_forced_level level)3918 static int si_dpm_force_performance_level(void *handle,
3919 enum amd_dpm_forced_level level)
3920 {
3921 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3922 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3923 struct si_ps *ps = si_get_ps(rps);
3924 u32 levels = ps->performance_level_count;
3925
3926 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3927 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3928 return -EINVAL;
3929
3930 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3931 return -EINVAL;
3932 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3933 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3934 return -EINVAL;
3935
3936 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3937 return -EINVAL;
3938 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3939 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3940 return -EINVAL;
3941
3942 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3943 return -EINVAL;
3944 }
3945
3946 adev->pm.dpm.forced_level = level;
3947
3948 return 0;
3949 }
3950
3951 #if 0
3952 static int si_set_boot_state(struct amdgpu_device *adev)
3953 {
3954 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3955 0 : -EINVAL;
3956 }
3957 #endif
3958
si_set_sw_state(struct amdgpu_device * adev)3959 static int si_set_sw_state(struct amdgpu_device *adev)
3960 {
3961 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3962 0 : -EINVAL;
3963 }
3964
si_halt_smc(struct amdgpu_device * adev)3965 static int si_halt_smc(struct amdgpu_device *adev)
3966 {
3967 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3968 return -EINVAL;
3969
3970 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3971 0 : -EINVAL;
3972 }
3973
si_resume_smc(struct amdgpu_device * adev)3974 static int si_resume_smc(struct amdgpu_device *adev)
3975 {
3976 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3977 return -EINVAL;
3978
3979 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3980 0 : -EINVAL;
3981 }
3982
si_dpm_start_smc(struct amdgpu_device * adev)3983 static void si_dpm_start_smc(struct amdgpu_device *adev)
3984 {
3985 amdgpu_si_program_jump_on_start(adev);
3986 amdgpu_si_start_smc(adev);
3987 amdgpu_si_smc_clock(adev, true);
3988 }
3989
si_dpm_stop_smc(struct amdgpu_device * adev)3990 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3991 {
3992 amdgpu_si_reset_smc(adev);
3993 amdgpu_si_smc_clock(adev, false);
3994 }
3995
si_process_firmware_header(struct amdgpu_device * adev)3996 static int si_process_firmware_header(struct amdgpu_device *adev)
3997 {
3998 struct si_power_info *si_pi = si_get_pi(adev);
3999 u32 tmp;
4000 int ret;
4001
4002 ret = amdgpu_si_read_smc_sram_dword(adev,
4003 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4004 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
4005 &tmp, si_pi->sram_end);
4006 if (ret)
4007 return ret;
4008
4009 si_pi->state_table_start = tmp;
4010
4011 ret = amdgpu_si_read_smc_sram_dword(adev,
4012 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4013 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4014 &tmp, si_pi->sram_end);
4015 if (ret)
4016 return ret;
4017
4018 si_pi->soft_regs_start = tmp;
4019
4020 ret = amdgpu_si_read_smc_sram_dword(adev,
4021 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4022 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4023 &tmp, si_pi->sram_end);
4024 if (ret)
4025 return ret;
4026
4027 si_pi->mc_reg_table_start = tmp;
4028
4029 ret = amdgpu_si_read_smc_sram_dword(adev,
4030 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4031 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4032 &tmp, si_pi->sram_end);
4033 if (ret)
4034 return ret;
4035
4036 si_pi->fan_table_start = tmp;
4037
4038 ret = amdgpu_si_read_smc_sram_dword(adev,
4039 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4040 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4041 &tmp, si_pi->sram_end);
4042 if (ret)
4043 return ret;
4044
4045 si_pi->arb_table_start = tmp;
4046
4047 ret = amdgpu_si_read_smc_sram_dword(adev,
4048 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4049 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4050 &tmp, si_pi->sram_end);
4051 if (ret)
4052 return ret;
4053
4054 si_pi->cac_table_start = tmp;
4055
4056 ret = amdgpu_si_read_smc_sram_dword(adev,
4057 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4058 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4059 &tmp, si_pi->sram_end);
4060 if (ret)
4061 return ret;
4062
4063 si_pi->dte_table_start = tmp;
4064
4065 ret = amdgpu_si_read_smc_sram_dword(adev,
4066 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4067 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4068 &tmp, si_pi->sram_end);
4069 if (ret)
4070 return ret;
4071
4072 si_pi->spll_table_start = tmp;
4073
4074 ret = amdgpu_si_read_smc_sram_dword(adev,
4075 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4076 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4077 &tmp, si_pi->sram_end);
4078 if (ret)
4079 return ret;
4080
4081 si_pi->papm_cfg_table_start = tmp;
4082
4083 return ret;
4084 }
4085
si_read_clock_registers(struct amdgpu_device * adev)4086 static void si_read_clock_registers(struct amdgpu_device *adev)
4087 {
4088 struct si_power_info *si_pi = si_get_pi(adev);
4089
4090 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL);
4091 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2);
4092 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3);
4093 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4);
4094 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM);
4095 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2);
4096 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4097 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4098 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4099 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4100 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4101 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4102 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4103 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4104 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4105 }
4106
si_enable_thermal_protection(struct amdgpu_device * adev,bool enable)4107 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4108 bool enable)
4109 {
4110 if (enable)
4111 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4112 else
4113 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4114 }
4115
si_enable_acpi_power_management(struct amdgpu_device * adev)4116 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4117 {
4118 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK);
4119 }
4120
4121 #if 0
4122 static int si_enter_ulp_state(struct amdgpu_device *adev)
4123 {
4124 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4125
4126 udelay(25000);
4127
4128 return 0;
4129 }
4130
4131 static int si_exit_ulp_state(struct amdgpu_device *adev)
4132 {
4133 int i;
4134
4135 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4136
4137 udelay(7000);
4138
4139 for (i = 0; i < adev->usec_timeout; i++) {
4140 if (RREG32(SMC_RESP_0) == 1)
4141 break;
4142 udelay(1000);
4143 }
4144
4145 return 0;
4146 }
4147 #endif
4148
si_notify_smc_display_change(struct amdgpu_device * adev,bool has_display)4149 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4150 bool has_display)
4151 {
4152 PPSMC_Msg msg = has_display ?
4153 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4154
4155 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4156 0 : -EINVAL;
4157 }
4158
si_program_response_times(struct amdgpu_device * adev)4159 static void si_program_response_times(struct amdgpu_device *adev)
4160 {
4161 u32 voltage_response_time, acpi_delay_time, vbi_time_out;
4162 u32 vddc_dly, acpi_dly, vbi_dly;
4163 u32 reference_clock;
4164
4165 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4166
4167 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4168
4169 if (voltage_response_time == 0)
4170 voltage_response_time = 1000;
4171
4172 acpi_delay_time = 15000;
4173 vbi_time_out = 100000;
4174
4175 reference_clock = amdgpu_asic_get_xclk(adev);
4176
4177 vddc_dly = (voltage_response_time * reference_clock) / 100;
4178 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4179 vbi_dly = (vbi_time_out * reference_clock) / 100;
4180
4181 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4182 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4183 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4184 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4185 }
4186
si_program_ds_registers(struct amdgpu_device * adev)4187 static void si_program_ds_registers(struct amdgpu_device *adev)
4188 {
4189 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4190 u32 tmp;
4191
4192 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4193 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4194 tmp = 0x10;
4195 else
4196 tmp = 0x1;
4197
4198 if (eg_pi->sclk_deep_sleep) {
4199 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK);
4200 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK,
4201 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK);
4202 }
4203 }
4204
si_program_display_gap(struct amdgpu_device * adev)4205 static void si_program_display_gap(struct amdgpu_device *adev)
4206 {
4207 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
4208 u32 tmp, pipe;
4209
4210 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4211 if (cfg->num_display > 0)
4212 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4213 else
4214 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4215
4216 if (cfg->num_display > 1)
4217 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4218 else
4219 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4220
4221 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4222
4223 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4224 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4225
4226 if (cfg->num_display > 0 && pipe != cfg->crtc_index) {
4227 pipe = cfg->crtc_index;
4228
4229 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4230 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4231 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4232 }
4233
4234 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4235 * This can be a problem on PowerXpress systems or if you want to use the card
4236 * for offscreen rendering or compute if there are no crtcs enabled.
4237 */
4238 si_notify_smc_display_change(adev, cfg->num_display > 0);
4239 }
4240
si_enable_spread_spectrum(struct amdgpu_device * adev,bool enable)4241 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4242 {
4243 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4244
4245 if (enable) {
4246 if (pi->sclk_ss)
4247 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4248 } else {
4249 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
4250 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4251 }
4252 }
4253
si_setup_bsp(struct amdgpu_device * adev)4254 static void si_setup_bsp(struct amdgpu_device *adev)
4255 {
4256 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4257 u32 xclk = amdgpu_asic_get_xclk(adev);
4258
4259 r600_calculate_u_and_p(pi->asi,
4260 xclk,
4261 16,
4262 &pi->bsp,
4263 &pi->bsu);
4264
4265 r600_calculate_u_and_p(pi->pasi,
4266 xclk,
4267 16,
4268 &pi->pbsp,
4269 &pi->pbsu);
4270
4271
4272 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT);
4273 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT);
4274
4275 WREG32(mmCG_BSP, pi->dsp);
4276 }
4277
si_program_git(struct amdgpu_device * adev)4278 static void si_program_git(struct amdgpu_device *adev)
4279 {
4280 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK);
4281 }
4282
si_program_tp(struct amdgpu_device * adev)4283 static void si_program_tp(struct amdgpu_device *adev)
4284 {
4285 int i;
4286 enum r600_td td = R600_TD_DFLT;
4287
4288 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4289 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT));
4290
4291 if (td == R600_TD_AUTO)
4292 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4293 else
4294 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4295
4296 if (td == R600_TD_UP)
4297 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4298
4299 if (td == R600_TD_DOWN)
4300 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4301 }
4302
si_program_tpp(struct amdgpu_device * adev)4303 static void si_program_tpp(struct amdgpu_device *adev)
4304 {
4305 WREG32(mmCG_TPC, R600_TPC_DFLT);
4306 }
4307
si_program_sstp(struct amdgpu_device * adev)4308 static void si_program_sstp(struct amdgpu_device *adev)
4309 {
4310 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT));
4311 }
4312
si_enable_display_gap(struct amdgpu_device * adev)4313 static void si_enable_display_gap(struct amdgpu_device *adev)
4314 {
4315 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);
4316
4317 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4318 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT |
4319 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT);
4320
4321 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK);
4322 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT |
4323 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT);
4324 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4325 }
4326
si_program_vc(struct amdgpu_device * adev)4327 static void si_program_vc(struct amdgpu_device *adev)
4328 {
4329 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4330
4331 WREG32(mmCG_FTV, pi->vrc);
4332 }
4333
si_clear_vc(struct amdgpu_device * adev)4334 static void si_clear_vc(struct amdgpu_device *adev)
4335 {
4336 WREG32(mmCG_FTV, 0);
4337 }
4338
si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)4339 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4340 {
4341 u8 mc_para_index;
4342
4343 if (memory_clock < 10000)
4344 mc_para_index = 0;
4345 else if (memory_clock >= 80000)
4346 mc_para_index = 0x0f;
4347 else
4348 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4349 return mc_para_index;
4350 }
4351
si_get_mclk_frequency_ratio(u32 memory_clock,bool strobe_mode)4352 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4353 {
4354 u8 mc_para_index;
4355
4356 if (strobe_mode) {
4357 if (memory_clock < 12500)
4358 mc_para_index = 0x00;
4359 else if (memory_clock > 47500)
4360 mc_para_index = 0x0f;
4361 else
4362 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4363 } else {
4364 if (memory_clock < 65000)
4365 mc_para_index = 0x00;
4366 else if (memory_clock > 135000)
4367 mc_para_index = 0x0f;
4368 else
4369 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4370 }
4371 return mc_para_index;
4372 }
4373
si_get_strobe_mode_settings(struct amdgpu_device * adev,u32 mclk)4374 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4375 {
4376 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4377 bool strobe_mode = false;
4378 u8 result = 0;
4379
4380 if (mclk <= pi->mclk_strobe_mode_threshold)
4381 strobe_mode = true;
4382
4383 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4384 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4385 else
4386 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4387
4388 if (strobe_mode)
4389 result |= SISLANDS_SMC_STROBE_ENABLE;
4390
4391 return result;
4392 }
4393
si_upload_firmware(struct amdgpu_device * adev)4394 static int si_upload_firmware(struct amdgpu_device *adev)
4395 {
4396 struct si_power_info *si_pi = si_get_pi(adev);
4397
4398 amdgpu_si_reset_smc(adev);
4399 amdgpu_si_smc_clock(adev, false);
4400
4401 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4402 }
4403
si_validate_phase_shedding_tables(struct amdgpu_device * adev,const struct atom_voltage_table * table,const struct amdgpu_phase_shedding_limits_table * limits)4404 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4405 const struct atom_voltage_table *table,
4406 const struct amdgpu_phase_shedding_limits_table *limits)
4407 {
4408 u32 data, num_bits, num_levels;
4409
4410 if ((table == NULL) || (limits == NULL))
4411 return false;
4412
4413 data = table->mask_low;
4414
4415 num_bits = hweight32(data);
4416
4417 if (num_bits == 0)
4418 return false;
4419
4420 num_levels = (1 << num_bits);
4421
4422 if (table->count != num_levels)
4423 return false;
4424
4425 if (limits->count != (num_levels - 1))
4426 return false;
4427
4428 return true;
4429 }
4430
si_trim_voltage_table_to_fit_state_table(struct amdgpu_device * adev,u32 max_voltage_steps,struct atom_voltage_table * voltage_table)4431 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4432 u32 max_voltage_steps,
4433 struct atom_voltage_table *voltage_table)
4434 {
4435 unsigned int i, diff;
4436
4437 if (voltage_table->count <= max_voltage_steps)
4438 return;
4439
4440 diff = voltage_table->count - max_voltage_steps;
4441
4442 for (i= 0; i < max_voltage_steps; i++)
4443 voltage_table->entries[i] = voltage_table->entries[i + diff];
4444
4445 voltage_table->count = max_voltage_steps;
4446 }
4447
si_get_svi2_voltage_table(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * voltage_dependency_table,struct atom_voltage_table * voltage_table)4448 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4449 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4450 struct atom_voltage_table *voltage_table)
4451 {
4452 u32 i;
4453
4454 if (voltage_dependency_table == NULL)
4455 return -EINVAL;
4456
4457 voltage_table->mask_low = 0;
4458 voltage_table->phase_delay = 0;
4459
4460 voltage_table->count = voltage_dependency_table->count;
4461 for (i = 0; i < voltage_table->count; i++) {
4462 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4463 voltage_table->entries[i].smio_low = 0;
4464 }
4465
4466 return 0;
4467 }
4468
si_construct_voltage_tables(struct amdgpu_device * adev)4469 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4470 {
4471 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4472 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4473 struct si_power_info *si_pi = si_get_pi(adev);
4474 int ret;
4475
4476 if (pi->voltage_control) {
4477 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4478 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4479 if (ret)
4480 return ret;
4481
4482 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4483 si_trim_voltage_table_to_fit_state_table(adev,
4484 SISLANDS_MAX_NO_VREG_STEPS,
4485 &eg_pi->vddc_voltage_table);
4486 } else if (si_pi->voltage_control_svi2) {
4487 ret = si_get_svi2_voltage_table(adev,
4488 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4489 &eg_pi->vddc_voltage_table);
4490 if (ret)
4491 return ret;
4492 } else {
4493 return -EINVAL;
4494 }
4495
4496 if (eg_pi->vddci_control) {
4497 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4498 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4499 if (ret)
4500 return ret;
4501
4502 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4503 si_trim_voltage_table_to_fit_state_table(adev,
4504 SISLANDS_MAX_NO_VREG_STEPS,
4505 &eg_pi->vddci_voltage_table);
4506 }
4507 if (si_pi->vddci_control_svi2) {
4508 ret = si_get_svi2_voltage_table(adev,
4509 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4510 &eg_pi->vddci_voltage_table);
4511 if (ret)
4512 return ret;
4513 }
4514
4515 if (pi->mvdd_control) {
4516 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4517 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4518
4519 if (ret) {
4520 pi->mvdd_control = false;
4521 return ret;
4522 }
4523
4524 if (si_pi->mvdd_voltage_table.count == 0) {
4525 pi->mvdd_control = false;
4526 return -EINVAL;
4527 }
4528
4529 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4530 si_trim_voltage_table_to_fit_state_table(adev,
4531 SISLANDS_MAX_NO_VREG_STEPS,
4532 &si_pi->mvdd_voltage_table);
4533 }
4534
4535 if (si_pi->vddc_phase_shed_control) {
4536 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4537 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4538 if (ret)
4539 si_pi->vddc_phase_shed_control = false;
4540
4541 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4542 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4543 si_pi->vddc_phase_shed_control = false;
4544 }
4545
4546 return 0;
4547 }
4548
si_populate_smc_voltage_table(struct amdgpu_device * adev,const struct atom_voltage_table * voltage_table,SISLANDS_SMC_STATETABLE * table)4549 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4550 const struct atom_voltage_table *voltage_table,
4551 SISLANDS_SMC_STATETABLE *table)
4552 {
4553 unsigned int i;
4554
4555 for (i = 0; i < voltage_table->count; i++)
4556 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4557 }
4558
si_populate_smc_voltage_tables(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)4559 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4560 SISLANDS_SMC_STATETABLE *table)
4561 {
4562 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4563 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4564 struct si_power_info *si_pi = si_get_pi(adev);
4565 u8 i;
4566
4567 if (si_pi->voltage_control_svi2) {
4568 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4569 si_pi->svc_gpio_id);
4570 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4571 si_pi->svd_gpio_id);
4572 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4573 2);
4574 } else {
4575 if (eg_pi->vddc_voltage_table.count) {
4576 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4577 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4578 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4579
4580 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4581 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4582 table->maxVDDCIndexInPPTable = i;
4583 break;
4584 }
4585 }
4586 }
4587
4588 if (eg_pi->vddci_voltage_table.count) {
4589 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4590
4591 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4592 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4593 }
4594
4595
4596 if (si_pi->mvdd_voltage_table.count) {
4597 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4598
4599 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4600 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4601 }
4602
4603 if (si_pi->vddc_phase_shed_control) {
4604 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4605 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4606 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4607
4608 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4609 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4610
4611 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4612 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4613 } else {
4614 si_pi->vddc_phase_shed_control = false;
4615 }
4616 }
4617 }
4618
4619 return 0;
4620 }
4621
si_populate_voltage_value(struct amdgpu_device * adev,const struct atom_voltage_table * table,u16 value,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4622 static int si_populate_voltage_value(struct amdgpu_device *adev,
4623 const struct atom_voltage_table *table,
4624 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4625 {
4626 unsigned int i;
4627
4628 for (i = 0; i < table->count; i++) {
4629 if (value <= table->entries[i].value) {
4630 voltage->index = (u8)i;
4631 voltage->value = cpu_to_be16(table->entries[i].value);
4632 break;
4633 }
4634 }
4635
4636 if (i >= table->count)
4637 return -EINVAL;
4638
4639 return 0;
4640 }
4641
si_populate_mvdd_value(struct amdgpu_device * adev,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4642 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4643 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4644 {
4645 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4646 struct si_power_info *si_pi = si_get_pi(adev);
4647
4648 if (pi->mvdd_control) {
4649 if (mclk <= pi->mvdd_split_frequency)
4650 voltage->index = 0;
4651 else
4652 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4653
4654 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4655 }
4656 return 0;
4657 }
4658
si_get_std_voltage_value(struct amdgpu_device * adev,SISLANDS_SMC_VOLTAGE_VALUE * voltage,u16 * std_voltage)4659 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4660 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4661 u16 *std_voltage)
4662 {
4663 u16 v_index;
4664 bool voltage_found = false;
4665 *std_voltage = be16_to_cpu(voltage->value);
4666
4667 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4668 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4669 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4670 return -EINVAL;
4671
4672 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4673 if (be16_to_cpu(voltage->value) ==
4674 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4675 voltage_found = true;
4676 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4677 *std_voltage =
4678 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4679 else
4680 *std_voltage =
4681 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4682 break;
4683 }
4684 }
4685
4686 if (!voltage_found) {
4687 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4688 if (be16_to_cpu(voltage->value) <=
4689 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4690 voltage_found = true;
4691 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4692 *std_voltage =
4693 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4694 else
4695 *std_voltage =
4696 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4697 break;
4698 }
4699 }
4700 }
4701 } else {
4702 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4703 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4704 }
4705 }
4706
4707 return 0;
4708 }
4709
si_populate_std_voltage_value(struct amdgpu_device * adev,u16 value,u8 index,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4710 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4711 u16 value, u8 index,
4712 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4713 {
4714 voltage->index = index;
4715 voltage->value = cpu_to_be16(value);
4716
4717 return 0;
4718 }
4719
si_populate_phase_shedding_value(struct amdgpu_device * adev,const struct amdgpu_phase_shedding_limits_table * limits,u16 voltage,u32 sclk,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * smc_voltage)4720 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4721 const struct amdgpu_phase_shedding_limits_table *limits,
4722 u16 voltage, u32 sclk, u32 mclk,
4723 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4724 {
4725 unsigned int i;
4726
4727 for (i = 0; i < limits->count; i++) {
4728 if ((voltage <= limits->entries[i].voltage) &&
4729 (sclk <= limits->entries[i].sclk) &&
4730 (mclk <= limits->entries[i].mclk))
4731 break;
4732 }
4733
4734 smc_voltage->phase_settings = (u8)i;
4735
4736 return 0;
4737 }
4738
si_init_arb_table_index(struct amdgpu_device * adev)4739 static int si_init_arb_table_index(struct amdgpu_device *adev)
4740 {
4741 struct si_power_info *si_pi = si_get_pi(adev);
4742 u32 tmp;
4743 int ret;
4744
4745 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4746 &tmp, si_pi->sram_end);
4747 if (ret)
4748 return ret;
4749
4750 tmp &= 0x00FFFFFF;
4751 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4752
4753 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4754 tmp, si_pi->sram_end);
4755 }
4756
si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device * adev)4757 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4758 {
4759 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4760 }
4761
si_reset_to_default(struct amdgpu_device * adev)4762 static int si_reset_to_default(struct amdgpu_device *adev)
4763 {
4764 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4765 0 : -EINVAL;
4766 }
4767
si_force_switch_to_arb_f0(struct amdgpu_device * adev)4768 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4769 {
4770 struct si_power_info *si_pi = si_get_pi(adev);
4771 u32 tmp;
4772 int ret;
4773
4774 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4775 &tmp, si_pi->sram_end);
4776 if (ret)
4777 return ret;
4778
4779 tmp = (tmp >> 24) & 0xff;
4780
4781 if (tmp == MC_CG_ARB_FREQ_F0)
4782 return 0;
4783
4784 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4785 }
4786
si_calculate_memory_refresh_rate(struct amdgpu_device * adev,u32 engine_clock)4787 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4788 u32 engine_clock)
4789 {
4790 u32 dram_rows;
4791 u32 dram_refresh_rate;
4792 u32 mc_arb_rfsh_rate;
4793 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;
4794
4795 if (tmp >= 4)
4796 dram_rows = 16384;
4797 else
4798 dram_rows = 1 << (tmp + 10);
4799
4800 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4801 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4802
4803 return mc_arb_rfsh_rate;
4804 }
4805
si_populate_memory_timing_parameters(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCArbDramTimingRegisterSet * arb_regs)4806 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4807 struct rv7xx_pl *pl,
4808 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4809 {
4810 u32 dram_timing;
4811 u32 dram_timing2;
4812 u32 burst_time;
4813 int ret;
4814
4815 arb_regs->mc_arb_rfsh_rate =
4816 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4817
4818 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk,
4819 pl->mclk);
4820 if (ret)
4821 return ret;
4822
4823 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4824 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4825 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4826
4827 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4828 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4829 arb_regs->mc_arb_burst_time = (u8)burst_time;
4830
4831 return 0;
4832 }
4833
si_do_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,unsigned int first_arb_set)4834 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4835 struct amdgpu_ps *amdgpu_state,
4836 unsigned int first_arb_set)
4837 {
4838 struct si_power_info *si_pi = si_get_pi(adev);
4839 struct si_ps *state = si_get_ps(amdgpu_state);
4840 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4841 int i, ret = 0;
4842
4843 for (i = 0; i < state->performance_level_count; i++) {
4844 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4845 if (ret)
4846 break;
4847 ret = amdgpu_si_copy_bytes_to_smc(adev,
4848 si_pi->arb_table_start +
4849 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4850 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4851 (u8 *)&arb_regs,
4852 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4853 si_pi->sram_end);
4854 if (ret)
4855 break;
4856 }
4857
4858 return ret;
4859 }
4860
si_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)4861 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4862 struct amdgpu_ps *amdgpu_new_state)
4863 {
4864 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4865 SISLANDS_DRIVER_STATE_ARB_INDEX);
4866 }
4867
si_populate_initial_mvdd_value(struct amdgpu_device * adev,struct SISLANDS_SMC_VOLTAGE_VALUE * voltage)4868 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4869 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4870 {
4871 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4872 struct si_power_info *si_pi = si_get_pi(adev);
4873
4874 if (pi->mvdd_control)
4875 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4876 si_pi->mvdd_bootup_value, voltage);
4877
4878 return 0;
4879 }
4880
si_populate_smc_initial_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_initial_state,SISLANDS_SMC_STATETABLE * table)4881 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4882 struct amdgpu_ps *amdgpu_initial_state,
4883 SISLANDS_SMC_STATETABLE *table)
4884 {
4885 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4886 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4887 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4888 struct si_power_info *si_pi = si_get_pi(adev);
4889 u32 reg;
4890 int ret;
4891
4892 table->initialState.level.mclk.vDLL_CNTL =
4893 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4894 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4895 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4896 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4897 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4898 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4899 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4900 table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4901 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4902 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4903 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4904 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4905 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4906 table->initialState.level.mclk.vMPLL_SS =
4907 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4908 table->initialState.level.mclk.vMPLL_SS2 =
4909 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4910
4911 table->initialState.level.mclk.mclk_value =
4912 cpu_to_be32(initial_state->performance_levels[0].mclk);
4913
4914 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4915 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4916 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4917 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4918 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4919 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4920 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4921 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4922 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4923 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4924 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4925 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4926
4927 table->initialState.level.sclk.sclk_value =
4928 cpu_to_be32(initial_state->performance_levels[0].sclk);
4929
4930 table->initialState.level.arbRefreshState =
4931 SISLANDS_INITIAL_STATE_ARB_INDEX;
4932
4933 table->initialState.level.ACIndex = 0;
4934
4935 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4936 initial_state->performance_levels[0].vddc,
4937 &table->initialState.level.vddc);
4938
4939 if (!ret) {
4940 u16 std_vddc;
4941
4942 ret = si_get_std_voltage_value(adev,
4943 &table->initialState.level.vddc,
4944 &std_vddc);
4945 if (!ret)
4946 si_populate_std_voltage_value(adev, std_vddc,
4947 table->initialState.level.vddc.index,
4948 &table->initialState.level.std_vddc);
4949 }
4950
4951 if (eg_pi->vddci_control)
4952 si_populate_voltage_value(adev,
4953 &eg_pi->vddci_voltage_table,
4954 initial_state->performance_levels[0].vddci,
4955 &table->initialState.level.vddci);
4956
4957 if (si_pi->vddc_phase_shed_control)
4958 si_populate_phase_shedding_value(adev,
4959 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4960 initial_state->performance_levels[0].vddc,
4961 initial_state->performance_levels[0].sclk,
4962 initial_state->performance_levels[0].mclk,
4963 &table->initialState.level.vddc);
4964
4965 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd);
4966
4967 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
4968 table->initialState.level.aT = cpu_to_be32(reg);
4969 table->initialState.level.bSP = cpu_to_be32(pi->dsp);
4970 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4971
4972 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4973 table->initialState.level.strobeMode =
4974 si_get_strobe_mode_settings(adev,
4975 initial_state->performance_levels[0].mclk);
4976
4977 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4978 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4979 else
4980 table->initialState.level.mcFlags = 0;
4981 }
4982
4983 table->initialState.levelCount = 1;
4984
4985 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4986
4987 table->initialState.level.dpm2.MaxPS = 0;
4988 table->initialState.level.dpm2.NearTDPDec = 0;
4989 table->initialState.level.dpm2.AboveSafeInc = 0;
4990 table->initialState.level.dpm2.BelowSafeInc = 0;
4991 table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4992
4993 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK |
4994 SQ_POWER_THROTTLE__MAX_POWER_MASK;
4995 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4996
4997 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
4998 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
4999 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
5000 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5001
5002 return 0;
5003 }
5004
si_gen_pcie_gen_support(struct amdgpu_device * adev,u32 sys_mask,enum si_pcie_gen asic_gen,enum si_pcie_gen default_gen)5005 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev,
5006 u32 sys_mask,
5007 enum si_pcie_gen asic_gen,
5008 enum si_pcie_gen default_gen)
5009 {
5010 switch (asic_gen) {
5011 case SI_PCIE_GEN1:
5012 return SI_PCIE_GEN1;
5013 case SI_PCIE_GEN2:
5014 return SI_PCIE_GEN2;
5015 case SI_PCIE_GEN3:
5016 return SI_PCIE_GEN3;
5017 default:
5018 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
5019 (default_gen == SI_PCIE_GEN3))
5020 return SI_PCIE_GEN3;
5021 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
5022 (default_gen == SI_PCIE_GEN2))
5023 return SI_PCIE_GEN2;
5024 else
5025 return SI_PCIE_GEN1;
5026 }
5027 return SI_PCIE_GEN1;
5028 }
5029
si_populate_smc_acpi_state(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)5030 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5031 SISLANDS_SMC_STATETABLE *table)
5032 {
5033 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5034 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5035 struct si_power_info *si_pi = si_get_pi(adev);
5036 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5037 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5038 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5039 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5040 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5041 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5042 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5043 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5044 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5045 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5046 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5047 u32 reg;
5048 int ret;
5049
5050 table->ACPIState = table->initialState;
5051
5052 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5053
5054 if (pi->acpi_vddc) {
5055 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5056 pi->acpi_vddc, &table->ACPIState.level.vddc);
5057 if (!ret) {
5058 u16 std_vddc;
5059
5060 ret = si_get_std_voltage_value(adev,
5061 &table->ACPIState.level.vddc, &std_vddc);
5062 if (!ret)
5063 si_populate_std_voltage_value(adev, std_vddc,
5064 table->ACPIState.level.vddc.index,
5065 &table->ACPIState.level.std_vddc);
5066 }
5067 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
5068
5069 if (si_pi->vddc_phase_shed_control) {
5070 si_populate_phase_shedding_value(adev,
5071 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5072 pi->acpi_vddc,
5073 0,
5074 0,
5075 &table->ACPIState.level.vddc);
5076 }
5077 } else {
5078 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5079 pi->min_vddc_in_table, &table->ACPIState.level.vddc);
5080 if (!ret) {
5081 u16 std_vddc;
5082
5083 ret = si_get_std_voltage_value(adev,
5084 &table->ACPIState.level.vddc, &std_vddc);
5085
5086 if (!ret)
5087 si_populate_std_voltage_value(adev, std_vddc,
5088 table->ACPIState.level.vddc.index,
5089 &table->ACPIState.level.std_vddc);
5090 }
5091 table->ACPIState.level.gen2PCIE =
5092 (u8)si_gen_pcie_gen_support(adev,
5093 si_pi->sys_pcie_mask,
5094 si_pi->boot_pcie_gen,
5095 SI_PCIE_GEN1);
5096
5097 if (si_pi->vddc_phase_shed_control)
5098 si_populate_phase_shedding_value(adev,
5099 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5100 pi->min_vddc_in_table,
5101 0,
5102 0,
5103 &table->ACPIState.level.vddc);
5104 }
5105
5106 if (pi->acpi_vddc) {
5107 if (eg_pi->acpi_vddci)
5108 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5109 eg_pi->acpi_vddci,
5110 &table->ACPIState.level.vddci);
5111 }
5112
5113 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5114 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5115
5116 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5117
5118 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5119 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5120
5121 table->ACPIState.level.mclk.vDLL_CNTL =
5122 cpu_to_be32(dll_cntl);
5123 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
5124 cpu_to_be32(mclk_pwrmgt_cntl);
5125 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
5126 cpu_to_be32(mpll_ad_func_cntl);
5127 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
5128 cpu_to_be32(mpll_dq_func_cntl);
5129 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
5130 cpu_to_be32(mpll_func_cntl);
5131 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
5132 cpu_to_be32(mpll_func_cntl_1);
5133 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
5134 cpu_to_be32(mpll_func_cntl_2);
5135 table->ACPIState.level.mclk.vMPLL_SS =
5136 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5137 table->ACPIState.level.mclk.vMPLL_SS2 =
5138 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5139
5140 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
5141 cpu_to_be32(spll_func_cntl);
5142 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
5143 cpu_to_be32(spll_func_cntl_2);
5144 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
5145 cpu_to_be32(spll_func_cntl_3);
5146 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
5147 cpu_to_be32(spll_func_cntl_4);
5148
5149 table->ACPIState.level.mclk.mclk_value = 0;
5150 table->ACPIState.level.sclk.sclk_value = 0;
5151
5152 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd);
5153
5154 if (eg_pi->dynamic_ac_timing)
5155 table->ACPIState.level.ACIndex = 0;
5156
5157 table->ACPIState.level.dpm2.MaxPS = 0;
5158 table->ACPIState.level.dpm2.NearTDPDec = 0;
5159 table->ACPIState.level.dpm2.AboveSafeInc = 0;
5160 table->ACPIState.level.dpm2.BelowSafeInc = 0;
5161 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
5162
5163 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK;
5164 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
5165
5166 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
5167 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5168
5169 return 0;
5170 }
5171
si_populate_ulv_state(struct amdgpu_device * adev,struct SISLANDS_SMC_SWSTATE_SINGLE * state)5172 static int si_populate_ulv_state(struct amdgpu_device *adev,
5173 struct SISLANDS_SMC_SWSTATE_SINGLE *state)
5174 {
5175 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5176 struct si_power_info *si_pi = si_get_pi(adev);
5177 struct si_ulv_param *ulv = &si_pi->ulv;
5178 u32 sclk_in_sr = 1350; /* ??? */
5179 int ret;
5180
5181 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5182 &state->level);
5183 if (!ret) {
5184 if (eg_pi->sclk_deep_sleep) {
5185 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5186 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5187 else
5188 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5189 }
5190 if (ulv->one_pcie_lane_in_ulv)
5191 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5192 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5193 state->level.ACIndex = 1;
5194 state->level.std_vddc = state->level.vddc;
5195 state->levelCount = 1;
5196
5197 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5198 }
5199
5200 return ret;
5201 }
5202
si_program_ulv_memory_timing_parameters(struct amdgpu_device * adev)5203 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5204 {
5205 struct si_power_info *si_pi = si_get_pi(adev);
5206 struct si_ulv_param *ulv = &si_pi->ulv;
5207 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5208 int ret;
5209
5210 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5211 &arb_regs);
5212 if (ret)
5213 return ret;
5214
5215 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5216 ulv->volt_change_delay);
5217
5218 ret = amdgpu_si_copy_bytes_to_smc(adev,
5219 si_pi->arb_table_start +
5220 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5221 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5222 (u8 *)&arb_regs,
5223 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5224 si_pi->sram_end);
5225
5226 return ret;
5227 }
5228
si_get_mvdd_configuration(struct amdgpu_device * adev)5229 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5230 {
5231 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5232
5233 pi->mvdd_split_frequency = 30000;
5234 }
5235
si_init_smc_table(struct amdgpu_device * adev)5236 static int si_init_smc_table(struct amdgpu_device *adev)
5237 {
5238 struct si_power_info *si_pi = si_get_pi(adev);
5239 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5240 const struct si_ulv_param *ulv = &si_pi->ulv;
5241 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5242 int ret;
5243 u32 lane_width;
5244 u32 vr_hot_gpio;
5245
5246 si_populate_smc_voltage_tables(adev, table);
5247
5248 switch (adev->pm.int_thermal_type) {
5249 case THERMAL_TYPE_SI:
5250 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5251 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5252 break;
5253 case THERMAL_TYPE_NONE:
5254 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5255 break;
5256 default:
5257 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5258 break;
5259 }
5260
5261 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5262 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5263
5264 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5265 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5266 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5267 }
5268
5269 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5270 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5271
5272 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5273 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5274
5275 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5276 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5277
5278 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5279 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5280 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5281 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5282 vr_hot_gpio);
5283 }
5284
5285 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5286 if (ret)
5287 return ret;
5288
5289 ret = si_populate_smc_acpi_state(adev, table);
5290 if (ret)
5291 return ret;
5292
5293 table->driverState.flags = table->initialState.flags;
5294 table->driverState.levelCount = table->initialState.levelCount;
5295 table->driverState.levels[0] = table->initialState.level;
5296
5297 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5298 SISLANDS_INITIAL_STATE_ARB_INDEX);
5299 if (ret)
5300 return ret;
5301
5302 if (ulv->supported && ulv->pl.vddc) {
5303 ret = si_populate_ulv_state(adev, &table->ULVState);
5304 if (ret)
5305 return ret;
5306
5307 ret = si_program_ulv_memory_timing_parameters(adev);
5308 if (ret)
5309 return ret;
5310
5311 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control);
5312 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5313
5314 lane_width = amdgpu_get_pcie_lanes(adev);
5315 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5316 } else {
5317 table->ULVState = table->initialState;
5318 }
5319
5320 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5321 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5322 si_pi->sram_end);
5323 }
5324
si_calculate_sclk_params(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5325 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5326 u32 engine_clock,
5327 SISLANDS_SMC_SCLK_VALUE *sclk)
5328 {
5329 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5330 struct si_power_info *si_pi = si_get_pi(adev);
5331 struct atom_clock_dividers dividers;
5332 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5333 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5334 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5335 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5336 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5337 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5338 u64 tmp;
5339 u32 reference_clock = adev->clock.spll.reference_freq;
5340 u32 reference_divider;
5341 u32 fbdiv;
5342 int ret;
5343
5344 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5345 engine_clock, false, ÷rs);
5346 if (ret)
5347 return ret;
5348
5349 reference_divider = 1 + dividers.ref_div;
5350
5351 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5352 do_div(tmp, reference_clock);
5353 fbdiv = (u32) tmp;
5354
5355 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK);
5356 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT;
5357 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
5358
5359 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5360 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5361
5362 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
5363 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
5364 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
5365
5366 if (pi->sclk_ss) {
5367 struct amdgpu_atom_ss ss;
5368 u32 vco_freq = engine_clock * dividers.post_div;
5369
5370 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5371 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5372 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5373 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5374
5375 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK;
5376 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
5377 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
5378
5379 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK;
5380 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
5381 }
5382 }
5383
5384 sclk->sclk_value = engine_clock;
5385 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5386 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5387 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5388 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5389 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5390 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5391
5392 return 0;
5393 }
5394
si_populate_sclk_value(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5395 static int si_populate_sclk_value(struct amdgpu_device *adev,
5396 u32 engine_clock,
5397 SISLANDS_SMC_SCLK_VALUE *sclk)
5398 {
5399 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5400 int ret;
5401
5402 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5403 if (!ret) {
5404 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5405 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5406 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5407 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5408 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5409 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5410 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5411 }
5412
5413 return ret;
5414 }
5415
si_populate_mclk_value(struct amdgpu_device * adev,u32 engine_clock,u32 memory_clock,SISLANDS_SMC_MCLK_VALUE * mclk,bool strobe_mode,bool dll_state_on)5416 static int si_populate_mclk_value(struct amdgpu_device *adev,
5417 u32 engine_clock,
5418 u32 memory_clock,
5419 SISLANDS_SMC_MCLK_VALUE *mclk,
5420 bool strobe_mode,
5421 bool dll_state_on)
5422 {
5423 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5424 struct si_power_info *si_pi = si_get_pi(adev);
5425 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5426 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5427 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5428 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5429 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5430 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5431 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5432 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5433 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5434 struct atom_mpll_param mpll_param;
5435 int ret;
5436
5437 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5438 if (ret)
5439 return ret;
5440
5441 mpll_func_cntl &= ~BWCTRL_MASK;
5442 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5443
5444 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5445 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5446 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5447
5448 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5449 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5450
5451 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5452 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5453 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5454 YCLK_POST_DIV(mpll_param.post_div);
5455 }
5456
5457 if (pi->mclk_ss) {
5458 struct amdgpu_atom_ss ss;
5459 u32 freq_nom;
5460 u32 tmp;
5461 u32 reference_clock = adev->clock.mpll.reference_freq;
5462
5463 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5464 freq_nom = memory_clock * 4;
5465 else
5466 freq_nom = memory_clock * 2;
5467
5468 tmp = freq_nom / reference_clock;
5469 tmp = tmp * tmp;
5470 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5471 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5472 u32 clks = reference_clock * 5 / ss.rate;
5473 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5474
5475 mpll_ss1 &= ~CLKV_MASK;
5476 mpll_ss1 |= CLKV(clkv);
5477
5478 mpll_ss2 &= ~CLKS_MASK;
5479 mpll_ss2 |= CLKS(clks);
5480 }
5481 }
5482
5483 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5484 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5485
5486 if (dll_state_on)
5487 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5488 else
5489 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5490
5491 mclk->mclk_value = cpu_to_be32(memory_clock);
5492 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5493 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5494 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5495 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5496 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5497 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5498 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5499 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5500 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5501
5502 return 0;
5503 }
5504
si_populate_smc_sp(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5505 static void si_populate_smc_sp(struct amdgpu_device *adev,
5506 struct amdgpu_ps *amdgpu_state,
5507 SISLANDS_SMC_SWSTATE *smc_state)
5508 {
5509 struct si_ps *ps = si_get_ps(amdgpu_state);
5510 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5511 int i;
5512
5513 for (i = 0; i < ps->performance_level_count - 1; i++)
5514 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5515
5516 smc_state->levels[ps->performance_level_count - 1].bSP =
5517 cpu_to_be32(pi->psp);
5518 }
5519
si_convert_power_level_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SISLANDS_SMC_HW_PERFORMANCE_LEVEL * level)5520 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5521 struct rv7xx_pl *pl,
5522 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5523 {
5524 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5525 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5526 struct si_power_info *si_pi = si_get_pi(adev);
5527 int ret;
5528 bool dll_state_on;
5529 u16 std_vddc;
5530
5531 if (eg_pi->pcie_performance_request &&
5532 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID))
5533 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5534 else
5535 level->gen2PCIE = (u8)pl->pcie_gen;
5536
5537 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5538 if (ret)
5539 return ret;
5540
5541 level->mcFlags = 0;
5542
5543 if (pi->mclk_stutter_mode_threshold &&
5544 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5545 !eg_pi->uvd_enabled &&
5546 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
5547 (adev->pm.pm_display_cfg.num_display <= 2)) {
5548 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5549 }
5550
5551 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5552 if (pl->mclk > pi->mclk_edc_enable_threshold)
5553 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5554
5555 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5556 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5557
5558 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5559
5560 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5561 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5562 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5563 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5564 else
5565 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5566 } else {
5567 dll_state_on = false;
5568 }
5569 } else {
5570 level->strobeMode = si_get_strobe_mode_settings(adev,
5571 pl->mclk);
5572
5573 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5574 }
5575
5576 ret = si_populate_mclk_value(adev,
5577 pl->sclk,
5578 pl->mclk,
5579 &level->mclk,
5580 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5581 if (ret)
5582 return ret;
5583
5584 ret = si_populate_voltage_value(adev,
5585 &eg_pi->vddc_voltage_table,
5586 pl->vddc, &level->vddc);
5587 if (ret)
5588 return ret;
5589
5590
5591 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5592 if (ret)
5593 return ret;
5594
5595 ret = si_populate_std_voltage_value(adev, std_vddc,
5596 level->vddc.index, &level->std_vddc);
5597 if (ret)
5598 return ret;
5599
5600 if (eg_pi->vddci_control) {
5601 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5602 pl->vddci, &level->vddci);
5603 if (ret)
5604 return ret;
5605 }
5606
5607 if (si_pi->vddc_phase_shed_control) {
5608 ret = si_populate_phase_shedding_value(adev,
5609 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5610 pl->vddc,
5611 pl->sclk,
5612 pl->mclk,
5613 &level->vddc);
5614 if (ret)
5615 return ret;
5616 }
5617
5618 level->MaxPoweredUpCU = si_pi->max_cu;
5619
5620 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5621
5622 return ret;
5623 }
5624
si_populate_smc_t(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5625 static int si_populate_smc_t(struct amdgpu_device *adev,
5626 struct amdgpu_ps *amdgpu_state,
5627 SISLANDS_SMC_SWSTATE *smc_state)
5628 {
5629 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5630 struct si_ps *state = si_get_ps(amdgpu_state);
5631 u32 a_t;
5632 u32 t_l, t_h;
5633 u32 high_bsp;
5634 int i, ret;
5635
5636 if (state->performance_level_count >= 9)
5637 return -EINVAL;
5638
5639 if (state->performance_level_count < 2) {
5640 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
5641 smc_state->levels[0].aT = cpu_to_be32(a_t);
5642 return 0;
5643 }
5644
5645 smc_state->levels[0].aT = cpu_to_be32(0);
5646
5647 for (i = 0; i <= state->performance_level_count - 2; i++) {
5648 ret = r600_calculate_at(
5649 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5650 100 * R600_AH_DFLT,
5651 state->performance_levels[i + 1].sclk,
5652 state->performance_levels[i].sclk,
5653 &t_l,
5654 &t_h);
5655
5656 if (ret) {
5657 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5658 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5659 }
5660
5661 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK;
5662 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT;
5663 smc_state->levels[i].aT = cpu_to_be32(a_t);
5664
5665 high_bsp = (i == state->performance_level_count - 2) ?
5666 pi->pbsp : pi->bsp;
5667 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT;
5668 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5669 }
5670
5671 return 0;
5672 }
5673
si_disable_ulv(struct amdgpu_device * adev)5674 static int si_disable_ulv(struct amdgpu_device *adev)
5675 {
5676 PPSMC_Result r;
5677
5678 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV);
5679 return (r == PPSMC_Result_OK) ? 0 : -EINVAL;
5680 }
5681
si_is_state_ulv_compatible(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)5682 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5683 struct amdgpu_ps *amdgpu_state)
5684 {
5685 const struct si_power_info *si_pi = si_get_pi(adev);
5686 const struct si_ulv_param *ulv = &si_pi->ulv;
5687 const struct si_ps *state = si_get_ps(amdgpu_state);
5688 int i;
5689
5690 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5691 return false;
5692
5693 /* XXX validate against display requirements! */
5694
5695 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5696 if (adev->pm.pm_display_cfg.display_clk <=
5697 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5698 if (ulv->pl.vddc <
5699 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5700 return false;
5701 }
5702 }
5703
5704 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5705 return false;
5706
5707 return true;
5708 }
5709
si_set_power_state_conditionally_enable_ulv(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5710 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5711 struct amdgpu_ps *amdgpu_new_state)
5712 {
5713 const struct si_power_info *si_pi = si_get_pi(adev);
5714 const struct si_ulv_param *ulv = &si_pi->ulv;
5715
5716 if (ulv->supported) {
5717 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5718 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5719 0 : -EINVAL;
5720 }
5721 return 0;
5722 }
5723
si_convert_power_state_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5724 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5725 struct amdgpu_ps *amdgpu_state,
5726 SISLANDS_SMC_SWSTATE *smc_state)
5727 {
5728 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5729 struct ni_power_info *ni_pi = ni_get_pi(adev);
5730 struct si_power_info *si_pi = si_get_pi(adev);
5731 struct si_ps *state = si_get_ps(amdgpu_state);
5732 int i, ret;
5733 u32 threshold;
5734 u32 sclk_in_sr = 1350; /* ??? */
5735
5736 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5737 return -EINVAL;
5738
5739 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5740
5741 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5742 eg_pi->uvd_enabled = true;
5743 if (eg_pi->smu_uvd_hs)
5744 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5745 } else {
5746 eg_pi->uvd_enabled = false;
5747 }
5748
5749 if (state->dc_compatible)
5750 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5751
5752 smc_state->levelCount = 0;
5753 for (i = 0; i < state->performance_level_count; i++) {
5754 if (eg_pi->sclk_deep_sleep) {
5755 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5756 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5757 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5758 else
5759 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5760 }
5761 }
5762
5763 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5764 &smc_state->levels[i]);
5765 smc_state->levels[i].arbRefreshState =
5766 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5767
5768 if (ret)
5769 return ret;
5770
5771 if (ni_pi->enable_power_containment)
5772 smc_state->levels[i].displayWatermark =
5773 (state->performance_levels[i].sclk < threshold) ?
5774 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5775 else
5776 smc_state->levels[i].displayWatermark = (i < 2) ?
5777 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5778
5779 if (eg_pi->dynamic_ac_timing)
5780 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5781 else
5782 smc_state->levels[i].ACIndex = 0;
5783
5784 smc_state->levelCount++;
5785 }
5786
5787 si_write_smc_soft_register(adev,
5788 SI_SMC_SOFT_REGISTER_watermark_threshold,
5789 threshold / 512);
5790
5791 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5792
5793 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5794 if (ret)
5795 ni_pi->enable_power_containment = false;
5796
5797 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5798 if (ret)
5799 ni_pi->enable_sq_ramping = false;
5800
5801 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5802 }
5803
si_upload_sw_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5804 static int si_upload_sw_state(struct amdgpu_device *adev,
5805 struct amdgpu_ps *amdgpu_new_state)
5806 {
5807 struct si_power_info *si_pi = si_get_pi(adev);
5808 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5809 int ret;
5810 u32 address = si_pi->state_table_start +
5811 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5812 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5813 size_t state_size = struct_size(smc_state, levels,
5814 new_state->performance_level_count);
5815 memset(smc_state, 0, state_size);
5816
5817 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5818 if (ret)
5819 return ret;
5820
5821 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5822 state_size, si_pi->sram_end);
5823 }
5824
si_upload_ulv_state(struct amdgpu_device * adev)5825 static int si_upload_ulv_state(struct amdgpu_device *adev)
5826 {
5827 struct si_power_info *si_pi = si_get_pi(adev);
5828 struct si_ulv_param *ulv = &si_pi->ulv;
5829 int ret = 0;
5830
5831 if (ulv->supported && ulv->pl.vddc) {
5832 u32 address = si_pi->state_table_start +
5833 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5834 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
5835 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5836
5837 memset(smc_state, 0, state_size);
5838
5839 ret = si_populate_ulv_state(adev, smc_state);
5840 if (!ret)
5841 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5842 state_size, si_pi->sram_end);
5843 }
5844
5845 return ret;
5846 }
5847
si_upload_smc_data(struct amdgpu_device * adev)5848 static int si_upload_smc_data(struct amdgpu_device *adev)
5849 {
5850 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
5851 u32 crtc_index = 0;
5852 u32 mclk_change_block_cp_min = 0;
5853 u32 mclk_change_block_cp_max = 0;
5854
5855 /* When a display is plugged in, program these so that the SMC
5856 * performs MCLK switching when it doesn't cause flickering.
5857 * When no display is plugged in, there is no need to restrict
5858 * MCLK switching, so program them to zero.
5859 */
5860 if (cfg->num_display) {
5861 crtc_index = cfg->crtc_index;
5862
5863 if (cfg->line_time_in_us) {
5864 mclk_change_block_cp_min = 200 / cfg->line_time_in_us;
5865 mclk_change_block_cp_max = 100 / cfg->line_time_in_us;
5866 }
5867 }
5868
5869 si_write_smc_soft_register(adev,
5870 SI_SMC_SOFT_REGISTER_crtc_index,
5871 crtc_index);
5872
5873 si_write_smc_soft_register(adev,
5874 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5875 mclk_change_block_cp_min);
5876
5877 si_write_smc_soft_register(adev,
5878 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5879 mclk_change_block_cp_max);
5880
5881 return 0;
5882 }
5883
si_set_mc_special_registers(struct amdgpu_device * adev,struct si_mc_reg_table * table)5884 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5885 struct si_mc_reg_table *table)
5886 {
5887 u8 i, j, k;
5888 u32 temp_reg;
5889
5890 for (i = 0, j = table->last; i < table->last; i++) {
5891 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5892 return -EINVAL;
5893 switch (table->mc_reg_address[i].s1) {
5894 case MC_SEQ_MISC1:
5895 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5896 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5897 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5898 for (k = 0; k < table->num_entries; k++)
5899 table->mc_reg_table_entry[k].mc_data[j] =
5900 ((temp_reg & 0xffff0000)) |
5901 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5902 j++;
5903
5904 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5905 return -EINVAL;
5906 temp_reg = RREG32(MC_PMG_CMD_MRS);
5907 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5908 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5909 for (k = 0; k < table->num_entries; k++) {
5910 table->mc_reg_table_entry[k].mc_data[j] =
5911 (temp_reg & 0xffff0000) |
5912 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5913 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5914 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5915 }
5916 j++;
5917
5918 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5919 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5920 return -EINVAL;
5921 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5922 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5923 for (k = 0; k < table->num_entries; k++)
5924 table->mc_reg_table_entry[k].mc_data[j] =
5925 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5926 j++;
5927 }
5928 break;
5929 case MC_SEQ_RESERVE_M:
5930 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5931 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5932 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5933 for(k = 0; k < table->num_entries; k++)
5934 table->mc_reg_table_entry[k].mc_data[j] =
5935 (temp_reg & 0xffff0000) |
5936 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5937 j++;
5938 break;
5939 default:
5940 break;
5941 }
5942 }
5943
5944 table->last = j;
5945
5946 return 0;
5947 }
5948
si_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)5949 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5950 {
5951 bool result = true;
5952 switch (in_reg) {
5953 case MC_SEQ_RAS_TIMING:
5954 *out_reg = MC_SEQ_RAS_TIMING_LP;
5955 break;
5956 case MC_SEQ_CAS_TIMING:
5957 *out_reg = MC_SEQ_CAS_TIMING_LP;
5958 break;
5959 case MC_SEQ_MISC_TIMING:
5960 *out_reg = MC_SEQ_MISC_TIMING_LP;
5961 break;
5962 case MC_SEQ_MISC_TIMING2:
5963 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5964 break;
5965 case MC_SEQ_RD_CTL_D0:
5966 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5967 break;
5968 case MC_SEQ_RD_CTL_D1:
5969 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5970 break;
5971 case MC_SEQ_WR_CTL_D0:
5972 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5973 break;
5974 case MC_SEQ_WR_CTL_D1:
5975 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5976 break;
5977 case MC_PMG_CMD_EMRS:
5978 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5979 break;
5980 case MC_PMG_CMD_MRS:
5981 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5982 break;
5983 case MC_PMG_CMD_MRS1:
5984 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5985 break;
5986 case MC_SEQ_PMG_TIMING:
5987 *out_reg = MC_SEQ_PMG_TIMING_LP;
5988 break;
5989 case MC_PMG_CMD_MRS2:
5990 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5991 break;
5992 case MC_SEQ_WR_CTL_2:
5993 *out_reg = MC_SEQ_WR_CTL_2_LP;
5994 break;
5995 default:
5996 result = false;
5997 break;
5998 }
5999
6000 return result;
6001 }
6002
si_set_valid_flag(struct si_mc_reg_table * table)6003 static void si_set_valid_flag(struct si_mc_reg_table *table)
6004 {
6005 u8 i, j;
6006
6007 for (i = 0; i < table->last; i++) {
6008 for (j = 1; j < table->num_entries; j++) {
6009 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6010 table->valid_flag |= 1 << i;
6011 break;
6012 }
6013 }
6014 }
6015 }
6016
si_set_s0_mc_reg_index(struct si_mc_reg_table * table)6017 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6018 {
6019 u32 i;
6020 u16 address;
6021
6022 for (i = 0; i < table->last; i++)
6023 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6024 address : table->mc_reg_address[i].s1;
6025
6026 }
6027
si_copy_vbios_mc_reg_table(struct atom_mc_reg_table * table,struct si_mc_reg_table * si_table)6028 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6029 struct si_mc_reg_table *si_table)
6030 {
6031 u8 i, j;
6032
6033 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6034 return -EINVAL;
6035 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6036 return -EINVAL;
6037
6038 for (i = 0; i < table->last; i++)
6039 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6040 si_table->last = table->last;
6041
6042 for (i = 0; i < table->num_entries; i++) {
6043 si_table->mc_reg_table_entry[i].mclk_max =
6044 table->mc_reg_table_entry[i].mclk_max;
6045 for (j = 0; j < table->last; j++) {
6046 si_table->mc_reg_table_entry[i].mc_data[j] =
6047 table->mc_reg_table_entry[i].mc_data[j];
6048 }
6049 }
6050 si_table->num_entries = table->num_entries;
6051
6052 return 0;
6053 }
6054
si_initialize_mc_reg_table(struct amdgpu_device * adev)6055 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6056 {
6057 struct si_power_info *si_pi = si_get_pi(adev);
6058 struct atom_mc_reg_table *table;
6059 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6060 u8 module_index = rv770_get_memory_module_index(adev);
6061 int ret;
6062
6063 table = kzalloc_obj(struct atom_mc_reg_table);
6064 if (!table)
6065 return -ENOMEM;
6066
6067 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6068 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6069 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6070 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6071 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6072 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6073 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6074 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6075 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6076 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6077 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6078 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6079 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6080 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6081
6082 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6083 if (ret)
6084 goto init_mc_done;
6085
6086 ret = si_copy_vbios_mc_reg_table(table, si_table);
6087 if (ret)
6088 goto init_mc_done;
6089
6090 si_set_s0_mc_reg_index(si_table);
6091
6092 ret = si_set_mc_special_registers(adev, si_table);
6093 if (ret)
6094 goto init_mc_done;
6095
6096 si_set_valid_flag(si_table);
6097
6098 init_mc_done:
6099 kfree(table);
6100
6101 return ret;
6102
6103 }
6104
si_populate_mc_reg_addresses(struct amdgpu_device * adev,SMC_SIslands_MCRegisters * mc_reg_table)6105 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6106 SMC_SIslands_MCRegisters *mc_reg_table)
6107 {
6108 struct si_power_info *si_pi = si_get_pi(adev);
6109 u32 i, j;
6110
6111 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6112 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6113 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6114 break;
6115 mc_reg_table->address[i].s0 =
6116 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6117 mc_reg_table->address[i].s1 =
6118 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6119 i++;
6120 }
6121 }
6122 mc_reg_table->last = (u8)i;
6123 }
6124
si_convert_mc_registers(const struct si_mc_reg_entry * entry,SMC_SIslands_MCRegisterSet * data,u32 num_entries,u32 valid_flag)6125 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6126 SMC_SIslands_MCRegisterSet *data,
6127 u32 num_entries, u32 valid_flag)
6128 {
6129 u32 i, j;
6130
6131 for(i = 0, j = 0; j < num_entries; j++) {
6132 if (valid_flag & (1 << j)) {
6133 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6134 i++;
6135 }
6136 }
6137 }
6138
si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCRegisterSet * mc_reg_table_data)6139 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6140 struct rv7xx_pl *pl,
6141 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6142 {
6143 struct si_power_info *si_pi = si_get_pi(adev);
6144 u32 i = 0;
6145
6146 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6147 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6148 break;
6149 }
6150
6151 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6152 --i;
6153
6154 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6155 mc_reg_table_data, si_pi->mc_reg_table.last,
6156 si_pi->mc_reg_table.valid_flag);
6157 }
6158
si_convert_mc_reg_table_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SMC_SIslands_MCRegisters * mc_reg_table)6159 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6160 struct amdgpu_ps *amdgpu_state,
6161 SMC_SIslands_MCRegisters *mc_reg_table)
6162 {
6163 struct si_ps *state = si_get_ps(amdgpu_state);
6164 int i;
6165
6166 for (i = 0; i < state->performance_level_count; i++) {
6167 si_convert_mc_reg_table_entry_to_smc(adev,
6168 &state->performance_levels[i],
6169 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6170 }
6171 }
6172
si_populate_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_boot_state)6173 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6174 struct amdgpu_ps *amdgpu_boot_state)
6175 {
6176 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6177 struct si_power_info *si_pi = si_get_pi(adev);
6178 struct si_ulv_param *ulv = &si_pi->ulv;
6179 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6180
6181 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6182
6183 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6184
6185 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6186
6187 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6188 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6189
6190 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6191 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6192 si_pi->mc_reg_table.last,
6193 si_pi->mc_reg_table.valid_flag);
6194
6195 if (ulv->supported && ulv->pl.vddc != 0)
6196 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6197 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6198 else
6199 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6200 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6201 si_pi->mc_reg_table.last,
6202 si_pi->mc_reg_table.valid_flag);
6203
6204 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6205
6206 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6207 (u8 *)smc_mc_reg_table,
6208 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6209 }
6210
si_upload_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)6211 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6212 struct amdgpu_ps *amdgpu_new_state)
6213 {
6214 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6215 struct si_power_info *si_pi = si_get_pi(adev);
6216 u32 address = si_pi->mc_reg_table_start +
6217 offsetof(SMC_SIslands_MCRegisters,
6218 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6219 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6220
6221 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6222
6223 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6224
6225 return amdgpu_si_copy_bytes_to_smc(adev, address,
6226 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6227 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6228 si_pi->sram_end);
6229 }
6230
si_enable_voltage_control(struct amdgpu_device * adev,bool enable)6231 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6232 {
6233 if (enable)
6234 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6235 else
6236 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6237 }
6238
si_get_maximum_link_speed(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)6239 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6240 struct amdgpu_ps *amdgpu_state)
6241 {
6242 struct si_ps *state = si_get_ps(amdgpu_state);
6243 int i;
6244 u16 pcie_speed, max_speed = 0;
6245
6246 for (i = 0; i < state->performance_level_count; i++) {
6247 pcie_speed = state->performance_levels[i].pcie_gen;
6248 if (max_speed < pcie_speed)
6249 max_speed = pcie_speed;
6250 }
6251 return max_speed;
6252 }
6253
si_get_current_pcie_speed(struct amdgpu_device * adev)6254 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6255 {
6256 u32 speed_cntl;
6257
6258 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
6259 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
6260
6261 return (u16)speed_cntl;
6262 }
6263
si_request_link_speed_change_before_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6264 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6265 struct amdgpu_ps *amdgpu_new_state,
6266 struct amdgpu_ps *amdgpu_current_state)
6267 {
6268 struct si_power_info *si_pi = si_get_pi(adev);
6269 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6270 enum si_pcie_gen current_link_speed;
6271
6272 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID)
6273 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6274 else
6275 current_link_speed = si_pi->force_pcie_gen;
6276
6277 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
6278 si_pi->pspp_notify_required = false;
6279 if (target_link_speed > current_link_speed) {
6280 switch (target_link_speed) {
6281 #if defined(CONFIG_ACPI)
6282 case SI_PCIE_GEN3:
6283 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6284 break;
6285 si_pi->force_pcie_gen = SI_PCIE_GEN2;
6286 if (current_link_speed == SI_PCIE_GEN2)
6287 break;
6288 fallthrough;
6289 case SI_PCIE_GEN2:
6290 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6291 break;
6292 fallthrough;
6293 #endif
6294 default:
6295 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6296 break;
6297 }
6298 } else {
6299 if (target_link_speed < current_link_speed)
6300 si_pi->pspp_notify_required = true;
6301 }
6302 }
6303
si_notify_link_speed_change_after_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6304 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6305 struct amdgpu_ps *amdgpu_new_state,
6306 struct amdgpu_ps *amdgpu_current_state)
6307 {
6308 struct si_power_info *si_pi = si_get_pi(adev);
6309 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6310 u8 request;
6311
6312 if (si_pi->pspp_notify_required) {
6313 if (target_link_speed == SI_PCIE_GEN3)
6314 request = PCIE_PERF_REQ_PECI_GEN3;
6315 else if (target_link_speed == SI_PCIE_GEN2)
6316 request = PCIE_PERF_REQ_PECI_GEN2;
6317 else
6318 request = PCIE_PERF_REQ_PECI_GEN1;
6319
6320 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6321 (si_get_current_pcie_speed(adev) > 0))
6322 return;
6323
6324 #if defined(CONFIG_ACPI)
6325 amdgpu_acpi_pcie_performance_request(adev, request, false);
6326 #endif
6327 }
6328 }
6329
6330 #if 0
6331 static int si_ds_request(struct amdgpu_device *adev,
6332 bool ds_status_on, u32 count_write)
6333 {
6334 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6335
6336 if (eg_pi->sclk_deep_sleep) {
6337 if (ds_status_on)
6338 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6339 PPSMC_Result_OK) ?
6340 0 : -EINVAL;
6341 else
6342 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6343 PPSMC_Result_OK) ? 0 : -EINVAL;
6344 }
6345 return 0;
6346 }
6347 #endif
6348
si_set_max_cu_value(struct amdgpu_device * adev)6349 static void si_set_max_cu_value(struct amdgpu_device *adev)
6350 {
6351 struct si_power_info *si_pi = si_get_pi(adev);
6352
6353 if (adev->asic_type == CHIP_VERDE) {
6354 switch (adev->pdev->device) {
6355 case 0x6820:
6356 case 0x6825:
6357 case 0x6821:
6358 case 0x6823:
6359 case 0x6827:
6360 si_pi->max_cu = 10;
6361 break;
6362 case 0x682D:
6363 case 0x6824:
6364 case 0x682F:
6365 case 0x6826:
6366 si_pi->max_cu = 8;
6367 break;
6368 case 0x6828:
6369 case 0x6830:
6370 case 0x6831:
6371 case 0x6838:
6372 case 0x6839:
6373 case 0x683D:
6374 si_pi->max_cu = 10;
6375 break;
6376 case 0x683B:
6377 case 0x683F:
6378 case 0x6829:
6379 si_pi->max_cu = 8;
6380 break;
6381 default:
6382 si_pi->max_cu = 0;
6383 break;
6384 }
6385 } else {
6386 si_pi->max_cu = 0;
6387 }
6388 }
6389
si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * table)6390 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6391 struct amdgpu_clock_voltage_dependency_table *table)
6392 {
6393 u32 i;
6394 int j;
6395 u16 leakage_voltage;
6396
6397 if (table) {
6398 for (i = 0; i < table->count; i++) {
6399 switch (si_get_leakage_voltage_from_leakage_index(adev,
6400 table->entries[i].v,
6401 &leakage_voltage)) {
6402 case 0:
6403 table->entries[i].v = leakage_voltage;
6404 break;
6405 case -EAGAIN:
6406 return -EINVAL;
6407 case -EINVAL:
6408 default:
6409 break;
6410 }
6411 }
6412
6413 for (j = (table->count - 2); j >= 0; j--) {
6414 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6415 table->entries[j].v : table->entries[j + 1].v;
6416 }
6417 }
6418 return 0;
6419 }
6420
si_patch_dependency_tables_based_on_leakage(struct amdgpu_device * adev)6421 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6422 {
6423 int ret = 0;
6424
6425 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6426 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6427 if (ret)
6428 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6429 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6430 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6431 if (ret)
6432 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6433 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6434 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6435 if (ret)
6436 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6437 return ret;
6438 }
6439
si_set_pcie_lane_width_in_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6440 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6441 struct amdgpu_ps *amdgpu_new_state,
6442 struct amdgpu_ps *amdgpu_current_state)
6443 {
6444 u32 lane_width;
6445 u32 new_lane_width =
6446 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6447 u32 current_lane_width =
6448 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6449
6450 if (new_lane_width != current_lane_width) {
6451 amdgpu_set_pcie_lanes(adev, new_lane_width);
6452 lane_width = amdgpu_get_pcie_lanes(adev);
6453 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6454 }
6455 }
6456
si_dpm_setup_asic(struct amdgpu_device * adev)6457 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6458 {
6459 si_read_clock_registers(adev);
6460 si_enable_acpi_power_management(adev);
6461 }
6462
si_thermal_enable_alert(struct amdgpu_device * adev,bool enable)6463 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6464 bool enable)
6465 {
6466 u32 thermal_int = RREG32(mmCG_THERMAL_INT);
6467
6468 if (enable) {
6469 PPSMC_Result result;
6470
6471 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK);
6472 WREG32(mmCG_THERMAL_INT, thermal_int);
6473 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6474 if (result != PPSMC_Result_OK) {
6475 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6476 return -EINVAL;
6477 }
6478 } else {
6479 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
6480 WREG32(mmCG_THERMAL_INT, thermal_int);
6481 }
6482
6483 return 0;
6484 }
6485
si_thermal_set_temperature_range(struct amdgpu_device * adev,int min_temp,int max_temp)6486 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6487 int min_temp, int max_temp)
6488 {
6489 int low_temp = 0 * 1000;
6490 int high_temp = 255 * 1000;
6491
6492 if (low_temp < min_temp)
6493 low_temp = min_temp;
6494 if (high_temp > max_temp)
6495 high_temp = max_temp;
6496 if (high_temp < low_temp) {
6497 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6498 return -EINVAL;
6499 }
6500
6501 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK);
6502 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK);
6503 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK);
6504
6505 adev->pm.dpm.thermal.min_temp = low_temp;
6506 adev->pm.dpm.thermal.max_temp = high_temp;
6507
6508 return 0;
6509 }
6510
si_fan_ctrl_set_static_mode(struct amdgpu_device * adev,u32 mode)6511 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6512 {
6513 struct si_power_info *si_pi = si_get_pi(adev);
6514 u32 tmp;
6515
6516 if (si_pi->fan_ctrl_is_in_default_mode) {
6517 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6518 si_pi->fan_ctrl_default_mode = tmp;
6519 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;
6520 si_pi->t_min = tmp;
6521 si_pi->fan_ctrl_is_in_default_mode = false;
6522 }
6523
6524 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6525 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
6526 WREG32(mmCG_FDO_CTRL2, tmp);
6527
6528 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6529 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6530 WREG32(mmCG_FDO_CTRL2, tmp);
6531 }
6532
si_thermal_setup_fan_table(struct amdgpu_device * adev)6533 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6534 {
6535 struct si_power_info *si_pi = si_get_pi(adev);
6536 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6537 u32 duty100;
6538 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6539 u16 fdo_min, slope1, slope2;
6540 u32 reference_clock, tmp;
6541 int ret;
6542 u64 tmp64;
6543
6544 if (!si_pi->fan_table_start) {
6545 adev->pm.dpm.fan.ucode_fan_control = false;
6546 return 0;
6547 }
6548
6549 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6550
6551 if (duty100 == 0) {
6552 adev->pm.dpm.fan.ucode_fan_control = false;
6553 return 0;
6554 }
6555
6556 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6557 do_div(tmp64, 10000);
6558 fdo_min = (u16)tmp64;
6559
6560 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6561 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6562
6563 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6564 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6565
6566 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6567 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6568
6569 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6570 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6571 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6572 fan_table.slope1 = cpu_to_be16(slope1);
6573 fan_table.slope2 = cpu_to_be16(slope2);
6574 fan_table.fdo_min = cpu_to_be16(fdo_min);
6575 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6576 fan_table.hys_up = cpu_to_be16(1);
6577 fan_table.hys_slope = cpu_to_be16(1);
6578 fan_table.temp_resp_lim = cpu_to_be16(5);
6579 reference_clock = amdgpu_asic_get_xclk(adev);
6580
6581 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6582 reference_clock) / 1600);
6583 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6584
6585 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
6586 fan_table.temp_src = (uint8_t)tmp;
6587
6588 ret = amdgpu_si_copy_bytes_to_smc(adev,
6589 si_pi->fan_table_start,
6590 (u8 *)(&fan_table),
6591 sizeof(fan_table),
6592 si_pi->sram_end);
6593
6594 if (ret) {
6595 DRM_ERROR("Failed to load fan table to the SMC.");
6596 adev->pm.dpm.fan.ucode_fan_control = false;
6597 }
6598
6599 return ret;
6600 }
6601
si_fan_ctrl_start_smc_fan_control(struct amdgpu_device * adev)6602 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6603 {
6604 struct si_power_info *si_pi = si_get_pi(adev);
6605 PPSMC_Result ret;
6606
6607 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6608 if (ret == PPSMC_Result_OK) {
6609 si_pi->fan_is_controlled_by_smc = true;
6610 return 0;
6611 } else {
6612 return -EINVAL;
6613 }
6614 }
6615
si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device * adev)6616 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6617 {
6618 struct si_power_info *si_pi = si_get_pi(adev);
6619 PPSMC_Result ret;
6620
6621 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6622
6623 if (ret == PPSMC_Result_OK) {
6624 si_pi->fan_is_controlled_by_smc = false;
6625 return 0;
6626 } else {
6627 return -EINVAL;
6628 }
6629 }
6630
si_dpm_get_fan_speed_pwm(void * handle,u32 * speed)6631 static int si_dpm_get_fan_speed_pwm(void *handle,
6632 u32 *speed)
6633 {
6634 u32 duty, duty100;
6635 u64 tmp64;
6636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6637
6638 if (!speed)
6639 return -EINVAL;
6640
6641 if (adev->pm.no_fan)
6642 return -ENOENT;
6643
6644 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6645 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
6646
6647 if (duty100 == 0)
6648 return -EINVAL;
6649
6650 tmp64 = (u64)duty * 255;
6651 do_div(tmp64, duty100);
6652 *speed = min_t(u32, tmp64, 255);
6653
6654 return 0;
6655 }
6656
si_dpm_set_fan_speed_pwm(void * handle,u32 speed)6657 static int si_dpm_set_fan_speed_pwm(void *handle,
6658 u32 speed)
6659 {
6660 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6661 struct si_power_info *si_pi = si_get_pi(adev);
6662 u32 tmp;
6663 u32 duty, duty100;
6664 u64 tmp64;
6665
6666 if (adev->pm.no_fan)
6667 return -ENOENT;
6668
6669 if (si_pi->fan_is_controlled_by_smc)
6670 return -EINVAL;
6671
6672 if (speed > 255)
6673 return -EINVAL;
6674
6675 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6676
6677 if (duty100 == 0)
6678 return -EINVAL;
6679
6680 tmp64 = (u64)speed * duty100;
6681 do_div(tmp64, 255);
6682 duty = (u32)tmp64;
6683
6684 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
6685 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
6686 WREG32(mmCG_FDO_CTRL0, tmp);
6687
6688 return 0;
6689 }
6690
si_dpm_set_fan_control_mode(void * handle,u32 mode)6691 static int si_dpm_set_fan_control_mode(void *handle, u32 mode)
6692 {
6693 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6694
6695 if (mode == U32_MAX)
6696 return -EINVAL;
6697
6698 if (mode) {
6699 /* stop auto-manage */
6700 if (adev->pm.dpm.fan.ucode_fan_control)
6701 si_fan_ctrl_stop_smc_fan_control(adev);
6702 si_fan_ctrl_set_static_mode(adev, mode);
6703 } else {
6704 /* restart auto-manage */
6705 if (adev->pm.dpm.fan.ucode_fan_control)
6706 si_thermal_start_smc_fan_control(adev);
6707 else
6708 si_fan_ctrl_set_default_mode(adev);
6709 }
6710
6711 return 0;
6712 }
6713
si_dpm_get_fan_control_mode(void * handle,u32 * fan_mode)6714 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode)
6715 {
6716 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6717 struct si_power_info *si_pi = si_get_pi(adev);
6718 u32 tmp;
6719
6720 if (!fan_mode)
6721 return -EINVAL;
6722
6723 if (si_pi->fan_is_controlled_by_smc)
6724 return 0;
6725
6726 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6727 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
6728
6729 return 0;
6730 }
6731
6732 #if 0
6733 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6734 u32 *speed)
6735 {
6736 u32 tach_period;
6737 u32 xclk = amdgpu_asic_get_xclk(adev);
6738
6739 if (adev->pm.no_fan)
6740 return -ENOENT;
6741
6742 if (adev->pm.fan_pulses_per_revolution == 0)
6743 return -ENOENT;
6744
6745 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
6746 if (tach_period == 0)
6747 return -ENOENT;
6748
6749 *speed = 60 * xclk * 10000 / tach_period;
6750
6751 return 0;
6752 }
6753
6754 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6755 u32 speed)
6756 {
6757 u32 tach_period, tmp;
6758 u32 xclk = amdgpu_asic_get_xclk(adev);
6759
6760 if (adev->pm.no_fan)
6761 return -ENOENT;
6762
6763 if (adev->pm.fan_pulses_per_revolution == 0)
6764 return -ENOENT;
6765
6766 if ((speed < adev->pm.fan_min_rpm) ||
6767 (speed > adev->pm.fan_max_rpm))
6768 return -EINVAL;
6769
6770 if (adev->pm.dpm.fan.ucode_fan_control)
6771 si_fan_ctrl_stop_smc_fan_control(adev);
6772
6773 tach_period = 60 * xclk * 10000 / (8 * speed);
6774 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
6775 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
6776 WREG32(mmCG_TACH_CTRL, tmp);
6777
6778 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6779
6780 return 0;
6781 }
6782 #endif
6783
si_fan_ctrl_set_default_mode(struct amdgpu_device * adev)6784 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6785 {
6786 struct si_power_info *si_pi = si_get_pi(adev);
6787 u32 tmp;
6788
6789 if (!si_pi->fan_ctrl_is_in_default_mode) {
6790 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6791 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6792 WREG32(mmCG_FDO_CTRL2, tmp);
6793
6794 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6795 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
6796 WREG32(mmCG_FDO_CTRL2, tmp);
6797 si_pi->fan_ctrl_is_in_default_mode = true;
6798 }
6799 }
6800
si_thermal_start_smc_fan_control(struct amdgpu_device * adev)6801 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6802 {
6803 if (adev->pm.dpm.fan.ucode_fan_control) {
6804 si_fan_ctrl_start_smc_fan_control(adev);
6805 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6806 }
6807 }
6808
si_thermal_initialize(struct amdgpu_device * adev)6809 static void si_thermal_initialize(struct amdgpu_device *adev)
6810 {
6811 u32 tmp;
6812
6813 if (adev->pm.fan_pulses_per_revolution) {
6814 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
6815 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
6816 WREG32(mmCG_TACH_CTRL, tmp);
6817 }
6818
6819 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
6820 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
6821 WREG32(mmCG_FDO_CTRL2, tmp);
6822 }
6823
si_thermal_start_thermal_controller(struct amdgpu_device * adev)6824 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6825 {
6826 int ret;
6827
6828 si_thermal_initialize(adev);
6829 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6830 if (ret)
6831 return ret;
6832 ret = si_thermal_enable_alert(adev, true);
6833 if (ret)
6834 return ret;
6835 if (adev->pm.dpm.fan.ucode_fan_control) {
6836 ret = si_halt_smc(adev);
6837 if (ret)
6838 return ret;
6839 ret = si_thermal_setup_fan_table(adev);
6840 if (ret)
6841 return ret;
6842 ret = si_resume_smc(adev);
6843 if (ret)
6844 return ret;
6845 si_thermal_start_smc_fan_control(adev);
6846 }
6847
6848 return 0;
6849 }
6850
si_thermal_stop_thermal_controller(struct amdgpu_device * adev)6851 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6852 {
6853 if (!adev->pm.no_fan) {
6854 si_fan_ctrl_set_default_mode(adev);
6855 si_fan_ctrl_stop_smc_fan_control(adev);
6856 }
6857 }
6858
si_dpm_enable(struct amdgpu_device * adev)6859 static int si_dpm_enable(struct amdgpu_device *adev)
6860 {
6861 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6862 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6863 struct si_power_info *si_pi = si_get_pi(adev);
6864 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6865 int ret;
6866
6867 if (amdgpu_si_is_smc_running(adev))
6868 return -EINVAL;
6869 if (pi->voltage_control || si_pi->voltage_control_svi2)
6870 si_enable_voltage_control(adev, true);
6871 if (pi->mvdd_control)
6872 si_get_mvdd_configuration(adev);
6873 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6874 ret = si_construct_voltage_tables(adev);
6875 if (ret) {
6876 DRM_ERROR("si_construct_voltage_tables failed\n");
6877 return ret;
6878 }
6879 }
6880 if (eg_pi->dynamic_ac_timing) {
6881 ret = si_initialize_mc_reg_table(adev);
6882 if (ret)
6883 eg_pi->dynamic_ac_timing = false;
6884 }
6885 if (pi->dynamic_ss)
6886 si_enable_spread_spectrum(adev, true);
6887 if (pi->thermal_protection)
6888 si_enable_thermal_protection(adev, true);
6889 si_setup_bsp(adev);
6890 si_program_git(adev);
6891 si_program_tp(adev);
6892 si_program_tpp(adev);
6893 si_program_sstp(adev);
6894 si_enable_display_gap(adev);
6895 si_program_vc(adev);
6896 ret = si_upload_firmware(adev);
6897 if (ret) {
6898 DRM_ERROR("si_upload_firmware failed\n");
6899 return ret;
6900 }
6901 ret = si_process_firmware_header(adev);
6902 if (ret) {
6903 DRM_ERROR("si_process_firmware_header failed\n");
6904 return ret;
6905 }
6906 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6907 if (ret) {
6908 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6909 return ret;
6910 }
6911 ret = si_init_smc_table(adev);
6912 if (ret) {
6913 DRM_ERROR("si_init_smc_table failed\n");
6914 return ret;
6915 }
6916 ret = si_init_smc_spll_table(adev);
6917 if (ret) {
6918 DRM_ERROR("si_init_smc_spll_table failed\n");
6919 return ret;
6920 }
6921 ret = si_init_arb_table_index(adev);
6922 if (ret) {
6923 DRM_ERROR("si_init_arb_table_index failed\n");
6924 return ret;
6925 }
6926 if (eg_pi->dynamic_ac_timing) {
6927 ret = si_populate_mc_reg_table(adev, boot_ps);
6928 if (ret) {
6929 DRM_ERROR("si_populate_mc_reg_table failed\n");
6930 return ret;
6931 }
6932 }
6933 ret = si_initialize_smc_cac_tables(adev);
6934 if (ret) {
6935 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6936 return ret;
6937 }
6938 ret = si_initialize_hardware_cac_manager(adev);
6939 if (ret) {
6940 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6941 return ret;
6942 }
6943 ret = si_initialize_smc_dte_tables(adev);
6944 if (ret) {
6945 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6946 return ret;
6947 }
6948 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6949 if (ret) {
6950 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6951 return ret;
6952 }
6953 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6954 if (ret) {
6955 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6956 return ret;
6957 }
6958 si_program_response_times(adev);
6959 si_program_ds_registers(adev);
6960 si_dpm_start_smc(adev);
6961 ret = si_notify_smc_display_change(adev, false);
6962 if (ret) {
6963 DRM_ERROR("si_notify_smc_display_change failed\n");
6964 return ret;
6965 }
6966 si_enable_sclk_control(adev, true);
6967 si_start_dpm(adev);
6968
6969 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6970 si_thermal_start_thermal_controller(adev);
6971
6972 ni_update_current_ps(adev, boot_ps);
6973
6974 return 0;
6975 }
6976
si_set_temperature_range(struct amdgpu_device * adev)6977 static int si_set_temperature_range(struct amdgpu_device *adev)
6978 {
6979 int ret;
6980
6981 ret = si_thermal_enable_alert(adev, false);
6982 if (ret)
6983 return ret;
6984 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6985 if (ret)
6986 return ret;
6987 ret = si_thermal_enable_alert(adev, true);
6988 if (ret)
6989 return ret;
6990
6991 return ret;
6992 }
6993
si_dpm_disable(struct amdgpu_device * adev)6994 static void si_dpm_disable(struct amdgpu_device *adev)
6995 {
6996 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6997 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6998
6999 if (!amdgpu_si_is_smc_running(adev))
7000 return;
7001 si_thermal_stop_thermal_controller(adev);
7002 si_disable_ulv(adev);
7003 si_clear_vc(adev);
7004 if (pi->thermal_protection)
7005 si_enable_thermal_protection(adev, false);
7006 si_enable_power_containment(adev, boot_ps, false);
7007 si_enable_smc_cac(adev, boot_ps, false);
7008 si_enable_spread_spectrum(adev, false);
7009 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
7010 si_stop_dpm(adev);
7011 si_reset_to_default(adev);
7012 si_dpm_stop_smc(adev);
7013 si_force_switch_to_arb_f0(adev);
7014
7015 ni_update_current_ps(adev, boot_ps);
7016 }
7017
si_dpm_pre_set_power_state(void * handle)7018 static int si_dpm_pre_set_power_state(void *handle)
7019 {
7020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7021 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7022 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
7023 struct amdgpu_ps *new_ps = &requested_ps;
7024
7025 ni_update_requested_ps(adev, new_ps);
7026 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7027
7028 return 0;
7029 }
7030
si_power_control_set_level(struct amdgpu_device * adev)7031 static int si_power_control_set_level(struct amdgpu_device *adev)
7032 {
7033 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7034 int ret;
7035
7036 ret = si_restrict_performance_levels_before_switch(adev);
7037 if (ret)
7038 return ret;
7039 ret = si_halt_smc(adev);
7040 if (ret)
7041 return ret;
7042 ret = si_populate_smc_tdp_limits(adev, new_ps);
7043 if (ret)
7044 return ret;
7045 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7046 if (ret)
7047 return ret;
7048 ret = si_resume_smc(adev);
7049 if (ret)
7050 return ret;
7051 return si_set_sw_state(adev);
7052 }
7053
si_set_vce_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_rps,struct amdgpu_ps * old_rps)7054 static void si_set_vce_clock(struct amdgpu_device *adev,
7055 struct amdgpu_ps *new_rps,
7056 struct amdgpu_ps *old_rps)
7057 {
7058 if ((old_rps->evclk != new_rps->evclk) ||
7059 (old_rps->ecclk != new_rps->ecclk)) {
7060 /* Turn the clocks on when encoding, off otherwise */
7061 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk);
7062
7063 if (new_rps->evclk || new_rps->ecclk) {
7064 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);
7065 amdgpu_device_ip_set_clockgating_state(
7066 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE);
7067 amdgpu_device_ip_set_powergating_state(
7068 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE);
7069 } else {
7070 amdgpu_device_ip_set_powergating_state(
7071 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE);
7072 amdgpu_device_ip_set_clockgating_state(
7073 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE);
7074 amdgpu_asic_set_vce_clocks(adev, 0, 0);
7075 }
7076 }
7077 }
7078
si_dpm_set_power_state(void * handle)7079 static int si_dpm_set_power_state(void *handle)
7080 {
7081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7082 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7083 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7084 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7085 int ret;
7086
7087 ret = si_disable_ulv(adev);
7088 if (ret) {
7089 DRM_ERROR("si_disable_ulv failed\n");
7090 return ret;
7091 }
7092 ret = si_restrict_performance_levels_before_switch(adev);
7093 if (ret) {
7094 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7095 return ret;
7096 }
7097 if (eg_pi->pcie_performance_request)
7098 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7099 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7100 ret = si_enable_power_containment(adev, new_ps, false);
7101 if (ret) {
7102 DRM_ERROR("si_enable_power_containment failed\n");
7103 return ret;
7104 }
7105 ret = si_enable_smc_cac(adev, new_ps, false);
7106 if (ret) {
7107 DRM_ERROR("si_enable_smc_cac failed\n");
7108 return ret;
7109 }
7110 ret = si_halt_smc(adev);
7111 if (ret) {
7112 DRM_ERROR("si_halt_smc failed\n");
7113 return ret;
7114 }
7115 ret = si_upload_sw_state(adev, new_ps);
7116 if (ret) {
7117 DRM_ERROR("si_upload_sw_state failed\n");
7118 return ret;
7119 }
7120 ret = si_upload_smc_data(adev);
7121 if (ret) {
7122 DRM_ERROR("si_upload_smc_data failed\n");
7123 return ret;
7124 }
7125 ret = si_upload_ulv_state(adev);
7126 if (ret) {
7127 DRM_ERROR("si_upload_ulv_state failed\n");
7128 return ret;
7129 }
7130 if (eg_pi->dynamic_ac_timing) {
7131 ret = si_upload_mc_reg_table(adev, new_ps);
7132 if (ret) {
7133 DRM_ERROR("si_upload_mc_reg_table failed\n");
7134 return ret;
7135 }
7136 }
7137 ret = si_program_memory_timing_parameters(adev, new_ps);
7138 if (ret) {
7139 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7140 return ret;
7141 }
7142 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7143
7144 ret = si_resume_smc(adev);
7145 if (ret) {
7146 DRM_ERROR("si_resume_smc failed\n");
7147 return ret;
7148 }
7149 ret = si_set_sw_state(adev);
7150 if (ret) {
7151 DRM_ERROR("si_set_sw_state failed\n");
7152 return ret;
7153 }
7154 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7155 si_set_vce_clock(adev, new_ps, old_ps);
7156 if (eg_pi->pcie_performance_request)
7157 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7158 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7159 if (ret) {
7160 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7161 return ret;
7162 }
7163 ret = si_enable_smc_cac(adev, new_ps, true);
7164 if (ret) {
7165 DRM_ERROR("si_enable_smc_cac failed\n");
7166 return ret;
7167 }
7168 ret = si_enable_power_containment(adev, new_ps, true);
7169 if (ret) {
7170 DRM_ERROR("si_enable_power_containment failed\n");
7171 return ret;
7172 }
7173
7174 ret = si_power_control_set_level(adev);
7175 if (ret) {
7176 DRM_ERROR("si_power_control_set_level failed\n");
7177 return ret;
7178 }
7179
7180 return 0;
7181 }
7182
si_dpm_post_set_power_state(void * handle)7183 static void si_dpm_post_set_power_state(void *handle)
7184 {
7185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7186 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7187 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7188
7189 ni_update_current_ps(adev, new_ps);
7190 }
7191
7192 #if 0
7193 void si_dpm_reset_asic(struct amdgpu_device *adev)
7194 {
7195 si_restrict_performance_levels_before_switch(adev);
7196 si_disable_ulv(adev);
7197 si_set_boot_state(adev);
7198 }
7199 #endif
7200
si_dpm_display_configuration_changed(void * handle)7201 static void si_dpm_display_configuration_changed(void *handle)
7202 {
7203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7204
7205 si_program_display_gap(adev);
7206 }
7207
7208
si_parse_pplib_non_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)7209 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7210 struct amdgpu_ps *rps,
7211 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7212 u8 table_rev)
7213 {
7214 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7215 rps->class = le16_to_cpu(non_clock_info->usClassification);
7216 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7217
7218 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7219 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7220 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7221 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7222 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7223 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7224 } else {
7225 rps->vclk = 0;
7226 rps->dclk = 0;
7227 }
7228
7229 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7230 adev->pm.dpm.boot_ps = rps;
7231 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7232 adev->pm.dpm.uvd_ps = rps;
7233 }
7234
si_parse_pplib_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,int index,union pplib_clock_info * clock_info)7235 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7236 struct amdgpu_ps *rps, int index,
7237 union pplib_clock_info *clock_info)
7238 {
7239 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7240 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7241 struct si_power_info *si_pi = si_get_pi(adev);
7242 struct si_ps *ps = si_get_ps(rps);
7243 u16 leakage_voltage;
7244 struct rv7xx_pl *pl = &ps->performance_levels[index];
7245 int ret;
7246
7247 ps->performance_level_count = index + 1;
7248
7249 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7250 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7251 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7252 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7253
7254 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7255 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7256 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7257 pl->pcie_gen = si_gen_pcie_gen_support(adev,
7258 si_pi->sys_pcie_mask,
7259 si_pi->boot_pcie_gen,
7260 clock_info->si.ucPCIEGen);
7261
7262 /* patch up vddc if necessary */
7263 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7264 &leakage_voltage);
7265 if (ret == 0)
7266 pl->vddc = leakage_voltage;
7267
7268 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7269 pi->acpi_vddc = pl->vddc;
7270 eg_pi->acpi_vddci = pl->vddci;
7271 si_pi->acpi_pcie_gen = pl->pcie_gen;
7272 }
7273
7274 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7275 index == 0) {
7276 /* XXX disable for A0 tahiti */
7277 si_pi->ulv.supported = false;
7278 si_pi->ulv.pl = *pl;
7279 si_pi->ulv.one_pcie_lane_in_ulv = false;
7280 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7281 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7282 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7283 }
7284
7285 if (pi->min_vddc_in_table > pl->vddc)
7286 pi->min_vddc_in_table = pl->vddc;
7287
7288 if (pi->max_vddc_in_table < pl->vddc)
7289 pi->max_vddc_in_table = pl->vddc;
7290
7291 /* patch up boot state */
7292 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7293 u16 vddc, vddci, mvdd;
7294 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7295 pl->mclk = adev->clock.default_mclk;
7296 pl->sclk = adev->clock.default_sclk;
7297 pl->vddc = vddc;
7298 pl->vddci = vddci;
7299 si_pi->mvdd_bootup_value = mvdd;
7300 }
7301
7302 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7303 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7304 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7305 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7306 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7307 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7308 }
7309 }
7310
7311 union pplib_power_state {
7312 struct _ATOM_PPLIB_STATE v1;
7313 struct _ATOM_PPLIB_STATE_V2 v2;
7314 };
7315
si_parse_power_table(struct amdgpu_device * adev)7316 static int si_parse_power_table(struct amdgpu_device *adev)
7317 {
7318 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7319 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7320 union pplib_power_state *power_state;
7321 int i, j, k, non_clock_array_index, clock_array_index;
7322 union pplib_clock_info *clock_info;
7323 struct _StateArray *state_array;
7324 struct _ClockInfoArray *clock_info_array;
7325 struct _NonClockInfoArray *non_clock_info_array;
7326 union power_info *power_info;
7327 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7328 u16 data_offset;
7329 u8 frev, crev;
7330 u8 *power_state_offset;
7331 struct si_ps *ps;
7332
7333 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7334 &frev, &crev, &data_offset))
7335 return -EINVAL;
7336 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7337
7338 amdgpu_add_thermal_controller(adev);
7339
7340 state_array = (struct _StateArray *)
7341 (mode_info->atom_context->bios + data_offset +
7342 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7343 clock_info_array = (struct _ClockInfoArray *)
7344 (mode_info->atom_context->bios + data_offset +
7345 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7346 non_clock_info_array = (struct _NonClockInfoArray *)
7347 (mode_info->atom_context->bios + data_offset +
7348 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7349
7350 adev->pm.dpm.ps = kzalloc_objs(struct amdgpu_ps,
7351 state_array->ucNumEntries);
7352 if (!adev->pm.dpm.ps)
7353 return -ENOMEM;
7354 power_state_offset = (u8 *)state_array->states;
7355 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) {
7356 u8 *idx;
7357 power_state = (union pplib_power_state *)power_state_offset;
7358 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7359 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7360 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7361 ps = kzalloc_obj(struct si_ps);
7362 if (ps == NULL)
7363 return -ENOMEM;
7364 adev->pm.dpm.ps[i].ps_priv = ps;
7365 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7366 non_clock_info,
7367 non_clock_info_array->ucEntrySize);
7368 k = 0;
7369 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7370 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7371 clock_array_index = idx[j];
7372 if (clock_array_index >= clock_info_array->ucNumEntries)
7373 continue;
7374 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7375 break;
7376 clock_info = (union pplib_clock_info *)
7377 ((u8 *)&clock_info_array->clockInfo[0] +
7378 (clock_array_index * clock_info_array->ucEntrySize));
7379 si_parse_pplib_clock_info(adev,
7380 &adev->pm.dpm.ps[i], k,
7381 clock_info);
7382 k++;
7383 }
7384 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7385 adev->pm.dpm.num_ps++;
7386 }
7387
7388 /* fill in the vce power states */
7389 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7390 u32 sclk, mclk;
7391 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7392 clock_info = (union pplib_clock_info *)
7393 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7394 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7395 sclk |= clock_info->si.ucEngineClockHigh << 16;
7396 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7397 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7398 adev->pm.dpm.vce_states[i].sclk = sclk;
7399 adev->pm.dpm.vce_states[i].mclk = mclk;
7400 }
7401
7402 return 0;
7403 }
7404
si_dpm_init(struct amdgpu_device * adev)7405 static int si_dpm_init(struct amdgpu_device *adev)
7406 {
7407 struct rv7xx_power_info *pi;
7408 struct evergreen_power_info *eg_pi;
7409 struct ni_power_info *ni_pi;
7410 struct si_power_info *si_pi;
7411 struct atom_clock_dividers dividers;
7412 int ret;
7413
7414 si_pi = kzalloc_obj(struct si_power_info);
7415 if (si_pi == NULL)
7416 return -ENOMEM;
7417 adev->pm.dpm.priv = si_pi;
7418 ni_pi = &si_pi->ni;
7419 eg_pi = &ni_pi->eg;
7420 pi = &eg_pi->rv7xx;
7421
7422 si_pi->sys_pcie_mask =
7423 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7424 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
7425 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7426
7427 si_set_max_cu_value(adev);
7428
7429 rv770_get_max_vddc(adev);
7430 si_get_leakage_vddc(adev);
7431 si_patch_dependency_tables_based_on_leakage(adev);
7432
7433 pi->acpi_vddc = 0;
7434 eg_pi->acpi_vddci = 0;
7435 pi->min_vddc_in_table = 0;
7436 pi->max_vddc_in_table = 0;
7437
7438 ret = amdgpu_get_platform_caps(adev);
7439 if (ret)
7440 return ret;
7441
7442 ret = amdgpu_parse_extended_power_table(adev);
7443 if (ret)
7444 return ret;
7445
7446 ret = si_parse_power_table(adev);
7447 if (ret)
7448 return ret;
7449
7450 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7451 kzalloc_objs(struct amdgpu_clock_voltage_dependency_entry, 4);
7452 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)
7453 return -ENOMEM;
7454
7455 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7456 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7457 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7458 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7459 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7460 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7461 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7462 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7463 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7464
7465 if (adev->pm.dpm.voltage_response_time == 0)
7466 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7467 if (adev->pm.dpm.backbias_response_time == 0)
7468 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7469
7470 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7471 0, false, ÷rs);
7472 if (ret)
7473 pi->ref_div = dividers.ref_div + 1;
7474 else
7475 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7476
7477 eg_pi->smu_uvd_hs = false;
7478
7479 pi->mclk_strobe_mode_threshold = 40000;
7480 if (si_is_special_1gb_platform(adev))
7481 pi->mclk_stutter_mode_threshold = 0;
7482 else
7483 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7484 pi->mclk_edc_enable_threshold = 40000;
7485 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7486
7487 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7488
7489 pi->voltage_control =
7490 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7491 VOLTAGE_OBJ_GPIO_LUT);
7492 if (!pi->voltage_control) {
7493 si_pi->voltage_control_svi2 =
7494 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7495 VOLTAGE_OBJ_SVID2);
7496 if (si_pi->voltage_control_svi2)
7497 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7498 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7499 }
7500
7501 pi->mvdd_control =
7502 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7503 VOLTAGE_OBJ_GPIO_LUT);
7504
7505 eg_pi->vddci_control =
7506 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7507 VOLTAGE_OBJ_GPIO_LUT);
7508 if (!eg_pi->vddci_control)
7509 si_pi->vddci_control_svi2 =
7510 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7511 VOLTAGE_OBJ_SVID2);
7512
7513 si_pi->vddc_phase_shed_control =
7514 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7515 VOLTAGE_OBJ_PHASE_LUT);
7516
7517 rv770_get_engine_memory_ss(adev);
7518
7519 pi->asi = RV770_ASI_DFLT;
7520 pi->pasi = CYPRESS_HASI_DFLT;
7521 pi->vrc = SISLANDS_VRC_DFLT;
7522
7523 eg_pi->sclk_deep_sleep = true;
7524 si_pi->sclk_deep_sleep_above_low = false;
7525
7526 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7527 pi->thermal_protection = true;
7528 else
7529 pi->thermal_protection = false;
7530
7531 eg_pi->dynamic_ac_timing = true;
7532
7533 #if defined(CONFIG_ACPI)
7534 eg_pi->pcie_performance_request =
7535 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7536 #else
7537 eg_pi->pcie_performance_request = false;
7538 #endif
7539
7540 si_pi->sram_end = SMC_RAM_END;
7541
7542 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7543 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7544 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7545 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7546 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7547 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7548 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7549
7550 si_initialize_powertune_defaults(adev);
7551
7552 /* make sure dc limits are valid */
7553 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7554 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7555 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7556 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7557
7558 si_pi->fan_ctrl_is_in_default_mode = true;
7559
7560 return 0;
7561 }
7562
si_dpm_fini(struct amdgpu_device * adev)7563 static void si_dpm_fini(struct amdgpu_device *adev)
7564 {
7565 int i;
7566
7567 if (adev->pm.dpm.ps)
7568 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7569 kfree(adev->pm.dpm.ps[i].ps_priv);
7570 kfree(adev->pm.dpm.ps);
7571 kfree(adev->pm.dpm.priv);
7572 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7573 amdgpu_free_extended_power_table(adev);
7574 }
7575
si_dpm_debugfs_print_current_performance_level(void * handle,struct seq_file * m)7576 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7577 struct seq_file *m)
7578 {
7579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7580 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7581 struct amdgpu_ps *rps = &eg_pi->current_rps;
7582 struct si_ps *ps = si_get_ps(rps);
7583 struct rv7xx_pl *pl;
7584 u32 current_index =
7585 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
7586 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
7587
7588 if (current_index >= ps->performance_level_count) {
7589 seq_printf(m, "invalid dpm profile %d\n", current_index);
7590 } else {
7591 pl = &ps->performance_levels[current_index];
7592 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7593 seq_printf(m, "vce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7594 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7595 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7596 }
7597 }
7598
si_dpm_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)7599 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7600 struct amdgpu_irq_src *source,
7601 unsigned type,
7602 enum amdgpu_interrupt_state state)
7603 {
7604 u32 cg_thermal_int;
7605
7606 switch (type) {
7607 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7608 switch (state) {
7609 case AMDGPU_IRQ_STATE_DISABLE:
7610 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7611 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7612 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7613 break;
7614 case AMDGPU_IRQ_STATE_ENABLE:
7615 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7616 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7617 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7618 break;
7619 default:
7620 break;
7621 }
7622 break;
7623
7624 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7625 switch (state) {
7626 case AMDGPU_IRQ_STATE_DISABLE:
7627 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7628 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7629 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7630 break;
7631 case AMDGPU_IRQ_STATE_ENABLE:
7632 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7633 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7634 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7635 break;
7636 default:
7637 break;
7638 }
7639 break;
7640
7641 default:
7642 break;
7643 }
7644 return 0;
7645 }
7646
si_dpm_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)7647 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7648 struct amdgpu_irq_src *source,
7649 struct amdgpu_iv_entry *entry)
7650 {
7651 bool queue_thermal = false;
7652
7653 if (entry == NULL)
7654 return -EINVAL;
7655
7656 switch (entry->src_id) {
7657 case 230: /* thermal low to high */
7658 DRM_DEBUG("IH: thermal low to high\n");
7659 adev->pm.dpm.thermal.high_to_low = false;
7660 queue_thermal = true;
7661 break;
7662 case 231: /* thermal high to low */
7663 DRM_DEBUG("IH: thermal high to low\n");
7664 adev->pm.dpm.thermal.high_to_low = true;
7665 queue_thermal = true;
7666 break;
7667 default:
7668 break;
7669 }
7670
7671 if (queue_thermal)
7672 schedule_work(&adev->pm.dpm.thermal.work);
7673
7674 return 0;
7675 }
7676
si_dpm_late_init(struct amdgpu_ip_block * ip_block)7677 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block)
7678 {
7679 int ret;
7680 struct amdgpu_device *adev = ip_block->adev;
7681
7682 if (!adev->pm.dpm_enabled)
7683 return 0;
7684
7685 ret = si_set_temperature_range(adev);
7686 if (ret)
7687 return ret;
7688 #if 0 //TODO ?
7689 si_dpm_powergate_uvd(adev, true);
7690 #endif
7691 return 0;
7692 }
7693
7694 /**
7695 * si_dpm_init_microcode - load ucode images from disk
7696 *
7697 * @adev: amdgpu_device pointer
7698 *
7699 * Use the firmware interface to load the ucode images into
7700 * the driver (not loaded into hw).
7701 * Returns 0 on success, error on failure.
7702 */
si_dpm_init_microcode(struct amdgpu_device * adev)7703 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7704 {
7705 const char *chip_name;
7706 int err;
7707
7708 DRM_DEBUG("\n");
7709 switch (adev->asic_type) {
7710 case CHIP_TAHITI:
7711 chip_name = "tahiti";
7712 break;
7713 case CHIP_PITCAIRN:
7714 if ((adev->pdev->revision == 0x81) &&
7715 ((adev->pdev->device == 0x6810) ||
7716 (adev->pdev->device == 0x6811)))
7717 chip_name = "pitcairn_k";
7718 else
7719 chip_name = "pitcairn";
7720 break;
7721 case CHIP_VERDE:
7722 if (((adev->pdev->device == 0x6820) &&
7723 ((adev->pdev->revision == 0x81) ||
7724 (adev->pdev->revision == 0x83))) ||
7725 ((adev->pdev->device == 0x6821) &&
7726 ((adev->pdev->revision == 0x83) ||
7727 (adev->pdev->revision == 0x87))) ||
7728 ((adev->pdev->revision == 0x87) &&
7729 ((adev->pdev->device == 0x6823) ||
7730 (adev->pdev->device == 0x682b))))
7731 chip_name = "verde_k";
7732 else
7733 chip_name = "verde";
7734 break;
7735 case CHIP_OLAND:
7736 if (((adev->pdev->revision == 0x81) &&
7737 ((adev->pdev->device == 0x6600) ||
7738 (adev->pdev->device == 0x6604) ||
7739 (adev->pdev->device == 0x6605) ||
7740 (adev->pdev->device == 0x6610))) ||
7741 ((adev->pdev->revision == 0x83) &&
7742 (adev->pdev->device == 0x6610)))
7743 chip_name = "oland_k";
7744 else
7745 chip_name = "oland";
7746 break;
7747 case CHIP_HAINAN:
7748 if (((adev->pdev->revision == 0x81) &&
7749 (adev->pdev->device == 0x6660)) ||
7750 ((adev->pdev->revision == 0x83) &&
7751 ((adev->pdev->device == 0x6660) ||
7752 (adev->pdev->device == 0x6663) ||
7753 (adev->pdev->device == 0x6665) ||
7754 (adev->pdev->device == 0x6667))))
7755 chip_name = "hainan_k";
7756 else if ((adev->pdev->revision == 0xc3) &&
7757 (adev->pdev->device == 0x6665))
7758 chip_name = "banks_k_2";
7759 else
7760 chip_name = "hainan";
7761 break;
7762 default: BUG();
7763 }
7764
7765 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
7766 "amdgpu/%s_smc.bin", chip_name);
7767 if (err) {
7768 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n",
7769 err, chip_name);
7770 amdgpu_ucode_release(&adev->pm.fw);
7771 }
7772 return err;
7773 }
7774
si_dpm_sw_init(struct amdgpu_ip_block * ip_block)7775 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block)
7776 {
7777 int ret;
7778 struct amdgpu_device *adev = ip_block->adev;
7779
7780 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7781 if (ret)
7782 return ret;
7783
7784 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7785 if (ret)
7786 return ret;
7787
7788 /* default to balanced state */
7789 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7790 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7791 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7792 adev->pm.default_sclk = adev->clock.default_sclk;
7793 adev->pm.default_mclk = adev->clock.default_mclk;
7794 adev->pm.current_sclk = adev->clock.default_sclk;
7795 adev->pm.current_mclk = adev->clock.default_mclk;
7796 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7797
7798 if (amdgpu_dpm == 0)
7799 return 0;
7800
7801 ret = si_dpm_init_microcode(adev);
7802 if (ret)
7803 return ret;
7804
7805 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7806 ret = si_dpm_init(adev);
7807 if (ret)
7808 goto dpm_failed;
7809 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7810 if (amdgpu_dpm == 1)
7811 amdgpu_pm_print_power_states(adev);
7812 drm_info(adev_to_drm(adev), "si dpm initialized\n");
7813 return 0;
7814
7815 dpm_failed:
7816 si_dpm_fini(adev);
7817 drm_err(adev_to_drm(adev), "dpm initialization failed\n");
7818 return ret;
7819 }
7820
si_dpm_sw_fini(struct amdgpu_ip_block * ip_block)7821 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block)
7822 {
7823 struct amdgpu_device *adev = ip_block->adev;
7824
7825 flush_work(&adev->pm.dpm.thermal.work);
7826
7827 si_dpm_fini(adev);
7828
7829 return 0;
7830 }
7831
si_dpm_hw_init(struct amdgpu_ip_block * ip_block)7832 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block)
7833 {
7834 int ret;
7835
7836 struct amdgpu_device *adev = ip_block->adev;
7837
7838 if (!amdgpu_dpm)
7839 return 0;
7840
7841 mutex_lock(&adev->pm.mutex);
7842 si_dpm_setup_asic(adev);
7843 ret = si_dpm_enable(adev);
7844 if (ret)
7845 adev->pm.dpm_enabled = false;
7846 else
7847 adev->pm.dpm_enabled = true;
7848 amdgpu_legacy_dpm_compute_clocks(adev);
7849 mutex_unlock(&adev->pm.mutex);
7850 return ret;
7851 }
7852
si_dpm_hw_fini(struct amdgpu_ip_block * ip_block)7853 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block)
7854 {
7855 struct amdgpu_device *adev = ip_block->adev;
7856
7857 if (adev->pm.dpm_enabled)
7858 si_dpm_disable(adev);
7859
7860 return 0;
7861 }
7862
si_dpm_suspend(struct amdgpu_ip_block * ip_block)7863 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block)
7864 {
7865 struct amdgpu_device *adev = ip_block->adev;
7866
7867 cancel_work_sync(&adev->pm.dpm.thermal.work);
7868
7869 if (adev->pm.dpm_enabled) {
7870 mutex_lock(&adev->pm.mutex);
7871 adev->pm.dpm_enabled = false;
7872 /* disable dpm */
7873 si_dpm_disable(adev);
7874 /* reset the power state */
7875 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7876 mutex_unlock(&adev->pm.mutex);
7877 }
7878
7879 return 0;
7880 }
7881
si_dpm_resume(struct amdgpu_ip_block * ip_block)7882 static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
7883 {
7884 int ret = 0;
7885 struct amdgpu_device *adev = ip_block->adev;
7886
7887 if (!amdgpu_dpm)
7888 return 0;
7889
7890 if (!adev->pm.dpm_enabled) {
7891 /* asic init will reset to the boot state */
7892 mutex_lock(&adev->pm.mutex);
7893 si_dpm_setup_asic(adev);
7894 ret = si_dpm_enable(adev);
7895 if (ret) {
7896 adev->pm.dpm_enabled = false;
7897 } else {
7898 adev->pm.dpm_enabled = true;
7899 amdgpu_legacy_dpm_compute_clocks(adev);
7900 }
7901 mutex_unlock(&adev->pm.mutex);
7902 }
7903
7904 return ret;
7905 }
7906
si_dpm_is_idle(struct amdgpu_ip_block * ip_block)7907 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
7908 {
7909 /* XXX */
7910 return true;
7911 }
7912
si_dpm_wait_for_idle(struct amdgpu_ip_block * ip_block)7913 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block)
7914 {
7915 /* XXX */
7916 return 0;
7917 }
7918
si_dpm_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)7919 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
7920 enum amd_clockgating_state state)
7921 {
7922 return 0;
7923 }
7924
si_dpm_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)7925 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
7926 enum amd_powergating_state state)
7927 {
7928 return 0;
7929 }
7930
7931 /* get temperature in millidegrees */
si_dpm_get_temp(void * handle)7932 static int si_dpm_get_temp(void *handle)
7933 {
7934 u32 temp;
7935 int actual_temp = 0;
7936 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7937
7938 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
7939 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
7940
7941 if (temp & 0x200)
7942 actual_temp = 255;
7943 else
7944 actual_temp = temp & 0x1ff;
7945
7946 actual_temp = (actual_temp * 1000);
7947
7948 return actual_temp;
7949 }
7950
si_dpm_get_sclk(void * handle,bool low)7951 static u32 si_dpm_get_sclk(void *handle, bool low)
7952 {
7953 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7954 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7955 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7956
7957 if (low)
7958 return requested_state->performance_levels[0].sclk;
7959 else
7960 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7961 }
7962
si_dpm_get_mclk(void * handle,bool low)7963 static u32 si_dpm_get_mclk(void *handle, bool low)
7964 {
7965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7966 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7967 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7968
7969 if (low)
7970 return requested_state->performance_levels[0].mclk;
7971 else
7972 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7973 }
7974
si_dpm_print_power_state(void * handle,void * current_ps)7975 static void si_dpm_print_power_state(void *handle,
7976 void *current_ps)
7977 {
7978 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7979 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7980 struct si_ps *ps = si_get_ps(rps);
7981 struct rv7xx_pl *pl;
7982 int i;
7983
7984 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
7985 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
7986 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7987 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7988 for (i = 0; i < ps->performance_level_count; i++) {
7989 pl = &ps->performance_levels[i];
7990 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7991 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7992 }
7993 amdgpu_dpm_dbg_print_ps_status(adev, rps);
7994 }
7995
si_dpm_early_init(struct amdgpu_ip_block * ip_block)7996 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block)
7997 {
7998
7999 struct amdgpu_device *adev = ip_block->adev;
8000
8001 adev->powerplay.pp_funcs = &si_dpm_funcs;
8002 adev->powerplay.pp_handle = adev;
8003 si_dpm_set_irq_funcs(adev);
8004 return 0;
8005 }
8006
si_are_power_levels_equal(const struct rv7xx_pl * si_cpl1,const struct rv7xx_pl * si_cpl2)8007 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
8008 const struct rv7xx_pl *si_cpl2)
8009 {
8010 return ((si_cpl1->mclk == si_cpl2->mclk) &&
8011 (si_cpl1->sclk == si_cpl2->sclk) &&
8012 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
8013 (si_cpl1->vddc == si_cpl2->vddc) &&
8014 (si_cpl1->vddci == si_cpl2->vddci));
8015 }
8016
si_check_state_equal(void * handle,void * current_ps,void * request_ps,bool * equal)8017 static int si_check_state_equal(void *handle,
8018 void *current_ps,
8019 void *request_ps,
8020 bool *equal)
8021 {
8022 struct si_ps *si_cps;
8023 struct si_ps *si_rps;
8024 int i;
8025 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
8026 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
8027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8028
8029 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
8030 return -EINVAL;
8031
8032 si_cps = si_get_ps((struct amdgpu_ps *)cps);
8033 si_rps = si_get_ps((struct amdgpu_ps *)rps);
8034
8035 if (si_cps == NULL) {
8036 printk("si_cps is NULL\n");
8037 *equal = false;
8038 return 0;
8039 }
8040
8041 if (si_cps->performance_level_count != si_rps->performance_level_count) {
8042 *equal = false;
8043 return 0;
8044 }
8045
8046 for (i = 0; i < si_cps->performance_level_count; i++) {
8047 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8048 &(si_rps->performance_levels[i]))) {
8049 *equal = false;
8050 return 0;
8051 }
8052 }
8053
8054 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8055 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8056 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8057
8058 return 0;
8059 }
8060
si_dpm_read_sensor(void * handle,int idx,void * value,int * size)8061 static int si_dpm_read_sensor(void *handle, int idx,
8062 void *value, int *size)
8063 {
8064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8065 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
8066 struct amdgpu_ps *rps = &eg_pi->current_rps;
8067 struct si_ps *ps = si_get_ps(rps);
8068 uint32_t sclk, mclk;
8069 u32 pl_index =
8070 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
8071 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
8072
8073 /* size must be at least 4 bytes for all sensors */
8074 if (*size < 4)
8075 return -EINVAL;
8076
8077 switch (idx) {
8078 case AMDGPU_PP_SENSOR_GFX_SCLK:
8079 if (pl_index < ps->performance_level_count) {
8080 sclk = ps->performance_levels[pl_index].sclk;
8081 *((uint32_t *)value) = sclk;
8082 *size = 4;
8083 return 0;
8084 }
8085 return -EINVAL;
8086 case AMDGPU_PP_SENSOR_GFX_MCLK:
8087 if (pl_index < ps->performance_level_count) {
8088 mclk = ps->performance_levels[pl_index].mclk;
8089 *((uint32_t *)value) = mclk;
8090 *size = 4;
8091 return 0;
8092 }
8093 return -EINVAL;
8094 case AMDGPU_PP_SENSOR_GPU_TEMP:
8095 *((uint32_t *)value) = si_dpm_get_temp(adev);
8096 *size = 4;
8097 return 0;
8098 default:
8099 return -EOPNOTSUPP;
8100 }
8101 }
8102
8103 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8104 .name = "si_dpm",
8105 .early_init = si_dpm_early_init,
8106 .late_init = si_dpm_late_init,
8107 .sw_init = si_dpm_sw_init,
8108 .sw_fini = si_dpm_sw_fini,
8109 .hw_init = si_dpm_hw_init,
8110 .hw_fini = si_dpm_hw_fini,
8111 .suspend = si_dpm_suspend,
8112 .resume = si_dpm_resume,
8113 .is_idle = si_dpm_is_idle,
8114 .wait_for_idle = si_dpm_wait_for_idle,
8115 .set_clockgating_state = si_dpm_set_clockgating_state,
8116 .set_powergating_state = si_dpm_set_powergating_state,
8117 };
8118
8119 const struct amdgpu_ip_block_version si_smu_ip_block =
8120 {
8121 .type = AMD_IP_BLOCK_TYPE_SMC,
8122 .major = 6,
8123 .minor = 0,
8124 .rev = 0,
8125 .funcs = &si_dpm_ip_funcs,
8126 };
8127
8128 static const struct amd_pm_funcs si_dpm_funcs = {
8129 .pre_set_power_state = &si_dpm_pre_set_power_state,
8130 .set_power_state = &si_dpm_set_power_state,
8131 .post_set_power_state = &si_dpm_post_set_power_state,
8132 .display_configuration_changed = &si_dpm_display_configuration_changed,
8133 .get_sclk = &si_dpm_get_sclk,
8134 .get_mclk = &si_dpm_get_mclk,
8135 .print_power_state = &si_dpm_print_power_state,
8136 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8137 .force_performance_level = &si_dpm_force_performance_level,
8138 .vblank_too_short = &si_dpm_vblank_too_short,
8139 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8140 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8141 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm,
8142 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm,
8143 .check_state_equal = &si_check_state_equal,
8144 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8145 .read_sensor = &si_dpm_read_sensor,
8146 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks,
8147 };
8148
8149 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8150 .set = si_dpm_set_interrupt_state,
8151 .process = si_dpm_process_interrupt,
8152 };
8153
si_dpm_set_irq_funcs(struct amdgpu_device * adev)8154 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8155 {
8156 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8157 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8158 }
8159
8160