1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/pci.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_atombios.h"
31 #include "amdgpu_dpm_internal.h"
32 #include "amd_pcie.h"
33 #include "atom.h"
34 #include "gfx_v6_0.h"
35 #include "r600_dpm.h"
36 #include "sid.h"
37 #include "si_dpm.h"
38 #include "../include/pptable.h"
39 #include <linux/math64.h>
40 #include <linux/seq_file.h>
41 #include <linux/firmware.h>
42 #include <legacy_dpm.h>
43
44 #include "bif/bif_3_0_d.h"
45 #include "bif/bif_3_0_sh_mask.h"
46
47 #include "dce/dce_6_0_d.h"
48 #include "dce/dce_6_0_sh_mask.h"
49
50 #include "gca/gfx_6_0_d.h"
51 #include "gca/gfx_6_0_sh_mask.h"
52
53 #include"gmc/gmc_6_0_d.h"
54 #include"gmc/gmc_6_0_sh_mask.h"
55
56 #include "smu/smu_6_0_d.h"
57 #include "smu/smu_6_0_sh_mask.h"
58
59 #define MC_CG_ARB_FREQ_F0 0x0a
60 #define MC_CG_ARB_FREQ_F1 0x0b
61 #define MC_CG_ARB_FREQ_F2 0x0c
62 #define MC_CG_ARB_FREQ_F3 0x0d
63
64 #define SMC_RAM_END 0x20000
65
66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
67
68
69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
76
77 #define BIOS_SCRATCH_4 0x5cd
78
79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
82 MODULE_FIRMWARE("amdgpu/verde_smc.bin");
83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
84 MODULE_FIRMWARE("amdgpu/oland_smc.bin");
85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
89
90 static const struct amd_pm_funcs si_dpm_funcs;
91
92 union power_info {
93 struct _ATOM_POWERPLAY_INFO info;
94 struct _ATOM_POWERPLAY_INFO_V2 info_2;
95 struct _ATOM_POWERPLAY_INFO_V3 info_3;
96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
101 };
102
103 union fan_info {
104 struct _ATOM_PPLIB_FANTABLE fan;
105 struct _ATOM_PPLIB_FANTABLE2 fan2;
106 struct _ATOM_PPLIB_FANTABLE3 fan3;
107 };
108
109 union pplib_clock_info {
110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
114 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
115 };
116
117 enum si_dpm_auto_throttle_src {
118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL,
119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL
120 };
121
122 enum si_dpm_event_src {
123 SI_DPM_EVENT_SRC_ANALOG = 0,
124 SI_DPM_EVENT_SRC_EXTERNAL = 1,
125 SI_DPM_EVENT_SRC_DIGITAL = 2,
126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
128 };
129
130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
131 {
132 R600_UTC_DFLT_00,
133 R600_UTC_DFLT_01,
134 R600_UTC_DFLT_02,
135 R600_UTC_DFLT_03,
136 R600_UTC_DFLT_04,
137 R600_UTC_DFLT_05,
138 R600_UTC_DFLT_06,
139 R600_UTC_DFLT_07,
140 R600_UTC_DFLT_08,
141 R600_UTC_DFLT_09,
142 R600_UTC_DFLT_10,
143 R600_UTC_DFLT_11,
144 R600_UTC_DFLT_12,
145 R600_UTC_DFLT_13,
146 R600_UTC_DFLT_14,
147 };
148
149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
150 {
151 R600_DTC_DFLT_00,
152 R600_DTC_DFLT_01,
153 R600_DTC_DFLT_02,
154 R600_DTC_DFLT_03,
155 R600_DTC_DFLT_04,
156 R600_DTC_DFLT_05,
157 R600_DTC_DFLT_06,
158 R600_DTC_DFLT_07,
159 R600_DTC_DFLT_08,
160 R600_DTC_DFLT_09,
161 R600_DTC_DFLT_10,
162 R600_DTC_DFLT_11,
163 R600_DTC_DFLT_12,
164 R600_DTC_DFLT_13,
165 R600_DTC_DFLT_14,
166 };
167
168 static const struct si_cac_config_reg cac_weights_tahiti[] =
169 {
170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
230 { 0xFFFFFFFF }
231 };
232
233 static const struct si_cac_config_reg lcac_tahiti[] =
234 {
235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
321 { 0xFFFFFFFF }
322
323 };
324
325 static const struct si_cac_config_reg cac_override_tahiti[] =
326 {
327 { 0xFFFFFFFF }
328 };
329
330 static const struct si_powertune_data powertune_data_tahiti =
331 {
332 ((1 << 16) | 27027),
333 6,
334 0,
335 4,
336 95,
337 {
338 0UL,
339 0UL,
340 4521550UL,
341 309631529UL,
342 -1270850L,
343 4513710L,
344 40
345 },
346 595000000UL,
347 12,
348 {
349 0,
350 0,
351 0,
352 0,
353 0,
354 0,
355 0,
356 0
357 },
358 true
359 };
360
361 static const struct si_dte_data dte_data_tahiti =
362 {
363 { 1159409, 0, 0, 0, 0 },
364 { 777, 0, 0, 0, 0 },
365 2,
366 54000,
367 127000,
368 25,
369 2,
370 10,
371 13,
372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
375 85,
376 false
377 };
378
379 static const struct si_dte_data dte_data_tahiti_pro =
380 {
381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
382 { 0x0, 0x0, 0x0, 0x0, 0x0 },
383 5,
384 45000,
385 100,
386 0xA,
387 1,
388 0,
389 0x10,
390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
393 90,
394 true
395 };
396
397 static const struct si_dte_data dte_data_new_zealand =
398 {
399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
401 0x5,
402 0xAFC8,
403 0x69,
404 0x32,
405 1,
406 0,
407 0x10,
408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
411 85,
412 true
413 };
414
415 static const struct si_dte_data dte_data_aruba_pro =
416 {
417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
418 { 0x0, 0x0, 0x0, 0x0, 0x0 },
419 5,
420 45000,
421 100,
422 0xA,
423 1,
424 0,
425 0x10,
426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
429 90,
430 true
431 };
432
433 static const struct si_dte_data dte_data_malta =
434 {
435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
436 { 0x0, 0x0, 0x0, 0x0, 0x0 },
437 5,
438 45000,
439 100,
440 0xA,
441 1,
442 0,
443 0x10,
444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
447 90,
448 true
449 };
450
451 static const struct si_cac_config_reg cac_weights_pitcairn[] =
452 {
453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
513 { 0xFFFFFFFF }
514 };
515
516 static const struct si_cac_config_reg lcac_pitcairn[] =
517 {
518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
604 { 0xFFFFFFFF }
605 };
606
607 static const struct si_cac_config_reg cac_override_pitcairn[] =
608 {
609 { 0xFFFFFFFF }
610 };
611
612 static const struct si_powertune_data powertune_data_pitcairn =
613 {
614 ((1 << 16) | 27027),
615 5,
616 0,
617 6,
618 100,
619 {
620 51600000UL,
621 1800000UL,
622 7194395UL,
623 309631529UL,
624 -1270850L,
625 4513710L,
626 100
627 },
628 117830498UL,
629 12,
630 {
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 0
639 },
640 true
641 };
642
643 static const struct si_dte_data dte_data_pitcairn =
644 {
645 { 0, 0, 0, 0, 0 },
646 { 0, 0, 0, 0, 0 },
647 0,
648 0,
649 0,
650 0,
651 0,
652 0,
653 0,
654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
657 0,
658 false
659 };
660
661 static const struct si_dte_data dte_data_curacao_xt =
662 {
663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
664 { 0x0, 0x0, 0x0, 0x0, 0x0 },
665 5,
666 45000,
667 100,
668 0xA,
669 1,
670 0,
671 0x10,
672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
675 90,
676 true
677 };
678
679 static const struct si_dte_data dte_data_curacao_pro =
680 {
681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
682 { 0x0, 0x0, 0x0, 0x0, 0x0 },
683 5,
684 45000,
685 100,
686 0xA,
687 1,
688 0,
689 0x10,
690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
693 90,
694 true
695 };
696
697 static const struct si_dte_data dte_data_neptune_xt =
698 {
699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
700 { 0x0, 0x0, 0x0, 0x0, 0x0 },
701 5,
702 45000,
703 100,
704 0xA,
705 1,
706 0,
707 0x10,
708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
711 90,
712 true
713 };
714
715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
716 {
717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
777 { 0xFFFFFFFF }
778 };
779
780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
781 {
782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
842 { 0xFFFFFFFF }
843 };
844
845 static const struct si_cac_config_reg cac_weights_heathrow[] =
846 {
847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
907 { 0xFFFFFFFF }
908 };
909
910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
911 {
912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
972 { 0xFFFFFFFF }
973 };
974
975 static const struct si_cac_config_reg cac_weights_cape_verde[] =
976 {
977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1037 { 0xFFFFFFFF }
1038 };
1039
1040 static const struct si_cac_config_reg lcac_cape_verde[] =
1041 {
1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1096 { 0xFFFFFFFF }
1097 };
1098
1099 static const struct si_cac_config_reg cac_override_cape_verde[] =
1100 {
1101 { 0xFFFFFFFF }
1102 };
1103
1104 static const struct si_powertune_data powertune_data_cape_verde =
1105 {
1106 ((1 << 16) | 0x6993),
1107 5,
1108 0,
1109 7,
1110 105,
1111 {
1112 0UL,
1113 0UL,
1114 7194395UL,
1115 309631529UL,
1116 -1270850L,
1117 4513710L,
1118 100
1119 },
1120 117830498UL,
1121 12,
1122 {
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 0
1131 },
1132 true
1133 };
1134
1135 static const struct si_dte_data dte_data_cape_verde =
1136 {
1137 { 0, 0, 0, 0, 0 },
1138 { 0, 0, 0, 0, 0 },
1139 0,
1140 0,
1141 0,
1142 0,
1143 0,
1144 0,
1145 0,
1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1149 0,
1150 false
1151 };
1152
1153 static const struct si_dte_data dte_data_venus_xtx =
1154 {
1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1157 5,
1158 55000,
1159 0x69,
1160 0xA,
1161 1,
1162 0,
1163 0x3,
1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 90,
1168 true
1169 };
1170
1171 static const struct si_dte_data dte_data_venus_xt =
1172 {
1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1175 5,
1176 55000,
1177 0x69,
1178 0xA,
1179 1,
1180 0,
1181 0x3,
1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 90,
1186 true
1187 };
1188
1189 static const struct si_dte_data dte_data_venus_pro =
1190 {
1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1193 5,
1194 55000,
1195 0x69,
1196 0xA,
1197 1,
1198 0,
1199 0x3,
1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1203 90,
1204 true
1205 };
1206
1207 static const struct si_cac_config_reg cac_weights_oland[] =
1208 {
1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1269 { 0xFFFFFFFF }
1270 };
1271
1272 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1273 {
1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1334 { 0xFFFFFFFF }
1335 };
1336
1337 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1338 {
1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1399 { 0xFFFFFFFF }
1400 };
1401
1402 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1403 {
1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1464 { 0xFFFFFFFF }
1465 };
1466
1467 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1468 {
1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1529 { 0xFFFFFFFF }
1530 };
1531
1532 static const struct si_cac_config_reg lcac_oland[] =
1533 {
1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0xFFFFFFFF }
1577 };
1578
1579 static const struct si_cac_config_reg lcac_mars_pro[] =
1580 {
1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1623 { 0xFFFFFFFF }
1624 };
1625
1626 static const struct si_cac_config_reg cac_override_oland[] =
1627 {
1628 { 0xFFFFFFFF }
1629 };
1630
1631 static const struct si_powertune_data powertune_data_oland =
1632 {
1633 ((1 << 16) | 0x6993),
1634 5,
1635 0,
1636 7,
1637 105,
1638 {
1639 0UL,
1640 0UL,
1641 7194395UL,
1642 309631529UL,
1643 -1270850L,
1644 4513710L,
1645 100
1646 },
1647 117830498UL,
1648 12,
1649 {
1650 0,
1651 0,
1652 0,
1653 0,
1654 0,
1655 0,
1656 0,
1657 0
1658 },
1659 true
1660 };
1661
1662 static const struct si_powertune_data powertune_data_mars_pro =
1663 {
1664 ((1 << 16) | 0x6993),
1665 5,
1666 0,
1667 7,
1668 105,
1669 {
1670 0UL,
1671 0UL,
1672 7194395UL,
1673 309631529UL,
1674 -1270850L,
1675 4513710L,
1676 100
1677 },
1678 117830498UL,
1679 12,
1680 {
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 0
1689 },
1690 true
1691 };
1692
1693 static const struct si_dte_data dte_data_oland =
1694 {
1695 { 0, 0, 0, 0, 0 },
1696 { 0, 0, 0, 0, 0 },
1697 0,
1698 0,
1699 0,
1700 0,
1701 0,
1702 0,
1703 0,
1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1707 0,
1708 false
1709 };
1710
1711 static const struct si_dte_data dte_data_mars_pro =
1712 {
1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1714 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1715 5,
1716 55000,
1717 105,
1718 0xA,
1719 1,
1720 0,
1721 0x10,
1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1725 90,
1726 true
1727 };
1728
1729 static const struct si_dte_data dte_data_sun_xt =
1730 {
1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1732 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1733 5,
1734 55000,
1735 105,
1736 0xA,
1737 1,
1738 0,
1739 0x10,
1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1743 90,
1744 true
1745 };
1746
1747
1748 static const struct si_cac_config_reg cac_weights_hainan[] =
1749 {
1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1810 { 0xFFFFFFFF }
1811 };
1812
1813 static const struct si_powertune_data powertune_data_hainan =
1814 {
1815 ((1 << 16) | 0x6993),
1816 5,
1817 0,
1818 9,
1819 105,
1820 {
1821 0UL,
1822 0UL,
1823 7194395UL,
1824 309631529UL,
1825 -1270850L,
1826 4513710L,
1827 100
1828 },
1829 117830498UL,
1830 12,
1831 {
1832 0,
1833 0,
1834 0,
1835 0,
1836 0,
1837 0,
1838 0,
1839 0
1840 },
1841 true
1842 };
1843
1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1848
1849 static int si_populate_voltage_value(struct amdgpu_device *adev,
1850 const struct atom_voltage_table *table,
1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1852 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1854 u16 *std_voltage);
1855 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1856 u16 reg_offset, u32 value);
1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1858 struct rv7xx_pl *pl,
1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1860 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1861 u32 engine_clock,
1862 SISLANDS_SMC_SCLK_VALUE *sclk);
1863
1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1867
si_get_pi(struct amdgpu_device * adev)1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1869 {
1870 struct si_power_info *pi = adev->pm.dpm.priv;
1871 return pi;
1872 }
1873
si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 ileakage,u32 * leakage)1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1875 u16 v, s32 t, u32 ileakage, u32 *leakage)
1876 {
1877 s64 kt, kv, leakage_w, i_leakage, vddc;
1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1879 s64 tmp;
1880
1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1882 vddc = div64_s64(drm_int2fixp(v), 1000);
1883 temperature = div64_s64(drm_int2fixp(t), 1000);
1884
1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1889 t_ref = drm_int2fixp(coeff->t_ref);
1890
1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1895
1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1897
1898 *leakage = drm_fixp2int(leakage_w * 1000);
1899 }
1900
si_calculate_leakage_for_v_and_t(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,u16 v,s32 t,u32 i_leakage,u32 * leakage)1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1902 const struct ni_leakage_coeffients *coeff,
1903 u16 v,
1904 s32 t,
1905 u32 i_leakage,
1906 u32 *leakage)
1907 {
1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1909 }
1910
si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 ileakage,u32 * leakage)1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1912 const u32 fixed_kt, u16 v,
1913 u32 ileakage, u32 *leakage)
1914 {
1915 s64 kt, kv, leakage_w, i_leakage, vddc;
1916
1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1918 vddc = div64_s64(drm_int2fixp(v), 1000);
1919
1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1923
1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1925
1926 *leakage = drm_fixp2int(leakage_w * 1000);
1927 }
1928
si_calculate_leakage_for_v(struct amdgpu_device * adev,const struct ni_leakage_coeffients * coeff,const u32 fixed_kt,u16 v,u32 i_leakage,u32 * leakage)1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1930 const struct ni_leakage_coeffients *coeff,
1931 const u32 fixed_kt,
1932 u16 v,
1933 u32 i_leakage,
1934 u32 *leakage)
1935 {
1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1937 }
1938
1939
si_update_dte_from_pl2(struct amdgpu_device * adev,struct si_dte_data * dte_data)1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1941 struct si_dte_data *dte_data)
1942 {
1943 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1945 u32 k = dte_data->k;
1946 u32 t_max = dte_data->max_t;
1947 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1948 u32 t_0 = dte_data->t0;
1949 u32 i;
1950
1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1952 dte_data->tdep_count = 3;
1953
1954 for (i = 0; i < k; i++) {
1955 dte_data->r[i] =
1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1957 (p_limit2 * (u32)100);
1958 }
1959
1960 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1961
1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1963 dte_data->tdep_r[i] = dte_data->r[4];
1964 }
1965 } else {
1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1967 }
1968 }
1969
rv770_get_pi(struct amdgpu_device * adev)1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1971 {
1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1973
1974 return pi;
1975 }
1976
ni_get_pi(struct amdgpu_device * adev)1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1978 {
1979 struct ni_power_info *pi = adev->pm.dpm.priv;
1980
1981 return pi;
1982 }
1983
si_get_ps(struct amdgpu_ps * aps)1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1985 {
1986 struct si_ps *ps = aps->ps_priv;
1987
1988 return ps;
1989 }
1990
si_initialize_powertune_defaults(struct amdgpu_device * adev)1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1992 {
1993 struct ni_power_info *ni_pi = ni_get_pi(adev);
1994 struct si_power_info *si_pi = si_get_pi(adev);
1995 bool update_dte_from_pl2 = false;
1996
1997 if (adev->asic_type == CHIP_TAHITI) {
1998 si_pi->cac_weights = cac_weights_tahiti;
1999 si_pi->lcac_config = lcac_tahiti;
2000 si_pi->cac_override = cac_override_tahiti;
2001 si_pi->powertune_data = &powertune_data_tahiti;
2002 si_pi->dte_data = dte_data_tahiti;
2003
2004 switch (adev->pdev->device) {
2005 case 0x6798:
2006 si_pi->dte_data.enable_dte_by_default = true;
2007 break;
2008 case 0x6799:
2009 si_pi->dte_data = dte_data_new_zealand;
2010 break;
2011 case 0x6790:
2012 case 0x6791:
2013 case 0x6792:
2014 case 0x679E:
2015 si_pi->dte_data = dte_data_aruba_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x679B:
2019 si_pi->dte_data = dte_data_malta;
2020 update_dte_from_pl2 = true;
2021 break;
2022 case 0x679A:
2023 si_pi->dte_data = dte_data_tahiti_pro;
2024 update_dte_from_pl2 = true;
2025 break;
2026 default:
2027 if (si_pi->dte_data.enable_dte_by_default == true)
2028 DRM_ERROR("DTE is not enabled!\n");
2029 break;
2030 }
2031 } else if (adev->asic_type == CHIP_PITCAIRN) {
2032 si_pi->cac_weights = cac_weights_pitcairn;
2033 si_pi->lcac_config = lcac_pitcairn;
2034 si_pi->cac_override = cac_override_pitcairn;
2035 si_pi->powertune_data = &powertune_data_pitcairn;
2036
2037 switch (adev->pdev->device) {
2038 case 0x6810:
2039 case 0x6818:
2040 si_pi->dte_data = dte_data_curacao_xt;
2041 update_dte_from_pl2 = true;
2042 break;
2043 case 0x6819:
2044 case 0x6811:
2045 si_pi->dte_data = dte_data_curacao_pro;
2046 update_dte_from_pl2 = true;
2047 break;
2048 case 0x6800:
2049 case 0x6806:
2050 si_pi->dte_data = dte_data_neptune_xt;
2051 update_dte_from_pl2 = true;
2052 break;
2053 default:
2054 si_pi->dte_data = dte_data_pitcairn;
2055 break;
2056 }
2057 } else if (adev->asic_type == CHIP_VERDE) {
2058 si_pi->lcac_config = lcac_cape_verde;
2059 si_pi->cac_override = cac_override_cape_verde;
2060 si_pi->powertune_data = &powertune_data_cape_verde;
2061
2062 switch (adev->pdev->device) {
2063 case 0x683B:
2064 case 0x683F:
2065 case 0x6829:
2066 case 0x6835:
2067 si_pi->cac_weights = cac_weights_cape_verde_pro;
2068 si_pi->dte_data = dte_data_cape_verde;
2069 break;
2070 case 0x682C:
2071 si_pi->cac_weights = cac_weights_cape_verde_pro;
2072 si_pi->dte_data = dte_data_sun_xt;
2073 update_dte_from_pl2 = true;
2074 break;
2075 case 0x6825:
2076 case 0x6827:
2077 si_pi->cac_weights = cac_weights_heathrow;
2078 si_pi->dte_data = dte_data_cape_verde;
2079 break;
2080 case 0x6824:
2081 case 0x682D:
2082 si_pi->cac_weights = cac_weights_chelsea_xt;
2083 si_pi->dte_data = dte_data_cape_verde;
2084 break;
2085 case 0x682F:
2086 si_pi->cac_weights = cac_weights_chelsea_pro;
2087 si_pi->dte_data = dte_data_cape_verde;
2088 break;
2089 case 0x6820:
2090 si_pi->cac_weights = cac_weights_heathrow;
2091 si_pi->dte_data = dte_data_venus_xtx;
2092 break;
2093 case 0x6821:
2094 si_pi->cac_weights = cac_weights_heathrow;
2095 si_pi->dte_data = dte_data_venus_xt;
2096 break;
2097 case 0x6823:
2098 case 0x682B:
2099 case 0x6822:
2100 case 0x682A:
2101 si_pi->cac_weights = cac_weights_chelsea_pro;
2102 si_pi->dte_data = dte_data_venus_pro;
2103 break;
2104 default:
2105 si_pi->cac_weights = cac_weights_cape_verde;
2106 si_pi->dte_data = dte_data_cape_verde;
2107 break;
2108 }
2109 } else if (adev->asic_type == CHIP_OLAND) {
2110 si_pi->lcac_config = lcac_mars_pro;
2111 si_pi->cac_override = cac_override_oland;
2112 si_pi->powertune_data = &powertune_data_mars_pro;
2113 si_pi->dte_data = dte_data_mars_pro;
2114
2115 switch (adev->pdev->device) {
2116 case 0x6601:
2117 case 0x6621:
2118 case 0x6603:
2119 case 0x6605:
2120 si_pi->cac_weights = cac_weights_mars_pro;
2121 update_dte_from_pl2 = true;
2122 break;
2123 case 0x6600:
2124 case 0x6606:
2125 case 0x6620:
2126 case 0x6604:
2127 si_pi->cac_weights = cac_weights_mars_xt;
2128 update_dte_from_pl2 = true;
2129 break;
2130 case 0x6611:
2131 case 0x6613:
2132 case 0x6608:
2133 si_pi->cac_weights = cac_weights_oland_pro;
2134 update_dte_from_pl2 = true;
2135 break;
2136 case 0x6610:
2137 si_pi->cac_weights = cac_weights_oland_xt;
2138 update_dte_from_pl2 = true;
2139 break;
2140 default:
2141 si_pi->cac_weights = cac_weights_oland;
2142 si_pi->lcac_config = lcac_oland;
2143 si_pi->cac_override = cac_override_oland;
2144 si_pi->powertune_data = &powertune_data_oland;
2145 si_pi->dte_data = dte_data_oland;
2146 break;
2147 }
2148 } else if (adev->asic_type == CHIP_HAINAN) {
2149 si_pi->cac_weights = cac_weights_hainan;
2150 si_pi->lcac_config = lcac_oland;
2151 si_pi->cac_override = cac_override_oland;
2152 si_pi->powertune_data = &powertune_data_hainan;
2153 si_pi->dte_data = dte_data_sun_xt;
2154 update_dte_from_pl2 = true;
2155 } else {
2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2157 return;
2158 }
2159
2160 ni_pi->enable_power_containment = false;
2161 ni_pi->enable_cac = false;
2162 ni_pi->enable_sq_ramping = false;
2163 si_pi->enable_dte = false;
2164
2165 if (si_pi->powertune_data->enable_powertune_by_default) {
2166 ni_pi->enable_power_containment = true;
2167 ni_pi->enable_cac = true;
2168 if (si_pi->dte_data.enable_dte_by_default) {
2169 si_pi->enable_dte = true;
2170 if (update_dte_from_pl2)
2171 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2172
2173 }
2174 ni_pi->enable_sq_ramping = true;
2175 }
2176
2177 ni_pi->driver_calculate_cac_leakage = true;
2178 ni_pi->cac_configuration_required = true;
2179
2180 if (ni_pi->cac_configuration_required) {
2181 ni_pi->support_cac_long_term_average = true;
2182 si_pi->dyn_powertune_data.l2_lta_window_size =
2183 si_pi->powertune_data->l2_lta_window_size_default;
2184 si_pi->dyn_powertune_data.lts_truncate =
2185 si_pi->powertune_data->lts_truncate_default;
2186 } else {
2187 ni_pi->support_cac_long_term_average = false;
2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2189 si_pi->dyn_powertune_data.lts_truncate = 0;
2190 }
2191
2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2193 }
2194
si_get_smc_power_scaling_factor(struct amdgpu_device * adev)2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2196 {
2197 return 1;
2198 }
2199
si_calculate_cac_wintime(struct amdgpu_device * adev)2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2201 {
2202 u32 xclk;
2203 u32 wintime;
2204 u32 cac_window;
2205 u32 cac_window_size;
2206
2207 xclk = amdgpu_asic_get_xclk(adev);
2208
2209 if (xclk == 0)
2210 return 0;
2211
2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK;
2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2214
2215 wintime = (cac_window_size * 100) / xclk;
2216
2217 return wintime;
2218 }
2219
si_scale_power_for_smc(u32 power_in_watts,u32 scaling_factor)2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2221 {
2222 return power_in_watts;
2223 }
2224
si_calculate_adjusted_tdp_limits(struct amdgpu_device * adev,bool adjust_polarity,u32 tdp_adjustment,u32 * tdp_limit,u32 * near_tdp_limit)2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2226 bool adjust_polarity,
2227 u32 tdp_adjustment,
2228 u32 *tdp_limit,
2229 u32 *near_tdp_limit)
2230 {
2231 u32 adjustment_delta, max_tdp_limit;
2232
2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2234 return -EINVAL;
2235
2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2237
2238 if (adjust_polarity) {
2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2241 } else {
2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2246 else
2247 *near_tdp_limit = 0;
2248 }
2249
2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2251 return -EINVAL;
2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2253 return -EINVAL;
2254
2255 return 0;
2256 }
2257
si_populate_smc_tdp_limits(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2259 struct amdgpu_ps *amdgpu_state)
2260 {
2261 struct ni_power_info *ni_pi = ni_get_pi(adev);
2262 struct si_power_info *si_pi = si_get_pi(adev);
2263
2264 if (ni_pi->enable_power_containment) {
2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2266 PP_SIslands_PAPMParameters *papm_parm;
2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2269 u32 tdp_limit;
2270 u32 near_tdp_limit;
2271 int ret;
2272
2273 if (scaling_factor == 0)
2274 return -EINVAL;
2275
2276 ret = si_calculate_adjusted_tdp_limits(adev,
2277 false, /* ??? */
2278 adev->pm.dpm.tdp_adjustment,
2279 &tdp_limit,
2280 &near_tdp_limit);
2281 if (ret)
2282 return ret;
2283
2284 if (adev->pdev->device == 0x6611 && adev->pdev->revision == 0x87) {
2285 /* Workaround buggy powertune on Radeon 430 and 520. */
2286 tdp_limit = 32;
2287 near_tdp_limit = 28;
2288 }
2289
2290 smc_table->dpm2Params.TDPLimit =
2291 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2292 smc_table->dpm2Params.NearTDPLimit =
2293 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2294 smc_table->dpm2Params.SafePowerLimit =
2295 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2296
2297 ret = amdgpu_si_copy_bytes_to_smc(adev,
2298 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2299 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2300 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2301 sizeof(u32) * 3,
2302 si_pi->sram_end);
2303 if (ret)
2304 return ret;
2305
2306 if (si_pi->enable_ppm) {
2307 papm_parm = &si_pi->papm_parm;
2308 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2309 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2310 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2311 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2312 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2313 papm_parm->PlatformPowerLimit = 0xffffffff;
2314 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2315
2316 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2317 (u8 *)papm_parm,
2318 sizeof(PP_SIslands_PAPMParameters),
2319 si_pi->sram_end);
2320 if (ret)
2321 return ret;
2322 }
2323 }
2324 return 0;
2325 }
2326
si_populate_smc_tdp_limits_2(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2327 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2328 struct amdgpu_ps *amdgpu_state)
2329 {
2330 struct ni_power_info *ni_pi = ni_get_pi(adev);
2331 struct si_power_info *si_pi = si_get_pi(adev);
2332
2333 if (ni_pi->enable_power_containment) {
2334 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2335 int ret;
2336
2337 ret = amdgpu_si_copy_bytes_to_smc(adev,
2338 (si_pi->state_table_start +
2339 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2340 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2341 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2342 sizeof(u32) * 2,
2343 si_pi->sram_end);
2344 if (ret)
2345 return ret;
2346 }
2347
2348 return 0;
2349 }
2350
si_calculate_power_efficiency_ratio(struct amdgpu_device * adev,const u16 prev_std_vddc,const u16 curr_std_vddc)2351 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2352 const u16 prev_std_vddc,
2353 const u16 curr_std_vddc)
2354 {
2355 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2356 u64 prev_vddc = (u64)prev_std_vddc;
2357 u64 curr_vddc = (u64)curr_std_vddc;
2358 u64 pwr_efficiency_ratio, n, d;
2359
2360 if ((prev_vddc == 0) || (curr_vddc == 0))
2361 return 0;
2362
2363 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2364 d = prev_vddc * prev_vddc;
2365 pwr_efficiency_ratio = div64_u64(n, d);
2366
2367 if (pwr_efficiency_ratio > (u64)0xFFFF)
2368 return 0;
2369
2370 return (u16)pwr_efficiency_ratio;
2371 }
2372
si_should_disable_uvd_powertune(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)2373 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2374 struct amdgpu_ps *amdgpu_state)
2375 {
2376 struct si_power_info *si_pi = si_get_pi(adev);
2377
2378 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2379 amdgpu_state->vclk && amdgpu_state->dclk)
2380 return true;
2381
2382 return false;
2383 }
2384
evergreen_get_pi(struct amdgpu_device * adev)2385 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2386 {
2387 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2388
2389 return pi;
2390 }
2391
si_populate_power_containment_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2392 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2393 struct amdgpu_ps *amdgpu_state,
2394 SISLANDS_SMC_SWSTATE *smc_state)
2395 {
2396 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2397 struct ni_power_info *ni_pi = ni_get_pi(adev);
2398 struct si_ps *state = si_get_ps(amdgpu_state);
2399 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2400 u32 prev_sclk;
2401 u32 max_sclk;
2402 u32 min_sclk;
2403 u16 prev_std_vddc;
2404 u16 curr_std_vddc;
2405 int i;
2406 u16 pwr_efficiency_ratio;
2407 u8 max_ps_percent;
2408 bool disable_uvd_power_tune;
2409 int ret;
2410
2411 if (ni_pi->enable_power_containment == false)
2412 return 0;
2413
2414 if (state->performance_level_count == 0)
2415 return -EINVAL;
2416
2417 if (smc_state->levelCount != state->performance_level_count)
2418 return -EINVAL;
2419
2420 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2421
2422 smc_state->levels[0].dpm2.MaxPS = 0;
2423 smc_state->levels[0].dpm2.NearTDPDec = 0;
2424 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2425 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2426 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2427
2428 for (i = 1; i < state->performance_level_count; i++) {
2429 prev_sclk = state->performance_levels[i-1].sclk;
2430 max_sclk = state->performance_levels[i].sclk;
2431 if (i == 1)
2432 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2433 else
2434 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2435
2436 if (prev_sclk > max_sclk)
2437 return -EINVAL;
2438
2439 if ((max_ps_percent == 0) ||
2440 (prev_sclk == max_sclk) ||
2441 disable_uvd_power_tune)
2442 min_sclk = max_sclk;
2443 else if (i == 1)
2444 min_sclk = prev_sclk;
2445 else
2446 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2447
2448 if (min_sclk < state->performance_levels[0].sclk)
2449 min_sclk = state->performance_levels[0].sclk;
2450
2451 if (min_sclk == 0)
2452 return -EINVAL;
2453
2454 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2455 state->performance_levels[i-1].vddc, &vddc);
2456 if (ret)
2457 return ret;
2458
2459 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2460 if (ret)
2461 return ret;
2462
2463 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2464 state->performance_levels[i].vddc, &vddc);
2465 if (ret)
2466 return ret;
2467
2468 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2469 if (ret)
2470 return ret;
2471
2472 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2473 prev_std_vddc, curr_std_vddc);
2474
2475 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2476 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2477 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2478 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2479 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2480 }
2481
2482 return 0;
2483 }
2484
si_populate_sq_ramping_values(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)2485 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2486 struct amdgpu_ps *amdgpu_state,
2487 SISLANDS_SMC_SWSTATE *smc_state)
2488 {
2489 struct ni_power_info *ni_pi = ni_get_pi(adev);
2490 struct si_ps *state = si_get_ps(amdgpu_state);
2491 u32 sq_power_throttle, sq_power_throttle2;
2492 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2493 int i;
2494
2495 if (state->performance_level_count == 0)
2496 return -EINVAL;
2497
2498 if (smc_state->levelCount != state->performance_level_count)
2499 return -EINVAL;
2500
2501 if (adev->pm.dpm.sq_ramping_threshold == 0)
2502 return -EINVAL;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT))
2505 enable_sq_ramping = false;
2506
2507 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT))
2508 enable_sq_ramping = false;
2509
2510 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT))
2511 enable_sq_ramping = false;
2512
2513 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT))
2514 enable_sq_ramping = false;
2515
2516 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT))
2517 enable_sq_ramping = false;
2518
2519 for (i = 0; i < state->performance_level_count; i++) {
2520 sq_power_throttle = 0;
2521 sq_power_throttle2 = 0;
2522
2523 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2524 enable_sq_ramping) {
2525 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT;
2526 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT;
2527 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT;
2528 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT;
2529 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT;
2530 } else {
2531 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK |
2532 SQ_POWER_THROTTLE__MIN_POWER_MASK;
2533 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
2534 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
2535 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
2536 }
2537
2538 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2539 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2540 }
2541
2542 return 0;
2543 }
2544
si_enable_power_containment(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2545 static int si_enable_power_containment(struct amdgpu_device *adev,
2546 struct amdgpu_ps *amdgpu_new_state,
2547 bool enable)
2548 {
2549 struct ni_power_info *ni_pi = ni_get_pi(adev);
2550 PPSMC_Result smc_result;
2551 int ret = 0;
2552
2553 if (ni_pi->enable_power_containment) {
2554 if (enable) {
2555 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2556 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2557 if (smc_result != PPSMC_Result_OK)
2558 ret = -EINVAL;
2559 }
2560 } else {
2561 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2562 if (smc_result != PPSMC_Result_OK)
2563 ret = -EINVAL;
2564 }
2565 }
2566
2567 return ret;
2568 }
2569
si_initialize_smc_dte_tables(struct amdgpu_device * adev)2570 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2571 {
2572 struct si_power_info *si_pi = si_get_pi(adev);
2573 int ret = 0;
2574 struct si_dte_data *dte_data = &si_pi->dte_data;
2575 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2576 u32 table_size;
2577 u8 tdep_count;
2578 u32 i;
2579
2580 if (dte_data == NULL)
2581 si_pi->enable_dte = false;
2582
2583 if (si_pi->enable_dte == false)
2584 return 0;
2585
2586 if (dte_data->k <= 0)
2587 return -EINVAL;
2588
2589 dte_tables = kzalloc_obj(Smc_SIslands_DTE_Configuration);
2590 if (dte_tables == NULL) {
2591 si_pi->enable_dte = false;
2592 return -ENOMEM;
2593 }
2594
2595 table_size = dte_data->k;
2596
2597 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2598 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2599
2600 tdep_count = dte_data->tdep_count;
2601 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2602 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2603
2604 dte_tables->K = cpu_to_be32(table_size);
2605 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2606 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2607 dte_tables->WindowSize = dte_data->window_size;
2608 dte_tables->temp_select = dte_data->temp_select;
2609 dte_tables->DTE_mode = dte_data->dte_mode;
2610 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2611
2612 if (tdep_count > 0)
2613 table_size--;
2614
2615 for (i = 0; i < table_size; i++) {
2616 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2617 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2618 }
2619
2620 dte_tables->Tdep_count = tdep_count;
2621
2622 for (i = 0; i < (u32)tdep_count; i++) {
2623 dte_tables->T_limits[i] = dte_data->t_limits[i];
2624 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2625 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2626 }
2627
2628 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2629 (u8 *)dte_tables,
2630 sizeof(Smc_SIslands_DTE_Configuration),
2631 si_pi->sram_end);
2632 kfree(dte_tables);
2633
2634 return ret;
2635 }
2636
si_get_cac_std_voltage_max_min(struct amdgpu_device * adev,u16 * max,u16 * min)2637 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2638 u16 *max, u16 *min)
2639 {
2640 struct si_power_info *si_pi = si_get_pi(adev);
2641 struct amdgpu_cac_leakage_table *table =
2642 &adev->pm.dpm.dyn_state.cac_leakage_table;
2643 u32 i;
2644 u32 v0_loadline;
2645
2646 if (table == NULL)
2647 return -EINVAL;
2648
2649 *max = 0;
2650 *min = 0xFFFF;
2651
2652 for (i = 0; i < table->count; i++) {
2653 if (table->entries[i].vddc > *max)
2654 *max = table->entries[i].vddc;
2655 if (table->entries[i].vddc < *min)
2656 *min = table->entries[i].vddc;
2657 }
2658
2659 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2660 return -EINVAL;
2661
2662 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2663
2664 if (v0_loadline > 0xFFFFUL)
2665 return -EINVAL;
2666
2667 *min = (u16)v0_loadline;
2668
2669 if ((*min > *max) || (*max == 0) || (*min == 0))
2670 return -EINVAL;
2671
2672 return 0;
2673 }
2674
si_get_cac_std_voltage_step(u16 max,u16 min)2675 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2676 {
2677 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2678 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2679 }
2680
si_init_dte_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step,u16 t0,u16 t_step)2681 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2682 PP_SIslands_CacConfig *cac_tables,
2683 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2684 u16 t0, u16 t_step)
2685 {
2686 struct si_power_info *si_pi = si_get_pi(adev);
2687 u32 leakage;
2688 unsigned int i, j;
2689 s32 t;
2690 u32 smc_leakage;
2691 u32 scaling_factor;
2692 u16 voltage;
2693
2694 scaling_factor = si_get_smc_power_scaling_factor(adev);
2695
2696 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2697 t = (1000 * (i * t_step + t0));
2698
2699 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2700 voltage = vddc_max - (vddc_step * j);
2701
2702 si_calculate_leakage_for_v_and_t(adev,
2703 &si_pi->powertune_data->leakage_coefficients,
2704 voltage,
2705 t,
2706 si_pi->dyn_powertune_data.cac_leakage,
2707 &leakage);
2708
2709 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2710
2711 if (smc_leakage > 0xFFFF)
2712 smc_leakage = 0xFFFF;
2713
2714 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2715 cpu_to_be16((u16)smc_leakage);
2716 }
2717 }
2718 return 0;
2719 }
2720
si_init_simplified_leakage_table(struct amdgpu_device * adev,PP_SIslands_CacConfig * cac_tables,u16 vddc_max,u16 vddc_min,u16 vddc_step)2721 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2722 PP_SIslands_CacConfig *cac_tables,
2723 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2724 {
2725 struct si_power_info *si_pi = si_get_pi(adev);
2726 u32 leakage;
2727 unsigned int i, j;
2728 u32 smc_leakage;
2729 u32 scaling_factor;
2730 u16 voltage;
2731
2732 scaling_factor = si_get_smc_power_scaling_factor(adev);
2733
2734 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2735 voltage = vddc_max - (vddc_step * j);
2736
2737 si_calculate_leakage_for_v(adev,
2738 &si_pi->powertune_data->leakage_coefficients,
2739 si_pi->powertune_data->fixed_kt,
2740 voltage,
2741 si_pi->dyn_powertune_data.cac_leakage,
2742 &leakage);
2743
2744 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2745
2746 if (smc_leakage > 0xFFFF)
2747 smc_leakage = 0xFFFF;
2748
2749 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2750 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2751 cpu_to_be16((u16)smc_leakage);
2752 }
2753 return 0;
2754 }
2755
si_initialize_smc_cac_tables(struct amdgpu_device * adev)2756 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2757 {
2758 struct ni_power_info *ni_pi = ni_get_pi(adev);
2759 struct si_power_info *si_pi = si_get_pi(adev);
2760 PP_SIslands_CacConfig *cac_tables = NULL;
2761 u16 vddc_max, vddc_min, vddc_step;
2762 u16 t0, t_step;
2763 u32 load_line_slope, reg;
2764 int ret = 0;
2765 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2766
2767 if (ni_pi->enable_cac == false)
2768 return 0;
2769
2770 cac_tables = kzalloc_obj(PP_SIslands_CacConfig);
2771 if (!cac_tables)
2772 return -ENOMEM;
2773
2774 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;
2775 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT);
2776 WREG32(mmCG_CAC_CTRL, reg);
2777
2778 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2779 si_pi->dyn_powertune_data.dc_pwr_value =
2780 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2781 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2782 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2783
2784 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2785
2786 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2787 if (ret)
2788 goto done_free;
2789
2790 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2791 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2792 t_step = 4;
2793 t0 = 60;
2794
2795 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2796 ret = si_init_dte_leakage_table(adev, cac_tables,
2797 vddc_max, vddc_min, vddc_step,
2798 t0, t_step);
2799 else
2800 ret = si_init_simplified_leakage_table(adev, cac_tables,
2801 vddc_max, vddc_min, vddc_step);
2802 if (ret)
2803 goto done_free;
2804
2805 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2806
2807 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2808 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2809 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2810 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2811 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2812 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2813 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2814 cac_tables->calculation_repeats = cpu_to_be32(2);
2815 cac_tables->dc_cac = cpu_to_be32(0);
2816 cac_tables->log2_PG_LKG_SCALE = 12;
2817 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2818 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2819 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2820
2821 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2822 (u8 *)cac_tables,
2823 sizeof(PP_SIslands_CacConfig),
2824 si_pi->sram_end);
2825
2826 if (ret)
2827 goto done_free;
2828
2829 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2830
2831 done_free:
2832 if (ret) {
2833 ni_pi->enable_cac = false;
2834 ni_pi->enable_power_containment = false;
2835 }
2836
2837 kfree(cac_tables);
2838
2839 return ret;
2840 }
2841
si_program_cac_config_registers(struct amdgpu_device * adev,const struct si_cac_config_reg * cac_config_regs)2842 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2843 const struct si_cac_config_reg *cac_config_regs)
2844 {
2845 const struct si_cac_config_reg *config_regs = cac_config_regs;
2846 u32 data = 0, offset;
2847
2848 if (!config_regs)
2849 return -EINVAL;
2850
2851 while (config_regs->offset != 0xFFFFFFFF) {
2852 switch (config_regs->type) {
2853 case SISLANDS_CACCONFIG_CGIND:
2854 offset = SMC_CG_IND_START + config_regs->offset;
2855 if (offset < SMC_CG_IND_END)
2856 data = RREG32_SMC(offset);
2857 break;
2858 default:
2859 data = RREG32(config_regs->offset);
2860 break;
2861 }
2862
2863 data &= ~config_regs->mask;
2864 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2865
2866 switch (config_regs->type) {
2867 case SISLANDS_CACCONFIG_CGIND:
2868 offset = SMC_CG_IND_START + config_regs->offset;
2869 if (offset < SMC_CG_IND_END)
2870 WREG32_SMC(offset, data);
2871 break;
2872 default:
2873 WREG32(config_regs->offset, data);
2874 break;
2875 }
2876 config_regs++;
2877 }
2878 return 0;
2879 }
2880
si_initialize_hardware_cac_manager(struct amdgpu_device * adev)2881 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2882 {
2883 struct ni_power_info *ni_pi = ni_get_pi(adev);
2884 struct si_power_info *si_pi = si_get_pi(adev);
2885 int ret;
2886
2887 if ((ni_pi->enable_cac == false) ||
2888 (ni_pi->cac_configuration_required == false))
2889 return 0;
2890
2891 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2892 if (ret)
2893 return ret;
2894 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2895 if (ret)
2896 return ret;
2897 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2898 if (ret)
2899 return ret;
2900
2901 return 0;
2902 }
2903
si_enable_smc_cac(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,bool enable)2904 static int si_enable_smc_cac(struct amdgpu_device *adev,
2905 struct amdgpu_ps *amdgpu_new_state,
2906 bool enable)
2907 {
2908 struct ni_power_info *ni_pi = ni_get_pi(adev);
2909 struct si_power_info *si_pi = si_get_pi(adev);
2910 PPSMC_Result smc_result;
2911 int ret = 0;
2912
2913 if (ni_pi->enable_cac) {
2914 if (enable) {
2915 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2916 if (ni_pi->support_cac_long_term_average) {
2917 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2918 if (smc_result != PPSMC_Result_OK)
2919 ni_pi->support_cac_long_term_average = false;
2920 }
2921
2922 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2923 if (smc_result != PPSMC_Result_OK) {
2924 ret = -EINVAL;
2925 ni_pi->cac_enabled = false;
2926 } else {
2927 ni_pi->cac_enabled = true;
2928 }
2929
2930 if (si_pi->enable_dte) {
2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2932 if (smc_result != PPSMC_Result_OK)
2933 ret = -EINVAL;
2934 }
2935 }
2936 } else if (ni_pi->cac_enabled) {
2937 if (si_pi->enable_dte)
2938 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2939
2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2941
2942 ni_pi->cac_enabled = false;
2943
2944 if (ni_pi->support_cac_long_term_average)
2945 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2946 }
2947 }
2948 return ret;
2949 }
2950
si_init_smc_spll_table(struct amdgpu_device * adev)2951 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2952 {
2953 struct ni_power_info *ni_pi = ni_get_pi(adev);
2954 struct si_power_info *si_pi = si_get_pi(adev);
2955 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2956 SISLANDS_SMC_SCLK_VALUE sclk_params;
2957 u32 fb_div, p_div;
2958 u32 clk_s, clk_v;
2959 u32 sclk = 0;
2960 int ret = 0;
2961 u32 tmp;
2962 int i;
2963
2964 if (si_pi->spll_table_start == 0)
2965 return -EINVAL;
2966
2967 spll_table = kzalloc_obj(SMC_SISLANDS_SPLL_DIV_TABLE);
2968 if (spll_table == NULL)
2969 return -ENOMEM;
2970
2971 for (i = 0; i < 256; i++) {
2972 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2973 if (ret)
2974 break;
2975 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
2977 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
2978 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
2979
2980 fb_div &= ~0x00001FFF;
2981 fb_div >>= 1;
2982 clk_v >>= 6;
2983
2984 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2985 ret = -EINVAL;
2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2987 ret = -EINVAL;
2988 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2989 ret = -EINVAL;
2990 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2991 ret = -EINVAL;
2992
2993 if (ret)
2994 break;
2995
2996 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2997 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2998 spll_table->freq[i] = cpu_to_be32(tmp);
2999
3000 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
3001 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
3002 spll_table->ss[i] = cpu_to_be32(tmp);
3003
3004 sclk += 512;
3005 }
3006
3007
3008 if (!ret)
3009 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3010 (u8 *)spll_table,
3011 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3012 si_pi->sram_end);
3013
3014 if (ret)
3015 ni_pi->enable_power_containment = false;
3016
3017 kfree(spll_table);
3018
3019 return ret;
3020 }
3021
si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device * adev,u16 vce_voltage)3022 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3023 u16 vce_voltage)
3024 {
3025 u16 highest_leakage = 0;
3026 struct si_power_info *si_pi = si_get_pi(adev);
3027 int i;
3028
3029 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3030 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3031 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3032 }
3033
3034 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3035 return highest_leakage;
3036
3037 return vce_voltage;
3038 }
3039
si_get_vce_clock_voltage(struct amdgpu_device * adev,u32 evclk,u32 ecclk,u16 * voltage)3040 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3041 u32 evclk, u32 ecclk, u16 *voltage)
3042 {
3043 u32 i;
3044 int ret = -EINVAL;
3045 struct amdgpu_vce_clock_voltage_dependency_table *table =
3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3047
3048 if (((evclk == 0) && (ecclk == 0)) ||
3049 (table && (table->count == 0))) {
3050 *voltage = 0;
3051 return 0;
3052 }
3053
3054 for (i = 0; i < table->count; i++) {
3055 if ((evclk <= table->entries[i].evclk) &&
3056 (ecclk <= table->entries[i].ecclk)) {
3057 *voltage = table->entries[i].v;
3058 ret = 0;
3059 break;
3060 }
3061 }
3062
3063 /* if no match return the highest voltage */
3064 if (ret)
3065 *voltage = table->entries[table->count - 1].v;
3066
3067 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3068
3069 return ret;
3070 }
3071
si_dpm_vblank_too_short(void * handle)3072 static bool si_dpm_vblank_too_short(void *handle)
3073 {
3074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3075 u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time;
3076 /* we never hit the non-gddr5 limit so disable it */
3077 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3078
3079 /* Consider zero vblank time too short and disable MCLK switching.
3080 * Note that the vblank time is set to maximum when no displays are attached,
3081 * so we'll still enable MCLK switching in that case.
3082 */
3083 if (vblank_time == 0)
3084 return true;
3085 else if (vblank_time < switch_limit)
3086 return true;
3087 else
3088 return false;
3089
3090 }
3091
ni_copy_and_switch_arb_sets(struct amdgpu_device * adev,u32 arb_freq_src,u32 arb_freq_dest)3092 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3093 u32 arb_freq_src, u32 arb_freq_dest)
3094 {
3095 u32 mc_arb_dram_timing;
3096 u32 mc_arb_dram_timing2;
3097 u32 burst_time;
3098 u32 mc_cg_config;
3099
3100 switch (arb_freq_src) {
3101 case MC_CG_ARB_FREQ_F0:
3102 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3103 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3104 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3105 break;
3106 case MC_CG_ARB_FREQ_F1:
3107 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3108 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3109 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3110 break;
3111 case MC_CG_ARB_FREQ_F2:
3112 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3113 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3114 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3115 break;
3116 case MC_CG_ARB_FREQ_F3:
3117 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3118 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3119 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3120 break;
3121 default:
3122 return -EINVAL;
3123 }
3124
3125 switch (arb_freq_dest) {
3126 case MC_CG_ARB_FREQ_F0:
3127 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3128 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3129 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3130 break;
3131 case MC_CG_ARB_FREQ_F1:
3132 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3133 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3134 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3135 break;
3136 case MC_CG_ARB_FREQ_F2:
3137 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3138 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3139 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3140 break;
3141 case MC_CG_ARB_FREQ_F3:
3142 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3143 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3144 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3145 break;
3146 default:
3147 return -EINVAL;
3148 }
3149
3150 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3151 WREG32(MC_CG_CONFIG, mc_cg_config);
3152 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3153
3154 return 0;
3155 }
3156
ni_update_current_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3157 static void ni_update_current_ps(struct amdgpu_device *adev,
3158 struct amdgpu_ps *rps)
3159 {
3160 struct si_ps *new_ps = si_get_ps(rps);
3161 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3162 struct ni_power_info *ni_pi = ni_get_pi(adev);
3163
3164 eg_pi->current_rps = *rps;
3165 ni_pi->current_ps = *new_ps;
3166 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3167 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3168 }
3169
ni_update_requested_ps(struct amdgpu_device * adev,struct amdgpu_ps * rps)3170 static void ni_update_requested_ps(struct amdgpu_device *adev,
3171 struct amdgpu_ps *rps)
3172 {
3173 struct si_ps *new_ps = si_get_ps(rps);
3174 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3175 struct ni_power_info *ni_pi = ni_get_pi(adev);
3176
3177 eg_pi->requested_rps = *rps;
3178 ni_pi->requested_ps = *new_ps;
3179 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3180 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3181 }
3182
ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3183 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3184 struct amdgpu_ps *new_ps,
3185 struct amdgpu_ps *old_ps)
3186 {
3187 struct si_ps *new_state = si_get_ps(new_ps);
3188 struct si_ps *current_state = si_get_ps(old_ps);
3189
3190 if ((new_ps->vclk == old_ps->vclk) &&
3191 (new_ps->dclk == old_ps->dclk))
3192 return;
3193
3194 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3195 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3196 return;
3197
3198 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3199 }
3200
ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_ps,struct amdgpu_ps * old_ps)3201 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3202 struct amdgpu_ps *new_ps,
3203 struct amdgpu_ps *old_ps)
3204 {
3205 struct si_ps *new_state = si_get_ps(new_ps);
3206 struct si_ps *current_state = si_get_ps(old_ps);
3207
3208 if ((new_ps->vclk == old_ps->vclk) &&
3209 (new_ps->dclk == old_ps->dclk))
3210 return;
3211
3212 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3213 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3214 return;
3215
3216 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3217 }
3218
btc_find_voltage(struct atom_voltage_table * table,u16 voltage)3219 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3220 {
3221 unsigned int i;
3222
3223 for (i = 0; i < table->count; i++)
3224 if (voltage <= table->entries[i].value)
3225 return table->entries[i].value;
3226
3227 return table->entries[table->count - 1].value;
3228 }
3229
btc_find_valid_clock(struct amdgpu_clock_array * clocks,u32 max_clock,u32 requested_clock)3230 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3231 u32 max_clock, u32 requested_clock)
3232 {
3233 unsigned int i;
3234
3235 if ((clocks == NULL) || (clocks->count == 0))
3236 return (requested_clock < max_clock) ? requested_clock : max_clock;
3237
3238 for (i = 0; i < clocks->count; i++) {
3239 if (clocks->values[i] >= requested_clock)
3240 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3241 }
3242
3243 return (clocks->values[clocks->count - 1] < max_clock) ?
3244 clocks->values[clocks->count - 1] : max_clock;
3245 }
3246
btc_get_valid_mclk(struct amdgpu_device * adev,u32 max_mclk,u32 requested_mclk)3247 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3248 u32 max_mclk, u32 requested_mclk)
3249 {
3250 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3251 max_mclk, requested_mclk);
3252 }
3253
btc_get_valid_sclk(struct amdgpu_device * adev,u32 max_sclk,u32 requested_sclk)3254 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3255 u32 max_sclk, u32 requested_sclk)
3256 {
3257 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3258 max_sclk, requested_sclk);
3259 }
3260
btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table * table,u32 * max_clock)3261 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3262 u32 *max_clock)
3263 {
3264 u32 i, clock = 0;
3265
3266 if ((table == NULL) || (table->count == 0)) {
3267 *max_clock = clock;
3268 return;
3269 }
3270
3271 for (i = 0; i < table->count; i++) {
3272 if (clock < table->entries[i].clk)
3273 clock = table->entries[i].clk;
3274 }
3275 *max_clock = clock;
3276 }
3277
btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table * table,u32 clock,u16 max_voltage,u16 * voltage)3278 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3279 u32 clock, u16 max_voltage, u16 *voltage)
3280 {
3281 u32 i;
3282
3283 if ((table == NULL) || (table->count == 0))
3284 return;
3285
3286 for (i= 0; i < table->count; i++) {
3287 if (clock <= table->entries[i].clk) {
3288 if (*voltage < table->entries[i].v)
3289 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3290 table->entries[i].v : max_voltage);
3291 return;
3292 }
3293 }
3294
3295 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3296 }
3297
btc_adjust_clock_combinations(struct amdgpu_device * adev,const struct amdgpu_clock_and_voltage_limits * max_limits,struct rv7xx_pl * pl)3298 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3299 const struct amdgpu_clock_and_voltage_limits *max_limits,
3300 struct rv7xx_pl *pl)
3301 {
3302
3303 if ((pl->mclk == 0) || (pl->sclk == 0))
3304 return;
3305
3306 if (pl->mclk == pl->sclk)
3307 return;
3308
3309 if (pl->mclk > pl->sclk) {
3310 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3311 pl->sclk = btc_get_valid_sclk(adev,
3312 max_limits->sclk,
3313 (pl->mclk +
3314 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3315 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3316 } else {
3317 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3318 pl->mclk = btc_get_valid_mclk(adev,
3319 max_limits->mclk,
3320 pl->sclk -
3321 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3322 }
3323 }
3324
btc_apply_voltage_delta_rules(struct amdgpu_device * adev,u16 max_vddc,u16 max_vddci,u16 * vddc,u16 * vddci)3325 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3326 u16 max_vddc, u16 max_vddci,
3327 u16 *vddc, u16 *vddci)
3328 {
3329 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3330 u16 new_voltage;
3331
3332 if ((0 == *vddc) || (0 == *vddci))
3333 return;
3334
3335 if (*vddc > *vddci) {
3336 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3337 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3338 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3339 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3340 }
3341 } else {
3342 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3343 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3344 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3345 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3346 }
3347 }
3348 }
3349
r600_calculate_u_and_p(u32 i,u32 r_c,u32 p_b,u32 * p,u32 * u)3350 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3351 u32 *p, u32 *u)
3352 {
3353 u32 b_c = 0;
3354 u32 i_c;
3355 u32 tmp;
3356
3357 i_c = (i * r_c) / 100;
3358 tmp = i_c >> p_b;
3359
3360 while (tmp) {
3361 b_c++;
3362 tmp >>= 1;
3363 }
3364
3365 *u = (b_c + 1) / 2;
3366 *p = i_c / (1 << (2 * (*u)));
3367 }
3368
r600_calculate_at(u32 t,u32 h,u32 fh,u32 fl,u32 * tl,u32 * th)3369 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3370 {
3371 u32 k, a, ah, al;
3372 u32 t1;
3373
3374 if ((fl == 0) || (fh == 0) || (fl > fh))
3375 return -EINVAL;
3376
3377 k = (100 * fh) / fl;
3378 t1 = (t * (k - 100));
3379 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3380 a = (a + 5) / 10;
3381 ah = ((a * t) + 5000) / 10000;
3382 al = a - ah;
3383
3384 *th = t - ah;
3385 *tl = t + al;
3386
3387 return 0;
3388 }
3389
r600_is_uvd_state(u32 class,u32 class2)3390 static bool r600_is_uvd_state(u32 class, u32 class2)
3391 {
3392 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3393 return true;
3394 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3395 return true;
3396 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3397 return true;
3398 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3399 return true;
3400 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3401 return true;
3402 return false;
3403 }
3404
rv770_get_memory_module_index(struct amdgpu_device * adev)3405 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3406 {
3407 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3408 }
3409
rv770_get_max_vddc(struct amdgpu_device * adev)3410 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3411 {
3412 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3413 u16 vddc;
3414
3415 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3416 pi->max_vddc = 0;
3417 else
3418 pi->max_vddc = vddc;
3419 }
3420
rv770_get_engine_memory_ss(struct amdgpu_device * adev)3421 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3422 {
3423 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3424 struct amdgpu_atom_ss ss;
3425
3426 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3427 ASIC_INTERNAL_ENGINE_SS, 0);
3428 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3429 ASIC_INTERNAL_MEMORY_SS, 0);
3430
3431 if (pi->sclk_ss || pi->mclk_ss)
3432 pi->dynamic_ss = true;
3433 else
3434 pi->dynamic_ss = false;
3435 }
3436
3437
si_apply_state_adjust_rules(struct amdgpu_device * adev,struct amdgpu_ps * rps)3438 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3439 struct amdgpu_ps *rps)
3440 {
3441 const struct amd_pp_display_configuration *display_cfg =
3442 &adev->pm.pm_display_cfg;
3443 struct si_ps *ps = si_get_ps(rps);
3444 struct amdgpu_clock_and_voltage_limits *max_limits;
3445 bool disable_mclk_switching = false;
3446 bool disable_sclk_switching = false;
3447 u32 mclk, sclk;
3448 u16 vddc, vddci, min_vce_voltage = 0;
3449 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3450 u32 max_sclk = 0, max_mclk = 0;
3451 u32 high_pixelclock_count = 0;
3452 int i;
3453
3454 if (adev->asic_type == CHIP_HAINAN) {
3455 if ((adev->pdev->revision == 0x81) ||
3456 (adev->pdev->revision == 0xC3) ||
3457 (adev->pdev->device == 0x6664) ||
3458 (adev->pdev->device == 0x6665) ||
3459 (adev->pdev->device == 0x6667)) {
3460 max_sclk = 75000;
3461 }
3462 if ((adev->pdev->revision == 0xC3) ||
3463 (adev->pdev->device == 0x6665)) {
3464 max_sclk = 60000;
3465 max_mclk = 80000;
3466 }
3467 if ((adev->pdev->device == 0x666f) &&
3468 (adev->pdev->revision == 0x00)) {
3469 max_sclk = 80000;
3470 max_mclk = 95000;
3471 }
3472 } else if (adev->asic_type == CHIP_OLAND) {
3473 if ((adev->pdev->revision == 0xC7) ||
3474 (adev->pdev->revision == 0x80) ||
3475 (adev->pdev->revision == 0x81) ||
3476 (adev->pdev->revision == 0x83) ||
3477 (adev->pdev->revision == 0x87 &&
3478 adev->pdev->device != 0x6611) ||
3479 (adev->pdev->device == 0x6604) ||
3480 (adev->pdev->device == 0x6605)) {
3481 max_sclk = 75000;
3482 } else if (adev->pdev->revision == 0x87 &&
3483 adev->pdev->device == 0x6611) {
3484 /* Radeon 430 and 520 */
3485 max_sclk = 78000;
3486 }
3487 }
3488
3489 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz.
3490 * For example, 4K 60Hz and 1080p 144Hz fall into this category.
3491 * Find number of such displays connected.
3492 */
3493 for (i = 0; i < display_cfg->num_display; i++) {
3494 /* The array only contains active displays. */
3495 if (display_cfg->displays[i].pixel_clock > 297000)
3496 high_pixelclock_count++;
3497 }
3498
3499 /* These are some ad-hoc fixes to some issues observed with SI GPUs.
3500 * They are necessary because we don't have something like dce_calcs
3501 * for these GPUs to calculate bandwidth requirements.
3502 */
3503 if (high_pixelclock_count) {
3504 /* Work around flickering lines at the bottom edge
3505 * of the screen when using a single 4K 60Hz monitor.
3506 */
3507 disable_mclk_switching = true;
3508
3509 /* On Oland, we observe some flickering when two 4K 60Hz
3510 * displays are connected, possibly because voltage is too low.
3511 * Raise the voltage by requiring a higher SCLK.
3512 * (Voltage cannot be adjusted independently without also SCLK.)
3513 */
3514 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND)
3515 disable_sclk_switching = true;
3516 }
3517
3518 if (rps->vce_active) {
3519 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3520 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3521 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3522 &min_vce_voltage);
3523 } else {
3524 rps->evclk = 0;
3525 rps->ecclk = 0;
3526 }
3527
3528 if ((adev->pm.pm_display_cfg.num_display > 1) ||
3529 si_dpm_vblank_too_short(adev))
3530 disable_mclk_switching = true;
3531
3532 if (rps->vclk || rps->dclk) {
3533 disable_mclk_switching = true;
3534 disable_sclk_switching = true;
3535 }
3536
3537 if (adev->pm.ac_power)
3538 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3539 else
3540 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3541
3542 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3543 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3544 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3545 }
3546 if (adev->pm.ac_power == false) {
3547 for (i = 0; i < ps->performance_level_count; i++) {
3548 if (ps->performance_levels[i].mclk > max_limits->mclk)
3549 ps->performance_levels[i].mclk = max_limits->mclk;
3550 if (ps->performance_levels[i].sclk > max_limits->sclk)
3551 ps->performance_levels[i].sclk = max_limits->sclk;
3552 if (ps->performance_levels[i].vddc > max_limits->vddc)
3553 ps->performance_levels[i].vddc = max_limits->vddc;
3554 if (ps->performance_levels[i].vddci > max_limits->vddci)
3555 ps->performance_levels[i].vddci = max_limits->vddci;
3556 }
3557 }
3558
3559 /* limit clocks to max supported clocks based on voltage dependency tables */
3560 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3561 &max_sclk_vddc);
3562 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3563 &max_mclk_vddci);
3564 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3565 &max_mclk_vddc);
3566
3567 for (i = 0; i < ps->performance_level_count; i++) {
3568 if (max_sclk_vddc) {
3569 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3570 ps->performance_levels[i].sclk = max_sclk_vddc;
3571 }
3572 if (max_mclk_vddci) {
3573 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3574 ps->performance_levels[i].mclk = max_mclk_vddci;
3575 }
3576 if (max_mclk_vddc) {
3577 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3578 ps->performance_levels[i].mclk = max_mclk_vddc;
3579 }
3580 if (max_mclk) {
3581 if (ps->performance_levels[i].mclk > max_mclk)
3582 ps->performance_levels[i].mclk = max_mclk;
3583 }
3584 if (max_sclk) {
3585 if (ps->performance_levels[i].sclk > max_sclk)
3586 ps->performance_levels[i].sclk = max_sclk;
3587 }
3588 }
3589
3590 /* XXX validate the min clocks required for display */
3591
3592 if (disable_mclk_switching) {
3593 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3594 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3595 } else {
3596 mclk = ps->performance_levels[0].mclk;
3597 vddci = ps->performance_levels[0].vddci;
3598 }
3599
3600 if (disable_sclk_switching) {
3601 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3602 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3603 } else {
3604 sclk = ps->performance_levels[0].sclk;
3605 vddc = ps->performance_levels[0].vddc;
3606 }
3607
3608 if (rps->vce_active) {
3609 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3610 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3611 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3612 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3613 }
3614
3615 /* adjusted low state */
3616 ps->performance_levels[0].sclk = sclk;
3617 ps->performance_levels[0].mclk = mclk;
3618 ps->performance_levels[0].vddc = vddc;
3619 ps->performance_levels[0].vddci = vddci;
3620
3621 if (disable_sclk_switching) {
3622 sclk = ps->performance_levels[0].sclk;
3623 for (i = 1; i < ps->performance_level_count; i++) {
3624 if (sclk < ps->performance_levels[i].sclk)
3625 sclk = ps->performance_levels[i].sclk;
3626 }
3627 for (i = 0; i < ps->performance_level_count; i++) {
3628 ps->performance_levels[i].sclk = sclk;
3629 ps->performance_levels[i].vddc = vddc;
3630 }
3631 } else {
3632 for (i = 1; i < ps->performance_level_count; i++) {
3633 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3634 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3635 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3636 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3637 }
3638 }
3639
3640 if (disable_mclk_switching) {
3641 mclk = ps->performance_levels[0].mclk;
3642 for (i = 1; i < ps->performance_level_count; i++) {
3643 if (mclk < ps->performance_levels[i].mclk)
3644 mclk = ps->performance_levels[i].mclk;
3645 }
3646 for (i = 0; i < ps->performance_level_count; i++) {
3647 ps->performance_levels[i].mclk = mclk;
3648 ps->performance_levels[i].vddci = vddci;
3649 }
3650 } else {
3651 for (i = 1; i < ps->performance_level_count; i++) {
3652 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3653 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3654 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3655 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3656 }
3657 }
3658
3659 for (i = 0; i < ps->performance_level_count; i++)
3660 btc_adjust_clock_combinations(adev, max_limits,
3661 &ps->performance_levels[i]);
3662
3663 for (i = 0; i < ps->performance_level_count; i++) {
3664 if (ps->performance_levels[i].vddc < min_vce_voltage)
3665 ps->performance_levels[i].vddc = min_vce_voltage;
3666 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3667 ps->performance_levels[i].sclk,
3668 max_limits->vddc, &ps->performance_levels[i].vddc);
3669 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3670 ps->performance_levels[i].mclk,
3671 max_limits->vddci, &ps->performance_levels[i].vddci);
3672 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3673 ps->performance_levels[i].mclk,
3674 max_limits->vddc, &ps->performance_levels[i].vddc);
3675 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3676 display_cfg->display_clk,
3677 max_limits->vddc, &ps->performance_levels[i].vddc);
3678 }
3679
3680 for (i = 0; i < ps->performance_level_count; i++) {
3681 btc_apply_voltage_delta_rules(adev,
3682 max_limits->vddc, max_limits->vddci,
3683 &ps->performance_levels[i].vddc,
3684 &ps->performance_levels[i].vddci);
3685 }
3686
3687 ps->dc_compatible = true;
3688 for (i = 0; i < ps->performance_level_count; i++) {
3689 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3690 ps->dc_compatible = false;
3691 }
3692 }
3693
3694 #if 0
3695 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3696 u16 reg_offset, u32 *value)
3697 {
3698 struct si_power_info *si_pi = si_get_pi(adev);
3699
3700 return amdgpu_si_read_smc_sram_dword(adev,
3701 si_pi->soft_regs_start + reg_offset, value,
3702 si_pi->sram_end);
3703 }
3704 #endif
3705
si_write_smc_soft_register(struct amdgpu_device * adev,u16 reg_offset,u32 value)3706 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3707 u16 reg_offset, u32 value)
3708 {
3709 struct si_power_info *si_pi = si_get_pi(adev);
3710
3711 return amdgpu_si_write_smc_sram_dword(adev,
3712 si_pi->soft_regs_start + reg_offset,
3713 value, si_pi->sram_end);
3714 }
3715
si_is_special_1gb_platform(struct amdgpu_device * adev)3716 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3717 {
3718 bool ret = false;
3719 u32 tmp, width, row, column, bank, density;
3720 bool is_memory_gddr5, is_special;
3721
3722 tmp = RREG32(MC_SEQ_MISC0);
3723 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3724 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3725 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3726
3727 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3728 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3729
3730 tmp = RREG32(mmMC_ARB_RAMCFG);
3731 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10;
3732 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8;
3733 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2;
3734
3735 density = (1 << (row + column - 20 + bank)) * width;
3736
3737 if ((adev->pdev->device == 0x6819) &&
3738 is_memory_gddr5 && is_special && (density == 0x400))
3739 ret = true;
3740
3741 return ret;
3742 }
3743
si_get_leakage_vddc(struct amdgpu_device * adev)3744 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3745 {
3746 struct si_power_info *si_pi = si_get_pi(adev);
3747 u16 vddc, count = 0;
3748 int i, ret;
3749
3750 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3751 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3752
3753 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3754 si_pi->leakage_voltage.entries[count].voltage = vddc;
3755 si_pi->leakage_voltage.entries[count].leakage_index =
3756 SISLANDS_LEAKAGE_INDEX0 + i;
3757 count++;
3758 }
3759 }
3760 si_pi->leakage_voltage.count = count;
3761 }
3762
si_get_leakage_voltage_from_leakage_index(struct amdgpu_device * adev,u32 index,u16 * leakage_voltage)3763 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3764 u32 index, u16 *leakage_voltage)
3765 {
3766 struct si_power_info *si_pi = si_get_pi(adev);
3767 int i;
3768
3769 if (leakage_voltage == NULL)
3770 return -EINVAL;
3771
3772 if ((index & 0xff00) != 0xff00)
3773 return -EINVAL;
3774
3775 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3776 return -EINVAL;
3777
3778 if (index < SISLANDS_LEAKAGE_INDEX0)
3779 return -EINVAL;
3780
3781 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3782 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3783 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3784 return 0;
3785 }
3786 }
3787 return -EAGAIN;
3788 }
3789
si_set_dpm_event_sources(struct amdgpu_device * adev,u32 sources)3790 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3791 {
3792 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3793 bool want_thermal_protection;
3794 enum si_dpm_event_src dpm_event_src;
3795
3796 switch (sources) {
3797 case 0:
3798 default:
3799 want_thermal_protection = false;
3800 break;
3801 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL):
3802 want_thermal_protection = true;
3803 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL;
3804 break;
3805 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3806 want_thermal_protection = true;
3807 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL;
3808 break;
3809 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3810 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3811 want_thermal_protection = true;
3812 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3813 break;
3814 }
3815
3816 if (want_thermal_protection) {
3817 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK);
3818 if (pi->thermal_protection)
3819 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3820 } else {
3821 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
3822 }
3823 }
3824
si_enable_auto_throttle_source(struct amdgpu_device * adev,enum si_dpm_auto_throttle_src source,bool enable)3825 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3826 enum si_dpm_auto_throttle_src source,
3827 bool enable)
3828 {
3829 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3830
3831 if (enable) {
3832 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3833 pi->active_auto_throttle_sources |= 1 << source;
3834 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3835 }
3836 } else {
3837 if (pi->active_auto_throttle_sources & (1 << source)) {
3838 pi->active_auto_throttle_sources &= ~(1 << source);
3839 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3840 }
3841 }
3842 }
3843
si_start_dpm(struct amdgpu_device * adev)3844 static void si_start_dpm(struct amdgpu_device *adev)
3845 {
3846 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3847 }
3848
si_stop_dpm(struct amdgpu_device * adev)3849 static void si_stop_dpm(struct amdgpu_device *adev)
3850 {
3851 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);
3852 }
3853
si_enable_sclk_control(struct amdgpu_device * adev,bool enable)3854 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3855 {
3856 if (enable)
3857 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3858 else
3859 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);
3860
3861 }
3862
3863 #if 0
3864 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3865 u32 thermal_level)
3866 {
3867 PPSMC_Result ret;
3868
3869 if (thermal_level == 0) {
3870 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3871 if (ret == PPSMC_Result_OK)
3872 return 0;
3873 else
3874 return -EINVAL;
3875 }
3876 return 0;
3877 }
3878
3879 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3880 {
3881 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3882 }
3883 #endif
3884
3885 #if 0
3886 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3887 {
3888 if (ac_power)
3889 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3890 0 : -EINVAL;
3891
3892 return 0;
3893 }
3894 #endif
3895
si_send_msg_to_smc_with_parameter(struct amdgpu_device * adev,PPSMC_Msg msg,u32 parameter)3896 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3897 PPSMC_Msg msg, u32 parameter)
3898 {
3899 WREG32(mmSMC_SCRATCH0, parameter);
3900 return amdgpu_si_send_msg_to_smc(adev, msg);
3901 }
3902
si_restrict_performance_levels_before_switch(struct amdgpu_device * adev)3903 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3904 {
3905 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3906 return -EINVAL;
3907
3908 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3909 0 : -EINVAL;
3910 }
3911
si_dpm_force_performance_level(void * handle,enum amd_dpm_forced_level level)3912 static int si_dpm_force_performance_level(void *handle,
3913 enum amd_dpm_forced_level level)
3914 {
3915 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3916 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3917 struct si_ps *ps = si_get_ps(rps);
3918 u32 levels = ps->performance_level_count;
3919
3920 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3921 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3922 return -EINVAL;
3923
3924 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3925 return -EINVAL;
3926 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3927 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3928 return -EINVAL;
3929
3930 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3931 return -EINVAL;
3932 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3933 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3934 return -EINVAL;
3935
3936 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3937 return -EINVAL;
3938 }
3939
3940 adev->pm.dpm.forced_level = level;
3941
3942 return 0;
3943 }
3944
3945 #if 0
3946 static int si_set_boot_state(struct amdgpu_device *adev)
3947 {
3948 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3949 0 : -EINVAL;
3950 }
3951 #endif
3952
si_set_sw_state(struct amdgpu_device * adev)3953 static int si_set_sw_state(struct amdgpu_device *adev)
3954 {
3955 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3956 0 : -EINVAL;
3957 }
3958
si_halt_smc(struct amdgpu_device * adev)3959 static int si_halt_smc(struct amdgpu_device *adev)
3960 {
3961 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3962 return -EINVAL;
3963
3964 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3965 0 : -EINVAL;
3966 }
3967
si_resume_smc(struct amdgpu_device * adev)3968 static int si_resume_smc(struct amdgpu_device *adev)
3969 {
3970 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3971 return -EINVAL;
3972
3973 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3974 0 : -EINVAL;
3975 }
3976
si_dpm_start_smc(struct amdgpu_device * adev)3977 static void si_dpm_start_smc(struct amdgpu_device *adev)
3978 {
3979 amdgpu_si_program_jump_on_start(adev);
3980 amdgpu_si_start_smc(adev);
3981 amdgpu_si_smc_clock(adev, true);
3982 }
3983
si_dpm_stop_smc(struct amdgpu_device * adev)3984 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3985 {
3986 amdgpu_si_reset_smc(adev);
3987 amdgpu_si_smc_clock(adev, false);
3988 }
3989
si_process_firmware_header(struct amdgpu_device * adev)3990 static int si_process_firmware_header(struct amdgpu_device *adev)
3991 {
3992 struct si_power_info *si_pi = si_get_pi(adev);
3993 u32 tmp;
3994 int ret;
3995
3996 ret = amdgpu_si_read_smc_sram_dword(adev,
3997 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3998 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3999 &tmp, si_pi->sram_end);
4000 if (ret)
4001 return ret;
4002
4003 si_pi->state_table_start = tmp;
4004
4005 ret = amdgpu_si_read_smc_sram_dword(adev,
4006 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4007 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4008 &tmp, si_pi->sram_end);
4009 if (ret)
4010 return ret;
4011
4012 si_pi->soft_regs_start = tmp;
4013
4014 ret = amdgpu_si_read_smc_sram_dword(adev,
4015 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4016 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4017 &tmp, si_pi->sram_end);
4018 if (ret)
4019 return ret;
4020
4021 si_pi->mc_reg_table_start = tmp;
4022
4023 ret = amdgpu_si_read_smc_sram_dword(adev,
4024 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4025 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4026 &tmp, si_pi->sram_end);
4027 if (ret)
4028 return ret;
4029
4030 si_pi->fan_table_start = tmp;
4031
4032 ret = amdgpu_si_read_smc_sram_dword(adev,
4033 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4034 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4035 &tmp, si_pi->sram_end);
4036 if (ret)
4037 return ret;
4038
4039 si_pi->arb_table_start = tmp;
4040
4041 ret = amdgpu_si_read_smc_sram_dword(adev,
4042 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4043 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4044 &tmp, si_pi->sram_end);
4045 if (ret)
4046 return ret;
4047
4048 si_pi->cac_table_start = tmp;
4049
4050 ret = amdgpu_si_read_smc_sram_dword(adev,
4051 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4052 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4053 &tmp, si_pi->sram_end);
4054 if (ret)
4055 return ret;
4056
4057 si_pi->dte_table_start = tmp;
4058
4059 ret = amdgpu_si_read_smc_sram_dword(adev,
4060 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4061 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4062 &tmp, si_pi->sram_end);
4063 if (ret)
4064 return ret;
4065
4066 si_pi->spll_table_start = tmp;
4067
4068 ret = amdgpu_si_read_smc_sram_dword(adev,
4069 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4070 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4071 &tmp, si_pi->sram_end);
4072 if (ret)
4073 return ret;
4074
4075 si_pi->papm_cfg_table_start = tmp;
4076
4077 return ret;
4078 }
4079
si_read_clock_registers(struct amdgpu_device * adev)4080 static void si_read_clock_registers(struct amdgpu_device *adev)
4081 {
4082 struct si_power_info *si_pi = si_get_pi(adev);
4083
4084 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL);
4085 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2);
4086 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3);
4087 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4);
4088 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM);
4089 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2);
4090 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4091 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4092 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4093 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4094 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4095 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4096 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4097 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4098 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4099 }
4100
si_enable_thermal_protection(struct amdgpu_device * adev,bool enable)4101 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4102 bool enable)
4103 {
4104 if (enable)
4105 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4106 else
4107 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);
4108 }
4109
si_enable_acpi_power_management(struct amdgpu_device * adev)4110 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4111 {
4112 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK);
4113 }
4114
4115 #if 0
4116 static int si_enter_ulp_state(struct amdgpu_device *adev)
4117 {
4118 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4119
4120 udelay(25000);
4121
4122 return 0;
4123 }
4124
4125 static int si_exit_ulp_state(struct amdgpu_device *adev)
4126 {
4127 int i;
4128
4129 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4130
4131 udelay(7000);
4132
4133 for (i = 0; i < adev->usec_timeout; i++) {
4134 if (RREG32(SMC_RESP_0) == 1)
4135 break;
4136 udelay(1000);
4137 }
4138
4139 return 0;
4140 }
4141 #endif
4142
si_notify_smc_display_change(struct amdgpu_device * adev,bool has_display)4143 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4144 bool has_display)
4145 {
4146 PPSMC_Msg msg = has_display ?
4147 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4148
4149 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4150 0 : -EINVAL;
4151 }
4152
si_program_response_times(struct amdgpu_device * adev)4153 static void si_program_response_times(struct amdgpu_device *adev)
4154 {
4155 u32 voltage_response_time, acpi_delay_time, vbi_time_out;
4156 u32 vddc_dly, acpi_dly, vbi_dly;
4157 u32 reference_clock;
4158
4159 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4160
4161 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4162
4163 if (voltage_response_time == 0)
4164 voltage_response_time = 1000;
4165
4166 acpi_delay_time = 15000;
4167 vbi_time_out = 100000;
4168
4169 reference_clock = amdgpu_asic_get_xclk(adev);
4170
4171 vddc_dly = (voltage_response_time * reference_clock) / 100;
4172 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4173 vbi_dly = (vbi_time_out * reference_clock) / 100;
4174
4175 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4176 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4177 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4178 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4179 }
4180
si_program_ds_registers(struct amdgpu_device * adev)4181 static void si_program_ds_registers(struct amdgpu_device *adev)
4182 {
4183 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4184 u32 tmp;
4185
4186 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4187 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4188 tmp = 0x10;
4189 else
4190 tmp = 0x1;
4191
4192 if (eg_pi->sclk_deep_sleep) {
4193 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK);
4194 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK,
4195 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK);
4196 }
4197 }
4198
si_program_display_gap(struct amdgpu_device * adev)4199 static void si_program_display_gap(struct amdgpu_device *adev)
4200 {
4201 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
4202 u32 tmp, pipe;
4203
4204 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4205 if (cfg->num_display > 0)
4206 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4207 else
4208 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT;
4209
4210 if (cfg->num_display > 1)
4211 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4212 else
4213 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT;
4214
4215 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4216
4217 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4218 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4219
4220 if (cfg->num_display > 0 && pipe != cfg->crtc_index) {
4221 pipe = cfg->crtc_index;
4222
4223 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4224 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4225 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4226 }
4227
4228 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4229 * This can be a problem on PowerXpress systems or if you want to use the card
4230 * for offscreen rendering or compute if there are no crtcs enabled.
4231 */
4232 si_notify_smc_display_change(adev, cfg->num_display > 0);
4233 }
4234
si_enable_spread_spectrum(struct amdgpu_device * adev,bool enable)4235 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4236 {
4237 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4238
4239 if (enable) {
4240 if (pi->sclk_ss)
4241 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4242 } else {
4243 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
4244 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);
4245 }
4246 }
4247
si_setup_bsp(struct amdgpu_device * adev)4248 static void si_setup_bsp(struct amdgpu_device *adev)
4249 {
4250 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4251 u32 xclk = amdgpu_asic_get_xclk(adev);
4252
4253 r600_calculate_u_and_p(pi->asi,
4254 xclk,
4255 16,
4256 &pi->bsp,
4257 &pi->bsu);
4258
4259 r600_calculate_u_and_p(pi->pasi,
4260 xclk,
4261 16,
4262 &pi->pbsp,
4263 &pi->pbsu);
4264
4265
4266 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT);
4267 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT);
4268
4269 WREG32(mmCG_BSP, pi->dsp);
4270 }
4271
si_program_git(struct amdgpu_device * adev)4272 static void si_program_git(struct amdgpu_device *adev)
4273 {
4274 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK);
4275 }
4276
si_program_tp(struct amdgpu_device * adev)4277 static void si_program_tp(struct amdgpu_device *adev)
4278 {
4279 int i;
4280 enum r600_td td = R600_TD_DFLT;
4281
4282 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4283 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT));
4284
4285 if (td == R600_TD_AUTO)
4286 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4287 else
4288 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);
4289
4290 if (td == R600_TD_UP)
4291 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4292
4293 if (td == R600_TD_DOWN)
4294 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);
4295 }
4296
si_program_tpp(struct amdgpu_device * adev)4297 static void si_program_tpp(struct amdgpu_device *adev)
4298 {
4299 WREG32(mmCG_TPC, R600_TPC_DFLT);
4300 }
4301
si_program_sstp(struct amdgpu_device * adev)4302 static void si_program_sstp(struct amdgpu_device *adev)
4303 {
4304 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT));
4305 }
4306
si_enable_display_gap(struct amdgpu_device * adev)4307 static void si_enable_display_gap(struct amdgpu_device *adev)
4308 {
4309 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);
4310
4311 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);
4312 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT |
4313 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT);
4314
4315 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK);
4316 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT |
4317 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT);
4318 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp);
4319 }
4320
si_program_vc(struct amdgpu_device * adev)4321 static void si_program_vc(struct amdgpu_device *adev)
4322 {
4323 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4324
4325 WREG32(mmCG_FTV, pi->vrc);
4326 }
4327
si_clear_vc(struct amdgpu_device * adev)4328 static void si_clear_vc(struct amdgpu_device *adev)
4329 {
4330 WREG32(mmCG_FTV, 0);
4331 }
4332
si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)4333 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4334 {
4335 u8 mc_para_index;
4336
4337 if (memory_clock < 10000)
4338 mc_para_index = 0;
4339 else if (memory_clock >= 80000)
4340 mc_para_index = 0x0f;
4341 else
4342 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4343 return mc_para_index;
4344 }
4345
si_get_mclk_frequency_ratio(u32 memory_clock,bool strobe_mode)4346 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4347 {
4348 u8 mc_para_index;
4349
4350 if (strobe_mode) {
4351 if (memory_clock < 12500)
4352 mc_para_index = 0x00;
4353 else if (memory_clock > 47500)
4354 mc_para_index = 0x0f;
4355 else
4356 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4357 } else {
4358 if (memory_clock < 65000)
4359 mc_para_index = 0x00;
4360 else if (memory_clock > 135000)
4361 mc_para_index = 0x0f;
4362 else
4363 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4364 }
4365 return mc_para_index;
4366 }
4367
si_get_strobe_mode_settings(struct amdgpu_device * adev,u32 mclk)4368 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4369 {
4370 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4371 bool strobe_mode = false;
4372 u8 result = 0;
4373
4374 if (mclk <= pi->mclk_strobe_mode_threshold)
4375 strobe_mode = true;
4376
4377 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4378 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4379 else
4380 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4381
4382 if (strobe_mode)
4383 result |= SISLANDS_SMC_STROBE_ENABLE;
4384
4385 return result;
4386 }
4387
si_upload_firmware(struct amdgpu_device * adev)4388 static int si_upload_firmware(struct amdgpu_device *adev)
4389 {
4390 struct si_power_info *si_pi = si_get_pi(adev);
4391
4392 amdgpu_si_reset_smc(adev);
4393 amdgpu_si_smc_clock(adev, false);
4394
4395 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4396 }
4397
si_validate_phase_shedding_tables(struct amdgpu_device * adev,const struct atom_voltage_table * table,const struct amdgpu_phase_shedding_limits_table * limits)4398 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4399 const struct atom_voltage_table *table,
4400 const struct amdgpu_phase_shedding_limits_table *limits)
4401 {
4402 u32 data, num_bits, num_levels;
4403
4404 if ((table == NULL) || (limits == NULL))
4405 return false;
4406
4407 data = table->mask_low;
4408
4409 num_bits = hweight32(data);
4410
4411 if (num_bits == 0)
4412 return false;
4413
4414 num_levels = (1 << num_bits);
4415
4416 if (table->count != num_levels)
4417 return false;
4418
4419 if (limits->count != (num_levels - 1))
4420 return false;
4421
4422 return true;
4423 }
4424
si_trim_voltage_table_to_fit_state_table(struct amdgpu_device * adev,u32 max_voltage_steps,struct atom_voltage_table * voltage_table)4425 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4426 u32 max_voltage_steps,
4427 struct atom_voltage_table *voltage_table)
4428 {
4429 unsigned int i, diff;
4430
4431 if (voltage_table->count <= max_voltage_steps)
4432 return;
4433
4434 diff = voltage_table->count - max_voltage_steps;
4435
4436 for (i= 0; i < max_voltage_steps; i++)
4437 voltage_table->entries[i] = voltage_table->entries[i + diff];
4438
4439 voltage_table->count = max_voltage_steps;
4440 }
4441
si_get_svi2_voltage_table(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * voltage_dependency_table,struct atom_voltage_table * voltage_table)4442 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4443 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4444 struct atom_voltage_table *voltage_table)
4445 {
4446 u32 i;
4447
4448 if (voltage_dependency_table == NULL)
4449 return -EINVAL;
4450
4451 voltage_table->mask_low = 0;
4452 voltage_table->phase_delay = 0;
4453
4454 voltage_table->count = voltage_dependency_table->count;
4455 for (i = 0; i < voltage_table->count; i++) {
4456 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4457 voltage_table->entries[i].smio_low = 0;
4458 }
4459
4460 return 0;
4461 }
4462
si_construct_voltage_tables(struct amdgpu_device * adev)4463 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4464 {
4465 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4466 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4467 struct si_power_info *si_pi = si_get_pi(adev);
4468 int ret;
4469
4470 if (pi->voltage_control) {
4471 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4472 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4473 if (ret)
4474 return ret;
4475
4476 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4477 si_trim_voltage_table_to_fit_state_table(adev,
4478 SISLANDS_MAX_NO_VREG_STEPS,
4479 &eg_pi->vddc_voltage_table);
4480 } else if (si_pi->voltage_control_svi2) {
4481 ret = si_get_svi2_voltage_table(adev,
4482 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4483 &eg_pi->vddc_voltage_table);
4484 if (ret)
4485 return ret;
4486 } else {
4487 return -EINVAL;
4488 }
4489
4490 if (eg_pi->vddci_control) {
4491 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4492 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4493 if (ret)
4494 return ret;
4495
4496 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4497 si_trim_voltage_table_to_fit_state_table(adev,
4498 SISLANDS_MAX_NO_VREG_STEPS,
4499 &eg_pi->vddci_voltage_table);
4500 }
4501 if (si_pi->vddci_control_svi2) {
4502 ret = si_get_svi2_voltage_table(adev,
4503 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4504 &eg_pi->vddci_voltage_table);
4505 if (ret)
4506 return ret;
4507 }
4508
4509 if (pi->mvdd_control) {
4510 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4511 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4512
4513 if (ret) {
4514 pi->mvdd_control = false;
4515 return ret;
4516 }
4517
4518 if (si_pi->mvdd_voltage_table.count == 0) {
4519 pi->mvdd_control = false;
4520 return -EINVAL;
4521 }
4522
4523 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4524 si_trim_voltage_table_to_fit_state_table(adev,
4525 SISLANDS_MAX_NO_VREG_STEPS,
4526 &si_pi->mvdd_voltage_table);
4527 }
4528
4529 if (si_pi->vddc_phase_shed_control) {
4530 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4531 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4532 if (ret)
4533 si_pi->vddc_phase_shed_control = false;
4534
4535 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4536 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4537 si_pi->vddc_phase_shed_control = false;
4538 }
4539
4540 return 0;
4541 }
4542
si_populate_smc_voltage_table(struct amdgpu_device * adev,const struct atom_voltage_table * voltage_table,SISLANDS_SMC_STATETABLE * table)4543 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4544 const struct atom_voltage_table *voltage_table,
4545 SISLANDS_SMC_STATETABLE *table)
4546 {
4547 unsigned int i;
4548
4549 for (i = 0; i < voltage_table->count; i++)
4550 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4551 }
4552
si_populate_smc_voltage_tables(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)4553 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4554 SISLANDS_SMC_STATETABLE *table)
4555 {
4556 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4557 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4558 struct si_power_info *si_pi = si_get_pi(adev);
4559 u8 i;
4560
4561 if (si_pi->voltage_control_svi2) {
4562 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4563 si_pi->svc_gpio_id);
4564 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4565 si_pi->svd_gpio_id);
4566 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4567 2);
4568 } else {
4569 if (eg_pi->vddc_voltage_table.count) {
4570 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4571 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4572 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4573
4574 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4575 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4576 table->maxVDDCIndexInPPTable = i;
4577 break;
4578 }
4579 }
4580 }
4581
4582 if (eg_pi->vddci_voltage_table.count) {
4583 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4584
4585 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4586 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4587 }
4588
4589
4590 if (si_pi->mvdd_voltage_table.count) {
4591 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4592
4593 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4594 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4595 }
4596
4597 if (si_pi->vddc_phase_shed_control) {
4598 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4599 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4600 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4601
4602 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4603 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4604
4605 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4606 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4607 } else {
4608 si_pi->vddc_phase_shed_control = false;
4609 }
4610 }
4611 }
4612
4613 return 0;
4614 }
4615
si_populate_voltage_value(struct amdgpu_device * adev,const struct atom_voltage_table * table,u16 value,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4616 static int si_populate_voltage_value(struct amdgpu_device *adev,
4617 const struct atom_voltage_table *table,
4618 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4619 {
4620 unsigned int i;
4621
4622 for (i = 0; i < table->count; i++) {
4623 if (value <= table->entries[i].value) {
4624 voltage->index = (u8)i;
4625 voltage->value = cpu_to_be16(table->entries[i].value);
4626 break;
4627 }
4628 }
4629
4630 if (i >= table->count)
4631 return -EINVAL;
4632
4633 return 0;
4634 }
4635
si_populate_mvdd_value(struct amdgpu_device * adev,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4636 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4637 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4638 {
4639 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4640 struct si_power_info *si_pi = si_get_pi(adev);
4641
4642 if (pi->mvdd_control) {
4643 if (mclk <= pi->mvdd_split_frequency)
4644 voltage->index = 0;
4645 else
4646 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4647
4648 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4649 }
4650 return 0;
4651 }
4652
si_get_std_voltage_value(struct amdgpu_device * adev,SISLANDS_SMC_VOLTAGE_VALUE * voltage,u16 * std_voltage)4653 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4654 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4655 u16 *std_voltage)
4656 {
4657 u16 v_index;
4658 bool voltage_found = false;
4659 *std_voltage = be16_to_cpu(voltage->value);
4660
4661 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4662 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4663 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4664 return -EINVAL;
4665
4666 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4667 if (be16_to_cpu(voltage->value) ==
4668 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4669 voltage_found = true;
4670 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4671 *std_voltage =
4672 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4673 else
4674 *std_voltage =
4675 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4676 break;
4677 }
4678 }
4679
4680 if (!voltage_found) {
4681 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4682 if (be16_to_cpu(voltage->value) <=
4683 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4684 voltage_found = true;
4685 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4686 *std_voltage =
4687 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4688 else
4689 *std_voltage =
4690 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4691 break;
4692 }
4693 }
4694 }
4695 } else {
4696 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4697 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4698 }
4699 }
4700
4701 return 0;
4702 }
4703
si_populate_std_voltage_value(struct amdgpu_device * adev,u16 value,u8 index,SISLANDS_SMC_VOLTAGE_VALUE * voltage)4704 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4705 u16 value, u8 index,
4706 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4707 {
4708 voltage->index = index;
4709 voltage->value = cpu_to_be16(value);
4710
4711 return 0;
4712 }
4713
si_populate_phase_shedding_value(struct amdgpu_device * adev,const struct amdgpu_phase_shedding_limits_table * limits,u16 voltage,u32 sclk,u32 mclk,SISLANDS_SMC_VOLTAGE_VALUE * smc_voltage)4714 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4715 const struct amdgpu_phase_shedding_limits_table *limits,
4716 u16 voltage, u32 sclk, u32 mclk,
4717 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4718 {
4719 unsigned int i;
4720
4721 for (i = 0; i < limits->count; i++) {
4722 if ((voltage <= limits->entries[i].voltage) &&
4723 (sclk <= limits->entries[i].sclk) &&
4724 (mclk <= limits->entries[i].mclk))
4725 break;
4726 }
4727
4728 smc_voltage->phase_settings = (u8)i;
4729
4730 return 0;
4731 }
4732
si_init_arb_table_index(struct amdgpu_device * adev)4733 static int si_init_arb_table_index(struct amdgpu_device *adev)
4734 {
4735 struct si_power_info *si_pi = si_get_pi(adev);
4736 u32 tmp;
4737 int ret;
4738
4739 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4740 &tmp, si_pi->sram_end);
4741 if (ret)
4742 return ret;
4743
4744 tmp &= 0x00FFFFFF;
4745 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4746
4747 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4748 tmp, si_pi->sram_end);
4749 }
4750
si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device * adev)4751 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4752 {
4753 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4754 }
4755
si_reset_to_default(struct amdgpu_device * adev)4756 static int si_reset_to_default(struct amdgpu_device *adev)
4757 {
4758 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4759 0 : -EINVAL;
4760 }
4761
si_force_switch_to_arb_f0(struct amdgpu_device * adev)4762 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4763 {
4764 struct si_power_info *si_pi = si_get_pi(adev);
4765 u32 tmp;
4766 int ret;
4767
4768 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4769 &tmp, si_pi->sram_end);
4770 if (ret)
4771 return ret;
4772
4773 tmp = (tmp >> 24) & 0xff;
4774
4775 if (tmp == MC_CG_ARB_FREQ_F0)
4776 return 0;
4777
4778 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4779 }
4780
si_calculate_memory_refresh_rate(struct amdgpu_device * adev,u32 engine_clock)4781 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4782 u32 engine_clock)
4783 {
4784 u32 dram_rows;
4785 u32 dram_refresh_rate;
4786 u32 mc_arb_rfsh_rate;
4787 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;
4788
4789 if (tmp >= 4)
4790 dram_rows = 16384;
4791 else
4792 dram_rows = 1 << (tmp + 10);
4793
4794 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4795 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4796
4797 return mc_arb_rfsh_rate;
4798 }
4799
si_populate_memory_timing_parameters(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCArbDramTimingRegisterSet * arb_regs)4800 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4801 struct rv7xx_pl *pl,
4802 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4803 {
4804 u32 dram_timing;
4805 u32 dram_timing2;
4806 u32 burst_time;
4807 int ret;
4808
4809 arb_regs->mc_arb_rfsh_rate =
4810 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4811
4812 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk,
4813 pl->mclk);
4814 if (ret)
4815 return ret;
4816
4817 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4818 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4819 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4820
4821 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4822 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4823 arb_regs->mc_arb_burst_time = (u8)burst_time;
4824
4825 return 0;
4826 }
4827
si_do_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,unsigned int first_arb_set)4828 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4829 struct amdgpu_ps *amdgpu_state,
4830 unsigned int first_arb_set)
4831 {
4832 struct si_power_info *si_pi = si_get_pi(adev);
4833 struct si_ps *state = si_get_ps(amdgpu_state);
4834 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4835 int i, ret = 0;
4836
4837 for (i = 0; i < state->performance_level_count; i++) {
4838 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4839 if (ret)
4840 break;
4841 ret = amdgpu_si_copy_bytes_to_smc(adev,
4842 si_pi->arb_table_start +
4843 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4844 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4845 (u8 *)&arb_regs,
4846 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4847 si_pi->sram_end);
4848 if (ret)
4849 break;
4850 }
4851
4852 return ret;
4853 }
4854
si_program_memory_timing_parameters(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)4855 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4856 struct amdgpu_ps *amdgpu_new_state)
4857 {
4858 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4859 SISLANDS_DRIVER_STATE_ARB_INDEX);
4860 }
4861
si_populate_initial_mvdd_value(struct amdgpu_device * adev,struct SISLANDS_SMC_VOLTAGE_VALUE * voltage)4862 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4863 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4864 {
4865 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4866 struct si_power_info *si_pi = si_get_pi(adev);
4867
4868 if (pi->mvdd_control)
4869 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4870 si_pi->mvdd_bootup_value, voltage);
4871
4872 return 0;
4873 }
4874
si_populate_smc_initial_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_initial_state,SISLANDS_SMC_STATETABLE * table)4875 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4876 struct amdgpu_ps *amdgpu_initial_state,
4877 SISLANDS_SMC_STATETABLE *table)
4878 {
4879 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4880 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4881 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4882 struct si_power_info *si_pi = si_get_pi(adev);
4883 u32 reg;
4884 int ret;
4885
4886 table->initialState.level.mclk.vDLL_CNTL =
4887 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4888 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4889 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4890 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4891 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4892 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4893 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4894 table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4895 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4896 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4897 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4898 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4899 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4900 table->initialState.level.mclk.vMPLL_SS =
4901 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4902 table->initialState.level.mclk.vMPLL_SS2 =
4903 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4904
4905 table->initialState.level.mclk.mclk_value =
4906 cpu_to_be32(initial_state->performance_levels[0].mclk);
4907
4908 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4909 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4910 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4911 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4912 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4913 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4914 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4915 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4916 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4917 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4918 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4919 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4920
4921 table->initialState.level.sclk.sclk_value =
4922 cpu_to_be32(initial_state->performance_levels[0].sclk);
4923
4924 table->initialState.level.arbRefreshState =
4925 SISLANDS_INITIAL_STATE_ARB_INDEX;
4926
4927 table->initialState.level.ACIndex = 0;
4928
4929 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4930 initial_state->performance_levels[0].vddc,
4931 &table->initialState.level.vddc);
4932
4933 if (!ret) {
4934 u16 std_vddc;
4935
4936 ret = si_get_std_voltage_value(adev,
4937 &table->initialState.level.vddc,
4938 &std_vddc);
4939 if (!ret)
4940 si_populate_std_voltage_value(adev, std_vddc,
4941 table->initialState.level.vddc.index,
4942 &table->initialState.level.std_vddc);
4943 }
4944
4945 if (eg_pi->vddci_control)
4946 si_populate_voltage_value(adev,
4947 &eg_pi->vddci_voltage_table,
4948 initial_state->performance_levels[0].vddci,
4949 &table->initialState.level.vddci);
4950
4951 if (si_pi->vddc_phase_shed_control)
4952 si_populate_phase_shedding_value(adev,
4953 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4954 initial_state->performance_levels[0].vddc,
4955 initial_state->performance_levels[0].sclk,
4956 initial_state->performance_levels[0].mclk,
4957 &table->initialState.level.vddc);
4958
4959 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd);
4960
4961 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
4962 table->initialState.level.aT = cpu_to_be32(reg);
4963 table->initialState.level.bSP = cpu_to_be32(pi->dsp);
4964 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4965
4966 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4967 table->initialState.level.strobeMode =
4968 si_get_strobe_mode_settings(adev,
4969 initial_state->performance_levels[0].mclk);
4970
4971 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4972 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4973 else
4974 table->initialState.level.mcFlags = 0;
4975 }
4976
4977 table->initialState.levelCount = 1;
4978
4979 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4980
4981 table->initialState.level.dpm2.MaxPS = 0;
4982 table->initialState.level.dpm2.NearTDPDec = 0;
4983 table->initialState.level.dpm2.AboveSafeInc = 0;
4984 table->initialState.level.dpm2.BelowSafeInc = 0;
4985 table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4986
4987 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK |
4988 SQ_POWER_THROTTLE__MAX_POWER_MASK;
4989 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4990
4991 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK |
4992 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK |
4993 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
4994 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4995
4996 return 0;
4997 }
4998
si_gen_pcie_gen_support(struct amdgpu_device * adev,u32 sys_mask,enum si_pcie_gen asic_gen,enum si_pcie_gen default_gen)4999 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev,
5000 u32 sys_mask,
5001 enum si_pcie_gen asic_gen,
5002 enum si_pcie_gen default_gen)
5003 {
5004 switch (asic_gen) {
5005 case SI_PCIE_GEN1:
5006 return SI_PCIE_GEN1;
5007 case SI_PCIE_GEN2:
5008 return SI_PCIE_GEN2;
5009 case SI_PCIE_GEN3:
5010 return SI_PCIE_GEN3;
5011 default:
5012 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
5013 (default_gen == SI_PCIE_GEN3))
5014 return SI_PCIE_GEN3;
5015 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
5016 (default_gen == SI_PCIE_GEN2))
5017 return SI_PCIE_GEN2;
5018 else
5019 return SI_PCIE_GEN1;
5020 }
5021 return SI_PCIE_GEN1;
5022 }
5023
si_populate_smc_acpi_state(struct amdgpu_device * adev,SISLANDS_SMC_STATETABLE * table)5024 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
5025 SISLANDS_SMC_STATETABLE *table)
5026 {
5027 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5028 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5029 struct si_power_info *si_pi = si_get_pi(adev);
5030 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5031 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5032 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5033 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5034 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5035 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5036 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5037 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5038 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5039 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5040 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5041 u32 reg;
5042 int ret;
5043
5044 table->ACPIState = table->initialState;
5045
5046 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5047
5048 if (pi->acpi_vddc) {
5049 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5050 pi->acpi_vddc, &table->ACPIState.level.vddc);
5051 if (!ret) {
5052 u16 std_vddc;
5053
5054 ret = si_get_std_voltage_value(adev,
5055 &table->ACPIState.level.vddc, &std_vddc);
5056 if (!ret)
5057 si_populate_std_voltage_value(adev, std_vddc,
5058 table->ACPIState.level.vddc.index,
5059 &table->ACPIState.level.std_vddc);
5060 }
5061 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
5062
5063 if (si_pi->vddc_phase_shed_control) {
5064 si_populate_phase_shedding_value(adev,
5065 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5066 pi->acpi_vddc,
5067 0,
5068 0,
5069 &table->ACPIState.level.vddc);
5070 }
5071 } else {
5072 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5073 pi->min_vddc_in_table, &table->ACPIState.level.vddc);
5074 if (!ret) {
5075 u16 std_vddc;
5076
5077 ret = si_get_std_voltage_value(adev,
5078 &table->ACPIState.level.vddc, &std_vddc);
5079
5080 if (!ret)
5081 si_populate_std_voltage_value(adev, std_vddc,
5082 table->ACPIState.level.vddc.index,
5083 &table->ACPIState.level.std_vddc);
5084 }
5085 table->ACPIState.level.gen2PCIE =
5086 (u8)si_gen_pcie_gen_support(adev,
5087 si_pi->sys_pcie_mask,
5088 si_pi->boot_pcie_gen,
5089 SI_PCIE_GEN1);
5090
5091 if (si_pi->vddc_phase_shed_control)
5092 si_populate_phase_shedding_value(adev,
5093 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5094 pi->min_vddc_in_table,
5095 0,
5096 0,
5097 &table->ACPIState.level.vddc);
5098 }
5099
5100 if (pi->acpi_vddc) {
5101 if (eg_pi->acpi_vddci)
5102 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5103 eg_pi->acpi_vddci,
5104 &table->ACPIState.level.vddci);
5105 }
5106
5107 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5108 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5109
5110 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5111
5112 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5113 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5114
5115 table->ACPIState.level.mclk.vDLL_CNTL =
5116 cpu_to_be32(dll_cntl);
5117 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
5118 cpu_to_be32(mclk_pwrmgt_cntl);
5119 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
5120 cpu_to_be32(mpll_ad_func_cntl);
5121 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
5122 cpu_to_be32(mpll_dq_func_cntl);
5123 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
5124 cpu_to_be32(mpll_func_cntl);
5125 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
5126 cpu_to_be32(mpll_func_cntl_1);
5127 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
5128 cpu_to_be32(mpll_func_cntl_2);
5129 table->ACPIState.level.mclk.vMPLL_SS =
5130 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5131 table->ACPIState.level.mclk.vMPLL_SS2 =
5132 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5133
5134 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
5135 cpu_to_be32(spll_func_cntl);
5136 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
5137 cpu_to_be32(spll_func_cntl_2);
5138 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
5139 cpu_to_be32(spll_func_cntl_3);
5140 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
5141 cpu_to_be32(spll_func_cntl_4);
5142
5143 table->ACPIState.level.mclk.mclk_value = 0;
5144 table->ACPIState.level.sclk.sclk_value = 0;
5145
5146 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd);
5147
5148 if (eg_pi->dynamic_ac_timing)
5149 table->ACPIState.level.ACIndex = 0;
5150
5151 table->ACPIState.level.dpm2.MaxPS = 0;
5152 table->ACPIState.level.dpm2.NearTDPDec = 0;
5153 table->ACPIState.level.dpm2.AboveSafeInc = 0;
5154 table->ACPIState.level.dpm2.BelowSafeInc = 0;
5155 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
5156
5157 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK;
5158 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
5159
5160 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK;
5161 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5162
5163 return 0;
5164 }
5165
si_populate_ulv_state(struct amdgpu_device * adev,struct SISLANDS_SMC_SWSTATE_SINGLE * state)5166 static int si_populate_ulv_state(struct amdgpu_device *adev,
5167 struct SISLANDS_SMC_SWSTATE_SINGLE *state)
5168 {
5169 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5170 struct si_power_info *si_pi = si_get_pi(adev);
5171 struct si_ulv_param *ulv = &si_pi->ulv;
5172 u32 sclk_in_sr = 1350; /* ??? */
5173 int ret;
5174
5175 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5176 &state->level);
5177 if (!ret) {
5178 if (eg_pi->sclk_deep_sleep) {
5179 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5180 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5181 else
5182 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5183 }
5184 if (ulv->one_pcie_lane_in_ulv)
5185 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5186 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5187 state->level.ACIndex = 1;
5188 state->level.std_vddc = state->level.vddc;
5189 state->levelCount = 1;
5190
5191 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5192 }
5193
5194 return ret;
5195 }
5196
si_program_ulv_memory_timing_parameters(struct amdgpu_device * adev)5197 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5198 {
5199 struct si_power_info *si_pi = si_get_pi(adev);
5200 struct si_ulv_param *ulv = &si_pi->ulv;
5201 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5202 int ret;
5203
5204 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5205 &arb_regs);
5206 if (ret)
5207 return ret;
5208
5209 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5210 ulv->volt_change_delay);
5211
5212 ret = amdgpu_si_copy_bytes_to_smc(adev,
5213 si_pi->arb_table_start +
5214 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5215 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5216 (u8 *)&arb_regs,
5217 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5218 si_pi->sram_end);
5219
5220 return ret;
5221 }
5222
si_get_mvdd_configuration(struct amdgpu_device * adev)5223 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5224 {
5225 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5226
5227 pi->mvdd_split_frequency = 30000;
5228 }
5229
si_init_smc_table(struct amdgpu_device * adev)5230 static int si_init_smc_table(struct amdgpu_device *adev)
5231 {
5232 struct si_power_info *si_pi = si_get_pi(adev);
5233 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5234 const struct si_ulv_param *ulv = &si_pi->ulv;
5235 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5236 int ret;
5237 u32 lane_width;
5238 u32 vr_hot_gpio;
5239
5240 si_populate_smc_voltage_tables(adev, table);
5241
5242 switch (adev->pm.int_thermal_type) {
5243 case THERMAL_TYPE_SI:
5244 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5245 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5246 break;
5247 case THERMAL_TYPE_NONE:
5248 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5249 break;
5250 default:
5251 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5252 break;
5253 }
5254
5255 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5256 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5257
5258 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5259 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5260 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5261 }
5262
5263 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5264 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5265
5266 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5267 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5268
5269 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5270 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5271
5272 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5273 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5274 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5275 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5276 vr_hot_gpio);
5277 }
5278
5279 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5280 if (ret)
5281 return ret;
5282
5283 ret = si_populate_smc_acpi_state(adev, table);
5284 if (ret)
5285 return ret;
5286
5287 table->driverState.flags = table->initialState.flags;
5288 table->driverState.levelCount = table->initialState.levelCount;
5289 table->driverState.levels[0] = table->initialState.level;
5290
5291 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5292 SISLANDS_INITIAL_STATE_ARB_INDEX);
5293 if (ret)
5294 return ret;
5295
5296 if (ulv->supported && ulv->pl.vddc) {
5297 ret = si_populate_ulv_state(adev, &table->ULVState);
5298 if (ret)
5299 return ret;
5300
5301 ret = si_program_ulv_memory_timing_parameters(adev);
5302 if (ret)
5303 return ret;
5304
5305 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control);
5306 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5307
5308 lane_width = amdgpu_get_pcie_lanes(adev);
5309 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5310 } else {
5311 table->ULVState = table->initialState;
5312 }
5313
5314 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5315 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5316 si_pi->sram_end);
5317 }
5318
si_calculate_sclk_params(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5319 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5320 u32 engine_clock,
5321 SISLANDS_SMC_SCLK_VALUE *sclk)
5322 {
5323 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5324 struct si_power_info *si_pi = si_get_pi(adev);
5325 struct atom_clock_dividers dividers;
5326 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5327 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5328 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5329 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5330 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5331 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5332 u64 tmp;
5333 u32 reference_clock = adev->clock.spll.reference_freq;
5334 u32 reference_divider;
5335 u32 fbdiv;
5336 int ret;
5337
5338 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5339 engine_clock, false, ÷rs);
5340 if (ret)
5341 return ret;
5342
5343 reference_divider = 1 + dividers.ref_div;
5344
5345 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5346 do_div(tmp, reference_clock);
5347 fbdiv = (u32) tmp;
5348
5349 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK);
5350 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT;
5351 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;
5352
5353 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
5354 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT;
5355
5356 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
5357 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT;
5358 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
5359
5360 if (pi->sclk_ss) {
5361 struct amdgpu_atom_ss ss;
5362 u32 vco_freq = engine_clock * dividers.post_div;
5363
5364 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5365 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5366 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5367 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5368
5369 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK;
5370 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT;
5371 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
5372
5373 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK;
5374 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT;
5375 }
5376 }
5377
5378 sclk->sclk_value = engine_clock;
5379 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5380 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5381 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5382 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5383 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5384 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5385
5386 return 0;
5387 }
5388
si_populate_sclk_value(struct amdgpu_device * adev,u32 engine_clock,SISLANDS_SMC_SCLK_VALUE * sclk)5389 static int si_populate_sclk_value(struct amdgpu_device *adev,
5390 u32 engine_clock,
5391 SISLANDS_SMC_SCLK_VALUE *sclk)
5392 {
5393 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5394 int ret;
5395
5396 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5397 if (!ret) {
5398 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5399 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5400 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5401 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5402 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5403 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5404 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5405 }
5406
5407 return ret;
5408 }
5409
si_populate_mclk_value(struct amdgpu_device * adev,u32 engine_clock,u32 memory_clock,SISLANDS_SMC_MCLK_VALUE * mclk,bool strobe_mode,bool dll_state_on)5410 static int si_populate_mclk_value(struct amdgpu_device *adev,
5411 u32 engine_clock,
5412 u32 memory_clock,
5413 SISLANDS_SMC_MCLK_VALUE *mclk,
5414 bool strobe_mode,
5415 bool dll_state_on)
5416 {
5417 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5418 struct si_power_info *si_pi = si_get_pi(adev);
5419 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5420 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5421 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5422 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5423 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5424 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5425 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5426 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5427 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5428 struct atom_mpll_param mpll_param;
5429 int ret;
5430
5431 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5432 if (ret)
5433 return ret;
5434
5435 mpll_func_cntl &= ~BWCTRL_MASK;
5436 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5437
5438 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5439 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5440 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5441
5442 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5443 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5444
5445 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5446 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5447 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5448 YCLK_POST_DIV(mpll_param.post_div);
5449 }
5450
5451 if (pi->mclk_ss) {
5452 struct amdgpu_atom_ss ss;
5453 u32 freq_nom;
5454 u32 tmp;
5455 u32 reference_clock = adev->clock.mpll.reference_freq;
5456
5457 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5458 freq_nom = memory_clock * 4;
5459 else
5460 freq_nom = memory_clock * 2;
5461
5462 tmp = freq_nom / reference_clock;
5463 tmp = tmp * tmp;
5464 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5465 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5466 u32 clks = reference_clock * 5 / ss.rate;
5467 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5468
5469 mpll_ss1 &= ~CLKV_MASK;
5470 mpll_ss1 |= CLKV(clkv);
5471
5472 mpll_ss2 &= ~CLKS_MASK;
5473 mpll_ss2 |= CLKS(clks);
5474 }
5475 }
5476
5477 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5478 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5479
5480 if (dll_state_on)
5481 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5482 else
5483 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5484
5485 mclk->mclk_value = cpu_to_be32(memory_clock);
5486 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5487 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5488 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5489 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5490 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5491 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5492 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5493 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5494 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5495
5496 return 0;
5497 }
5498
si_populate_smc_sp(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5499 static void si_populate_smc_sp(struct amdgpu_device *adev,
5500 struct amdgpu_ps *amdgpu_state,
5501 SISLANDS_SMC_SWSTATE *smc_state)
5502 {
5503 struct si_ps *ps = si_get_ps(amdgpu_state);
5504 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5505 int i;
5506
5507 for (i = 0; i < ps->performance_level_count - 1; i++)
5508 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5509
5510 smc_state->levels[ps->performance_level_count - 1].bSP =
5511 cpu_to_be32(pi->psp);
5512 }
5513
si_convert_power_level_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SISLANDS_SMC_HW_PERFORMANCE_LEVEL * level)5514 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5515 struct rv7xx_pl *pl,
5516 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5517 {
5518 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5519 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5520 struct si_power_info *si_pi = si_get_pi(adev);
5521 int ret;
5522 bool dll_state_on;
5523 u16 std_vddc;
5524
5525 if (eg_pi->pcie_performance_request &&
5526 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID))
5527 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5528 else
5529 level->gen2PCIE = (u8)pl->pcie_gen;
5530
5531 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5532 if (ret)
5533 return ret;
5534
5535 level->mcFlags = 0;
5536
5537 if (pi->mclk_stutter_mode_threshold &&
5538 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5539 !eg_pi->uvd_enabled &&
5540 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
5541 (adev->pm.pm_display_cfg.num_display <= 2)) {
5542 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5543 }
5544
5545 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5546 if (pl->mclk > pi->mclk_edc_enable_threshold)
5547 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5548
5549 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5550 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5551
5552 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5553
5554 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5555 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5556 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5557 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5558 else
5559 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5560 } else {
5561 dll_state_on = false;
5562 }
5563 } else {
5564 level->strobeMode = si_get_strobe_mode_settings(adev,
5565 pl->mclk);
5566
5567 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5568 }
5569
5570 ret = si_populate_mclk_value(adev,
5571 pl->sclk,
5572 pl->mclk,
5573 &level->mclk,
5574 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5575 if (ret)
5576 return ret;
5577
5578 ret = si_populate_voltage_value(adev,
5579 &eg_pi->vddc_voltage_table,
5580 pl->vddc, &level->vddc);
5581 if (ret)
5582 return ret;
5583
5584
5585 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5586 if (ret)
5587 return ret;
5588
5589 ret = si_populate_std_voltage_value(adev, std_vddc,
5590 level->vddc.index, &level->std_vddc);
5591 if (ret)
5592 return ret;
5593
5594 if (eg_pi->vddci_control) {
5595 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5596 pl->vddci, &level->vddci);
5597 if (ret)
5598 return ret;
5599 }
5600
5601 if (si_pi->vddc_phase_shed_control) {
5602 ret = si_populate_phase_shedding_value(adev,
5603 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5604 pl->vddc,
5605 pl->sclk,
5606 pl->mclk,
5607 &level->vddc);
5608 if (ret)
5609 return ret;
5610 }
5611
5612 level->MaxPoweredUpCU = si_pi->max_cu;
5613
5614 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5615
5616 return ret;
5617 }
5618
si_populate_smc_t(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5619 static int si_populate_smc_t(struct amdgpu_device *adev,
5620 struct amdgpu_ps *amdgpu_state,
5621 SISLANDS_SMC_SWSTATE *smc_state)
5622 {
5623 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5624 struct si_ps *state = si_get_ps(amdgpu_state);
5625 u32 a_t;
5626 u32 t_l, t_h;
5627 u32 high_bsp;
5628 int i, ret;
5629
5630 if (state->performance_level_count >= 9)
5631 return -EINVAL;
5632
5633 if (state->performance_level_count < 2) {
5634 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT;
5635 smc_state->levels[0].aT = cpu_to_be32(a_t);
5636 return 0;
5637 }
5638
5639 smc_state->levels[0].aT = cpu_to_be32(0);
5640
5641 for (i = 0; i <= state->performance_level_count - 2; i++) {
5642 ret = r600_calculate_at(
5643 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5644 100 * R600_AH_DFLT,
5645 state->performance_levels[i + 1].sclk,
5646 state->performance_levels[i].sclk,
5647 &t_l,
5648 &t_h);
5649
5650 if (ret) {
5651 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5652 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5653 }
5654
5655 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK;
5656 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT;
5657 smc_state->levels[i].aT = cpu_to_be32(a_t);
5658
5659 high_bsp = (i == state->performance_level_count - 2) ?
5660 pi->pbsp : pi->bsp;
5661 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT;
5662 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5663 }
5664
5665 return 0;
5666 }
5667
si_disable_ulv(struct amdgpu_device * adev)5668 static int si_disable_ulv(struct amdgpu_device *adev)
5669 {
5670 PPSMC_Result r;
5671
5672 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV);
5673 return (r == PPSMC_Result_OK) ? 0 : -EINVAL;
5674 }
5675
si_is_state_ulv_compatible(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)5676 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5677 struct amdgpu_ps *amdgpu_state)
5678 {
5679 const struct si_power_info *si_pi = si_get_pi(adev);
5680 const struct si_ulv_param *ulv = &si_pi->ulv;
5681 const struct si_ps *state = si_get_ps(amdgpu_state);
5682 int i;
5683
5684 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5685 return false;
5686
5687 /* XXX validate against display requirements! */
5688
5689 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5690 if (adev->pm.pm_display_cfg.display_clk <=
5691 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5692 if (ulv->pl.vddc <
5693 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5694 return false;
5695 }
5696 }
5697
5698 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5699 return false;
5700
5701 return true;
5702 }
5703
si_set_power_state_conditionally_enable_ulv(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5704 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5705 struct amdgpu_ps *amdgpu_new_state)
5706 {
5707 const struct si_power_info *si_pi = si_get_pi(adev);
5708 const struct si_ulv_param *ulv = &si_pi->ulv;
5709
5710 if (ulv->supported) {
5711 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5712 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5713 0 : -EINVAL;
5714 }
5715 return 0;
5716 }
5717
si_convert_power_state_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SISLANDS_SMC_SWSTATE * smc_state)5718 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5719 struct amdgpu_ps *amdgpu_state,
5720 SISLANDS_SMC_SWSTATE *smc_state)
5721 {
5722 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5723 struct ni_power_info *ni_pi = ni_get_pi(adev);
5724 struct si_power_info *si_pi = si_get_pi(adev);
5725 struct si_ps *state = si_get_ps(amdgpu_state);
5726 int i, ret;
5727 u32 threshold;
5728 u32 sclk_in_sr = 1350; /* ??? */
5729
5730 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5731 return -EINVAL;
5732
5733 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5734
5735 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5736 eg_pi->uvd_enabled = true;
5737 if (eg_pi->smu_uvd_hs)
5738 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5739 } else {
5740 eg_pi->uvd_enabled = false;
5741 }
5742
5743 if (state->dc_compatible)
5744 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5745
5746 smc_state->levelCount = 0;
5747 for (i = 0; i < state->performance_level_count; i++) {
5748 if (eg_pi->sclk_deep_sleep) {
5749 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5750 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5751 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5752 else
5753 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5754 }
5755 }
5756
5757 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5758 &smc_state->levels[i]);
5759 smc_state->levels[i].arbRefreshState =
5760 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5761
5762 if (ret)
5763 return ret;
5764
5765 if (ni_pi->enable_power_containment)
5766 smc_state->levels[i].displayWatermark =
5767 (state->performance_levels[i].sclk < threshold) ?
5768 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5769 else
5770 smc_state->levels[i].displayWatermark = (i < 2) ?
5771 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5772
5773 if (eg_pi->dynamic_ac_timing)
5774 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5775 else
5776 smc_state->levels[i].ACIndex = 0;
5777
5778 smc_state->levelCount++;
5779 }
5780
5781 si_write_smc_soft_register(adev,
5782 SI_SMC_SOFT_REGISTER_watermark_threshold,
5783 threshold / 512);
5784
5785 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5786
5787 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5788 if (ret)
5789 ni_pi->enable_power_containment = false;
5790
5791 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5792 if (ret)
5793 ni_pi->enable_sq_ramping = false;
5794
5795 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5796 }
5797
si_upload_sw_state(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)5798 static int si_upload_sw_state(struct amdgpu_device *adev,
5799 struct amdgpu_ps *amdgpu_new_state)
5800 {
5801 struct si_power_info *si_pi = si_get_pi(adev);
5802 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5803 int ret;
5804 u32 address = si_pi->state_table_start +
5805 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5806 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5807 size_t state_size = struct_size(smc_state, levels,
5808 new_state->performance_level_count);
5809 memset(smc_state, 0, state_size);
5810
5811 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5812 if (ret)
5813 return ret;
5814
5815 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5816 state_size, si_pi->sram_end);
5817 }
5818
si_upload_ulv_state(struct amdgpu_device * adev)5819 static int si_upload_ulv_state(struct amdgpu_device *adev)
5820 {
5821 struct si_power_info *si_pi = si_get_pi(adev);
5822 struct si_ulv_param *ulv = &si_pi->ulv;
5823 int ret = 0;
5824
5825 if (ulv->supported && ulv->pl.vddc) {
5826 u32 address = si_pi->state_table_start +
5827 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5828 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
5829 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5830
5831 memset(smc_state, 0, state_size);
5832
5833 ret = si_populate_ulv_state(adev, smc_state);
5834 if (!ret)
5835 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5836 state_size, si_pi->sram_end);
5837 }
5838
5839 return ret;
5840 }
5841
si_upload_smc_data(struct amdgpu_device * adev)5842 static int si_upload_smc_data(struct amdgpu_device *adev)
5843 {
5844 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
5845 u32 crtc_index = 0;
5846 u32 mclk_change_block_cp_min = 0;
5847 u32 mclk_change_block_cp_max = 0;
5848
5849 /* When a display is plugged in, program these so that the SMC
5850 * performs MCLK switching when it doesn't cause flickering.
5851 * When no display is plugged in, there is no need to restrict
5852 * MCLK switching, so program them to zero.
5853 */
5854 if (cfg->num_display) {
5855 crtc_index = cfg->crtc_index;
5856
5857 if (cfg->line_time_in_us) {
5858 mclk_change_block_cp_min = 200 / cfg->line_time_in_us;
5859 mclk_change_block_cp_max = 100 / cfg->line_time_in_us;
5860 }
5861 }
5862
5863 si_write_smc_soft_register(adev,
5864 SI_SMC_SOFT_REGISTER_crtc_index,
5865 crtc_index);
5866
5867 si_write_smc_soft_register(adev,
5868 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5869 mclk_change_block_cp_min);
5870
5871 si_write_smc_soft_register(adev,
5872 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5873 mclk_change_block_cp_max);
5874
5875 return 0;
5876 }
5877
si_set_mc_special_registers(struct amdgpu_device * adev,struct si_mc_reg_table * table)5878 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5879 struct si_mc_reg_table *table)
5880 {
5881 u8 i, j, k;
5882 u32 temp_reg;
5883
5884 for (i = 0, j = table->last; i < table->last; i++) {
5885 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5886 return -EINVAL;
5887 switch (table->mc_reg_address[i].s1) {
5888 case MC_SEQ_MISC1:
5889 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5890 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5891 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5892 for (k = 0; k < table->num_entries; k++)
5893 table->mc_reg_table_entry[k].mc_data[j] =
5894 ((temp_reg & 0xffff0000)) |
5895 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5896 j++;
5897
5898 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5899 return -EINVAL;
5900 temp_reg = RREG32(MC_PMG_CMD_MRS);
5901 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5902 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5903 for (k = 0; k < table->num_entries; k++) {
5904 table->mc_reg_table_entry[k].mc_data[j] =
5905 (temp_reg & 0xffff0000) |
5906 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5907 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5908 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5909 }
5910 j++;
5911
5912 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5913 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5914 return -EINVAL;
5915 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5916 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5917 for (k = 0; k < table->num_entries; k++)
5918 table->mc_reg_table_entry[k].mc_data[j] =
5919 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5920 j++;
5921 }
5922 break;
5923 case MC_SEQ_RESERVE_M:
5924 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5925 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5926 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5927 for(k = 0; k < table->num_entries; k++)
5928 table->mc_reg_table_entry[k].mc_data[j] =
5929 (temp_reg & 0xffff0000) |
5930 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5931 j++;
5932 break;
5933 default:
5934 break;
5935 }
5936 }
5937
5938 table->last = j;
5939
5940 return 0;
5941 }
5942
si_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)5943 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5944 {
5945 bool result = true;
5946 switch (in_reg) {
5947 case MC_SEQ_RAS_TIMING:
5948 *out_reg = MC_SEQ_RAS_TIMING_LP;
5949 break;
5950 case MC_SEQ_CAS_TIMING:
5951 *out_reg = MC_SEQ_CAS_TIMING_LP;
5952 break;
5953 case MC_SEQ_MISC_TIMING:
5954 *out_reg = MC_SEQ_MISC_TIMING_LP;
5955 break;
5956 case MC_SEQ_MISC_TIMING2:
5957 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5958 break;
5959 case MC_SEQ_RD_CTL_D0:
5960 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5961 break;
5962 case MC_SEQ_RD_CTL_D1:
5963 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5964 break;
5965 case MC_SEQ_WR_CTL_D0:
5966 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5967 break;
5968 case MC_SEQ_WR_CTL_D1:
5969 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5970 break;
5971 case MC_PMG_CMD_EMRS:
5972 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5973 break;
5974 case MC_PMG_CMD_MRS:
5975 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5976 break;
5977 case MC_PMG_CMD_MRS1:
5978 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5979 break;
5980 case MC_SEQ_PMG_TIMING:
5981 *out_reg = MC_SEQ_PMG_TIMING_LP;
5982 break;
5983 case MC_PMG_CMD_MRS2:
5984 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5985 break;
5986 case MC_SEQ_WR_CTL_2:
5987 *out_reg = MC_SEQ_WR_CTL_2_LP;
5988 break;
5989 default:
5990 result = false;
5991 break;
5992 }
5993
5994 return result;
5995 }
5996
si_set_valid_flag(struct si_mc_reg_table * table)5997 static void si_set_valid_flag(struct si_mc_reg_table *table)
5998 {
5999 u8 i, j;
6000
6001 for (i = 0; i < table->last; i++) {
6002 for (j = 1; j < table->num_entries; j++) {
6003 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
6004 table->valid_flag |= 1 << i;
6005 break;
6006 }
6007 }
6008 }
6009 }
6010
si_set_s0_mc_reg_index(struct si_mc_reg_table * table)6011 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
6012 {
6013 u32 i;
6014 u16 address;
6015
6016 for (i = 0; i < table->last; i++)
6017 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6018 address : table->mc_reg_address[i].s1;
6019
6020 }
6021
si_copy_vbios_mc_reg_table(struct atom_mc_reg_table * table,struct si_mc_reg_table * si_table)6022 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6023 struct si_mc_reg_table *si_table)
6024 {
6025 u8 i, j;
6026
6027 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6028 return -EINVAL;
6029 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6030 return -EINVAL;
6031
6032 for (i = 0; i < table->last; i++)
6033 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6034 si_table->last = table->last;
6035
6036 for (i = 0; i < table->num_entries; i++) {
6037 si_table->mc_reg_table_entry[i].mclk_max =
6038 table->mc_reg_table_entry[i].mclk_max;
6039 for (j = 0; j < table->last; j++) {
6040 si_table->mc_reg_table_entry[i].mc_data[j] =
6041 table->mc_reg_table_entry[i].mc_data[j];
6042 }
6043 }
6044 si_table->num_entries = table->num_entries;
6045
6046 return 0;
6047 }
6048
si_initialize_mc_reg_table(struct amdgpu_device * adev)6049 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6050 {
6051 struct si_power_info *si_pi = si_get_pi(adev);
6052 struct atom_mc_reg_table *table;
6053 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6054 u8 module_index = rv770_get_memory_module_index(adev);
6055 int ret;
6056
6057 table = kzalloc_obj(struct atom_mc_reg_table);
6058 if (!table)
6059 return -ENOMEM;
6060
6061 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6062 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6063 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6064 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6065 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6066 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6067 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6068 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6069 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6070 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6071 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6072 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6073 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6074 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6075
6076 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6077 if (ret)
6078 goto init_mc_done;
6079
6080 ret = si_copy_vbios_mc_reg_table(table, si_table);
6081 if (ret)
6082 goto init_mc_done;
6083
6084 si_set_s0_mc_reg_index(si_table);
6085
6086 ret = si_set_mc_special_registers(adev, si_table);
6087 if (ret)
6088 goto init_mc_done;
6089
6090 si_set_valid_flag(si_table);
6091
6092 init_mc_done:
6093 kfree(table);
6094
6095 return ret;
6096
6097 }
6098
si_populate_mc_reg_addresses(struct amdgpu_device * adev,SMC_SIslands_MCRegisters * mc_reg_table)6099 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6100 SMC_SIslands_MCRegisters *mc_reg_table)
6101 {
6102 struct si_power_info *si_pi = si_get_pi(adev);
6103 u32 i, j;
6104
6105 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6106 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6107 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6108 break;
6109 mc_reg_table->address[i].s0 =
6110 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6111 mc_reg_table->address[i].s1 =
6112 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6113 i++;
6114 }
6115 }
6116 mc_reg_table->last = (u8)i;
6117 }
6118
si_convert_mc_registers(const struct si_mc_reg_entry * entry,SMC_SIslands_MCRegisterSet * data,u32 num_entries,u32 valid_flag)6119 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6120 SMC_SIslands_MCRegisterSet *data,
6121 u32 num_entries, u32 valid_flag)
6122 {
6123 u32 i, j;
6124
6125 for(i = 0, j = 0; j < num_entries; j++) {
6126 if (valid_flag & (1 << j)) {
6127 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6128 i++;
6129 }
6130 }
6131 }
6132
si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device * adev,struct rv7xx_pl * pl,SMC_SIslands_MCRegisterSet * mc_reg_table_data)6133 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6134 struct rv7xx_pl *pl,
6135 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6136 {
6137 struct si_power_info *si_pi = si_get_pi(adev);
6138 u32 i = 0;
6139
6140 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6141 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6142 break;
6143 }
6144
6145 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6146 --i;
6147
6148 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6149 mc_reg_table_data, si_pi->mc_reg_table.last,
6150 si_pi->mc_reg_table.valid_flag);
6151 }
6152
si_convert_mc_reg_table_to_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state,SMC_SIslands_MCRegisters * mc_reg_table)6153 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6154 struct amdgpu_ps *amdgpu_state,
6155 SMC_SIslands_MCRegisters *mc_reg_table)
6156 {
6157 struct si_ps *state = si_get_ps(amdgpu_state);
6158 int i;
6159
6160 for (i = 0; i < state->performance_level_count; i++) {
6161 si_convert_mc_reg_table_entry_to_smc(adev,
6162 &state->performance_levels[i],
6163 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6164 }
6165 }
6166
si_populate_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_boot_state)6167 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6168 struct amdgpu_ps *amdgpu_boot_state)
6169 {
6170 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6171 struct si_power_info *si_pi = si_get_pi(adev);
6172 struct si_ulv_param *ulv = &si_pi->ulv;
6173 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6174
6175 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6176
6177 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6178
6179 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6180
6181 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6182 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6183
6184 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6185 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6186 si_pi->mc_reg_table.last,
6187 si_pi->mc_reg_table.valid_flag);
6188
6189 if (ulv->supported && ulv->pl.vddc != 0)
6190 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6191 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6192 else
6193 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6194 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6195 si_pi->mc_reg_table.last,
6196 si_pi->mc_reg_table.valid_flag);
6197
6198 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6199
6200 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6201 (u8 *)smc_mc_reg_table,
6202 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6203 }
6204
si_upload_mc_reg_table(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state)6205 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6206 struct amdgpu_ps *amdgpu_new_state)
6207 {
6208 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6209 struct si_power_info *si_pi = si_get_pi(adev);
6210 u32 address = si_pi->mc_reg_table_start +
6211 offsetof(SMC_SIslands_MCRegisters,
6212 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6213 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6214
6215 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6216
6217 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6218
6219 return amdgpu_si_copy_bytes_to_smc(adev, address,
6220 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6221 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6222 si_pi->sram_end);
6223 }
6224
si_enable_voltage_control(struct amdgpu_device * adev,bool enable)6225 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6226 {
6227 if (enable)
6228 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6229 else
6230 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);
6231 }
6232
si_get_maximum_link_speed(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_state)6233 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6234 struct amdgpu_ps *amdgpu_state)
6235 {
6236 struct si_ps *state = si_get_ps(amdgpu_state);
6237 int i;
6238 u16 pcie_speed, max_speed = 0;
6239
6240 for (i = 0; i < state->performance_level_count; i++) {
6241 pcie_speed = state->performance_levels[i].pcie_gen;
6242 if (max_speed < pcie_speed)
6243 max_speed = pcie_speed;
6244 }
6245 return max_speed;
6246 }
6247
si_get_current_pcie_speed(struct amdgpu_device * adev)6248 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6249 {
6250 u32 speed_cntl;
6251
6252 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
6253 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
6254
6255 return (u16)speed_cntl;
6256 }
6257
si_request_link_speed_change_before_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6258 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6259 struct amdgpu_ps *amdgpu_new_state,
6260 struct amdgpu_ps *amdgpu_current_state)
6261 {
6262 struct si_power_info *si_pi = si_get_pi(adev);
6263 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6264 enum si_pcie_gen current_link_speed;
6265
6266 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID)
6267 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6268 else
6269 current_link_speed = si_pi->force_pcie_gen;
6270
6271 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
6272 si_pi->pspp_notify_required = false;
6273 if (target_link_speed > current_link_speed) {
6274 switch (target_link_speed) {
6275 #if defined(CONFIG_ACPI)
6276 case SI_PCIE_GEN3:
6277 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6278 break;
6279 si_pi->force_pcie_gen = SI_PCIE_GEN2;
6280 if (current_link_speed == SI_PCIE_GEN2)
6281 break;
6282 fallthrough;
6283 case SI_PCIE_GEN2:
6284 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6285 break;
6286 fallthrough;
6287 #endif
6288 default:
6289 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6290 break;
6291 }
6292 } else {
6293 if (target_link_speed < current_link_speed)
6294 si_pi->pspp_notify_required = true;
6295 }
6296 }
6297
si_notify_link_speed_change_after_state_change(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6298 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6299 struct amdgpu_ps *amdgpu_new_state,
6300 struct amdgpu_ps *amdgpu_current_state)
6301 {
6302 struct si_power_info *si_pi = si_get_pi(adev);
6303 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6304 u8 request;
6305
6306 if (si_pi->pspp_notify_required) {
6307 if (target_link_speed == SI_PCIE_GEN3)
6308 request = PCIE_PERF_REQ_PECI_GEN3;
6309 else if (target_link_speed == SI_PCIE_GEN2)
6310 request = PCIE_PERF_REQ_PECI_GEN2;
6311 else
6312 request = PCIE_PERF_REQ_PECI_GEN1;
6313
6314 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6315 (si_get_current_pcie_speed(adev) > 0))
6316 return;
6317
6318 #if defined(CONFIG_ACPI)
6319 amdgpu_acpi_pcie_performance_request(adev, request, false);
6320 #endif
6321 }
6322 }
6323
6324 #if 0
6325 static int si_ds_request(struct amdgpu_device *adev,
6326 bool ds_status_on, u32 count_write)
6327 {
6328 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6329
6330 if (eg_pi->sclk_deep_sleep) {
6331 if (ds_status_on)
6332 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6333 PPSMC_Result_OK) ?
6334 0 : -EINVAL;
6335 else
6336 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6337 PPSMC_Result_OK) ? 0 : -EINVAL;
6338 }
6339 return 0;
6340 }
6341 #endif
6342
si_set_max_cu_value(struct amdgpu_device * adev)6343 static void si_set_max_cu_value(struct amdgpu_device *adev)
6344 {
6345 struct si_power_info *si_pi = si_get_pi(adev);
6346
6347 if (adev->asic_type == CHIP_VERDE) {
6348 switch (adev->pdev->device) {
6349 case 0x6820:
6350 case 0x6825:
6351 case 0x6821:
6352 case 0x6823:
6353 case 0x6827:
6354 si_pi->max_cu = 10;
6355 break;
6356 case 0x682D:
6357 case 0x6824:
6358 case 0x682F:
6359 case 0x6826:
6360 si_pi->max_cu = 8;
6361 break;
6362 case 0x6828:
6363 case 0x6830:
6364 case 0x6831:
6365 case 0x6838:
6366 case 0x6839:
6367 case 0x683D:
6368 si_pi->max_cu = 10;
6369 break;
6370 case 0x683B:
6371 case 0x683F:
6372 case 0x6829:
6373 si_pi->max_cu = 8;
6374 break;
6375 default:
6376 si_pi->max_cu = 0;
6377 break;
6378 }
6379 } else {
6380 si_pi->max_cu = 0;
6381 }
6382 }
6383
si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device * adev,struct amdgpu_clock_voltage_dependency_table * table)6384 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6385 struct amdgpu_clock_voltage_dependency_table *table)
6386 {
6387 u32 i;
6388 int j;
6389 u16 leakage_voltage;
6390
6391 if (table) {
6392 for (i = 0; i < table->count; i++) {
6393 switch (si_get_leakage_voltage_from_leakage_index(adev,
6394 table->entries[i].v,
6395 &leakage_voltage)) {
6396 case 0:
6397 table->entries[i].v = leakage_voltage;
6398 break;
6399 case -EAGAIN:
6400 return -EINVAL;
6401 case -EINVAL:
6402 default:
6403 break;
6404 }
6405 }
6406
6407 for (j = (table->count - 2); j >= 0; j--) {
6408 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6409 table->entries[j].v : table->entries[j + 1].v;
6410 }
6411 }
6412 return 0;
6413 }
6414
si_patch_dependency_tables_based_on_leakage(struct amdgpu_device * adev)6415 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6416 {
6417 int ret = 0;
6418
6419 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6420 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6421 if (ret)
6422 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6423 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6424 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6425 if (ret)
6426 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6427 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6428 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6429 if (ret)
6430 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6431 return ret;
6432 }
6433
si_set_pcie_lane_width_in_smc(struct amdgpu_device * adev,struct amdgpu_ps * amdgpu_new_state,struct amdgpu_ps * amdgpu_current_state)6434 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6435 struct amdgpu_ps *amdgpu_new_state,
6436 struct amdgpu_ps *amdgpu_current_state)
6437 {
6438 u32 lane_width;
6439 u32 new_lane_width =
6440 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6441 u32 current_lane_width =
6442 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6443
6444 if (new_lane_width != current_lane_width) {
6445 amdgpu_set_pcie_lanes(adev, new_lane_width);
6446 lane_width = amdgpu_get_pcie_lanes(adev);
6447 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6448 }
6449 }
6450
si_dpm_setup_asic(struct amdgpu_device * adev)6451 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6452 {
6453 si_read_clock_registers(adev);
6454 si_enable_acpi_power_management(adev);
6455 }
6456
si_thermal_enable_alert(struct amdgpu_device * adev,bool enable)6457 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6458 bool enable)
6459 {
6460 u32 thermal_int = RREG32(mmCG_THERMAL_INT);
6461
6462 if (enable) {
6463 PPSMC_Result result;
6464
6465 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK);
6466 WREG32(mmCG_THERMAL_INT, thermal_int);
6467 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6468 if (result != PPSMC_Result_OK) {
6469 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6470 return -EINVAL;
6471 }
6472 } else {
6473 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
6474 WREG32(mmCG_THERMAL_INT, thermal_int);
6475 }
6476
6477 return 0;
6478 }
6479
si_thermal_set_temperature_range(struct amdgpu_device * adev,int min_temp,int max_temp)6480 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6481 int min_temp, int max_temp)
6482 {
6483 int low_temp = 0 * 1000;
6484 int high_temp = 255 * 1000;
6485
6486 if (low_temp < min_temp)
6487 low_temp = min_temp;
6488 if (high_temp > max_temp)
6489 high_temp = max_temp;
6490 if (high_temp < low_temp) {
6491 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6492 return -EINVAL;
6493 }
6494
6495 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK);
6496 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK);
6497 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK);
6498
6499 adev->pm.dpm.thermal.min_temp = low_temp;
6500 adev->pm.dpm.thermal.max_temp = high_temp;
6501
6502 return 0;
6503 }
6504
si_fan_ctrl_set_static_mode(struct amdgpu_device * adev,u32 mode)6505 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6506 {
6507 struct si_power_info *si_pi = si_get_pi(adev);
6508 u32 tmp;
6509
6510 if (si_pi->fan_ctrl_is_in_default_mode) {
6511 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6512 si_pi->fan_ctrl_default_mode = tmp;
6513 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;
6514 si_pi->t_min = tmp;
6515 si_pi->fan_ctrl_is_in_default_mode = false;
6516 }
6517
6518 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6519 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
6520 WREG32(mmCG_FDO_CTRL2, tmp);
6521
6522 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6523 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6524 WREG32(mmCG_FDO_CTRL2, tmp);
6525 }
6526
si_thermal_setup_fan_table(struct amdgpu_device * adev)6527 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6528 {
6529 struct si_power_info *si_pi = si_get_pi(adev);
6530 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6531 u32 duty100;
6532 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6533 u16 fdo_min, slope1, slope2;
6534 u32 reference_clock, tmp;
6535 int ret;
6536 u64 tmp64;
6537
6538 if (!si_pi->fan_table_start) {
6539 adev->pm.dpm.fan.ucode_fan_control = false;
6540 return 0;
6541 }
6542
6543 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6544
6545 if (duty100 == 0) {
6546 adev->pm.dpm.fan.ucode_fan_control = false;
6547 return 0;
6548 }
6549
6550 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6551 do_div(tmp64, 10000);
6552 fdo_min = (u16)tmp64;
6553
6554 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6555 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6556
6557 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6558 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6559
6560 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6561 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6562
6563 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6564 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6565 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6566 fan_table.slope1 = cpu_to_be16(slope1);
6567 fan_table.slope2 = cpu_to_be16(slope2);
6568 fan_table.fdo_min = cpu_to_be16(fdo_min);
6569 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6570 fan_table.hys_up = cpu_to_be16(1);
6571 fan_table.hys_slope = cpu_to_be16(1);
6572 fan_table.temp_resp_lim = cpu_to_be16(5);
6573 reference_clock = amdgpu_asic_get_xclk(adev);
6574
6575 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6576 reference_clock) / 1600);
6577 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6578
6579 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
6580 fan_table.temp_src = (uint8_t)tmp;
6581
6582 ret = amdgpu_si_copy_bytes_to_smc(adev,
6583 si_pi->fan_table_start,
6584 (u8 *)(&fan_table),
6585 sizeof(fan_table),
6586 si_pi->sram_end);
6587
6588 if (ret) {
6589 DRM_ERROR("Failed to load fan table to the SMC.");
6590 adev->pm.dpm.fan.ucode_fan_control = false;
6591 }
6592
6593 return ret;
6594 }
6595
si_fan_ctrl_start_smc_fan_control(struct amdgpu_device * adev)6596 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6597 {
6598 struct si_power_info *si_pi = si_get_pi(adev);
6599 PPSMC_Result ret;
6600
6601 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6602 if (ret == PPSMC_Result_OK) {
6603 si_pi->fan_is_controlled_by_smc = true;
6604 return 0;
6605 } else {
6606 return -EINVAL;
6607 }
6608 }
6609
si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device * adev)6610 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6611 {
6612 struct si_power_info *si_pi = si_get_pi(adev);
6613 PPSMC_Result ret;
6614
6615 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6616
6617 if (ret == PPSMC_Result_OK) {
6618 si_pi->fan_is_controlled_by_smc = false;
6619 return 0;
6620 } else {
6621 return -EINVAL;
6622 }
6623 }
6624
si_dpm_get_fan_speed_pwm(void * handle,u32 * speed)6625 static int si_dpm_get_fan_speed_pwm(void *handle,
6626 u32 *speed)
6627 {
6628 u32 duty, duty100;
6629 u64 tmp64;
6630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6631
6632 if (!speed)
6633 return -EINVAL;
6634
6635 if (adev->pm.no_fan)
6636 return -ENOENT;
6637
6638 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6639 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
6640
6641 if (duty100 == 0)
6642 return -EINVAL;
6643
6644 tmp64 = (u64)duty * 255;
6645 do_div(tmp64, duty100);
6646 *speed = min_t(u32, tmp64, 255);
6647
6648 return 0;
6649 }
6650
si_dpm_set_fan_speed_pwm(void * handle,u32 speed)6651 static int si_dpm_set_fan_speed_pwm(void *handle,
6652 u32 speed)
6653 {
6654 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6655 struct si_power_info *si_pi = si_get_pi(adev);
6656 u32 tmp;
6657 u32 duty, duty100;
6658 u64 tmp64;
6659
6660 if (adev->pm.no_fan)
6661 return -ENOENT;
6662
6663 if (si_pi->fan_is_controlled_by_smc)
6664 return -EINVAL;
6665
6666 if (speed > 255)
6667 return -EINVAL;
6668
6669 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
6670
6671 if (duty100 == 0)
6672 return -EINVAL;
6673
6674 tmp64 = (u64)speed * duty100;
6675 do_div(tmp64, 255);
6676 duty = (u32)tmp64;
6677
6678 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
6679 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
6680 WREG32(mmCG_FDO_CTRL0, tmp);
6681
6682 return 0;
6683 }
6684
si_dpm_set_fan_control_mode(void * handle,u32 mode)6685 static int si_dpm_set_fan_control_mode(void *handle, u32 mode)
6686 {
6687 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6688
6689 if (mode == U32_MAX)
6690 return -EINVAL;
6691
6692 if (mode) {
6693 /* stop auto-manage */
6694 if (adev->pm.dpm.fan.ucode_fan_control)
6695 si_fan_ctrl_stop_smc_fan_control(adev);
6696 si_fan_ctrl_set_static_mode(adev, mode);
6697 } else {
6698 /* restart auto-manage */
6699 if (adev->pm.dpm.fan.ucode_fan_control)
6700 si_thermal_start_smc_fan_control(adev);
6701 else
6702 si_fan_ctrl_set_default_mode(adev);
6703 }
6704
6705 return 0;
6706 }
6707
si_dpm_get_fan_control_mode(void * handle,u32 * fan_mode)6708 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode)
6709 {
6710 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6711 struct si_power_info *si_pi = si_get_pi(adev);
6712 u32 tmp;
6713
6714 if (!fan_mode)
6715 return -EINVAL;
6716
6717 if (si_pi->fan_is_controlled_by_smc)
6718 return 0;
6719
6720 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6721 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
6722
6723 return 0;
6724 }
6725
6726 #if 0
6727 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6728 u32 *speed)
6729 {
6730 u32 tach_period;
6731 u32 xclk = amdgpu_asic_get_xclk(adev);
6732
6733 if (adev->pm.no_fan)
6734 return -ENOENT;
6735
6736 if (adev->pm.fan_pulses_per_revolution == 0)
6737 return -ENOENT;
6738
6739 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
6740 if (tach_period == 0)
6741 return -ENOENT;
6742
6743 *speed = 60 * xclk * 10000 / tach_period;
6744
6745 return 0;
6746 }
6747
6748 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6749 u32 speed)
6750 {
6751 u32 tach_period, tmp;
6752 u32 xclk = amdgpu_asic_get_xclk(adev);
6753
6754 if (adev->pm.no_fan)
6755 return -ENOENT;
6756
6757 if (adev->pm.fan_pulses_per_revolution == 0)
6758 return -ENOENT;
6759
6760 if ((speed < adev->pm.fan_min_rpm) ||
6761 (speed > adev->pm.fan_max_rpm))
6762 return -EINVAL;
6763
6764 if (adev->pm.dpm.fan.ucode_fan_control)
6765 si_fan_ctrl_stop_smc_fan_control(adev);
6766
6767 tach_period = 60 * xclk * 10000 / (8 * speed);
6768 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
6769 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
6770 WREG32(mmCG_TACH_CTRL, tmp);
6771
6772 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6773
6774 return 0;
6775 }
6776 #endif
6777
si_fan_ctrl_set_default_mode(struct amdgpu_device * adev)6778 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6779 {
6780 struct si_power_info *si_pi = si_get_pi(adev);
6781 u32 tmp;
6782
6783 if (!si_pi->fan_ctrl_is_in_default_mode) {
6784 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
6785 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
6786 WREG32(mmCG_FDO_CTRL2, tmp);
6787
6788 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
6789 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
6790 WREG32(mmCG_FDO_CTRL2, tmp);
6791 si_pi->fan_ctrl_is_in_default_mode = true;
6792 }
6793 }
6794
si_thermal_start_smc_fan_control(struct amdgpu_device * adev)6795 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6796 {
6797 if (adev->pm.dpm.fan.ucode_fan_control) {
6798 si_fan_ctrl_start_smc_fan_control(adev);
6799 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6800 }
6801 }
6802
si_thermal_initialize(struct amdgpu_device * adev)6803 static void si_thermal_initialize(struct amdgpu_device *adev)
6804 {
6805 u32 tmp;
6806
6807 if (adev->pm.fan_pulses_per_revolution) {
6808 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
6809 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
6810 WREG32(mmCG_TACH_CTRL, tmp);
6811 }
6812
6813 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
6814 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
6815 WREG32(mmCG_FDO_CTRL2, tmp);
6816 }
6817
si_thermal_start_thermal_controller(struct amdgpu_device * adev)6818 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6819 {
6820 int ret;
6821
6822 si_thermal_initialize(adev);
6823 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6824 if (ret)
6825 return ret;
6826 ret = si_thermal_enable_alert(adev, true);
6827 if (ret)
6828 return ret;
6829 if (adev->pm.dpm.fan.ucode_fan_control) {
6830 ret = si_halt_smc(adev);
6831 if (ret)
6832 return ret;
6833 ret = si_thermal_setup_fan_table(adev);
6834 if (ret)
6835 return ret;
6836 ret = si_resume_smc(adev);
6837 if (ret)
6838 return ret;
6839 si_thermal_start_smc_fan_control(adev);
6840 }
6841
6842 return 0;
6843 }
6844
si_thermal_stop_thermal_controller(struct amdgpu_device * adev)6845 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6846 {
6847 if (!adev->pm.no_fan) {
6848 si_fan_ctrl_set_default_mode(adev);
6849 si_fan_ctrl_stop_smc_fan_control(adev);
6850 }
6851 }
6852
si_dpm_enable(struct amdgpu_device * adev)6853 static int si_dpm_enable(struct amdgpu_device *adev)
6854 {
6855 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6856 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6857 struct si_power_info *si_pi = si_get_pi(adev);
6858 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6859 int ret;
6860
6861 if (amdgpu_si_is_smc_running(adev))
6862 return -EINVAL;
6863 if (pi->voltage_control || si_pi->voltage_control_svi2)
6864 si_enable_voltage_control(adev, true);
6865 if (pi->mvdd_control)
6866 si_get_mvdd_configuration(adev);
6867 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6868 ret = si_construct_voltage_tables(adev);
6869 if (ret) {
6870 DRM_ERROR("si_construct_voltage_tables failed\n");
6871 return ret;
6872 }
6873 }
6874 if (eg_pi->dynamic_ac_timing) {
6875 ret = si_initialize_mc_reg_table(adev);
6876 if (ret)
6877 eg_pi->dynamic_ac_timing = false;
6878 }
6879 if (pi->dynamic_ss)
6880 si_enable_spread_spectrum(adev, true);
6881 if (pi->thermal_protection)
6882 si_enable_thermal_protection(adev, true);
6883 si_setup_bsp(adev);
6884 si_program_git(adev);
6885 si_program_tp(adev);
6886 si_program_tpp(adev);
6887 si_program_sstp(adev);
6888 si_enable_display_gap(adev);
6889 si_program_vc(adev);
6890 ret = si_upload_firmware(adev);
6891 if (ret) {
6892 DRM_ERROR("si_upload_firmware failed\n");
6893 return ret;
6894 }
6895 ret = si_process_firmware_header(adev);
6896 if (ret) {
6897 DRM_ERROR("si_process_firmware_header failed\n");
6898 return ret;
6899 }
6900 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6901 if (ret) {
6902 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6903 return ret;
6904 }
6905 ret = si_init_smc_table(adev);
6906 if (ret) {
6907 DRM_ERROR("si_init_smc_table failed\n");
6908 return ret;
6909 }
6910 ret = si_init_smc_spll_table(adev);
6911 if (ret) {
6912 DRM_ERROR("si_init_smc_spll_table failed\n");
6913 return ret;
6914 }
6915 ret = si_init_arb_table_index(adev);
6916 if (ret) {
6917 DRM_ERROR("si_init_arb_table_index failed\n");
6918 return ret;
6919 }
6920 if (eg_pi->dynamic_ac_timing) {
6921 ret = si_populate_mc_reg_table(adev, boot_ps);
6922 if (ret) {
6923 DRM_ERROR("si_populate_mc_reg_table failed\n");
6924 return ret;
6925 }
6926 }
6927 ret = si_initialize_smc_cac_tables(adev);
6928 if (ret) {
6929 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6930 return ret;
6931 }
6932 ret = si_initialize_hardware_cac_manager(adev);
6933 if (ret) {
6934 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6935 return ret;
6936 }
6937 ret = si_initialize_smc_dte_tables(adev);
6938 if (ret) {
6939 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6940 return ret;
6941 }
6942 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6943 if (ret) {
6944 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6945 return ret;
6946 }
6947 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6948 if (ret) {
6949 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6950 return ret;
6951 }
6952 si_program_response_times(adev);
6953 si_program_ds_registers(adev);
6954 si_dpm_start_smc(adev);
6955 ret = si_notify_smc_display_change(adev, false);
6956 if (ret) {
6957 DRM_ERROR("si_notify_smc_display_change failed\n");
6958 return ret;
6959 }
6960 si_enable_sclk_control(adev, true);
6961 si_start_dpm(adev);
6962
6963 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6964 si_thermal_start_thermal_controller(adev);
6965
6966 ni_update_current_ps(adev, boot_ps);
6967
6968 return 0;
6969 }
6970
si_set_temperature_range(struct amdgpu_device * adev)6971 static int si_set_temperature_range(struct amdgpu_device *adev)
6972 {
6973 int ret;
6974
6975 ret = si_thermal_enable_alert(adev, false);
6976 if (ret)
6977 return ret;
6978 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6979 if (ret)
6980 return ret;
6981 ret = si_thermal_enable_alert(adev, true);
6982 if (ret)
6983 return ret;
6984
6985 return ret;
6986 }
6987
si_dpm_disable(struct amdgpu_device * adev)6988 static void si_dpm_disable(struct amdgpu_device *adev)
6989 {
6990 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6991 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6992
6993 if (!amdgpu_si_is_smc_running(adev))
6994 return;
6995 si_thermal_stop_thermal_controller(adev);
6996 si_disable_ulv(adev);
6997 si_clear_vc(adev);
6998 if (pi->thermal_protection)
6999 si_enable_thermal_protection(adev, false);
7000 si_enable_power_containment(adev, boot_ps, false);
7001 si_enable_smc_cac(adev, boot_ps, false);
7002 si_enable_spread_spectrum(adev, false);
7003 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
7004 si_stop_dpm(adev);
7005 si_reset_to_default(adev);
7006 si_dpm_stop_smc(adev);
7007 si_force_switch_to_arb_f0(adev);
7008
7009 ni_update_current_ps(adev, boot_ps);
7010 }
7011
si_dpm_pre_set_power_state(void * handle)7012 static int si_dpm_pre_set_power_state(void *handle)
7013 {
7014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7015 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7016 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
7017 struct amdgpu_ps *new_ps = &requested_ps;
7018
7019 ni_update_requested_ps(adev, new_ps);
7020 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
7021
7022 return 0;
7023 }
7024
si_power_control_set_level(struct amdgpu_device * adev)7025 static int si_power_control_set_level(struct amdgpu_device *adev)
7026 {
7027 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
7028 int ret;
7029
7030 ret = si_restrict_performance_levels_before_switch(adev);
7031 if (ret)
7032 return ret;
7033 ret = si_halt_smc(adev);
7034 if (ret)
7035 return ret;
7036 ret = si_populate_smc_tdp_limits(adev, new_ps);
7037 if (ret)
7038 return ret;
7039 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7040 if (ret)
7041 return ret;
7042 ret = si_resume_smc(adev);
7043 if (ret)
7044 return ret;
7045 return si_set_sw_state(adev);
7046 }
7047
si_set_vce_clock(struct amdgpu_device * adev,struct amdgpu_ps * new_rps,struct amdgpu_ps * old_rps)7048 static void si_set_vce_clock(struct amdgpu_device *adev,
7049 struct amdgpu_ps *new_rps,
7050 struct amdgpu_ps *old_rps)
7051 {
7052 if ((old_rps->evclk != new_rps->evclk) ||
7053 (old_rps->ecclk != new_rps->ecclk)) {
7054 /* Turn the clocks on when encoding, off otherwise */
7055 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk);
7056
7057 if (new_rps->evclk || new_rps->ecclk) {
7058 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);
7059 amdgpu_device_ip_set_clockgating_state(
7060 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE);
7061 amdgpu_device_ip_set_powergating_state(
7062 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE);
7063 } else {
7064 amdgpu_device_ip_set_powergating_state(
7065 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE);
7066 amdgpu_device_ip_set_clockgating_state(
7067 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE);
7068 amdgpu_asic_set_vce_clocks(adev, 0, 0);
7069 }
7070 }
7071 }
7072
si_dpm_set_power_state(void * handle)7073 static int si_dpm_set_power_state(void *handle)
7074 {
7075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7076 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7077 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7078 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7079 int ret;
7080
7081 ret = si_disable_ulv(adev);
7082 if (ret) {
7083 DRM_ERROR("si_disable_ulv failed\n");
7084 return ret;
7085 }
7086 ret = si_restrict_performance_levels_before_switch(adev);
7087 if (ret) {
7088 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7089 return ret;
7090 }
7091 if (eg_pi->pcie_performance_request)
7092 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7093 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7094 ret = si_enable_power_containment(adev, new_ps, false);
7095 if (ret) {
7096 DRM_ERROR("si_enable_power_containment failed\n");
7097 return ret;
7098 }
7099 ret = si_enable_smc_cac(adev, new_ps, false);
7100 if (ret) {
7101 DRM_ERROR("si_enable_smc_cac failed\n");
7102 return ret;
7103 }
7104 ret = si_halt_smc(adev);
7105 if (ret) {
7106 DRM_ERROR("si_halt_smc failed\n");
7107 return ret;
7108 }
7109 ret = si_upload_sw_state(adev, new_ps);
7110 if (ret) {
7111 DRM_ERROR("si_upload_sw_state failed\n");
7112 return ret;
7113 }
7114 ret = si_upload_smc_data(adev);
7115 if (ret) {
7116 DRM_ERROR("si_upload_smc_data failed\n");
7117 return ret;
7118 }
7119 ret = si_upload_ulv_state(adev);
7120 if (ret) {
7121 DRM_ERROR("si_upload_ulv_state failed\n");
7122 return ret;
7123 }
7124 if (eg_pi->dynamic_ac_timing) {
7125 ret = si_upload_mc_reg_table(adev, new_ps);
7126 if (ret) {
7127 DRM_ERROR("si_upload_mc_reg_table failed\n");
7128 return ret;
7129 }
7130 }
7131 ret = si_program_memory_timing_parameters(adev, new_ps);
7132 if (ret) {
7133 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7134 return ret;
7135 }
7136 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7137
7138 ret = si_resume_smc(adev);
7139 if (ret) {
7140 DRM_ERROR("si_resume_smc failed\n");
7141 return ret;
7142 }
7143 ret = si_set_sw_state(adev);
7144 if (ret) {
7145 DRM_ERROR("si_set_sw_state failed\n");
7146 return ret;
7147 }
7148 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7149 si_set_vce_clock(adev, new_ps, old_ps);
7150 if (eg_pi->pcie_performance_request)
7151 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7152 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7153 if (ret) {
7154 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7155 return ret;
7156 }
7157 ret = si_enable_smc_cac(adev, new_ps, true);
7158 if (ret) {
7159 DRM_ERROR("si_enable_smc_cac failed\n");
7160 return ret;
7161 }
7162 ret = si_enable_power_containment(adev, new_ps, true);
7163 if (ret) {
7164 DRM_ERROR("si_enable_power_containment failed\n");
7165 return ret;
7166 }
7167
7168 ret = si_power_control_set_level(adev);
7169 if (ret) {
7170 DRM_ERROR("si_power_control_set_level failed\n");
7171 return ret;
7172 }
7173
7174 return 0;
7175 }
7176
si_dpm_post_set_power_state(void * handle)7177 static void si_dpm_post_set_power_state(void *handle)
7178 {
7179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7180 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7181 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7182
7183 ni_update_current_ps(adev, new_ps);
7184 }
7185
7186 #if 0
7187 void si_dpm_reset_asic(struct amdgpu_device *adev)
7188 {
7189 si_restrict_performance_levels_before_switch(adev);
7190 si_disable_ulv(adev);
7191 si_set_boot_state(adev);
7192 }
7193 #endif
7194
si_dpm_display_configuration_changed(void * handle)7195 static void si_dpm_display_configuration_changed(void *handle)
7196 {
7197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7198
7199 si_program_display_gap(adev);
7200 }
7201
7202
si_parse_pplib_non_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)7203 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7204 struct amdgpu_ps *rps,
7205 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7206 u8 table_rev)
7207 {
7208 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7209 rps->class = le16_to_cpu(non_clock_info->usClassification);
7210 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7211
7212 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7213 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7214 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7215 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7216 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7217 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7218 } else {
7219 rps->vclk = 0;
7220 rps->dclk = 0;
7221 }
7222
7223 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7224 adev->pm.dpm.boot_ps = rps;
7225 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7226 adev->pm.dpm.uvd_ps = rps;
7227 }
7228
si_parse_pplib_clock_info(struct amdgpu_device * adev,struct amdgpu_ps * rps,int index,union pplib_clock_info * clock_info)7229 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7230 struct amdgpu_ps *rps, int index,
7231 union pplib_clock_info *clock_info)
7232 {
7233 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7234 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7235 struct si_power_info *si_pi = si_get_pi(adev);
7236 struct si_ps *ps = si_get_ps(rps);
7237 u16 leakage_voltage;
7238 struct rv7xx_pl *pl = &ps->performance_levels[index];
7239 int ret;
7240
7241 ps->performance_level_count = index + 1;
7242
7243 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7244 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7245 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7246 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7247
7248 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7249 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7250 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7251 pl->pcie_gen = si_gen_pcie_gen_support(adev,
7252 si_pi->sys_pcie_mask,
7253 si_pi->boot_pcie_gen,
7254 clock_info->si.ucPCIEGen);
7255
7256 /* patch up vddc if necessary */
7257 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7258 &leakage_voltage);
7259 if (ret == 0)
7260 pl->vddc = leakage_voltage;
7261
7262 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7263 pi->acpi_vddc = pl->vddc;
7264 eg_pi->acpi_vddci = pl->vddci;
7265 si_pi->acpi_pcie_gen = pl->pcie_gen;
7266 }
7267
7268 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7269 index == 0) {
7270 /* XXX disable for A0 tahiti */
7271 si_pi->ulv.supported = false;
7272 si_pi->ulv.pl = *pl;
7273 si_pi->ulv.one_pcie_lane_in_ulv = false;
7274 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7275 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7276 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7277 }
7278
7279 if (pi->min_vddc_in_table > pl->vddc)
7280 pi->min_vddc_in_table = pl->vddc;
7281
7282 if (pi->max_vddc_in_table < pl->vddc)
7283 pi->max_vddc_in_table = pl->vddc;
7284
7285 /* patch up boot state */
7286 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7287 u16 vddc, vddci, mvdd;
7288 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7289 pl->mclk = adev->clock.default_mclk;
7290 pl->sclk = adev->clock.default_sclk;
7291 pl->vddc = vddc;
7292 pl->vddci = vddci;
7293 si_pi->mvdd_bootup_value = mvdd;
7294 }
7295
7296 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7297 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7298 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7299 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7300 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7301 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7302 }
7303 }
7304
7305 union pplib_power_state {
7306 struct _ATOM_PPLIB_STATE v1;
7307 struct _ATOM_PPLIB_STATE_V2 v2;
7308 };
7309
si_parse_power_table(struct amdgpu_device * adev)7310 static int si_parse_power_table(struct amdgpu_device *adev)
7311 {
7312 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7313 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7314 union pplib_power_state *power_state;
7315 int i, j, k, non_clock_array_index, clock_array_index;
7316 union pplib_clock_info *clock_info;
7317 struct _StateArray *state_array;
7318 struct _ClockInfoArray *clock_info_array;
7319 struct _NonClockInfoArray *non_clock_info_array;
7320 union power_info *power_info;
7321 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7322 u16 data_offset;
7323 u8 frev, crev;
7324 u8 *power_state_offset;
7325 struct si_ps *ps;
7326
7327 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7328 &frev, &crev, &data_offset))
7329 return -EINVAL;
7330 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7331
7332 amdgpu_add_thermal_controller(adev);
7333
7334 state_array = (struct _StateArray *)
7335 (mode_info->atom_context->bios + data_offset +
7336 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7337 clock_info_array = (struct _ClockInfoArray *)
7338 (mode_info->atom_context->bios + data_offset +
7339 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7340 non_clock_info_array = (struct _NonClockInfoArray *)
7341 (mode_info->atom_context->bios + data_offset +
7342 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7343
7344 adev->pm.dpm.ps = kzalloc_objs(struct amdgpu_ps,
7345 state_array->ucNumEntries);
7346 if (!adev->pm.dpm.ps)
7347 return -ENOMEM;
7348 power_state_offset = (u8 *)state_array->states;
7349 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) {
7350 u8 *idx;
7351 power_state = (union pplib_power_state *)power_state_offset;
7352 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7353 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7354 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7355 ps = kzalloc_obj(struct si_ps);
7356 if (ps == NULL)
7357 return -ENOMEM;
7358 adev->pm.dpm.ps[i].ps_priv = ps;
7359 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7360 non_clock_info,
7361 non_clock_info_array->ucEntrySize);
7362 k = 0;
7363 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7364 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7365 clock_array_index = idx[j];
7366 if (clock_array_index >= clock_info_array->ucNumEntries)
7367 continue;
7368 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7369 break;
7370 clock_info = (union pplib_clock_info *)
7371 ((u8 *)&clock_info_array->clockInfo[0] +
7372 (clock_array_index * clock_info_array->ucEntrySize));
7373 si_parse_pplib_clock_info(adev,
7374 &adev->pm.dpm.ps[i], k,
7375 clock_info);
7376 k++;
7377 }
7378 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7379 adev->pm.dpm.num_ps++;
7380 }
7381
7382 /* fill in the vce power states */
7383 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7384 u32 sclk, mclk;
7385 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7386 clock_info = (union pplib_clock_info *)
7387 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7388 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7389 sclk |= clock_info->si.ucEngineClockHigh << 16;
7390 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7391 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7392 adev->pm.dpm.vce_states[i].sclk = sclk;
7393 adev->pm.dpm.vce_states[i].mclk = mclk;
7394 }
7395
7396 return 0;
7397 }
7398
si_dpm_init(struct amdgpu_device * adev)7399 static int si_dpm_init(struct amdgpu_device *adev)
7400 {
7401 struct rv7xx_power_info *pi;
7402 struct evergreen_power_info *eg_pi;
7403 struct ni_power_info *ni_pi;
7404 struct si_power_info *si_pi;
7405 struct atom_clock_dividers dividers;
7406 int ret;
7407
7408 si_pi = kzalloc_obj(struct si_power_info);
7409 if (si_pi == NULL)
7410 return -ENOMEM;
7411 adev->pm.dpm.priv = si_pi;
7412 ni_pi = &si_pi->ni;
7413 eg_pi = &ni_pi->eg;
7414 pi = &eg_pi->rv7xx;
7415
7416 si_pi->sys_pcie_mask =
7417 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7418 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID;
7419 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7420
7421 si_set_max_cu_value(adev);
7422
7423 rv770_get_max_vddc(adev);
7424 si_get_leakage_vddc(adev);
7425 si_patch_dependency_tables_based_on_leakage(adev);
7426
7427 pi->acpi_vddc = 0;
7428 eg_pi->acpi_vddci = 0;
7429 pi->min_vddc_in_table = 0;
7430 pi->max_vddc_in_table = 0;
7431
7432 ret = amdgpu_get_platform_caps(adev);
7433 if (ret)
7434 return ret;
7435
7436 ret = amdgpu_parse_extended_power_table(adev);
7437 if (ret)
7438 return ret;
7439
7440 ret = si_parse_power_table(adev);
7441 if (ret)
7442 return ret;
7443
7444 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7445 kzalloc_objs(struct amdgpu_clock_voltage_dependency_entry, 4);
7446 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)
7447 return -ENOMEM;
7448
7449 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7450 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7451 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7452 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7453 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7454 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7455 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7456 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7457 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7458
7459 if (adev->pm.dpm.voltage_response_time == 0)
7460 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7461 if (adev->pm.dpm.backbias_response_time == 0)
7462 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7463
7464 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7465 0, false, ÷rs);
7466 if (ret)
7467 pi->ref_div = dividers.ref_div + 1;
7468 else
7469 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7470
7471 eg_pi->smu_uvd_hs = false;
7472
7473 pi->mclk_strobe_mode_threshold = 40000;
7474 if (si_is_special_1gb_platform(adev))
7475 pi->mclk_stutter_mode_threshold = 0;
7476 else
7477 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7478 pi->mclk_edc_enable_threshold = 40000;
7479 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7480
7481 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7482
7483 pi->voltage_control =
7484 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7485 VOLTAGE_OBJ_GPIO_LUT);
7486 if (!pi->voltage_control) {
7487 si_pi->voltage_control_svi2 =
7488 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7489 VOLTAGE_OBJ_SVID2);
7490 if (si_pi->voltage_control_svi2)
7491 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7492 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7493 }
7494
7495 pi->mvdd_control =
7496 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7497 VOLTAGE_OBJ_GPIO_LUT);
7498
7499 eg_pi->vddci_control =
7500 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7501 VOLTAGE_OBJ_GPIO_LUT);
7502 if (!eg_pi->vddci_control)
7503 si_pi->vddci_control_svi2 =
7504 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7505 VOLTAGE_OBJ_SVID2);
7506
7507 si_pi->vddc_phase_shed_control =
7508 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7509 VOLTAGE_OBJ_PHASE_LUT);
7510
7511 rv770_get_engine_memory_ss(adev);
7512
7513 pi->asi = RV770_ASI_DFLT;
7514 pi->pasi = CYPRESS_HASI_DFLT;
7515 pi->vrc = SISLANDS_VRC_DFLT;
7516
7517 eg_pi->sclk_deep_sleep = true;
7518 si_pi->sclk_deep_sleep_above_low = false;
7519
7520 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7521 pi->thermal_protection = true;
7522 else
7523 pi->thermal_protection = false;
7524
7525 eg_pi->dynamic_ac_timing = true;
7526
7527 #if defined(CONFIG_ACPI)
7528 eg_pi->pcie_performance_request =
7529 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7530 #else
7531 eg_pi->pcie_performance_request = false;
7532 #endif
7533
7534 si_pi->sram_end = SMC_RAM_END;
7535
7536 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7537 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7538 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7539 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7540 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7541 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7542 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7543
7544 si_initialize_powertune_defaults(adev);
7545
7546 /* make sure dc limits are valid */
7547 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7548 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7549 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7550 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7551
7552 si_pi->fan_ctrl_is_in_default_mode = true;
7553
7554 return 0;
7555 }
7556
si_dpm_fini(struct amdgpu_device * adev)7557 static void si_dpm_fini(struct amdgpu_device *adev)
7558 {
7559 int i;
7560
7561 if (adev->pm.dpm.ps)
7562 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7563 kfree(adev->pm.dpm.ps[i].ps_priv);
7564 kfree(adev->pm.dpm.ps);
7565 kfree(adev->pm.dpm.priv);
7566 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7567 amdgpu_free_extended_power_table(adev);
7568 }
7569
si_dpm_debugfs_print_current_performance_level(void * handle,struct seq_file * m)7570 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7571 struct seq_file *m)
7572 {
7573 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7574 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7575 struct amdgpu_ps *rps = &eg_pi->current_rps;
7576 struct si_ps *ps = si_get_ps(rps);
7577 struct rv7xx_pl *pl;
7578 u32 current_index =
7579 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
7580 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
7581
7582 if (current_index >= ps->performance_level_count) {
7583 seq_printf(m, "invalid dpm profile %d\n", current_index);
7584 } else {
7585 pl = &ps->performance_levels[current_index];
7586 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7587 seq_printf(m, "vce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7588 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7589 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7590 }
7591 }
7592
si_dpm_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)7593 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7594 struct amdgpu_irq_src *source,
7595 unsigned type,
7596 enum amdgpu_interrupt_state state)
7597 {
7598 u32 cg_thermal_int;
7599
7600 switch (type) {
7601 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7602 switch (state) {
7603 case AMDGPU_IRQ_STATE_DISABLE:
7604 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7605 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7606 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7607 break;
7608 case AMDGPU_IRQ_STATE_ENABLE:
7609 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7610 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
7611 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7612 break;
7613 default:
7614 break;
7615 }
7616 break;
7617
7618 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7619 switch (state) {
7620 case AMDGPU_IRQ_STATE_DISABLE:
7621 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7622 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7623 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7624 break;
7625 case AMDGPU_IRQ_STATE_ENABLE:
7626 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
7627 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
7628 WREG32(mmCG_THERMAL_INT, cg_thermal_int);
7629 break;
7630 default:
7631 break;
7632 }
7633 break;
7634
7635 default:
7636 break;
7637 }
7638 return 0;
7639 }
7640
si_dpm_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)7641 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7642 struct amdgpu_irq_src *source,
7643 struct amdgpu_iv_entry *entry)
7644 {
7645 bool queue_thermal = false;
7646
7647 if (entry == NULL)
7648 return -EINVAL;
7649
7650 switch (entry->src_id) {
7651 case 230: /* thermal low to high */
7652 DRM_DEBUG("IH: thermal low to high\n");
7653 adev->pm.dpm.thermal.high_to_low = false;
7654 queue_thermal = true;
7655 break;
7656 case 231: /* thermal high to low */
7657 DRM_DEBUG("IH: thermal high to low\n");
7658 adev->pm.dpm.thermal.high_to_low = true;
7659 queue_thermal = true;
7660 break;
7661 default:
7662 break;
7663 }
7664
7665 if (queue_thermal)
7666 schedule_work(&adev->pm.dpm.thermal.work);
7667
7668 return 0;
7669 }
7670
si_dpm_late_init(struct amdgpu_ip_block * ip_block)7671 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block)
7672 {
7673 int ret;
7674 struct amdgpu_device *adev = ip_block->adev;
7675
7676 if (!adev->pm.dpm_enabled)
7677 return 0;
7678
7679 ret = si_set_temperature_range(adev);
7680 if (ret)
7681 return ret;
7682 #if 0 //TODO ?
7683 si_dpm_powergate_uvd(adev, true);
7684 #endif
7685 return 0;
7686 }
7687
7688 /**
7689 * si_dpm_init_microcode - load ucode images from disk
7690 *
7691 * @adev: amdgpu_device pointer
7692 *
7693 * Use the firmware interface to load the ucode images into
7694 * the driver (not loaded into hw).
7695 * Returns 0 on success, error on failure.
7696 */
si_dpm_init_microcode(struct amdgpu_device * adev)7697 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7698 {
7699 const char *chip_name;
7700 int err;
7701
7702 DRM_DEBUG("\n");
7703 switch (adev->asic_type) {
7704 case CHIP_TAHITI:
7705 chip_name = "tahiti";
7706 break;
7707 case CHIP_PITCAIRN:
7708 if ((adev->pdev->revision == 0x81) &&
7709 ((adev->pdev->device == 0x6810) ||
7710 (adev->pdev->device == 0x6811)))
7711 chip_name = "pitcairn_k";
7712 else
7713 chip_name = "pitcairn";
7714 break;
7715 case CHIP_VERDE:
7716 if (((adev->pdev->device == 0x6820) &&
7717 ((adev->pdev->revision == 0x81) ||
7718 (adev->pdev->revision == 0x83))) ||
7719 ((adev->pdev->device == 0x6821) &&
7720 ((adev->pdev->revision == 0x83) ||
7721 (adev->pdev->revision == 0x87))) ||
7722 ((adev->pdev->revision == 0x87) &&
7723 ((adev->pdev->device == 0x6823) ||
7724 (adev->pdev->device == 0x682b))))
7725 chip_name = "verde_k";
7726 else
7727 chip_name = "verde";
7728 break;
7729 case CHIP_OLAND:
7730 if (((adev->pdev->revision == 0x81) &&
7731 ((adev->pdev->device == 0x6600) ||
7732 (adev->pdev->device == 0x6604) ||
7733 (adev->pdev->device == 0x6605) ||
7734 (adev->pdev->device == 0x6610))) ||
7735 ((adev->pdev->revision == 0x83) &&
7736 (adev->pdev->device == 0x6610)))
7737 chip_name = "oland_k";
7738 else
7739 chip_name = "oland";
7740 break;
7741 case CHIP_HAINAN:
7742 if (((adev->pdev->revision == 0x81) &&
7743 (adev->pdev->device == 0x6660)) ||
7744 ((adev->pdev->revision == 0x83) &&
7745 ((adev->pdev->device == 0x6660) ||
7746 (adev->pdev->device == 0x6663) ||
7747 (adev->pdev->device == 0x6665) ||
7748 (adev->pdev->device == 0x6667))))
7749 chip_name = "hainan_k";
7750 else if ((adev->pdev->revision == 0xc3) &&
7751 (adev->pdev->device == 0x6665))
7752 chip_name = "banks_k_2";
7753 else
7754 chip_name = "hainan";
7755 break;
7756 default: BUG();
7757 }
7758
7759 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
7760 "amdgpu/%s_smc.bin", chip_name);
7761 if (err) {
7762 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n",
7763 err, chip_name);
7764 amdgpu_ucode_release(&adev->pm.fw);
7765 }
7766 return err;
7767 }
7768
si_dpm_sw_init(struct amdgpu_ip_block * ip_block)7769 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block)
7770 {
7771 int ret;
7772 struct amdgpu_device *adev = ip_block->adev;
7773
7774 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7775 if (ret)
7776 return ret;
7777
7778 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7779 if (ret)
7780 return ret;
7781
7782 /* default to balanced state */
7783 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7784 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7785 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7786 adev->pm.default_sclk = adev->clock.default_sclk;
7787 adev->pm.default_mclk = adev->clock.default_mclk;
7788 adev->pm.current_sclk = adev->clock.default_sclk;
7789 adev->pm.current_mclk = adev->clock.default_mclk;
7790 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7791
7792 if (amdgpu_dpm == 0)
7793 return 0;
7794
7795 ret = si_dpm_init_microcode(adev);
7796 if (ret)
7797 return ret;
7798
7799 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7800 ret = si_dpm_init(adev);
7801 if (ret)
7802 goto dpm_failed;
7803 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7804 if (amdgpu_dpm == 1)
7805 amdgpu_pm_print_power_states(adev);
7806 drm_info(adev_to_drm(adev), "si dpm initialized\n");
7807 return 0;
7808
7809 dpm_failed:
7810 si_dpm_fini(adev);
7811 drm_err(adev_to_drm(adev), "dpm initialization failed\n");
7812 return ret;
7813 }
7814
si_dpm_sw_fini(struct amdgpu_ip_block * ip_block)7815 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block)
7816 {
7817 struct amdgpu_device *adev = ip_block->adev;
7818
7819 flush_work(&adev->pm.dpm.thermal.work);
7820
7821 si_dpm_fini(adev);
7822
7823 return 0;
7824 }
7825
si_dpm_hw_init(struct amdgpu_ip_block * ip_block)7826 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block)
7827 {
7828 int ret;
7829
7830 struct amdgpu_device *adev = ip_block->adev;
7831
7832 if (!amdgpu_dpm)
7833 return 0;
7834
7835 mutex_lock(&adev->pm.mutex);
7836 si_dpm_setup_asic(adev);
7837 ret = si_dpm_enable(adev);
7838 if (ret)
7839 adev->pm.dpm_enabled = false;
7840 else
7841 adev->pm.dpm_enabled = true;
7842 amdgpu_legacy_dpm_compute_clocks(adev);
7843 mutex_unlock(&adev->pm.mutex);
7844 return ret;
7845 }
7846
si_dpm_hw_fini(struct amdgpu_ip_block * ip_block)7847 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block)
7848 {
7849 struct amdgpu_device *adev = ip_block->adev;
7850
7851 if (adev->pm.dpm_enabled)
7852 si_dpm_disable(adev);
7853
7854 return 0;
7855 }
7856
si_dpm_suspend(struct amdgpu_ip_block * ip_block)7857 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block)
7858 {
7859 struct amdgpu_device *adev = ip_block->adev;
7860
7861 cancel_work_sync(&adev->pm.dpm.thermal.work);
7862
7863 if (adev->pm.dpm_enabled) {
7864 mutex_lock(&adev->pm.mutex);
7865 adev->pm.dpm_enabled = false;
7866 /* disable dpm */
7867 si_dpm_disable(adev);
7868 /* reset the power state */
7869 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7870 mutex_unlock(&adev->pm.mutex);
7871 }
7872
7873 return 0;
7874 }
7875
si_dpm_resume(struct amdgpu_ip_block * ip_block)7876 static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
7877 {
7878 int ret = 0;
7879 struct amdgpu_device *adev = ip_block->adev;
7880
7881 if (!amdgpu_dpm)
7882 return 0;
7883
7884 if (!adev->pm.dpm_enabled) {
7885 /* asic init will reset to the boot state */
7886 mutex_lock(&adev->pm.mutex);
7887 si_dpm_setup_asic(adev);
7888 ret = si_dpm_enable(adev);
7889 if (ret) {
7890 adev->pm.dpm_enabled = false;
7891 } else {
7892 adev->pm.dpm_enabled = true;
7893 amdgpu_legacy_dpm_compute_clocks(adev);
7894 }
7895 mutex_unlock(&adev->pm.mutex);
7896 }
7897
7898 return ret;
7899 }
7900
si_dpm_is_idle(struct amdgpu_ip_block * ip_block)7901 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
7902 {
7903 /* XXX */
7904 return true;
7905 }
7906
si_dpm_wait_for_idle(struct amdgpu_ip_block * ip_block)7907 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block)
7908 {
7909 /* XXX */
7910 return 0;
7911 }
7912
si_dpm_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)7913 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
7914 enum amd_clockgating_state state)
7915 {
7916 return 0;
7917 }
7918
si_dpm_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)7919 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
7920 enum amd_powergating_state state)
7921 {
7922 return 0;
7923 }
7924
7925 /* get temperature in millidegrees */
si_dpm_get_temp(void * handle)7926 static int si_dpm_get_temp(void *handle)
7927 {
7928 u32 temp;
7929 int actual_temp = 0;
7930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7931
7932 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
7933 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
7934
7935 if (temp & 0x200)
7936 actual_temp = 255;
7937 else
7938 actual_temp = temp & 0x1ff;
7939
7940 actual_temp = (actual_temp * 1000);
7941
7942 return actual_temp;
7943 }
7944
si_dpm_get_sclk(void * handle,bool low)7945 static u32 si_dpm_get_sclk(void *handle, bool low)
7946 {
7947 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7948 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7949 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7950
7951 if (low)
7952 return requested_state->performance_levels[0].sclk;
7953 else
7954 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7955 }
7956
si_dpm_get_mclk(void * handle,bool low)7957 static u32 si_dpm_get_mclk(void *handle, bool low)
7958 {
7959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7960 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7961 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7962
7963 if (low)
7964 return requested_state->performance_levels[0].mclk;
7965 else
7966 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7967 }
7968
si_dpm_print_power_state(void * handle,void * current_ps)7969 static void si_dpm_print_power_state(void *handle,
7970 void *current_ps)
7971 {
7972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7973 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7974 struct si_ps *ps = si_get_ps(rps);
7975 struct rv7xx_pl *pl;
7976 int i;
7977
7978 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2);
7979 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps);
7980 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7981 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
7982 for (i = 0; i < ps->performance_level_count; i++) {
7983 pl = &ps->performance_levels[i];
7984 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7985 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7986 }
7987 amdgpu_dpm_dbg_print_ps_status(adev, rps);
7988 }
7989
si_dpm_early_init(struct amdgpu_ip_block * ip_block)7990 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block)
7991 {
7992
7993 struct amdgpu_device *adev = ip_block->adev;
7994
7995 adev->powerplay.pp_funcs = &si_dpm_funcs;
7996 adev->powerplay.pp_handle = adev;
7997 si_dpm_set_irq_funcs(adev);
7998 return 0;
7999 }
8000
si_are_power_levels_equal(const struct rv7xx_pl * si_cpl1,const struct rv7xx_pl * si_cpl2)8001 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
8002 const struct rv7xx_pl *si_cpl2)
8003 {
8004 return ((si_cpl1->mclk == si_cpl2->mclk) &&
8005 (si_cpl1->sclk == si_cpl2->sclk) &&
8006 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
8007 (si_cpl1->vddc == si_cpl2->vddc) &&
8008 (si_cpl1->vddci == si_cpl2->vddci));
8009 }
8010
si_check_state_equal(void * handle,void * current_ps,void * request_ps,bool * equal)8011 static int si_check_state_equal(void *handle,
8012 void *current_ps,
8013 void *request_ps,
8014 bool *equal)
8015 {
8016 struct si_ps *si_cps;
8017 struct si_ps *si_rps;
8018 int i;
8019 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
8020 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
8021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8022
8023 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
8024 return -EINVAL;
8025
8026 si_cps = si_get_ps((struct amdgpu_ps *)cps);
8027 si_rps = si_get_ps((struct amdgpu_ps *)rps);
8028
8029 if (si_cps == NULL) {
8030 printk("si_cps is NULL\n");
8031 *equal = false;
8032 return 0;
8033 }
8034
8035 if (si_cps->performance_level_count != si_rps->performance_level_count) {
8036 *equal = false;
8037 return 0;
8038 }
8039
8040 for (i = 0; i < si_cps->performance_level_count; i++) {
8041 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8042 &(si_rps->performance_levels[i]))) {
8043 *equal = false;
8044 return 0;
8045 }
8046 }
8047
8048 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8049 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8050 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8051
8052 return 0;
8053 }
8054
si_dpm_read_sensor(void * handle,int idx,void * value,int * size)8055 static int si_dpm_read_sensor(void *handle, int idx,
8056 void *value, int *size)
8057 {
8058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8059 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
8060 struct amdgpu_ps *rps = &eg_pi->current_rps;
8061 struct si_ps *ps = si_get_ps(rps);
8062 uint32_t sclk, mclk;
8063 u32 pl_index =
8064 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>
8065 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT;
8066
8067 /* size must be at least 4 bytes for all sensors */
8068 if (*size < 4)
8069 return -EINVAL;
8070
8071 switch (idx) {
8072 case AMDGPU_PP_SENSOR_GFX_SCLK:
8073 if (pl_index < ps->performance_level_count) {
8074 sclk = ps->performance_levels[pl_index].sclk;
8075 *((uint32_t *)value) = sclk;
8076 *size = 4;
8077 return 0;
8078 }
8079 return -EINVAL;
8080 case AMDGPU_PP_SENSOR_GFX_MCLK:
8081 if (pl_index < ps->performance_level_count) {
8082 mclk = ps->performance_levels[pl_index].mclk;
8083 *((uint32_t *)value) = mclk;
8084 *size = 4;
8085 return 0;
8086 }
8087 return -EINVAL;
8088 case AMDGPU_PP_SENSOR_GPU_TEMP:
8089 *((uint32_t *)value) = si_dpm_get_temp(adev);
8090 *size = 4;
8091 return 0;
8092 default:
8093 return -EOPNOTSUPP;
8094 }
8095 }
8096
8097 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8098 .name = "si_dpm",
8099 .early_init = si_dpm_early_init,
8100 .late_init = si_dpm_late_init,
8101 .sw_init = si_dpm_sw_init,
8102 .sw_fini = si_dpm_sw_fini,
8103 .hw_init = si_dpm_hw_init,
8104 .hw_fini = si_dpm_hw_fini,
8105 .suspend = si_dpm_suspend,
8106 .resume = si_dpm_resume,
8107 .is_idle = si_dpm_is_idle,
8108 .wait_for_idle = si_dpm_wait_for_idle,
8109 .set_clockgating_state = si_dpm_set_clockgating_state,
8110 .set_powergating_state = si_dpm_set_powergating_state,
8111 };
8112
8113 const struct amdgpu_ip_block_version si_smu_ip_block =
8114 {
8115 .type = AMD_IP_BLOCK_TYPE_SMC,
8116 .major = 6,
8117 .minor = 0,
8118 .rev = 0,
8119 .funcs = &si_dpm_ip_funcs,
8120 };
8121
8122 static const struct amd_pm_funcs si_dpm_funcs = {
8123 .pre_set_power_state = &si_dpm_pre_set_power_state,
8124 .set_power_state = &si_dpm_set_power_state,
8125 .post_set_power_state = &si_dpm_post_set_power_state,
8126 .display_configuration_changed = &si_dpm_display_configuration_changed,
8127 .get_sclk = &si_dpm_get_sclk,
8128 .get_mclk = &si_dpm_get_mclk,
8129 .print_power_state = &si_dpm_print_power_state,
8130 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8131 .force_performance_level = &si_dpm_force_performance_level,
8132 .vblank_too_short = &si_dpm_vblank_too_short,
8133 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8134 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8135 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm,
8136 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm,
8137 .check_state_equal = &si_check_state_equal,
8138 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8139 .read_sensor = &si_dpm_read_sensor,
8140 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks,
8141 };
8142
8143 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8144 .set = si_dpm_set_interrupt_state,
8145 .process = si_dpm_process_interrupt,
8146 };
8147
si_dpm_set_irq_funcs(struct amdgpu_device * adev)8148 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8149 {
8150 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8151 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8152 }
8153
8154