1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Procfs interface for the PCI bus 4 * 5 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/slab.h> 11 #include <linux/module.h> 12 #include <linux/proc_fs.h> 13 #include <linux/seq_file.h> 14 #include <linux/capability.h> 15 #include <linux/uaccess.h> 16 #include <linux/security.h> 17 #include <asm/byteorder.h> 18 #include "pci.h" 19 20 static int proc_initialized; /* = 0 */ 21 static DEFINE_MUTEX(pci_proc_lock); 22 23 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence) 24 { 25 struct pci_dev *dev = pde_data(file_inode(file)); 26 return fixed_size_llseek(file, off, whence, dev->cfg_size); 27 } 28 29 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf, 30 size_t nbytes, loff_t *ppos) 31 { 32 struct pci_dev *dev = pde_data(file_inode(file)); 33 unsigned int pos = *ppos; 34 unsigned int cnt, size; 35 36 /* 37 * Normal users can read only the standardized portion of the 38 * configuration space as several chips lock up when trying to read 39 * undefined locations (think of Intel PIIX4 as a typical example). 40 */ 41 42 if (capable(CAP_SYS_ADMIN)) 43 size = dev->cfg_size; 44 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 45 size = 128; 46 else 47 size = 64; 48 49 if (pos >= size) 50 return 0; 51 if (nbytes >= size) 52 nbytes = size; 53 if (pos + nbytes > size) 54 nbytes = size - pos; 55 cnt = nbytes; 56 57 if (!access_ok(buf, cnt)) 58 return -EINVAL; 59 60 pci_config_pm_runtime_get(dev); 61 62 if ((pos & 1) && cnt) { 63 unsigned char val; 64 pci_user_read_config_byte(dev, pos, &val); 65 __put_user(val, buf); 66 buf++; 67 pos++; 68 cnt--; 69 } 70 71 if ((pos & 3) && cnt > 2) { 72 unsigned short val; 73 pci_user_read_config_word(dev, pos, &val); 74 __put_user(cpu_to_le16(val), (__le16 __user *) buf); 75 buf += 2; 76 pos += 2; 77 cnt -= 2; 78 } 79 80 while (cnt >= 4) { 81 unsigned int val; 82 pci_user_read_config_dword(dev, pos, &val); 83 __put_user(cpu_to_le32(val), (__le32 __user *) buf); 84 buf += 4; 85 pos += 4; 86 cnt -= 4; 87 cond_resched(); 88 } 89 90 if (cnt >= 2) { 91 unsigned short val; 92 pci_user_read_config_word(dev, pos, &val); 93 __put_user(cpu_to_le16(val), (__le16 __user *) buf); 94 buf += 2; 95 pos += 2; 96 cnt -= 2; 97 } 98 99 if (cnt) { 100 unsigned char val; 101 pci_user_read_config_byte(dev, pos, &val); 102 __put_user(val, buf); 103 pos++; 104 } 105 106 pci_config_pm_runtime_put(dev); 107 108 *ppos = pos; 109 return nbytes; 110 } 111 112 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf, 113 size_t nbytes, loff_t *ppos) 114 { 115 struct inode *ino = file_inode(file); 116 struct pci_dev *dev = pde_data(ino); 117 int pos = *ppos; 118 int size = dev->cfg_size; 119 int cnt, ret; 120 121 ret = security_locked_down(LOCKDOWN_PCI_ACCESS); 122 if (ret) 123 return ret; 124 125 if (pos >= size) 126 return 0; 127 if (nbytes >= size) 128 nbytes = size; 129 if (pos + nbytes > size) 130 nbytes = size - pos; 131 cnt = nbytes; 132 133 if (!access_ok(buf, cnt)) 134 return -EINVAL; 135 136 pci_config_pm_runtime_get(dev); 137 138 if ((pos & 1) && cnt) { 139 unsigned char val; 140 __get_user(val, buf); 141 pci_user_write_config_byte(dev, pos, val); 142 buf++; 143 pos++; 144 cnt--; 145 } 146 147 if ((pos & 3) && cnt > 2) { 148 __le16 val; 149 __get_user(val, (__le16 __user *) buf); 150 pci_user_write_config_word(dev, pos, le16_to_cpu(val)); 151 buf += 2; 152 pos += 2; 153 cnt -= 2; 154 } 155 156 while (cnt >= 4) { 157 __le32 val; 158 __get_user(val, (__le32 __user *) buf); 159 pci_user_write_config_dword(dev, pos, le32_to_cpu(val)); 160 buf += 4; 161 pos += 4; 162 cnt -= 4; 163 } 164 165 if (cnt >= 2) { 166 __le16 val; 167 __get_user(val, (__le16 __user *) buf); 168 pci_user_write_config_word(dev, pos, le16_to_cpu(val)); 169 buf += 2; 170 pos += 2; 171 cnt -= 2; 172 } 173 174 if (cnt) { 175 unsigned char val; 176 __get_user(val, buf); 177 pci_user_write_config_byte(dev, pos, val); 178 pos++; 179 } 180 181 pci_config_pm_runtime_put(dev); 182 183 *ppos = pos; 184 i_size_write(ino, dev->cfg_size); 185 return nbytes; 186 } 187 188 #ifdef HAVE_PCI_MMAP 189 struct pci_filp_private { 190 enum pci_mmap_state mmap_state; 191 int write_combine; 192 }; 193 #endif /* HAVE_PCI_MMAP */ 194 195 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd, 196 unsigned long arg) 197 { 198 struct pci_dev *dev = pde_data(file_inode(file)); 199 #ifdef HAVE_PCI_MMAP 200 struct pci_filp_private *fpriv = file->private_data; 201 #endif /* HAVE_PCI_MMAP */ 202 int ret = 0; 203 204 ret = security_locked_down(LOCKDOWN_PCI_ACCESS); 205 if (ret) 206 return ret; 207 208 switch (cmd) { 209 case PCIIOC_CONTROLLER: 210 ret = pci_domain_nr(dev->bus); 211 break; 212 213 #ifdef HAVE_PCI_MMAP 214 case PCIIOC_MMAP_IS_IO: 215 if (!arch_can_pci_mmap_io()) 216 return -EINVAL; 217 fpriv->mmap_state = pci_mmap_io; 218 break; 219 220 case PCIIOC_MMAP_IS_MEM: 221 fpriv->mmap_state = pci_mmap_mem; 222 break; 223 224 case PCIIOC_WRITE_COMBINE: 225 if (arch_can_pci_mmap_wc()) { 226 if (arg) 227 fpriv->write_combine = 1; 228 else 229 fpriv->write_combine = 0; 230 break; 231 } 232 /* If arch decided it can't, fall through... */ 233 fallthrough; 234 #endif /* HAVE_PCI_MMAP */ 235 default: 236 ret = -EINVAL; 237 break; 238 } 239 240 return ret; 241 } 242 243 #ifdef HAVE_PCI_MMAP 244 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma) 245 { 246 struct pci_dev *dev = pde_data(file_inode(file)); 247 struct pci_filp_private *fpriv = file->private_data; 248 resource_size_t start, end; 249 int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM; 250 251 if (!capable(CAP_SYS_RAWIO) || 252 security_locked_down(LOCKDOWN_PCI_ACCESS)) 253 return -EPERM; 254 255 /* Skip devices with non-mappable BARs */ 256 if (dev->non_mappable_bars) 257 return -EINVAL; 258 259 if (fpriv->mmap_state == pci_mmap_io) { 260 if (!arch_can_pci_mmap_io()) 261 return -EINVAL; 262 res_bit = IORESOURCE_IO; 263 } 264 265 /* Make sure the caller is mapping a real resource for this device */ 266 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 267 if (dev->resource[i].flags & res_bit && 268 pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS)) 269 break; 270 } 271 272 if (i >= PCI_STD_NUM_BARS) 273 return -ENODEV; 274 275 if (fpriv->mmap_state == pci_mmap_mem && 276 fpriv->write_combine) { 277 if (dev->resource[i].flags & IORESOURCE_PREFETCH) 278 write_combine = 1; 279 else 280 return -EINVAL; 281 } 282 283 if (dev->resource[i].flags & IORESOURCE_MEM && 284 iomem_is_exclusive(dev->resource[i].start)) 285 return -EINVAL; 286 287 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end); 288 289 /* Adjust vm_pgoff to be the offset within the resource */ 290 vma->vm_pgoff -= start >> PAGE_SHIFT; 291 ret = pci_mmap_resource_range(dev, i, vma, 292 fpriv->mmap_state, write_combine); 293 if (ret < 0) 294 return ret; 295 296 return 0; 297 } 298 299 static int proc_bus_pci_open(struct inode *inode, struct file *file) 300 { 301 struct pci_filp_private *fpriv = kmalloc_obj(*fpriv); 302 303 if (!fpriv) 304 return -ENOMEM; 305 306 fpriv->mmap_state = pci_mmap_io; 307 fpriv->write_combine = 0; 308 309 file->private_data = fpriv; 310 file->f_mapping = iomem_get_mapping(); 311 312 return 0; 313 } 314 315 static int proc_bus_pci_release(struct inode *inode, struct file *file) 316 { 317 kfree(file->private_data); 318 file->private_data = NULL; 319 320 return 0; 321 } 322 #endif /* HAVE_PCI_MMAP */ 323 324 static const struct proc_ops proc_bus_pci_ops = { 325 .proc_lseek = proc_bus_pci_lseek, 326 .proc_read = proc_bus_pci_read, 327 .proc_write = proc_bus_pci_write, 328 .proc_ioctl = proc_bus_pci_ioctl, 329 #ifdef CONFIG_COMPAT 330 .proc_compat_ioctl = proc_bus_pci_ioctl, 331 #endif 332 #ifdef HAVE_PCI_MMAP 333 .proc_open = proc_bus_pci_open, 334 .proc_release = proc_bus_pci_release, 335 .proc_mmap = proc_bus_pci_mmap, 336 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA 337 .proc_get_unmapped_area = get_pci_unmapped_area, 338 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */ 339 #endif /* HAVE_PCI_MMAP */ 340 }; 341 342 /* iterator */ 343 static void *pci_seq_start(struct seq_file *m, loff_t *pos) 344 { 345 struct pci_dev *dev = NULL; 346 loff_t n = *pos; 347 348 for_each_pci_dev(dev) { 349 if (!n--) 350 break; 351 } 352 return dev; 353 } 354 355 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos) 356 { 357 struct pci_dev *dev = v; 358 359 (*pos)++; 360 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); 361 return dev; 362 } 363 364 static void pci_seq_stop(struct seq_file *m, void *v) 365 { 366 if (v) { 367 struct pci_dev *dev = v; 368 pci_dev_put(dev); 369 } 370 } 371 372 static int show_device(struct seq_file *m, void *v) 373 { 374 const struct pci_dev *dev = v; 375 const struct pci_driver *drv; 376 int i; 377 378 if (dev == NULL) 379 return 0; 380 381 drv = pci_dev_driver(dev); 382 seq_printf(m, "%02x%02x\t%04x%04x\t%x", 383 dev->bus->number, 384 dev->devfn, 385 dev->vendor, 386 dev->device, 387 dev->irq); 388 389 /* only print standard and ROM resources to preserve compatibility */ 390 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 391 resource_size_t start, end; 392 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end); 393 seq_printf(m, "\t%16llx", 394 (unsigned long long)(start | 395 (dev->resource[i].flags & PCI_REGION_FLAG_MASK))); 396 } 397 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 398 resource_size_t start, end; 399 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end); 400 seq_printf(m, "\t%16llx", 401 dev->resource[i].start < dev->resource[i].end ? 402 (unsigned long long)(end - start) + 1 : 0); 403 } 404 seq_putc(m, '\t'); 405 if (drv) 406 seq_puts(m, drv->name); 407 seq_putc(m, '\n'); 408 return 0; 409 } 410 411 static const struct seq_operations proc_bus_pci_devices_op = { 412 .start = pci_seq_start, 413 .next = pci_seq_next, 414 .stop = pci_seq_stop, 415 .show = show_device 416 }; 417 418 static struct proc_dir_entry *proc_bus_pci_dir; 419 420 static int __pci_proc_attach_bus(struct pci_bus *bus) 421 { 422 struct proc_dir_entry *dir; 423 char name[16]; 424 425 lockdep_assert_held(&pci_proc_lock); 426 427 if (!proc_initialized) 428 return -EACCES; 429 430 if (bus->procdir) 431 return 0; 432 433 if (pci_proc_domain(bus)) 434 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number); 435 else 436 sprintf(name, "%02x", bus->number); 437 438 dir = proc_mkdir(name, proc_bus_pci_dir); 439 if (!dir) 440 return -ENOMEM; 441 442 bus->procdir = dir; 443 444 return 0; 445 } 446 447 int pci_proc_attach_device(struct pci_dev *dev) 448 { 449 struct pci_bus *bus = dev->bus; 450 struct proc_dir_entry *entry; 451 char name[16]; 452 int ret; 453 454 guard(mutex)(&pci_proc_lock); 455 456 if (dev->procent) 457 return 0; 458 459 ret = __pci_proc_attach_bus(bus); 460 if (ret) 461 return ret; 462 463 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 464 entry = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, 465 bus->procdir, &proc_bus_pci_ops, dev); 466 if (!entry) 467 return -ENOMEM; 468 469 proc_set_size(entry, dev->cfg_size); 470 dev->procent = entry; 471 472 return 0; 473 } 474 475 int pci_proc_detach_device(struct pci_dev *dev) 476 { 477 guard(mutex)(&pci_proc_lock); 478 proc_remove(dev->procent); 479 dev->procent = NULL; 480 return 0; 481 } 482 483 int pci_proc_detach_bus(struct pci_bus *bus) 484 { 485 guard(mutex)(&pci_proc_lock); 486 proc_remove(bus->procdir); 487 bus->procdir = NULL; 488 return 0; 489 } 490 491 static int __init pci_proc_init(void) 492 { 493 struct pci_dev *dev = NULL; 494 495 scoped_guard(mutex, &pci_proc_lock) { 496 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL); 497 proc_create_seq("devices", 0, proc_bus_pci_dir, 498 &proc_bus_pci_devices_op); 499 proc_initialized = 1; 500 } 501 502 pci_lock_rescan_remove(); 503 for_each_pci_dev(dev) 504 pci_proc_attach_device(dev); 505 pci_unlock_rescan_remove(); 506 507 return 0; 508 } 509 device_initcall(pci_proc_init); 510