1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 #include "spl/dc_spl_types.h" 50 51 struct abm_save_restore; 52 53 /* forward declaration */ 54 struct aux_payload; 55 struct set_config_cmd_payload; 56 struct dmub_notification; 57 58 #define DC_VER "3.2.316" 59 60 #define MAX_SURFACES 4 61 #define MAX_PLANES 6 62 #define MAX_STREAMS 6 63 #define MIN_VIEWPORT_SIZE 12 64 #define MAX_NUM_EDP 2 65 #define MAX_HOST_ROUTERS_NUM 2 66 67 /* Display Core Interfaces */ 68 struct dc_versions { 69 const char *dc_ver; 70 struct dmcu_version dmcu_version; 71 }; 72 73 enum dp_protocol_version { 74 DP_VERSION_1_4 = 0, 75 DP_VERSION_2_1, 76 DP_VERSION_UNKNOWN, 77 }; 78 79 enum dc_plane_type { 80 DC_PLANE_TYPE_INVALID, 81 DC_PLANE_TYPE_DCE_RGB, 82 DC_PLANE_TYPE_DCE_UNDERLAY, 83 DC_PLANE_TYPE_DCN_UNIVERSAL, 84 }; 85 86 // Sizes defined as multiples of 64KB 87 enum det_size { 88 DET_SIZE_DEFAULT = 0, 89 DET_SIZE_192KB = 3, 90 DET_SIZE_256KB = 4, 91 DET_SIZE_320KB = 5, 92 DET_SIZE_384KB = 6 93 }; 94 95 96 struct dc_plane_cap { 97 enum dc_plane_type type; 98 uint32_t per_pixel_alpha : 1; 99 struct { 100 uint32_t argb8888 : 1; 101 uint32_t nv12 : 1; 102 uint32_t fp16 : 1; 103 uint32_t p010 : 1; 104 uint32_t ayuv : 1; 105 } pixel_format_support; 106 // max upscaling factor x1000 107 // upscaling factors are always >= 1 108 // for example, 1080p -> 8K is 4.0, or 4000 raw value 109 struct { 110 uint32_t argb8888; 111 uint32_t nv12; 112 uint32_t fp16; 113 } max_upscale_factor; 114 // max downscale factor x1000 115 // downscale factors are always <= 1 116 // for example, 8K -> 1080p is 0.25, or 250 raw value 117 struct { 118 uint32_t argb8888; 119 uint32_t nv12; 120 uint32_t fp16; 121 } max_downscale_factor; 122 // minimal width/height 123 uint32_t min_width; 124 uint32_t min_height; 125 }; 126 127 /** 128 * DOC: color-management-caps 129 * 130 * **Color management caps (DPP and MPC)** 131 * 132 * Modules/color calculates various color operations which are translated to 133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 134 * DCN1, every new generation comes with fairly major differences in color 135 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 136 * decide mapping to HW block based on logical capabilities. 137 */ 138 139 /** 140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 141 * @srgb: RGB color space transfer func 142 * @bt2020: BT.2020 transfer func 143 * @gamma2_2: standard gamma 144 * @pq: perceptual quantizer transfer function 145 * @hlg: hybrid log–gamma transfer function 146 */ 147 struct rom_curve_caps { 148 uint16_t srgb : 1; 149 uint16_t bt2020 : 1; 150 uint16_t gamma2_2 : 1; 151 uint16_t pq : 1; 152 uint16_t hlg : 1; 153 }; 154 155 /** 156 * struct dpp_color_caps - color pipeline capabilities for display pipe and 157 * plane blocks 158 * 159 * @dcn_arch: all DCE generations treated the same 160 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 161 * just plain 256-entry lookup 162 * @icsc: input color space conversion 163 * @dgam_ram: programmable degamma LUT 164 * @post_csc: post color space conversion, before gamut remap 165 * @gamma_corr: degamma correction 166 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 167 * with MPC by setting mpc:shared_3d_lut flag 168 * @ogam_ram: programmable out/blend gamma LUT 169 * @ocsc: output color space conversion 170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 172 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 173 * 174 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 175 */ 176 struct dpp_color_caps { 177 uint16_t dcn_arch : 1; 178 uint16_t input_lut_shared : 1; 179 uint16_t icsc : 1; 180 uint16_t dgam_ram : 1; 181 uint16_t post_csc : 1; 182 uint16_t gamma_corr : 1; 183 uint16_t hw_3d_lut : 1; 184 uint16_t ogam_ram : 1; 185 uint16_t ocsc : 1; 186 uint16_t dgam_rom_for_yuv : 1; 187 struct rom_curve_caps dgam_rom_caps; 188 struct rom_curve_caps ogam_rom_caps; 189 }; 190 191 /** 192 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 193 * plane combined blocks 194 * 195 * @gamut_remap: color transformation matrix 196 * @ogam_ram: programmable out gamma LUT 197 * @ocsc: output color space conversion matrix 198 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 199 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 200 * instance 201 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 202 */ 203 struct mpc_color_caps { 204 uint16_t gamut_remap : 1; 205 uint16_t ogam_ram : 1; 206 uint16_t ocsc : 1; 207 uint16_t num_3dluts : 3; 208 uint16_t shared_3d_lut:1; 209 struct rom_curve_caps ogam_rom_caps; 210 }; 211 212 /** 213 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 214 * @dpp: color pipes caps for DPP 215 * @mpc: color pipes caps for MPC 216 */ 217 struct dc_color_caps { 218 struct dpp_color_caps dpp; 219 struct mpc_color_caps mpc; 220 }; 221 222 struct dc_dmub_caps { 223 bool psr; 224 bool mclk_sw; 225 bool subvp_psr; 226 bool gecc_enable; 227 uint8_t fams_ver; 228 bool aux_backlight_support; 229 }; 230 231 struct dc_scl_caps { 232 bool sharpener_support; 233 }; 234 235 struct dc_caps { 236 uint32_t max_streams; 237 uint32_t max_links; 238 uint32_t max_audios; 239 uint32_t max_slave_planes; 240 uint32_t max_slave_yuv_planes; 241 uint32_t max_slave_rgb_planes; 242 uint32_t max_planes; 243 uint32_t max_downscale_ratio; 244 uint32_t i2c_speed_in_khz; 245 uint32_t i2c_speed_in_khz_hdcp; 246 uint32_t dmdata_alloc_size; 247 unsigned int max_cursor_size; 248 unsigned int max_video_width; 249 /* 250 * max video plane width that can be safely assumed to be always 251 * supported by single DPP pipe. 252 */ 253 unsigned int max_optimizable_video_width; 254 unsigned int min_horizontal_blanking_period; 255 int linear_pitch_alignment; 256 bool dcc_const_color; 257 bool dynamic_audio; 258 bool is_apu; 259 bool dual_link_dvi; 260 bool post_blend_color_processing; 261 bool force_dp_tps4_for_cp2520; 262 bool disable_dp_clk_share; 263 bool psp_setup_panel_mode; 264 bool extended_aux_timeout_support; 265 bool dmcub_support; 266 bool zstate_support; 267 bool ips_support; 268 uint32_t num_of_internal_disp; 269 enum dp_protocol_version max_dp_protocol_version; 270 unsigned int mall_size_per_mem_channel; 271 unsigned int mall_size_total; 272 unsigned int cursor_cache_size; 273 struct dc_plane_cap planes[MAX_PLANES]; 274 struct dc_color_caps color; 275 struct dc_dmub_caps dmub_caps; 276 bool dp_hpo; 277 bool dp_hdmi21_pcon_support; 278 bool edp_dsc_support; 279 bool vbios_lttpr_aware; 280 bool vbios_lttpr_enable; 281 uint32_t max_otg_num; 282 uint32_t max_cab_allocation_bytes; 283 uint32_t cache_line_size; 284 uint32_t cache_num_ways; 285 uint16_t subvp_fw_processing_delay_us; 286 uint8_t subvp_drr_max_vblank_margin_us; 287 uint16_t subvp_prefetch_end_to_mall_start_us; 288 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 289 uint16_t subvp_pstate_allow_width_us; 290 uint16_t subvp_vertical_int_margin_us; 291 bool seamless_odm; 292 uint32_t max_v_total; 293 bool vtotal_limited_by_fp2; 294 uint32_t max_disp_clock_khz_at_vmin; 295 uint8_t subvp_drr_vblank_start_margin_us; 296 bool cursor_not_scaled; 297 bool dcmode_power_limits_present; 298 bool sequential_ono; 299 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 300 uint32_t dcc_plane_width_limit; 301 struct dc_scl_caps scl_caps; 302 }; 303 304 struct dc_bug_wa { 305 bool no_connect_phy_config; 306 bool dedcn20_305_wa; 307 bool skip_clock_update; 308 bool lt_early_cr_pattern; 309 struct { 310 uint8_t uclk : 1; 311 uint8_t fclk : 1; 312 uint8_t dcfclk : 1; 313 uint8_t dcfclk_ds: 1; 314 } clock_update_disable_mask; 315 bool skip_psr_ips_crtc_disable; 316 }; 317 struct dc_dcc_surface_param { 318 struct dc_size surface_size; 319 enum surface_pixel_format format; 320 unsigned int plane0_pitch; 321 struct dc_size plane1_size; 322 unsigned int plane1_pitch; 323 union { 324 enum swizzle_mode_values swizzle_mode; 325 enum swizzle_mode_addr3_values swizzle_mode_addr3; 326 }; 327 enum dc_scan_direction scan; 328 }; 329 330 struct dc_dcc_setting { 331 unsigned int max_compressed_blk_size; 332 unsigned int max_uncompressed_blk_size; 333 bool independent_64b_blks; 334 //These bitfields to be used starting with DCN 3.0 335 struct { 336 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 337 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 338 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 339 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 340 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 341 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 342 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 343 } dcc_controls; 344 }; 345 346 struct dc_surface_dcc_cap { 347 union { 348 struct { 349 struct dc_dcc_setting rgb; 350 } grph; 351 352 struct { 353 struct dc_dcc_setting luma; 354 struct dc_dcc_setting chroma; 355 } video; 356 }; 357 358 bool capable; 359 bool const_color_support; 360 }; 361 362 struct dc_static_screen_params { 363 struct { 364 bool force_trigger; 365 bool cursor_update; 366 bool surface_update; 367 bool overlay_update; 368 } triggers; 369 unsigned int num_frames; 370 }; 371 372 373 /* Surface update type is used by dc_update_surfaces_and_stream 374 * The update type is determined at the very beginning of the function based 375 * on parameters passed in and decides how much programming (or updating) is 376 * going to be done during the call. 377 * 378 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 379 * logical calculations or hardware register programming. This update MUST be 380 * ISR safe on windows. Currently fast update will only be used to flip surface 381 * address. 382 * 383 * UPDATE_TYPE_MED is used for slower updates which require significant hw 384 * re-programming however do not affect bandwidth consumption or clock 385 * requirements. At present, this is the level at which front end updates 386 * that do not require us to run bw_calcs happen. These are in/out transfer func 387 * updates, viewport offset changes, recout size changes and pixel depth changes. 388 * This update can be done at ISR, but we want to minimize how often this happens. 389 * 390 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 391 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 392 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 393 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 394 * a full update. This cannot be done at ISR level and should be a rare event. 395 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 396 * underscan we don't expect to see this call at all. 397 */ 398 399 enum surface_update_type { 400 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 401 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 402 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 403 }; 404 405 /* Forward declaration*/ 406 struct dc; 407 struct dc_plane_state; 408 struct dc_state; 409 410 struct dc_cap_funcs { 411 bool (*get_dcc_compression_cap)(const struct dc *dc, 412 const struct dc_dcc_surface_param *input, 413 struct dc_surface_dcc_cap *output); 414 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 415 }; 416 417 struct link_training_settings; 418 419 union allow_lttpr_non_transparent_mode { 420 struct { 421 bool DP1_4A : 1; 422 bool DP2_0 : 1; 423 } bits; 424 unsigned char raw; 425 }; 426 427 /* Structure to hold configuration flags set by dm at dc creation. */ 428 struct dc_config { 429 bool gpu_vm_support; 430 bool disable_disp_pll_sharing; 431 bool fbc_support; 432 bool disable_fractional_pwm; 433 bool allow_seamless_boot_optimization; 434 bool seamless_boot_edp_requested; 435 bool edp_not_connected; 436 bool edp_no_power_sequencing; 437 bool force_enum_edp; 438 bool forced_clocks; 439 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 440 bool multi_mon_pp_mclk_switch; 441 bool disable_dmcu; 442 bool enable_4to1MPC; 443 bool enable_windowed_mpo_odm; 444 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 445 uint32_t allow_edp_hotplug_detection; 446 bool clamp_min_dcfclk; 447 uint64_t vblank_alignment_dto_params; 448 uint8_t vblank_alignment_max_frame_time_diff; 449 bool is_asymmetric_memory; 450 bool is_single_rank_dimm; 451 bool is_vmin_only_asic; 452 bool use_spl; 453 bool prefer_easf; 454 bool use_pipe_ctx_sync_logic; 455 bool ignore_dpref_ss; 456 bool enable_mipi_converter_optimization; 457 bool use_default_clock_table; 458 bool force_bios_enable_lttpr; 459 uint8_t force_bios_fixed_vs; 460 int sdpif_request_limit_words_per_umc; 461 bool dc_mode_clk_limit_support; 462 bool EnableMinDispClkODM; 463 bool enable_auto_dpm_test_logs; 464 unsigned int disable_ips; 465 unsigned int disable_ips_in_vpb; 466 bool disable_ips_in_dpms_off; 467 bool usb4_bw_alloc_support; 468 bool allow_0_dtb_clk; 469 bool use_assr_psp_message; 470 bool support_edp0_on_dp1; 471 unsigned int enable_fpo_flicker_detection; 472 bool disable_hbr_audio_dp2; 473 bool consolidated_dpia_dp_lt; 474 bool set_pipe_unlock_order; 475 bool enable_dpia_pre_training; 476 }; 477 478 enum visual_confirm { 479 VISUAL_CONFIRM_DISABLE = 0, 480 VISUAL_CONFIRM_SURFACE = 1, 481 VISUAL_CONFIRM_HDR = 2, 482 VISUAL_CONFIRM_MPCTREE = 4, 483 VISUAL_CONFIRM_PSR = 5, 484 VISUAL_CONFIRM_SWAPCHAIN = 6, 485 VISUAL_CONFIRM_FAMS = 7, 486 VISUAL_CONFIRM_SWIZZLE = 9, 487 VISUAL_CONFIRM_REPLAY = 12, 488 VISUAL_CONFIRM_SUBVP = 14, 489 VISUAL_CONFIRM_MCLK_SWITCH = 16, 490 VISUAL_CONFIRM_FAMS2 = 19, 491 VISUAL_CONFIRM_HW_CURSOR = 20, 492 VISUAL_CONFIRM_VABC = 21, 493 }; 494 495 enum dc_psr_power_opts { 496 psr_power_opt_invalid = 0x0, 497 psr_power_opt_smu_opt_static_screen = 0x1, 498 psr_power_opt_z10_static_screen = 0x10, 499 psr_power_opt_ds_disable_allow = 0x100, 500 }; 501 502 enum dml_hostvm_override_opts { 503 DML_HOSTVM_NO_OVERRIDE = 0x0, 504 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 505 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 506 }; 507 508 enum dc_replay_power_opts { 509 replay_power_opt_invalid = 0x0, 510 replay_power_opt_smu_opt_static_screen = 0x1, 511 replay_power_opt_z10_static_screen = 0x10, 512 }; 513 514 enum dcc_option { 515 DCC_ENABLE = 0, 516 DCC_DISABLE = 1, 517 DCC_HALF_REQ_DISALBE = 2, 518 }; 519 520 enum in_game_fams_config { 521 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 522 INGAME_FAMS_DISABLE, // disable in-game fams 523 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 524 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 525 }; 526 527 /** 528 * enum pipe_split_policy - Pipe split strategy supported by DCN 529 * 530 * This enum is used to define the pipe split policy supported by DCN. By 531 * default, DC favors MPC_SPLIT_DYNAMIC. 532 */ 533 enum pipe_split_policy { 534 /** 535 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 536 * pipe in order to bring the best trade-off between performance and 537 * power consumption. This is the recommended option. 538 */ 539 MPC_SPLIT_DYNAMIC = 0, 540 541 /** 542 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 543 * try any sort of split optimization. 544 */ 545 MPC_SPLIT_AVOID = 1, 546 547 /** 548 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 549 * optimize the pipe utilization when using a single display; if the 550 * user connects to a second display, DC will avoid pipe split. 551 */ 552 MPC_SPLIT_AVOID_MULT_DISP = 2, 553 }; 554 555 enum wm_report_mode { 556 WM_REPORT_DEFAULT = 0, 557 WM_REPORT_OVERRIDE = 1, 558 }; 559 enum dtm_pstate{ 560 dtm_level_p0 = 0,/*highest voltage*/ 561 dtm_level_p1, 562 dtm_level_p2, 563 dtm_level_p3, 564 dtm_level_p4,/*when active_display_count = 0*/ 565 }; 566 567 enum dcn_pwr_state { 568 DCN_PWR_STATE_UNKNOWN = -1, 569 DCN_PWR_STATE_MISSION_MODE = 0, 570 DCN_PWR_STATE_LOW_POWER = 3, 571 }; 572 573 enum dcn_zstate_support_state { 574 DCN_ZSTATE_SUPPORT_UNKNOWN, 575 DCN_ZSTATE_SUPPORT_ALLOW, 576 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 577 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 578 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 579 DCN_ZSTATE_SUPPORT_DISALLOW, 580 }; 581 582 /* 583 * struct dc_clocks - DC pipe clocks 584 * 585 * For any clocks that may differ per pipe only the max is stored in this 586 * structure 587 */ 588 struct dc_clocks { 589 int dispclk_khz; 590 int actual_dispclk_khz; 591 int dppclk_khz; 592 int actual_dppclk_khz; 593 int disp_dpp_voltage_level_khz; 594 int dcfclk_khz; 595 int socclk_khz; 596 int dcfclk_deep_sleep_khz; 597 int fclk_khz; 598 int phyclk_khz; 599 int dramclk_khz; 600 bool p_state_change_support; 601 enum dcn_zstate_support_state zstate_support; 602 bool dtbclk_en; 603 int ref_dtbclk_khz; 604 bool fclk_p_state_change_support; 605 enum dcn_pwr_state pwr_state; 606 /* 607 * Elements below are not compared for the purposes of 608 * optimization required 609 */ 610 bool prev_p_state_change_support; 611 bool fclk_prev_p_state_change_support; 612 int num_ways; 613 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 614 615 /* 616 * @fw_based_mclk_switching 617 * 618 * DC has a mechanism that leverage the variable refresh rate to switch 619 * memory clock in cases that we have a large latency to achieve the 620 * memory clock change and a short vblank window. DC has some 621 * requirements to enable this feature, and this field describes if the 622 * system support or not such a feature. 623 */ 624 bool fw_based_mclk_switching; 625 bool fw_based_mclk_switching_shut_down; 626 int prev_num_ways; 627 enum dtm_pstate dtm_level; 628 int max_supported_dppclk_khz; 629 int max_supported_dispclk_khz; 630 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 631 int bw_dispclk_khz; 632 int idle_dramclk_khz; 633 int idle_fclk_khz; 634 int subvp_prefetch_dramclk_khz; 635 int subvp_prefetch_fclk_khz; 636 }; 637 638 struct dc_bw_validation_profile { 639 bool enable; 640 641 unsigned long long total_ticks; 642 unsigned long long voltage_level_ticks; 643 unsigned long long watermark_ticks; 644 unsigned long long rq_dlg_ticks; 645 646 unsigned long long total_count; 647 unsigned long long skip_fast_count; 648 unsigned long long skip_pass_count; 649 unsigned long long skip_fail_count; 650 }; 651 652 #define BW_VAL_TRACE_SETUP() \ 653 unsigned long long end_tick = 0; \ 654 unsigned long long voltage_level_tick = 0; \ 655 unsigned long long watermark_tick = 0; \ 656 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 657 dm_get_timestamp(dc->ctx) : 0 658 659 #define BW_VAL_TRACE_COUNT() \ 660 if (dc->debug.bw_val_profile.enable) \ 661 dc->debug.bw_val_profile.total_count++ 662 663 #define BW_VAL_TRACE_SKIP(status) \ 664 if (dc->debug.bw_val_profile.enable) { \ 665 if (!voltage_level_tick) \ 666 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 667 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 668 } 669 670 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 671 if (dc->debug.bw_val_profile.enable) \ 672 voltage_level_tick = dm_get_timestamp(dc->ctx) 673 674 #define BW_VAL_TRACE_END_WATERMARKS() \ 675 if (dc->debug.bw_val_profile.enable) \ 676 watermark_tick = dm_get_timestamp(dc->ctx) 677 678 #define BW_VAL_TRACE_FINISH() \ 679 if (dc->debug.bw_val_profile.enable) { \ 680 end_tick = dm_get_timestamp(dc->ctx); \ 681 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 682 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 683 if (watermark_tick) { \ 684 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 685 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 686 } \ 687 } 688 689 union mem_low_power_enable_options { 690 struct { 691 bool vga: 1; 692 bool i2c: 1; 693 bool dmcu: 1; 694 bool dscl: 1; 695 bool cm: 1; 696 bool mpc: 1; 697 bool optc: 1; 698 bool vpg: 1; 699 bool afmt: 1; 700 } bits; 701 uint32_t u32All; 702 }; 703 704 union root_clock_optimization_options { 705 struct { 706 bool dpp: 1; 707 bool dsc: 1; 708 bool hdmistream: 1; 709 bool hdmichar: 1; 710 bool dpstream: 1; 711 bool symclk32_se: 1; 712 bool symclk32_le: 1; 713 bool symclk_fe: 1; 714 bool physymclk: 1; 715 bool dpiasymclk: 1; 716 uint32_t reserved: 22; 717 } bits; 718 uint32_t u32All; 719 }; 720 721 union fine_grain_clock_gating_enable_options { 722 struct { 723 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 724 bool dchub : 1; /* Display controller hub */ 725 bool dchubbub : 1; 726 bool dpp : 1; /* Display pipes and planes */ 727 bool opp : 1; /* Output pixel processing */ 728 bool optc : 1; /* Output pipe timing combiner */ 729 bool dio : 1; /* Display output */ 730 bool dwb : 1; /* Display writeback */ 731 bool mmhubbub : 1; /* Multimedia hub */ 732 bool dmu : 1; /* Display core management unit */ 733 bool az : 1; /* Azalia */ 734 bool dchvm : 1; 735 bool dsc : 1; /* Display stream compression */ 736 737 uint32_t reserved : 19; 738 } bits; 739 uint32_t u32All; 740 }; 741 742 enum pg_hw_pipe_resources { 743 PG_HUBP = 0, 744 PG_DPP, 745 PG_DSC, 746 PG_MPCC, 747 PG_OPP, 748 PG_OPTC, 749 PG_DPSTREAM, 750 PG_HDMISTREAM, 751 PG_PHYSYMCLK, 752 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 753 }; 754 755 enum pg_hw_resources { 756 PG_DCCG = 0, 757 PG_DCIO, 758 PG_DIO, 759 PG_DCHUBBUB, 760 PG_DCHVM, 761 PG_DWB, 762 PG_HPO, 763 PG_HW_RESOURCES_NUM_ELEMENT 764 }; 765 766 struct pg_block_update { 767 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 768 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 769 }; 770 771 union dpia_debug_options { 772 struct { 773 uint32_t disable_dpia:1; /* bit 0 */ 774 uint32_t force_non_lttpr:1; /* bit 1 */ 775 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 776 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 777 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 778 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 779 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 780 uint32_t enable_dpia_pre_training:1; /* bit 7 */ 781 uint32_t reserved:24; 782 } bits; 783 uint32_t raw; 784 }; 785 786 /* AUX wake work around options 787 * 0: enable/disable work around 788 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 789 * 15-2: reserved 790 * 31-16: timeout in ms 791 */ 792 union aux_wake_wa_options { 793 struct { 794 uint32_t enable_wa : 1; 795 uint32_t use_default_timeout : 1; 796 uint32_t rsvd: 14; 797 uint32_t timeout_ms : 16; 798 } bits; 799 uint32_t raw; 800 }; 801 802 struct dc_debug_data { 803 uint32_t ltFailCount; 804 uint32_t i2cErrorCount; 805 uint32_t auxErrorCount; 806 }; 807 808 struct dc_phy_addr_space_config { 809 struct { 810 uint64_t start_addr; 811 uint64_t end_addr; 812 uint64_t fb_top; 813 uint64_t fb_offset; 814 uint64_t fb_base; 815 uint64_t agp_top; 816 uint64_t agp_bot; 817 uint64_t agp_base; 818 } system_aperture; 819 820 struct { 821 uint64_t page_table_start_addr; 822 uint64_t page_table_end_addr; 823 uint64_t page_table_base_addr; 824 bool base_addr_is_mc_addr; 825 } gart_config; 826 827 bool valid; 828 bool is_hvm_enabled; 829 uint64_t page_table_default_page_addr; 830 }; 831 832 struct dc_virtual_addr_space_config { 833 uint64_t page_table_base_addr; 834 uint64_t page_table_start_addr; 835 uint64_t page_table_end_addr; 836 uint32_t page_table_block_size_in_bytes; 837 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 838 }; 839 840 struct dc_bounding_box_overrides { 841 int sr_exit_time_ns; 842 int sr_enter_plus_exit_time_ns; 843 int sr_exit_z8_time_ns; 844 int sr_enter_plus_exit_z8_time_ns; 845 int urgent_latency_ns; 846 int percent_of_ideal_drambw; 847 int dram_clock_change_latency_ns; 848 int dummy_clock_change_latency_ns; 849 int fclk_clock_change_latency_ns; 850 /* This forces a hard min on the DCFCLK we use 851 * for DML. Unlike the debug option for forcing 852 * DCFCLK, this override affects watermark calculations 853 */ 854 int min_dcfclk_mhz; 855 }; 856 857 struct dc_state; 858 struct resource_pool; 859 struct dce_hwseq; 860 struct link_service; 861 862 /* 863 * struct dc_debug_options - DC debug struct 864 * 865 * This struct provides a simple mechanism for developers to change some 866 * configurations, enable/disable features, and activate extra debug options. 867 * This can be very handy to narrow down whether some specific feature is 868 * causing an issue or not. 869 */ 870 struct dc_debug_options { 871 bool native422_support; 872 bool disable_dsc; 873 enum visual_confirm visual_confirm; 874 int visual_confirm_rect_height; 875 876 bool sanity_checks; 877 bool max_disp_clk; 878 bool surface_trace; 879 bool clock_trace; 880 bool validation_trace; 881 bool bandwidth_calcs_trace; 882 int max_downscale_src_width; 883 884 /* stutter efficiency related */ 885 bool disable_stutter; 886 bool use_max_lb; 887 enum dcc_option disable_dcc; 888 889 /* 890 * @pipe_split_policy: Define which pipe split policy is used by the 891 * display core. 892 */ 893 enum pipe_split_policy pipe_split_policy; 894 bool force_single_disp_pipe_split; 895 bool voltage_align_fclk; 896 bool disable_min_fclk; 897 898 bool disable_dfs_bypass; 899 bool disable_dpp_power_gate; 900 bool disable_hubp_power_gate; 901 bool disable_dsc_power_gate; 902 bool disable_optc_power_gate; 903 bool disable_hpo_power_gate; 904 int dsc_min_slice_height_override; 905 int dsc_bpp_increment_div; 906 bool disable_pplib_wm_range; 907 enum wm_report_mode pplib_wm_report_mode; 908 unsigned int min_disp_clk_khz; 909 unsigned int min_dpp_clk_khz; 910 unsigned int min_dram_clk_khz; 911 int sr_exit_time_dpm0_ns; 912 int sr_enter_plus_exit_time_dpm0_ns; 913 int sr_exit_time_ns; 914 int sr_enter_plus_exit_time_ns; 915 int sr_exit_z8_time_ns; 916 int sr_enter_plus_exit_z8_time_ns; 917 int urgent_latency_ns; 918 uint32_t underflow_assert_delay_us; 919 int percent_of_ideal_drambw; 920 int dram_clock_change_latency_ns; 921 bool optimized_watermark; 922 int always_scale; 923 bool disable_pplib_clock_request; 924 bool disable_clock_gate; 925 bool disable_mem_low_power; 926 bool pstate_enabled; 927 bool disable_dmcu; 928 bool force_abm_enable; 929 bool disable_stereo_support; 930 bool vsr_support; 931 bool performance_trace; 932 bool az_endpoint_mute_only; 933 bool always_use_regamma; 934 bool recovery_enabled; 935 bool avoid_vbios_exec_table; 936 bool scl_reset_length10; 937 bool hdmi20_disable; 938 bool skip_detection_link_training; 939 uint32_t edid_read_retry_times; 940 unsigned int force_odm_combine; //bit vector based on otg inst 941 unsigned int seamless_boot_odm_combine; 942 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 943 int minimum_z8_residency_time; 944 int minimum_z10_residency_time; 945 bool disable_z9_mpc; 946 unsigned int force_fclk_khz; 947 bool enable_tri_buf; 948 bool ips_disallow_entry; 949 bool dmub_offload_enabled; 950 bool dmcub_emulation; 951 bool disable_idle_power_optimizations; 952 unsigned int mall_size_override; 953 unsigned int mall_additional_timer_percent; 954 bool mall_error_as_fatal; 955 bool dmub_command_table; /* for testing only */ 956 struct dc_bw_validation_profile bw_val_profile; 957 bool disable_fec; 958 bool disable_48mhz_pwrdwn; 959 /* This forces a hard min on the DCFCLK requested to SMU/PP 960 * watermarks are not affected. 961 */ 962 unsigned int force_min_dcfclk_mhz; 963 int dwb_fi_phase; 964 bool disable_timing_sync; 965 bool cm_in_bypass; 966 int force_clock_mode;/*every mode change.*/ 967 968 bool disable_dram_clock_change_vactive_support; 969 bool validate_dml_output; 970 bool enable_dmcub_surface_flip; 971 bool usbc_combo_phy_reset_wa; 972 bool enable_dram_clock_change_one_display_vactive; 973 /* TODO - remove once tested */ 974 bool legacy_dp2_lt; 975 bool set_mst_en_for_sst; 976 bool disable_uhbr; 977 bool force_dp2_lt_fallback_method; 978 bool ignore_cable_id; 979 union mem_low_power_enable_options enable_mem_low_power; 980 union root_clock_optimization_options root_clock_optimization; 981 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 982 bool hpo_optimization; 983 bool force_vblank_alignment; 984 985 /* Enable dmub aux for legacy ddc */ 986 bool enable_dmub_aux_for_legacy_ddc; 987 bool disable_fams; 988 enum in_game_fams_config disable_fams_gaming; 989 /* FEC/PSR1 sequence enable delay in 100us */ 990 uint8_t fec_enable_delay_in100us; 991 bool enable_driver_sequence_debug; 992 enum det_size crb_alloc_policy; 993 int crb_alloc_policy_min_disp_count; 994 bool disable_z10; 995 bool enable_z9_disable_interface; 996 bool psr_skip_crtc_disable; 997 uint32_t ips_skip_crtc_disable_mask; 998 union dpia_debug_options dpia_debug; 999 bool disable_fixed_vs_aux_timeout_wa; 1000 uint32_t fixed_vs_aux_delay_config_wa; 1001 bool force_disable_subvp; 1002 bool force_subvp_mclk_switch; 1003 bool allow_sw_cursor_fallback; 1004 unsigned int force_subvp_num_ways; 1005 unsigned int force_mall_ss_num_ways; 1006 bool alloc_extra_way_for_cursor; 1007 uint32_t subvp_extra_lines; 1008 bool force_usr_allow; 1009 /* uses value at boot and disables switch */ 1010 bool disable_dtb_ref_clk_switch; 1011 bool extended_blank_optimization; 1012 union aux_wake_wa_options aux_wake_wa; 1013 uint32_t mst_start_top_delay; 1014 uint8_t psr_power_use_phy_fsm; 1015 enum dml_hostvm_override_opts dml_hostvm_override; 1016 bool dml_disallow_alternate_prefetch_modes; 1017 bool use_legacy_soc_bb_mechanism; 1018 bool exit_idle_opt_for_cursor_updates; 1019 bool using_dml2; 1020 bool enable_single_display_2to1_odm_policy; 1021 bool enable_double_buffered_dsc_pg_support; 1022 bool enable_dp_dig_pixel_rate_div_policy; 1023 bool using_dml21; 1024 enum lttpr_mode lttpr_mode_override; 1025 unsigned int dsc_delay_factor_wa_x1000; 1026 unsigned int min_prefetch_in_strobe_ns; 1027 bool disable_unbounded_requesting; 1028 bool dig_fifo_off_in_blank; 1029 bool override_dispclk_programming; 1030 bool otg_crc_db; 1031 bool disallow_dispclk_dppclk_ds; 1032 bool disable_fpo_optimizations; 1033 bool support_eDP1_5; 1034 uint32_t fpo_vactive_margin_us; 1035 bool disable_fpo_vactive; 1036 bool disable_boot_optimizations; 1037 bool override_odm_optimization; 1038 bool minimize_dispclk_using_odm; 1039 bool disable_subvp_high_refresh; 1040 bool disable_dp_plus_plus_wa; 1041 uint32_t fpo_vactive_min_active_margin_us; 1042 uint32_t fpo_vactive_max_blank_us; 1043 bool enable_hpo_pg_support; 1044 bool enable_legacy_fast_update; 1045 bool disable_dc_mode_overwrite; 1046 bool replay_skip_crtc_disabled; 1047 bool ignore_pg;/*do nothing, let pmfw control it*/ 1048 bool psp_disabled_wa; 1049 unsigned int ips2_eval_delay_us; 1050 unsigned int ips2_entry_delay_us; 1051 bool optimize_ips_handshake; 1052 bool disable_dmub_reallow_idle; 1053 bool disable_timeout; 1054 bool disable_extblankadj; 1055 bool enable_idle_reg_checks; 1056 unsigned int static_screen_wait_frames; 1057 uint32_t pwm_freq; 1058 bool force_chroma_subsampling_1tap; 1059 unsigned int dcc_meta_propagation_delay_us; 1060 bool disable_422_left_edge_pixel; 1061 bool dml21_force_pstate_method; 1062 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1063 uint32_t dml21_disable_pstate_method_mask; 1064 union fw_assisted_mclk_switch_version fams_version; 1065 union dmub_fams2_global_feature_config fams2_config; 1066 unsigned int force_cositing; 1067 unsigned int disable_spl; 1068 unsigned int force_easf; 1069 unsigned int force_sharpness; 1070 unsigned int force_sharpness_level; 1071 unsigned int force_lls; 1072 bool notify_dpia_hr_bw; 1073 bool enable_ips_visual_confirm; 1074 unsigned int sharpen_policy; 1075 unsigned int scale_to_sharpness_policy; 1076 bool skip_full_updated_if_possible; 1077 unsigned int enable_oled_edp_power_up_opt; 1078 bool enable_hblank_borrow; 1079 bool force_subvp_df_throttle; 1080 }; 1081 1082 1083 /* Generic structure that can be used to query properties of DC. More fields 1084 * can be added as required. 1085 */ 1086 struct dc_current_properties { 1087 unsigned int cursor_size_limit; 1088 }; 1089 1090 enum frame_buffer_mode { 1091 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1092 FRAME_BUFFER_MODE_ZFB_ONLY, 1093 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1094 } ; 1095 1096 struct dchub_init_data { 1097 int64_t zfb_phys_addr_base; 1098 int64_t zfb_mc_base_addr; 1099 uint64_t zfb_size_in_byte; 1100 enum frame_buffer_mode fb_mode; 1101 bool dchub_initialzied; 1102 bool dchub_info_valid; 1103 }; 1104 1105 struct dml2_soc_bb; 1106 1107 struct dc_init_data { 1108 struct hw_asic_id asic_id; 1109 void *driver; /* ctx */ 1110 struct cgs_device *cgs_device; 1111 struct dc_bounding_box_overrides bb_overrides; 1112 1113 int num_virtual_links; 1114 /* 1115 * If 'vbios_override' not NULL, it will be called instead 1116 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1117 */ 1118 struct dc_bios *vbios_override; 1119 enum dce_environment dce_environment; 1120 1121 struct dmub_offload_funcs *dmub_if; 1122 struct dc_reg_helper_state *dmub_offload; 1123 1124 struct dc_config flags; 1125 uint64_t log_mask; 1126 1127 struct dpcd_vendor_signature vendor_signature; 1128 bool force_smu_not_present; 1129 /* 1130 * IP offset for run time initializaion of register addresses 1131 * 1132 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1133 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1134 * before them. 1135 */ 1136 uint32_t *dcn_reg_offsets; 1137 uint32_t *nbio_reg_offsets; 1138 uint32_t *clk_reg_offsets; 1139 struct dml2_soc_bb *bb_from_dmub; 1140 }; 1141 1142 struct dc_callback_init { 1143 struct cp_psp cp_psp; 1144 }; 1145 1146 struct dc *dc_create(const struct dc_init_data *init_params); 1147 void dc_hardware_init(struct dc *dc); 1148 1149 int dc_get_vmid_use_vector(struct dc *dc); 1150 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1151 /* Returns the number of vmids supported */ 1152 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1153 void dc_init_callbacks(struct dc *dc, 1154 const struct dc_callback_init *init_params); 1155 void dc_deinit_callbacks(struct dc *dc); 1156 void dc_destroy(struct dc **dc); 1157 1158 /* Surface Interfaces */ 1159 1160 enum { 1161 TRANSFER_FUNC_POINTS = 1025 1162 }; 1163 1164 struct dc_hdr_static_metadata { 1165 /* display chromaticities and white point in units of 0.00001 */ 1166 unsigned int chromaticity_green_x; 1167 unsigned int chromaticity_green_y; 1168 unsigned int chromaticity_blue_x; 1169 unsigned int chromaticity_blue_y; 1170 unsigned int chromaticity_red_x; 1171 unsigned int chromaticity_red_y; 1172 unsigned int chromaticity_white_point_x; 1173 unsigned int chromaticity_white_point_y; 1174 1175 uint32_t min_luminance; 1176 uint32_t max_luminance; 1177 uint32_t maximum_content_light_level; 1178 uint32_t maximum_frame_average_light_level; 1179 }; 1180 1181 enum dc_transfer_func_type { 1182 TF_TYPE_PREDEFINED, 1183 TF_TYPE_DISTRIBUTED_POINTS, 1184 TF_TYPE_BYPASS, 1185 TF_TYPE_HWPWL 1186 }; 1187 1188 struct dc_transfer_func_distributed_points { 1189 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1190 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1191 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1192 1193 uint16_t end_exponent; 1194 uint16_t x_point_at_y1_red; 1195 uint16_t x_point_at_y1_green; 1196 uint16_t x_point_at_y1_blue; 1197 }; 1198 1199 enum dc_transfer_func_predefined { 1200 TRANSFER_FUNCTION_SRGB, 1201 TRANSFER_FUNCTION_BT709, 1202 TRANSFER_FUNCTION_PQ, 1203 TRANSFER_FUNCTION_LINEAR, 1204 TRANSFER_FUNCTION_UNITY, 1205 TRANSFER_FUNCTION_HLG, 1206 TRANSFER_FUNCTION_HLG12, 1207 TRANSFER_FUNCTION_GAMMA22, 1208 TRANSFER_FUNCTION_GAMMA24, 1209 TRANSFER_FUNCTION_GAMMA26 1210 }; 1211 1212 1213 struct dc_transfer_func { 1214 struct kref refcount; 1215 enum dc_transfer_func_type type; 1216 enum dc_transfer_func_predefined tf; 1217 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1218 uint32_t sdr_ref_white_level; 1219 union { 1220 struct pwl_params pwl; 1221 struct dc_transfer_func_distributed_points tf_pts; 1222 }; 1223 }; 1224 1225 1226 union dc_3dlut_state { 1227 struct { 1228 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1229 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1230 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1231 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1232 uint32_t mpc_rmu1_mux:4; 1233 uint32_t mpc_rmu2_mux:4; 1234 uint32_t reserved:15; 1235 } bits; 1236 uint32_t raw; 1237 }; 1238 1239 1240 struct dc_3dlut { 1241 struct kref refcount; 1242 struct tetrahedral_params lut_3d; 1243 struct fixed31_32 hdr_multiplier; 1244 union dc_3dlut_state state; 1245 }; 1246 /* 1247 * This structure is filled in by dc_surface_get_status and contains 1248 * the last requested address and the currently active address so the called 1249 * can determine if there are any outstanding flips 1250 */ 1251 struct dc_plane_status { 1252 struct dc_plane_address requested_address; 1253 struct dc_plane_address current_address; 1254 bool is_flip_pending; 1255 bool is_right_eye; 1256 }; 1257 1258 union surface_update_flags { 1259 1260 struct { 1261 uint32_t addr_update:1; 1262 /* Medium updates */ 1263 uint32_t dcc_change:1; 1264 uint32_t color_space_change:1; 1265 uint32_t horizontal_mirror_change:1; 1266 uint32_t per_pixel_alpha_change:1; 1267 uint32_t global_alpha_change:1; 1268 uint32_t hdr_mult:1; 1269 uint32_t rotation_change:1; 1270 uint32_t swizzle_change:1; 1271 uint32_t scaling_change:1; 1272 uint32_t position_change:1; 1273 uint32_t in_transfer_func_change:1; 1274 uint32_t input_csc_change:1; 1275 uint32_t coeff_reduction_change:1; 1276 uint32_t output_tf_change:1; 1277 uint32_t pixel_format_change:1; 1278 uint32_t plane_size_change:1; 1279 uint32_t gamut_remap_change:1; 1280 1281 /* Full updates */ 1282 uint32_t new_plane:1; 1283 uint32_t bpp_change:1; 1284 uint32_t gamma_change:1; 1285 uint32_t bandwidth_change:1; 1286 uint32_t clock_change:1; 1287 uint32_t stereo_format_change:1; 1288 uint32_t lut_3d:1; 1289 uint32_t tmz_changed:1; 1290 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1291 uint32_t full_update:1; 1292 uint32_t sdr_white_level_nits:1; 1293 } bits; 1294 1295 uint32_t raw; 1296 }; 1297 1298 #define DC_REMOVE_PLANE_POINTERS 1 1299 1300 struct dc_plane_state { 1301 struct dc_plane_address address; 1302 struct dc_plane_flip_time time; 1303 bool triplebuffer_flips; 1304 struct scaling_taps scaling_quality; 1305 struct rect src_rect; 1306 struct rect dst_rect; 1307 struct rect clip_rect; 1308 1309 struct plane_size plane_size; 1310 struct dc_tiling_info tiling_info; 1311 1312 struct dc_plane_dcc_param dcc; 1313 1314 struct dc_gamma gamma_correction; 1315 struct dc_transfer_func in_transfer_func; 1316 struct dc_bias_and_scale bias_and_scale; 1317 struct dc_csc_transform input_csc_color_matrix; 1318 struct fixed31_32 coeff_reduction_factor; 1319 struct fixed31_32 hdr_mult; 1320 struct colorspace_transform gamut_remap_matrix; 1321 1322 // TODO: No longer used, remove 1323 struct dc_hdr_static_metadata hdr_static_ctx; 1324 1325 enum dc_color_space color_space; 1326 1327 struct dc_3dlut lut3d_func; 1328 struct dc_transfer_func in_shaper_func; 1329 struct dc_transfer_func blend_tf; 1330 1331 struct dc_transfer_func *gamcor_tf; 1332 enum surface_pixel_format format; 1333 enum dc_rotation_angle rotation; 1334 enum plane_stereo_format stereo_format; 1335 1336 bool is_tiling_rotated; 1337 bool per_pixel_alpha; 1338 bool pre_multiplied_alpha; 1339 bool global_alpha; 1340 int global_alpha_value; 1341 bool visible; 1342 bool flip_immediate; 1343 bool horizontal_mirror; 1344 int layer_index; 1345 1346 union surface_update_flags update_flags; 1347 bool flip_int_enabled; 1348 bool skip_manual_trigger; 1349 1350 /* private to DC core */ 1351 struct dc_plane_status status; 1352 struct dc_context *ctx; 1353 1354 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1355 bool force_full_update; 1356 1357 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1358 1359 /* private to dc_surface.c */ 1360 enum dc_irq_source irq_source; 1361 struct kref refcount; 1362 struct tg_color visual_confirm_color; 1363 1364 bool is_statically_allocated; 1365 enum chroma_cositing cositing; 1366 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1367 bool mcm_lut1d_enable; 1368 struct dc_cm2_func_luts mcm_luts; 1369 bool lut_bank_a; 1370 enum mpcc_movable_cm_location mcm_location; 1371 struct dc_csc_transform cursor_csc_color_matrix; 1372 bool adaptive_sharpness_en; 1373 int adaptive_sharpness_policy; 1374 int sharpness_level; 1375 enum linear_light_scaling linear_light_scaling; 1376 unsigned int sdr_white_level_nits; 1377 }; 1378 1379 struct dc_plane_info { 1380 struct plane_size plane_size; 1381 struct dc_tiling_info tiling_info; 1382 struct dc_plane_dcc_param dcc; 1383 enum surface_pixel_format format; 1384 enum dc_rotation_angle rotation; 1385 enum plane_stereo_format stereo_format; 1386 enum dc_color_space color_space; 1387 bool horizontal_mirror; 1388 bool visible; 1389 bool per_pixel_alpha; 1390 bool pre_multiplied_alpha; 1391 bool global_alpha; 1392 int global_alpha_value; 1393 bool input_csc_enabled; 1394 int layer_index; 1395 enum chroma_cositing cositing; 1396 }; 1397 1398 #include "dc_stream.h" 1399 1400 struct dc_scratch_space { 1401 /* used to temporarily backup plane states of a stream during 1402 * dc update. The reason is that plane states are overwritten 1403 * with surface updates in dc update. Once they are overwritten 1404 * current state is no longer valid. We want to temporarily 1405 * store current value in plane states so we can still recover 1406 * a valid current state during dc update. 1407 */ 1408 struct dc_plane_state plane_states[MAX_SURFACES]; 1409 1410 struct dc_stream_state stream_state; 1411 }; 1412 1413 struct dc { 1414 struct dc_debug_options debug; 1415 struct dc_versions versions; 1416 struct dc_caps caps; 1417 struct dc_cap_funcs cap_funcs; 1418 struct dc_config config; 1419 struct dc_bounding_box_overrides bb_overrides; 1420 struct dc_bug_wa work_arounds; 1421 struct dc_context *ctx; 1422 struct dc_phy_addr_space_config vm_pa_config; 1423 1424 uint8_t link_count; 1425 struct dc_link *links[MAX_LINKS]; 1426 struct link_service *link_srv; 1427 1428 struct dc_state *current_state; 1429 struct resource_pool *res_pool; 1430 1431 struct clk_mgr *clk_mgr; 1432 1433 /* Display Engine Clock levels */ 1434 struct dm_pp_clock_levels sclk_lvls; 1435 1436 /* Inputs into BW and WM calculations. */ 1437 struct bw_calcs_dceip *bw_dceip; 1438 struct bw_calcs_vbios *bw_vbios; 1439 struct dcn_soc_bounding_box *dcn_soc; 1440 struct dcn_ip_params *dcn_ip; 1441 struct display_mode_lib dml; 1442 1443 /* HW functions */ 1444 struct hw_sequencer_funcs hwss; 1445 struct dce_hwseq *hwseq; 1446 1447 /* Require to optimize clocks and bandwidth for added/removed planes */ 1448 bool optimized_required; 1449 bool wm_optimized_required; 1450 bool idle_optimizations_allowed; 1451 bool enable_c20_dtm_b0; 1452 1453 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1454 1455 /* FBC compressor */ 1456 struct compressor *fbc_compressor; 1457 1458 struct dc_debug_data debug_data; 1459 struct dpcd_vendor_signature vendor_signature; 1460 1461 const char *build_id; 1462 struct vm_helper *vm_helper; 1463 1464 uint32_t *dcn_reg_offsets; 1465 uint32_t *nbio_reg_offsets; 1466 uint32_t *clk_reg_offsets; 1467 1468 /* Scratch memory */ 1469 struct { 1470 struct { 1471 /* 1472 * For matching clock_limits table in driver with table 1473 * from PMFW. 1474 */ 1475 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1476 } update_bw_bounding_box; 1477 struct dc_scratch_space current_state; 1478 struct dc_scratch_space new_state; 1479 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1480 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1481 } scratch; 1482 1483 struct dml2_configuration_options dml2_options; 1484 struct dml2_configuration_options dml2_tmp; 1485 enum dc_acpi_cm_power_state power_state; 1486 1487 }; 1488 1489 struct dc_scaling_info { 1490 struct rect src_rect; 1491 struct rect dst_rect; 1492 struct rect clip_rect; 1493 struct scaling_taps scaling_quality; 1494 }; 1495 1496 struct dc_fast_update { 1497 const struct dc_flip_addrs *flip_addr; 1498 const struct dc_gamma *gamma; 1499 const struct colorspace_transform *gamut_remap_matrix; 1500 const struct dc_csc_transform *input_csc_color_matrix; 1501 const struct fixed31_32 *coeff_reduction_factor; 1502 struct dc_transfer_func *out_transfer_func; 1503 struct dc_csc_transform *output_csc_transform; 1504 const struct dc_csc_transform *cursor_csc_color_matrix; 1505 }; 1506 1507 struct dc_surface_update { 1508 struct dc_plane_state *surface; 1509 1510 /* isr safe update parameters. null means no updates */ 1511 const struct dc_flip_addrs *flip_addr; 1512 const struct dc_plane_info *plane_info; 1513 const struct dc_scaling_info *scaling_info; 1514 struct fixed31_32 hdr_mult; 1515 /* following updates require alloc/sleep/spin that is not isr safe, 1516 * null means no updates 1517 */ 1518 const struct dc_gamma *gamma; 1519 const struct dc_transfer_func *in_transfer_func; 1520 1521 const struct dc_csc_transform *input_csc_color_matrix; 1522 const struct fixed31_32 *coeff_reduction_factor; 1523 const struct dc_transfer_func *func_shaper; 1524 const struct dc_3dlut *lut3d_func; 1525 const struct dc_transfer_func *blend_tf; 1526 const struct colorspace_transform *gamut_remap_matrix; 1527 /* 1528 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1529 * 1530 * change cm2_params.component_settings: Full update 1531 * change cm2_params.cm2_luts: Fast update 1532 */ 1533 const struct dc_cm2_parameters *cm2_params; 1534 const struct dc_csc_transform *cursor_csc_color_matrix; 1535 unsigned int sdr_white_level_nits; 1536 struct dc_bias_and_scale bias_and_scale; 1537 }; 1538 1539 /* 1540 * Create a new surface with default parameters; 1541 */ 1542 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1543 void dc_gamma_release(struct dc_gamma **dc_gamma); 1544 struct dc_gamma *dc_create_gamma(void); 1545 1546 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1547 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1548 struct dc_transfer_func *dc_create_transfer_func(void); 1549 1550 struct dc_3dlut *dc_create_3dlut_func(void); 1551 void dc_3dlut_func_release(struct dc_3dlut *lut); 1552 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1553 1554 void dc_post_update_surfaces_to_stream( 1555 struct dc *dc); 1556 1557 #include "dc_stream.h" 1558 1559 /** 1560 * struct dc_validation_set - Struct to store surface/stream associations for validation 1561 */ 1562 struct dc_validation_set { 1563 /** 1564 * @stream: Stream state properties 1565 */ 1566 struct dc_stream_state *stream; 1567 1568 /** 1569 * @plane_states: Surface state 1570 */ 1571 struct dc_plane_state *plane_states[MAX_SURFACES]; 1572 1573 /** 1574 * @plane_count: Total of active planes 1575 */ 1576 uint8_t plane_count; 1577 }; 1578 1579 bool dc_validate_boot_timing(const struct dc *dc, 1580 const struct dc_sink *sink, 1581 struct dc_crtc_timing *crtc_timing); 1582 1583 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1584 1585 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1586 1587 enum dc_status dc_validate_with_context(struct dc *dc, 1588 const struct dc_validation_set set[], 1589 int set_count, 1590 struct dc_state *context, 1591 bool fast_validate); 1592 1593 bool dc_set_generic_gpio_for_stereo(bool enable, 1594 struct gpio_service *gpio_service); 1595 1596 /* 1597 * fast_validate: we return after determining if we can support the new state, 1598 * but before we populate the programming info 1599 */ 1600 enum dc_status dc_validate_global_state( 1601 struct dc *dc, 1602 struct dc_state *new_ctx, 1603 bool fast_validate); 1604 1605 bool dc_acquire_release_mpc_3dlut( 1606 struct dc *dc, bool acquire, 1607 struct dc_stream_state *stream, 1608 struct dc_3dlut **lut, 1609 struct dc_transfer_func **shaper); 1610 1611 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1612 void get_audio_check(struct audio_info *aud_modes, 1613 struct audio_check *aud_chk); 1614 1615 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1616 void populate_fast_updates(struct dc_fast_update *fast_update, 1617 struct dc_surface_update *srf_updates, 1618 int surface_count, 1619 struct dc_stream_update *stream_update); 1620 /* 1621 * Set up streams and links associated to drive sinks 1622 * The streams parameter is an absolute set of all active streams. 1623 * 1624 * After this call: 1625 * Phy, Encoder, Timing Generator are programmed and enabled. 1626 * New streams are enabled with blank stream; no memory read. 1627 */ 1628 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1629 1630 1631 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1632 struct dc_stream_state *stream, 1633 int mpcc_inst); 1634 1635 1636 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1637 1638 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1639 1640 /* The function returns minimum bandwidth required to drive a given timing 1641 * return - minimum required timing bandwidth in kbps. 1642 */ 1643 uint32_t dc_bandwidth_in_kbps_from_timing( 1644 const struct dc_crtc_timing *timing, 1645 const enum dc_link_encoding_format link_encoding); 1646 1647 /* Link Interfaces */ 1648 /* 1649 * A link contains one or more sinks and their connected status. 1650 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1651 */ 1652 struct dc_link { 1653 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1654 unsigned int sink_count; 1655 struct dc_sink *local_sink; 1656 unsigned int link_index; 1657 enum dc_connection_type type; 1658 enum signal_type connector_signal; 1659 enum dc_irq_source irq_source_hpd; 1660 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1661 1662 bool is_hpd_filter_disabled; 1663 bool dp_ss_off; 1664 1665 /** 1666 * @link_state_valid: 1667 * 1668 * If there is no link and local sink, this variable should be set to 1669 * false. Otherwise, it should be set to true; usually, the function 1670 * core_link_enable_stream sets this field to true. 1671 */ 1672 bool link_state_valid; 1673 bool aux_access_disabled; 1674 bool sync_lt_in_progress; 1675 bool skip_stream_reenable; 1676 bool is_internal_display; 1677 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1678 bool is_dig_mapping_flexible; 1679 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1680 bool is_hpd_pending; /* Indicates a new received hpd */ 1681 1682 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1683 * for every link training. This is incompatible with DP LL compliance automation, 1684 * which expects the same link settings to be used every retry on a link loss. 1685 * This flag is used to skip the fallback when link loss occurs during automation. 1686 */ 1687 bool skip_fallback_on_link_loss; 1688 1689 bool edp_sink_present; 1690 1691 struct dp_trace dp_trace; 1692 1693 /* caps is the same as reported_link_cap. link_traing use 1694 * reported_link_cap. Will clean up. TODO 1695 */ 1696 struct dc_link_settings reported_link_cap; 1697 struct dc_link_settings verified_link_cap; 1698 struct dc_link_settings cur_link_settings; 1699 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1700 struct dc_link_settings preferred_link_setting; 1701 /* preferred_training_settings are override values that 1702 * come from DM. DM is responsible for the memory 1703 * management of the override pointers. 1704 */ 1705 struct dc_link_training_overrides preferred_training_settings; 1706 struct dp_audio_test_data audio_test_data; 1707 1708 uint8_t ddc_hw_inst; 1709 1710 uint8_t hpd_src; 1711 1712 uint8_t link_enc_hw_inst; 1713 /* DIG link encoder ID. Used as index in link encoder resource pool. 1714 * For links with fixed mapping to DIG, this is not changed after dc_link 1715 * object creation. 1716 */ 1717 enum engine_id eng_id; 1718 enum engine_id dpia_preferred_eng_id; 1719 1720 bool test_pattern_enabled; 1721 /* Pending/Current test pattern are only used to perform and track 1722 * FIXED_VS retimer test pattern/lane adjustment override state. 1723 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1724 * to perform specific lane adjust overrides before setting certain 1725 * PHY test patterns. In cases when lane adjust and set test pattern 1726 * calls are not performed atomically (i.e. performing link training), 1727 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1728 * and current_test_pattern will contain required context for any future 1729 * set pattern/set lane adjust to transition between override state(s). 1730 * */ 1731 enum dp_test_pattern current_test_pattern; 1732 enum dp_test_pattern pending_test_pattern; 1733 1734 union compliance_test_state compliance_test_state; 1735 1736 void *priv; 1737 1738 struct ddc_service *ddc; 1739 1740 enum dp_panel_mode panel_mode; 1741 bool aux_mode; 1742 1743 /* Private to DC core */ 1744 1745 const struct dc *dc; 1746 1747 struct dc_context *ctx; 1748 1749 struct panel_cntl *panel_cntl; 1750 struct link_encoder *link_enc; 1751 struct graphics_object_id link_id; 1752 /* Endpoint type distinguishes display endpoints which do not have entries 1753 * in the BIOS connector table from those that do. Helps when tracking link 1754 * encoder to display endpoint assignments. 1755 */ 1756 enum display_endpoint_type ep_type; 1757 union ddi_channel_mapping ddi_channel_mapping; 1758 struct connector_device_tag_info device_tag; 1759 struct dpcd_caps dpcd_caps; 1760 uint32_t dongle_max_pix_clk; 1761 unsigned short chip_caps; 1762 unsigned int dpcd_sink_count; 1763 struct hdcp_caps hdcp_caps; 1764 enum edp_revision edp_revision; 1765 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1766 1767 struct psr_settings psr_settings; 1768 struct replay_settings replay_settings; 1769 1770 /* Drive settings read from integrated info table */ 1771 struct dc_lane_settings bios_forced_drive_settings; 1772 1773 /* Vendor specific LTTPR workaround variables */ 1774 uint8_t vendor_specific_lttpr_link_rate_wa; 1775 bool apply_vendor_specific_lttpr_link_rate_wa; 1776 1777 /* MST record stream using this link */ 1778 struct link_flags { 1779 bool dp_keep_receiver_powered; 1780 bool dp_skip_DID2; 1781 bool dp_skip_reset_segment; 1782 bool dp_skip_fs_144hz; 1783 bool dp_mot_reset_segment; 1784 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1785 bool dpia_mst_dsc_always_on; 1786 /* Forced DPIA into TBT3 compatibility mode. */ 1787 bool dpia_forced_tbt3_mode; 1788 bool dongle_mode_timing_override; 1789 bool blank_stream_on_ocs_change; 1790 bool read_dpcd204h_on_irq_hpd; 1791 } wa_flags; 1792 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1793 1794 struct dc_link_status link_status; 1795 struct dprx_states dprx_states; 1796 1797 struct gpio *hpd_gpio; 1798 enum dc_link_fec_state fec_state; 1799 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1800 1801 struct dc_panel_config panel_config; 1802 struct phy_state phy_state; 1803 // BW ALLOCATON USB4 ONLY 1804 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1805 bool skip_implict_edp_power_control; 1806 enum backlight_control_type backlight_control_type; 1807 }; 1808 1809 /* Return an enumerated dc_link. 1810 * dc_link order is constant and determined at 1811 * boot time. They cannot be created or destroyed. 1812 * Use dc_get_caps() to get number of links. 1813 */ 1814 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1815 1816 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1817 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1818 const struct dc_link *link, 1819 unsigned int *inst_out); 1820 1821 /* Return an array of link pointers to edp links. */ 1822 void dc_get_edp_links(const struct dc *dc, 1823 struct dc_link **edp_links, 1824 int *edp_num); 1825 1826 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1827 bool powerOn); 1828 1829 /* The function initiates detection handshake over the given link. It first 1830 * determines if there are display connections over the link. If so it initiates 1831 * detection protocols supported by the connected receiver device. The function 1832 * contains protocol specific handshake sequences which are sometimes mandatory 1833 * to establish a proper connection between TX and RX. So it is always 1834 * recommended to call this function as the first link operation upon HPD event 1835 * or power up event. Upon completion, the function will update link structure 1836 * in place based on latest RX capabilities. The function may also cause dpms 1837 * to be reset to off for all currently enabled streams to the link. It is DM's 1838 * responsibility to serialize detection and DPMS updates. 1839 * 1840 * @reason - Indicate which event triggers this detection. dc may customize 1841 * detection flow depending on the triggering events. 1842 * return false - if detection is not fully completed. This could happen when 1843 * there is an unrecoverable error during detection or detection is partially 1844 * completed (detection has been delegated to dm mst manager ie. 1845 * link->connection_type == dc_connection_mst_branch when returning false). 1846 * return true - detection is completed, link has been fully updated with latest 1847 * detection result. 1848 */ 1849 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1850 1851 struct dc_sink_init_data; 1852 1853 /* When link connection type is dc_connection_mst_branch, remote sink can be 1854 * added to the link. The interface creates a remote sink and associates it with 1855 * current link. The sink will be retained by link until remove remote sink is 1856 * called. 1857 * 1858 * @dc_link - link the remote sink will be added to. 1859 * @edid - byte array of EDID raw data. 1860 * @len - size of the edid in byte 1861 * @init_data - 1862 */ 1863 struct dc_sink *dc_link_add_remote_sink( 1864 struct dc_link *dc_link, 1865 const uint8_t *edid, 1866 int len, 1867 struct dc_sink_init_data *init_data); 1868 1869 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1870 * @link - link the sink should be removed from 1871 * @sink - sink to be removed. 1872 */ 1873 void dc_link_remove_remote_sink( 1874 struct dc_link *link, 1875 struct dc_sink *sink); 1876 1877 /* Enable HPD interrupt handler for a given link */ 1878 void dc_link_enable_hpd(const struct dc_link *link); 1879 1880 /* Disable HPD interrupt handler for a given link */ 1881 void dc_link_disable_hpd(const struct dc_link *link); 1882 1883 /* determine if there is a sink connected to the link 1884 * 1885 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1886 * return - false if an unexpected error occurs, true otherwise. 1887 * 1888 * NOTE: This function doesn't detect downstream sink connections i.e 1889 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1890 * return dc_connection_single if the branch device is connected despite of 1891 * downstream sink's connection status. 1892 */ 1893 bool dc_link_detect_connection_type(struct dc_link *link, 1894 enum dc_connection_type *type); 1895 1896 /* query current hpd pin value 1897 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1898 * 1899 */ 1900 bool dc_link_get_hpd_state(struct dc_link *link); 1901 1902 /* Getter for cached link status from given link */ 1903 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1904 1905 /* enable/disable hardware HPD filter. 1906 * 1907 * @link - The link the HPD pin is associated with. 1908 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1909 * handler once after no HPD change has been detected within dc default HPD 1910 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1911 * pulses within default HPD interval, no HPD event will be received until HPD 1912 * toggles have stopped. Then HPD event will be queued to irq handler once after 1913 * dc default HPD filtering interval since last HPD event. 1914 * 1915 * @enable = false - disable hardware HPD filter. HPD event will be queued 1916 * immediately to irq handler after no HPD change has been detected within 1917 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1918 */ 1919 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1920 1921 /* submit i2c read/write payloads through ddc channel 1922 * @link_index - index to a link with ddc in i2c mode 1923 * @cmd - i2c command structure 1924 * return - true if success, false otherwise. 1925 */ 1926 bool dc_submit_i2c( 1927 struct dc *dc, 1928 uint32_t link_index, 1929 struct i2c_command *cmd); 1930 1931 /* submit i2c read/write payloads through oem channel 1932 * @link_index - index to a link with ddc in i2c mode 1933 * @cmd - i2c command structure 1934 * return - true if success, false otherwise. 1935 */ 1936 bool dc_submit_i2c_oem( 1937 struct dc *dc, 1938 struct i2c_command *cmd); 1939 1940 enum aux_return_code_type; 1941 /* Attempt to transfer the given aux payload. This function does not perform 1942 * retries or handle error states. The reply is returned in the payload->reply 1943 * and the result through operation_result. Returns the number of bytes 1944 * transferred,or -1 on a failure. 1945 */ 1946 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1947 struct aux_payload *payload, 1948 enum aux_return_code_type *operation_result); 1949 1950 bool dc_is_oem_i2c_device_present( 1951 struct dc *dc, 1952 size_t slave_address 1953 ); 1954 1955 /* return true if the connected receiver supports the hdcp version */ 1956 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1957 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1958 1959 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1960 * 1961 * TODO - When defer_handling is true the function will have a different purpose. 1962 * It no longer does complete hpd rx irq handling. We should create a separate 1963 * interface specifically for this case. 1964 * 1965 * Return: 1966 * true - Downstream port status changed. DM should call DC to do the 1967 * detection. 1968 * false - no change in Downstream port status. No further action required 1969 * from DM. 1970 */ 1971 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1972 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1973 bool defer_handling, bool *has_left_work); 1974 /* handle DP specs define test automation sequence*/ 1975 void dc_link_dp_handle_automated_test(struct dc_link *link); 1976 1977 /* handle DP Link loss sequence and try to recover RX link loss with best 1978 * effort 1979 */ 1980 void dc_link_dp_handle_link_loss(struct dc_link *link); 1981 1982 /* Determine if hpd rx irq should be handled or ignored 1983 * return true - hpd rx irq should be handled. 1984 * return false - it is safe to ignore hpd rx irq event 1985 */ 1986 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1987 1988 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1989 * @link - link the hpd irq data associated with 1990 * @hpd_irq_dpcd_data - input hpd irq data 1991 * return - true if hpd irq data indicates a link lost 1992 */ 1993 bool dc_link_check_link_loss_status(struct dc_link *link, 1994 union hpd_irq_data *hpd_irq_dpcd_data); 1995 1996 /* Read hpd rx irq data from a given link 1997 * @link - link where the hpd irq data should be read from 1998 * @irq_data - output hpd irq data 1999 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2000 * read has failed. 2001 */ 2002 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2003 struct dc_link *link, 2004 union hpd_irq_data *irq_data); 2005 2006 /* The function clears recorded DP RX states in the link. DM should call this 2007 * function when it is resuming from S3 power state to previously connected links. 2008 * 2009 * TODO - in the future we should consider to expand link resume interface to 2010 * support clearing previous rx states. So we don't have to rely on dm to call 2011 * this interface explicitly. 2012 */ 2013 void dc_link_clear_dprx_states(struct dc_link *link); 2014 2015 /* Destruct the mst topology of the link and reset the allocated payload table 2016 * 2017 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2018 * still wants to reset MST topology on an unplug event */ 2019 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2020 2021 /* The function calculates effective DP link bandwidth when a given link is 2022 * using the given link settings. 2023 * 2024 * return - total effective link bandwidth in kbps. 2025 */ 2026 uint32_t dc_link_bandwidth_kbps( 2027 const struct dc_link *link, 2028 const struct dc_link_settings *link_setting); 2029 2030 struct dp_audio_bandwidth_params { 2031 const struct dc_crtc_timing *crtc_timing; 2032 enum dp_link_encoding link_encoding; 2033 uint32_t channel_count; 2034 uint32_t sample_rate_hz; 2035 }; 2036 2037 /* The function calculates the minimum size of hblank (in bytes) needed to 2038 * support the specified channel count and sample rate combination, given the 2039 * link encoding and timing to be used. This calculation is not supported 2040 * for 8b/10b SST. 2041 * 2042 * return - min hblank size in bytes, 0 if 8b/10b SST. 2043 */ 2044 uint32_t dc_link_required_hblank_size_bytes( 2045 const struct dc_link *link, 2046 struct dp_audio_bandwidth_params *audio_params); 2047 2048 /* The function takes a snapshot of current link resource allocation state 2049 * @dc: pointer to dc of the dm calling this 2050 * @map: a dc link resource snapshot defined internally to dc. 2051 * 2052 * DM needs to capture a snapshot of current link resource allocation mapping 2053 * and store it in its persistent storage. 2054 * 2055 * Some of the link resource is using first come first serve policy. 2056 * The allocation mapping depends on original hotplug order. This information 2057 * is lost after driver is loaded next time. The snapshot is used in order to 2058 * restore link resource to its previous state so user will get consistent 2059 * link capability allocation across reboot. 2060 * 2061 */ 2062 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2063 2064 /* This function restores link resource allocation state from a snapshot 2065 * @dc: pointer to dc of the dm calling this 2066 * @map: a dc link resource snapshot defined internally to dc. 2067 * 2068 * DM needs to call this function after initial link detection on boot and 2069 * before first commit streams to restore link resource allocation state 2070 * from previous boot session. 2071 * 2072 * Some of the link resource is using first come first serve policy. 2073 * The allocation mapping depends on original hotplug order. This information 2074 * is lost after driver is loaded next time. The snapshot is used in order to 2075 * restore link resource to its previous state so user will get consistent 2076 * link capability allocation across reboot. 2077 * 2078 */ 2079 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2080 2081 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2082 * interface i.e stream_update->dsc_config 2083 */ 2084 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2085 2086 /* translate a raw link rate data to bandwidth in kbps */ 2087 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2088 2089 /* determine the optimal bandwidth given link and required bw. 2090 * @link - current detected link 2091 * @req_bw - requested bandwidth in kbps 2092 * @link_settings - returned most optimal link settings that can fit the 2093 * requested bandwidth 2094 * return - false if link can't support requested bandwidth, true if link 2095 * settings is found. 2096 */ 2097 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2098 struct dc_link_settings *link_settings, 2099 uint32_t req_bw); 2100 2101 /* return the max dp link settings can be driven by the link without considering 2102 * connected RX device and its capability 2103 */ 2104 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2105 struct dc_link_settings *max_link_enc_cap); 2106 2107 /* determine when the link is driving MST mode, what DP link channel coding 2108 * format will be used. The decision will remain unchanged until next HPD event. 2109 * 2110 * @link - a link with DP RX connection 2111 * return - if stream is committed to this link with MST signal type, type of 2112 * channel coding format dc will choose. 2113 */ 2114 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2115 const struct dc_link *link); 2116 2117 /* get max dp link settings the link can enable with all things considered. (i.e 2118 * TX/RX/Cable capabilities and dp override policies. 2119 * 2120 * @link - a link with DP RX connection 2121 * return - max dp link settings the link can enable. 2122 * 2123 */ 2124 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2125 2126 /* Get the highest encoding format that the link supports; highest meaning the 2127 * encoding format which supports the maximum bandwidth. 2128 * 2129 * @link - a link with DP RX connection 2130 * return - highest encoding format link supports. 2131 */ 2132 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2133 2134 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2135 * to a link with dp connector signal type. 2136 * @link - a link with dp connector signal type 2137 * return - true if connected, false otherwise 2138 */ 2139 bool dc_link_is_dp_sink_present(struct dc_link *link); 2140 2141 /* Force DP lane settings update to main-link video signal and notify the change 2142 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2143 * tuning purpose. The interface assumes link has already been enabled with DP 2144 * signal. 2145 * 2146 * @lt_settings - a container structure with desired hw_lane_settings 2147 */ 2148 void dc_link_set_drive_settings(struct dc *dc, 2149 struct link_training_settings *lt_settings, 2150 struct dc_link *link); 2151 2152 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2153 * test or debugging purpose. The test pattern will remain until next un-plug. 2154 * 2155 * @link - active link with DP signal output enabled. 2156 * @test_pattern - desired test pattern to output. 2157 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2158 * @test_pattern_color_space - for video test pattern choose a desired color 2159 * space. 2160 * @p_link_settings - For PHY pattern choose a desired link settings 2161 * @p_custom_pattern - some test pattern will require a custom input to 2162 * customize some pattern details. Otherwise keep it to NULL. 2163 * @cust_pattern_size - size of the custom pattern input. 2164 * 2165 */ 2166 bool dc_link_dp_set_test_pattern( 2167 struct dc_link *link, 2168 enum dp_test_pattern test_pattern, 2169 enum dp_test_pattern_color_space test_pattern_color_space, 2170 const struct link_training_settings *p_link_settings, 2171 const unsigned char *p_custom_pattern, 2172 unsigned int cust_pattern_size); 2173 2174 /* Force DP link settings to always use a specific value until reboot to a 2175 * specific link. If link has already been enabled, the interface will also 2176 * switch to desired link settings immediately. This is a debug interface to 2177 * generic dp issue trouble shooting. 2178 */ 2179 void dc_link_set_preferred_link_settings(struct dc *dc, 2180 struct dc_link_settings *link_setting, 2181 struct dc_link *link); 2182 2183 /* Force DP link to customize a specific link training behavior by overriding to 2184 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2185 * display specific link training issues or apply some display specific 2186 * workaround in link training. 2187 * 2188 * @link_settings - if not NULL, force preferred link settings to the link. 2189 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2190 * will apply this particular override in future link training. If NULL is 2191 * passed in, dc resets previous overrides. 2192 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2193 * training settings. 2194 */ 2195 void dc_link_set_preferred_training_settings(struct dc *dc, 2196 struct dc_link_settings *link_setting, 2197 struct dc_link_training_overrides *lt_overrides, 2198 struct dc_link *link, 2199 bool skip_immediate_retrain); 2200 2201 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2202 bool dc_link_is_fec_supported(const struct dc_link *link); 2203 2204 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2205 * link enablement. 2206 * return - true if FEC should be enabled, false otherwise. 2207 */ 2208 bool dc_link_should_enable_fec(const struct dc_link *link); 2209 2210 /* determine lttpr mode the current link should be enabled with a specific link 2211 * settings. 2212 */ 2213 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2214 struct dc_link_settings *link_setting); 2215 2216 /* Force DP RX to update its power state. 2217 * NOTE: this interface doesn't update dp main-link. Calling this function will 2218 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2219 * RX power state back upon finish DM specific execution requiring DP RX in a 2220 * specific power state. 2221 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2222 * state. 2223 */ 2224 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2225 2226 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2227 * current value read from extended receiver cap from 02200h - 0220Fh. 2228 * Some DP RX has problems of providing accurate DP receiver caps from extended 2229 * field, this interface is a workaround to revert link back to use base caps. 2230 */ 2231 void dc_link_overwrite_extended_receiver_cap( 2232 struct dc_link *link); 2233 2234 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2235 bool wait_for_hpd); 2236 2237 /* Set backlight level of an embedded panel (eDP, LVDS). 2238 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2239 * and 16 bit fractional, where 1.0 is max backlight value. 2240 */ 2241 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2242 struct set_backlight_level_params *backlight_level_params); 2243 2244 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2245 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2246 bool isHDR, 2247 uint32_t backlight_millinits, 2248 uint32_t transition_time_in_ms); 2249 2250 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2251 uint32_t *backlight_millinits, 2252 uint32_t *backlight_millinits_peak); 2253 2254 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2255 2256 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2257 2258 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2259 bool wait, bool force_static, const unsigned int *power_opts); 2260 2261 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2262 2263 bool dc_link_setup_psr(struct dc_link *dc_link, 2264 const struct dc_stream_state *stream, struct psr_config *psr_config, 2265 struct psr_context *psr_context); 2266 2267 /* 2268 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2269 * 2270 * @link: pointer to the dc_link struct instance 2271 * @enable: enable(active) or disable(inactive) replay 2272 * @wait: state transition need to wait the active set completed. 2273 * @force_static: force disable(inactive) the replay 2274 * @power_opts: set power optimazation parameters to DMUB. 2275 * 2276 * return: allow Replay active will return true, else will return false. 2277 */ 2278 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2279 bool wait, bool force_static, const unsigned int *power_opts); 2280 2281 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2282 2283 /* On eDP links this function call will stall until T12 has elapsed. 2284 * If the panel is not in power off state, this function will return 2285 * immediately. 2286 */ 2287 bool dc_link_wait_for_t12(struct dc_link *link); 2288 2289 /* Determine if dp trace has been initialized to reflect upto date result * 2290 * return - true if trace is initialized and has valid data. False dp trace 2291 * doesn't have valid result. 2292 */ 2293 bool dc_dp_trace_is_initialized(struct dc_link *link); 2294 2295 /* Query a dp trace flag to indicate if the current dp trace data has been 2296 * logged before 2297 */ 2298 bool dc_dp_trace_is_logged(struct dc_link *link, 2299 bool in_detection); 2300 2301 /* Set dp trace flag to indicate whether DM has already logged the current dp 2302 * trace data. DM can set is_logged to true upon logging and check 2303 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2304 */ 2305 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2306 bool in_detection, 2307 bool is_logged); 2308 2309 /* Obtain driver time stamp for last dp link training end. The time stamp is 2310 * formatted based on dm_get_timestamp DM function. 2311 * @in_detection - true to get link training end time stamp of last link 2312 * training in detection sequence. false to get link training end time stamp 2313 * of last link training in commit (dpms) sequence 2314 */ 2315 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2316 bool in_detection); 2317 2318 /* Get how many link training attempts dc has done with latest sequence. 2319 * @in_detection - true to get link training count of last link 2320 * training in detection sequence. false to get link training count of last link 2321 * training in commit (dpms) sequence 2322 */ 2323 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2324 bool in_detection); 2325 2326 /* Get how many link loss has happened since last link training attempts */ 2327 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2328 2329 /* 2330 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2331 */ 2332 /* 2333 * Send a request from DP-Tx requesting to allocate BW remotely after 2334 * allocating it locally. This will get processed by CM and a CB function 2335 * will be called. 2336 * 2337 * @link: pointer to the dc_link struct instance 2338 * @req_bw: The requested bw in Kbyte to allocated 2339 * 2340 * return: none 2341 */ 2342 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2343 2344 /* 2345 * Handle function for when the status of the Request above is complete. 2346 * We will find out the result of allocating on CM and update structs. 2347 * 2348 * @link: pointer to the dc_link struct instance 2349 * @bw: Allocated or Estimated BW depending on the result 2350 * @result: Response type 2351 * 2352 * return: none 2353 */ 2354 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2355 uint8_t bw, uint8_t result); 2356 2357 /* 2358 * Handle the USB4 BW Allocation related functionality here: 2359 * Plug => Try to allocate max bw from timing parameters supported by the sink 2360 * Unplug => de-allocate bw 2361 * 2362 * @link: pointer to the dc_link struct instance 2363 * @peak_bw: Peak bw used by the link/sink 2364 * 2365 * return: allocated bw else return 0 2366 */ 2367 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2368 struct dc_link *link, int peak_bw); 2369 2370 /* 2371 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2372 * available BW for each host router 2373 * 2374 * @dc: pointer to dc struct 2375 * @stream: pointer to all possible streams 2376 * @count: number of valid DPIA streams 2377 * 2378 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2379 */ 2380 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2381 const unsigned int count); 2382 2383 /* Sink Interfaces - A sink corresponds to a display output device */ 2384 2385 struct dc_container_id { 2386 // 128bit GUID in binary form 2387 unsigned char guid[16]; 2388 // 8 byte port ID -> ELD.PortID 2389 unsigned int portId[2]; 2390 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2391 unsigned short manufacturerName; 2392 // 2 byte product code -> ELD.ProductCode 2393 unsigned short productCode; 2394 }; 2395 2396 2397 struct dc_sink_dsc_caps { 2398 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2399 // 'false' if they are sink's DSC caps 2400 bool is_virtual_dpcd_dsc; 2401 // 'true' if MST topology supports DSC passthrough for sink 2402 // 'false' if MST topology does not support DSC passthrough 2403 bool is_dsc_passthrough_supported; 2404 struct dsc_dec_dpcd_caps dsc_dec_caps; 2405 }; 2406 2407 struct dc_sink_hblank_expansion_caps { 2408 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2409 // 'false' if they are sink's HBlank expansion caps 2410 bool is_virtual_dpcd_hblank_expansion; 2411 struct hblank_expansion_dpcd_caps dpcd_caps; 2412 }; 2413 2414 struct dc_sink_fec_caps { 2415 bool is_rx_fec_supported; 2416 bool is_topology_fec_supported; 2417 }; 2418 2419 struct scdc_caps { 2420 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2421 union hdmi_scdc_device_id_data device_id; 2422 }; 2423 2424 /* 2425 * The sink structure contains EDID and other display device properties 2426 */ 2427 struct dc_sink { 2428 enum signal_type sink_signal; 2429 struct dc_edid dc_edid; /* raw edid */ 2430 struct dc_edid_caps edid_caps; /* parse display caps */ 2431 struct dc_container_id *dc_container_id; 2432 uint32_t dongle_max_pix_clk; 2433 void *priv; 2434 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2435 bool converter_disable_audio; 2436 2437 struct scdc_caps scdc_caps; 2438 struct dc_sink_dsc_caps dsc_caps; 2439 struct dc_sink_fec_caps fec_caps; 2440 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2441 2442 bool is_vsc_sdp_colorimetry_supported; 2443 2444 /* private to DC core */ 2445 struct dc_link *link; 2446 struct dc_context *ctx; 2447 2448 uint32_t sink_id; 2449 2450 /* private to dc_sink.c */ 2451 // refcount must be the last member in dc_sink, since we want the 2452 // sink structure to be logically cloneable up to (but not including) 2453 // refcount 2454 struct kref refcount; 2455 }; 2456 2457 void dc_sink_retain(struct dc_sink *sink); 2458 void dc_sink_release(struct dc_sink *sink); 2459 2460 struct dc_sink_init_data { 2461 enum signal_type sink_signal; 2462 struct dc_link *link; 2463 uint32_t dongle_max_pix_clk; 2464 bool converter_disable_audio; 2465 }; 2466 2467 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2468 2469 /* Newer interfaces */ 2470 struct dc_cursor { 2471 struct dc_plane_address address; 2472 struct dc_cursor_attributes attributes; 2473 }; 2474 2475 2476 /* Interrupt interfaces */ 2477 enum dc_irq_source dc_interrupt_to_irq_source( 2478 struct dc *dc, 2479 uint32_t src_id, 2480 uint32_t ext_id); 2481 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2482 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2483 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2484 struct dc *dc, uint32_t link_index); 2485 2486 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2487 2488 /* Power Interfaces */ 2489 2490 void dc_set_power_state( 2491 struct dc *dc, 2492 enum dc_acpi_cm_power_state power_state); 2493 void dc_resume(struct dc *dc); 2494 2495 void dc_power_down_on_boot(struct dc *dc); 2496 2497 /* 2498 * HDCP Interfaces 2499 */ 2500 enum hdcp_message_status dc_process_hdcp_msg( 2501 enum signal_type signal, 2502 struct dc_link *link, 2503 struct hdcp_protection_message *message_info); 2504 bool dc_is_dmcu_initialized(struct dc *dc); 2505 2506 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2507 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2508 2509 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2510 unsigned int pitch, 2511 unsigned int height, 2512 enum surface_pixel_format format, 2513 struct dc_cursor_attributes *cursor_attr); 2514 2515 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2516 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2517 2518 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2519 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2520 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2521 2522 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2523 void dc_unlock_memory_clock_frequency(struct dc *dc); 2524 2525 /* set min memory clock to the min required for current mode, max to maxDPM */ 2526 void dc_lock_memory_clock_frequency(struct dc *dc); 2527 2528 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2529 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2530 2531 /* cleanup on driver unload */ 2532 void dc_hardware_release(struct dc *dc); 2533 2534 /* disables fw based mclk switch */ 2535 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2536 2537 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2538 2539 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2540 2541 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2542 2543 void dc_z10_restore(const struct dc *dc); 2544 void dc_z10_save_init(struct dc *dc); 2545 2546 bool dc_is_dmub_outbox_supported(struct dc *dc); 2547 bool dc_enable_dmub_notifications(struct dc *dc); 2548 2549 bool dc_abm_save_restore( 2550 struct dc *dc, 2551 struct dc_stream_state *stream, 2552 struct abm_save_restore *pData); 2553 2554 void dc_enable_dmub_outbox(struct dc *dc); 2555 2556 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2557 uint32_t link_index, 2558 struct aux_payload *payload); 2559 2560 /* Get dc link index from dpia port index */ 2561 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2562 uint8_t dpia_port_index); 2563 2564 bool dc_process_dmub_set_config_async(struct dc *dc, 2565 uint32_t link_index, 2566 struct set_config_cmd_payload *payload, 2567 struct dmub_notification *notify); 2568 2569 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2570 uint32_t link_index, 2571 uint8_t mst_alloc_slots, 2572 uint8_t *mst_slots_in_use); 2573 2574 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2575 2576 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2577 uint32_t hpd_int_enable); 2578 2579 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2580 2581 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2582 2583 struct dc_power_profile { 2584 int power_level; /* Lower is better */ 2585 }; 2586 2587 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2588 2589 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2590 2591 /* DSC Interfaces */ 2592 #include "dc_dsc.h" 2593 2594 /* Disable acc mode Interfaces */ 2595 void dc_disable_accelerated_mode(struct dc *dc); 2596 2597 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2598 struct dc_stream_state *new_stream); 2599 2600 #endif /* DC_INTERFACE_H_ */ 2601