1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 */ 6 7 #ifndef __DW_HDMI_QP__ 8 #define __DW_HDMI_QP__ 9 10 struct device; 11 struct drm_encoder; 12 struct dw_hdmi_qp; 13 struct platform_device; 14 15 struct dw_hdmi_qp_phy_ops { 16 int (*init)(struct dw_hdmi_qp *hdmi, void *data); 17 void (*disable)(struct dw_hdmi_qp *hdmi, void *data); 18 enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, void *data); 19 void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data); 20 }; 21 22 struct dw_hdmi_qp_plat_data { 23 const struct dw_hdmi_qp_phy_ops *phy_ops; 24 void *phy_data; 25 int main_irq; 26 int cec_irq; 27 unsigned long ref_clk_rate; 28 /* Supported output formats: bitmask of @hdmi_colorspace */ 29 unsigned int supported_formats; 30 /* Maximum bits per color channel: 8, 10 or 12 */ 31 unsigned int max_bpc; 32 }; 33 34 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, 35 struct drm_encoder *encoder, 36 const struct dw_hdmi_qp_plat_data *plat_data); 37 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi); 38 #endif /* __DW_HDMI_QP__ */ 39