1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/dmaengine.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/dma/qcom-gpi-dma.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/log2.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_opp.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/property.h> 16 #include <linux/soc/qcom/geni-se.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spinlock.h> 19 20 /* SPI SE specific registers and respective register fields */ 21 #define SE_SPI_CPHA 0x224 22 #define CPHA BIT(0) 23 24 #define SE_SPI_LOOPBACK 0x22c 25 #define LOOPBACK_ENABLE 0x1 26 #define NORMAL_MODE 0x0 27 #define LOOPBACK_MSK GENMASK(1, 0) 28 29 #define SE_SPI_CPOL 0x230 30 #define CPOL BIT(2) 31 32 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 33 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 34 35 #define SE_SPI_DEMUX_SEL 0x250 36 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 37 38 #define SE_SPI_TRANS_CFG 0x25c 39 #define CS_TOGGLE BIT(1) 40 41 #define SE_SPI_WORD_LEN 0x268 42 #define WORD_LEN_MSK GENMASK(9, 0) 43 #define MIN_WORD_LEN 4 44 45 #define SE_SPI_TX_TRANS_LEN 0x26c 46 #define SE_SPI_RX_TRANS_LEN 0x270 47 #define TRANS_LEN_MSK GENMASK(23, 0) 48 49 #define SE_SPI_PRE_POST_CMD_DLY 0x274 50 51 #define SE_SPI_DELAY_COUNTERS 0x278 52 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 53 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 54 #define SPI_CS_CLK_DELAY_SHFT 10 55 56 #define SE_SPI_SLAVE_EN (0x2BC) 57 #define SPI_SLAVE_EN BIT(0) 58 59 /* M_CMD OP codes for SPI */ 60 #define SPI_TX_ONLY 1 61 #define SPI_RX_ONLY 2 62 #define SPI_TX_RX 7 63 #define SPI_CS_ASSERT 8 64 #define SPI_CS_DEASSERT 9 65 #define SPI_SCK_ONLY 10 66 /* M_CMD params for SPI */ 67 #define SPI_PRE_CMD_DELAY BIT(0) 68 #define TIMESTAMP_BEFORE BIT(1) 69 #define FRAGMENTATION BIT(2) 70 #define TIMESTAMP_AFTER BIT(3) 71 #define POST_CMD_DELAY BIT(4) 72 73 #define GSI_LOOPBACK_EN BIT(0) 74 #define GSI_CS_TOGGLE BIT(3) 75 #define GSI_CPHA BIT(4) 76 #define GSI_CPOL BIT(5) 77 78 struct spi_geni_master { 79 struct geni_se se; 80 struct device *dev; 81 u32 tx_fifo_depth; 82 u32 fifo_width_bits; 83 u32 tx_wm; 84 u32 last_mode; 85 u8 last_cs; 86 unsigned long cur_speed_hz; 87 unsigned long cur_sclk_hz; 88 unsigned int cur_bits_per_word; 89 unsigned int tx_rem_bytes; 90 unsigned int rx_rem_bytes; 91 const struct spi_transfer *cur_xfer; 92 struct completion cs_done; 93 struct completion cancel_done; 94 struct completion abort_done; 95 struct completion tx_reset_done; 96 struct completion rx_reset_done; 97 unsigned int oversampling; 98 spinlock_t lock; 99 int irq; 100 bool cs_flag; 101 bool abort_failed; 102 struct dma_chan *tx; 103 struct dma_chan *rx; 104 int cur_xfer_mode; 105 }; 106 107 static void spi_slv_setup(struct spi_geni_master *mas) 108 { 109 struct geni_se *se = &mas->se; 110 111 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); 112 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); 113 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); 114 dev_dbg(mas->dev, "spi slave setup done\n"); 115 } 116 117 static int get_spi_clk_cfg(unsigned int speed_hz, 118 struct spi_geni_master *mas, 119 unsigned int *clk_idx, 120 unsigned int *clk_div) 121 { 122 unsigned long sclk_freq; 123 unsigned int actual_hz; 124 int ret; 125 126 ret = geni_se_clk_freq_match(&mas->se, 127 speed_hz * mas->oversampling, 128 clk_idx, &sclk_freq, false); 129 if (ret) { 130 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 131 ret, speed_hz); 132 return ret; 133 } 134 135 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 136 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 137 138 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 139 actual_hz, sclk_freq, *clk_idx, *clk_div); 140 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 141 if (ret) 142 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 143 else 144 mas->cur_sclk_hz = sclk_freq; 145 146 return ret; 147 } 148 149 static void handle_se_timeout(struct spi_controller *spi) 150 { 151 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 152 unsigned long time_left; 153 struct geni_se *se = &mas->se; 154 const struct spi_transfer *xfer; 155 156 spin_lock_irq(&mas->lock); 157 if (mas->cur_xfer_mode == GENI_SE_FIFO) 158 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 159 160 xfer = mas->cur_xfer; 161 mas->cur_xfer = NULL; 162 163 /* The controller doesn't support the Cancel commnand in target mode */ 164 if (!spi->target) { 165 reinit_completion(&mas->cancel_done); 166 geni_se_cancel_m_cmd(se); 167 168 spin_unlock_irq(&mas->lock); 169 170 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 171 if (time_left) 172 goto reset_if_dma; 173 174 spin_lock_irq(&mas->lock); 175 } 176 177 reinit_completion(&mas->abort_done); 178 geni_se_abort_m_cmd(se); 179 spin_unlock_irq(&mas->lock); 180 181 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 182 if (!time_left) { 183 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 184 185 /* 186 * No need for a lock since SPI core has a lock and we never 187 * access this from an interrupt. 188 */ 189 mas->abort_failed = true; 190 } 191 192 reset_if_dma: 193 if (mas->cur_xfer_mode == GENI_SE_DMA) { 194 if (xfer) { 195 if (xfer->tx_buf) { 196 spin_lock_irq(&mas->lock); 197 reinit_completion(&mas->tx_reset_done); 198 writel(1, se->base + SE_DMA_TX_FSM_RST); 199 spin_unlock_irq(&mas->lock); 200 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); 201 if (!time_left) 202 dev_err(mas->dev, "DMA TX RESET failed\n"); 203 } 204 if (xfer->rx_buf) { 205 spin_lock_irq(&mas->lock); 206 reinit_completion(&mas->rx_reset_done); 207 writel(1, se->base + SE_DMA_RX_FSM_RST); 208 spin_unlock_irq(&mas->lock); 209 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); 210 if (!time_left) 211 dev_err(mas->dev, "DMA RX RESET failed\n"); 212 } 213 } else { 214 /* 215 * This can happen if a timeout happened and we had to wait 216 * for lock in this function because isr was holding the lock 217 * and handling transfer completion at that time. 218 */ 219 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); 220 } 221 } 222 } 223 224 static void handle_gpi_timeout(struct spi_controller *spi) 225 { 226 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 227 228 dmaengine_terminate_sync(mas->tx); 229 dmaengine_terminate_sync(mas->rx); 230 } 231 232 static void spi_geni_handle_err(struct spi_controller *spi, struct spi_message *msg) 233 { 234 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 235 236 switch (mas->cur_xfer_mode) { 237 case GENI_SE_FIFO: 238 case GENI_SE_DMA: 239 handle_se_timeout(spi); 240 break; 241 case GENI_GPI_DMA: 242 handle_gpi_timeout(spi); 243 break; 244 default: 245 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); 246 } 247 } 248 249 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 250 { 251 struct geni_se *se = &mas->se; 252 u32 m_irq, m_irq_en; 253 254 if (!mas->abort_failed) 255 return false; 256 257 /* 258 * The only known case where a transfer times out and then a cancel 259 * times out then an abort times out is if something is blocking our 260 * interrupt handler from running. Avoid starting any new transfers 261 * until that sorts itself out. 262 */ 263 spin_lock_irq(&mas->lock); 264 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 265 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 266 spin_unlock_irq(&mas->lock); 267 268 if (m_irq & m_irq_en) { 269 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 270 m_irq & m_irq_en); 271 return true; 272 } 273 274 /* 275 * If we're here the problem resolved itself so no need to check more 276 * on future transfers. 277 */ 278 mas->abort_failed = false; 279 280 return false; 281 } 282 283 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 284 unsigned int bits_per_word) 285 { 286 unsigned int pack_words; 287 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 288 struct geni_se *se = &mas->se; 289 u32 word_len; 290 291 /* 292 * If bits_per_word isn't a byte aligned value, set the packing to be 293 * 1 SPI word per FIFO word. 294 */ 295 if (!(mas->fifo_width_bits % bits_per_word)) 296 pack_words = mas->fifo_width_bits / bits_per_word; 297 else 298 pack_words = 1; 299 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 300 true, true); 301 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 302 writel(word_len, se->base + SE_SPI_WORD_LEN); 303 } 304 305 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 306 unsigned long clk_hz) 307 { 308 u32 clk_sel, m_clk_cfg, idx, div; 309 struct geni_se *se = &mas->se; 310 int ret; 311 312 if (clk_hz == mas->cur_speed_hz) 313 return 0; 314 315 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 316 if (ret) { 317 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 318 return ret; 319 } 320 321 /* 322 * SPI core clock gets configured with the requested frequency 323 * or the frequency closer to the requested frequency. 324 * For that reason requested frequency is stored in the 325 * cur_speed_hz and referred in the consecutive transfer instead 326 * of calling clk_get_rate() API. 327 */ 328 mas->cur_speed_hz = clk_hz; 329 330 clk_sel = idx & CLK_SEL_MSK; 331 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 332 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 333 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 334 335 /* Set BW quota for CPU as driver supports FIFO mode only. */ 336 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 337 ret = geni_icc_set_bw(se); 338 if (ret) 339 return ret; 340 341 return 0; 342 } 343 344 static int setup_fifo_params(struct spi_device *spi_slv, 345 struct spi_controller *spi) 346 { 347 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 348 struct geni_se *se = &mas->se; 349 u8 chipselect = spi_get_chipselect(spi_slv, 0); 350 bool cs_changed = (mas->last_cs != chipselect); 351 u32 mode_changed = mas->last_mode ^ spi_slv->mode; 352 353 mas->last_cs = chipselect; 354 mas->last_mode = spi_slv->mode; 355 356 if (mode_changed & SPI_LSB_FIRST) 357 mas->cur_bits_per_word = 0; /* force next setup_se_xfer to call spi_setup_word_len */ 358 if (mode_changed & SPI_LOOP) 359 writel((spi_slv->mode & SPI_LOOP) ? LOOPBACK_ENABLE : 0, se->base + SE_SPI_LOOPBACK); 360 if (cs_changed) 361 writel(chipselect, se->base + SE_SPI_DEMUX_SEL); 362 if (mode_changed & SPI_CPHA) 363 writel((spi_slv->mode & SPI_CPHA) ? CPHA : 0, se->base + SE_SPI_CPHA); 364 if (mode_changed & SPI_CPOL) 365 writel((spi_slv->mode & SPI_CPOL) ? CPOL : 0, se->base + SE_SPI_CPOL); 366 if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH))) 367 writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV); 368 369 return 0; 370 } 371 372 static void 373 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 374 { 375 struct spi_controller *spi = cb; 376 377 spi->cur_msg->status = -EIO; 378 if (result->result != DMA_TRANS_NOERROR) { 379 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 380 spi_finalize_current_transfer(spi); 381 return; 382 } 383 384 if (!result->residue) { 385 spi->cur_msg->status = 0; 386 dev_dbg(&spi->dev, "DMA txn completed\n"); 387 } else { 388 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 389 } 390 391 spi_finalize_current_transfer(spi); 392 } 393 394 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 395 struct spi_device *spi_slv, struct spi_controller *spi) 396 { 397 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 398 struct dma_slave_config config = {}; 399 struct gpi_spi_config peripheral = {}; 400 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 401 int ret; 402 403 config.peripheral_config = &peripheral; 404 config.peripheral_size = sizeof(peripheral); 405 peripheral.set_config = true; 406 407 if (xfer->bits_per_word != mas->cur_bits_per_word || 408 xfer->speed_hz != mas->cur_speed_hz) { 409 mas->cur_bits_per_word = xfer->bits_per_word; 410 mas->cur_speed_hz = xfer->speed_hz; 411 } 412 413 if (xfer->tx_buf && xfer->rx_buf) { 414 peripheral.cmd = SPI_DUPLEX; 415 } else if (xfer->tx_buf) { 416 peripheral.cmd = SPI_TX; 417 peripheral.rx_len = 0; 418 } else if (xfer->rx_buf) { 419 peripheral.cmd = SPI_RX; 420 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 421 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 422 } else { 423 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 424 425 peripheral.rx_len = (xfer->len / bytes_per_word); 426 } 427 } 428 429 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 430 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 431 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 432 peripheral.cs = spi_get_chipselect(spi_slv, 0); 433 peripheral.pack_en = true; 434 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 435 436 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 437 &peripheral.clk_src, &peripheral.clk_div); 438 if (ret) { 439 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 440 return ret; 441 } 442 443 /* 444 * Set fragmentation to keep CS asserted after this transfer when: 445 * - non-last transfer with cs_change=0: keep CS asserted between chained transfers 446 * - last transfer with cs_change=1: keep CS asserted after the message 447 * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to 448 * keep CS asserted across header, wait-state and data phases) 449 */ 450 peripheral.fragmentation = list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ? 451 xfer->cs_change : !xfer->cs_change; 452 453 if (peripheral.cmd & SPI_RX) { 454 dmaengine_slave_config(mas->rx, &config); 455 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 456 DMA_DEV_TO_MEM, flags); 457 if (!rx_desc) { 458 dev_err(mas->dev, "Err setting up rx desc\n"); 459 return -EIO; 460 } 461 } 462 463 /* 464 * Prepare the TX always, even for RX or tx_buf being null, we would 465 * need TX to be prepared per GSI spec 466 */ 467 dmaengine_slave_config(mas->tx, &config); 468 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 469 DMA_MEM_TO_DEV, flags); 470 if (!tx_desc) { 471 dev_err(mas->dev, "Err setting up tx desc\n"); 472 return -EIO; 473 } 474 475 tx_desc->callback_result = spi_gsi_callback_result; 476 tx_desc->callback_param = spi; 477 478 if (peripheral.cmd & SPI_RX) 479 dmaengine_submit(rx_desc); 480 dmaengine_submit(tx_desc); 481 482 if (peripheral.cmd & SPI_RX) 483 dma_async_issue_pending(mas->rx); 484 485 dma_async_issue_pending(mas->tx); 486 return 1; 487 } 488 489 static u32 get_xfer_len_in_words(struct spi_transfer *xfer, 490 struct spi_geni_master *mas) 491 { 492 u32 len; 493 494 if (!(xfer->bits_per_word % MIN_WORD_LEN)) 495 len = xfer->len * BITS_PER_BYTE / xfer->bits_per_word; 496 else 497 len = xfer->len / (xfer->bits_per_word / BITS_PER_BYTE + 1); 498 len &= TRANS_LEN_MSK; 499 500 return len; 501 } 502 503 static bool geni_can_dma(struct spi_controller *ctlr, 504 struct spi_device *slv, struct spi_transfer *xfer) 505 { 506 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller); 507 u32 len, fifo_size; 508 509 if (mas->cur_xfer_mode == GENI_GPI_DMA) 510 return true; 511 512 /* Set SE DMA mode for SPI target. */ 513 if (ctlr->target) 514 return true; 515 516 len = get_xfer_len_in_words(xfer, mas); 517 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / xfer->bits_per_word; 518 519 if (len > fifo_size) 520 return true; 521 else 522 return false; 523 } 524 525 static int spi_geni_prepare_message(struct spi_controller *spi, 526 struct spi_message *spi_msg) 527 { 528 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 529 int ret; 530 531 switch (mas->cur_xfer_mode) { 532 case GENI_SE_FIFO: 533 case GENI_SE_DMA: 534 if (spi_geni_is_abort_still_pending(mas)) 535 return -EBUSY; 536 ret = setup_fifo_params(spi_msg->spi, spi); 537 if (ret) 538 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 539 return ret; 540 541 case GENI_GPI_DMA: 542 /* nothing to do for GPI DMA */ 543 return 0; 544 } 545 546 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 547 return -EINVAL; 548 } 549 550 static void spi_geni_release_dma_chan(void *data) 551 { 552 struct spi_geni_master *mas = data; 553 554 if (mas->rx) { 555 dma_release_channel(mas->rx); 556 mas->rx = NULL; 557 } 558 559 if (mas->tx) { 560 dma_release_channel(mas->tx); 561 mas->tx = NULL; 562 } 563 } 564 565 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 566 { 567 int ret; 568 569 mas->tx = dma_request_chan(mas->dev, "tx"); 570 if (IS_ERR(mas->tx)) { 571 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), 572 "Failed to get tx DMA ch\n"); 573 goto err_tx; 574 } 575 576 mas->rx = dma_request_chan(mas->dev, "rx"); 577 if (IS_ERR(mas->rx)) { 578 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), 579 "Failed to get rx DMA ch\n"); 580 goto err_rx; 581 } 582 583 ret = devm_add_action_or_reset(mas->dev, spi_geni_release_dma_chan, mas); 584 if (ret) { 585 dev_err(mas->dev, "Unable to add action.\n"); 586 return ret; 587 } 588 589 return 0; 590 591 err_rx: 592 mas->rx = NULL; 593 dma_release_channel(mas->tx); 594 err_tx: 595 mas->tx = NULL; 596 return ret; 597 } 598 599 static int spi_geni_init(struct spi_geni_master *mas) 600 { 601 struct spi_controller *spi = dev_get_drvdata(mas->dev); 602 struct geni_se *se = &mas->se; 603 unsigned int proto, major, minor, ver; 604 u32 spi_tx_cfg, fifo_disable; 605 int ret = -ENXIO; 606 607 pm_runtime_get_sync(mas->dev); 608 609 proto = geni_se_read_proto(se); 610 611 if (spi->target) { 612 if (proto != GENI_SE_SPI_SLAVE) { 613 dev_err(mas->dev, "Invalid proto %d\n", proto); 614 goto out_pm; 615 } 616 spi_slv_setup(mas); 617 } else if (proto == GENI_SE_INVALID_PROTO) { 618 ret = geni_load_se_firmware(se, GENI_SE_SPI); 619 if (ret) { 620 dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret); 621 goto out_pm; 622 } 623 } else if (proto != GENI_SE_SPI) { 624 dev_err(mas->dev, "Invalid proto %d\n", proto); 625 goto out_pm; 626 } 627 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 628 629 /* Width of Tx and Rx FIFO is same */ 630 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 631 632 /* 633 * Hardware programming guide suggests to configure 634 * RX FIFO RFR level to fifo_depth-2. 635 */ 636 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 637 /* Transmit an entire FIFO worth of data per IRQ */ 638 mas->tx_wm = 1; 639 ver = geni_se_get_qup_hw_version(se); 640 major = GENI_SE_VERSION_MAJOR(ver); 641 minor = GENI_SE_VERSION_MINOR(ver); 642 643 if (major == 1 && minor == 0) 644 mas->oversampling = 2; 645 else 646 mas->oversampling = 1; 647 648 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 649 switch (fifo_disable) { 650 case 1: 651 ret = spi_geni_grab_gpi_chan(mas); 652 if (!ret) { /* success case */ 653 mas->cur_xfer_mode = GENI_GPI_DMA; 654 geni_se_select_mode(se, GENI_GPI_DMA); 655 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 656 break; 657 } else if (ret == -EPROBE_DEFER) { 658 goto out_pm; 659 } 660 /* 661 * in case of failure to get gpi dma channel, we can still do the 662 * FIFO mode, so fallthrough 663 */ 664 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 665 fallthrough; 666 667 case 0: 668 mas->cur_xfer_mode = GENI_SE_FIFO; 669 geni_se_select_mode(se, GENI_SE_FIFO); 670 /* setup_fifo_params assumes that these registers start with a zero value */ 671 writel(0, se->base + SE_SPI_LOOPBACK); 672 writel(0, se->base + SE_SPI_DEMUX_SEL); 673 writel(0, se->base + SE_SPI_CPHA); 674 writel(0, se->base + SE_SPI_CPOL); 675 writel(0, se->base + SE_SPI_DEMUX_OUTPUT_INV); 676 ret = 0; 677 break; 678 } 679 680 /* We never control CS manually */ 681 if (!spi->target) { 682 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 683 spi_tx_cfg &= ~CS_TOGGLE; 684 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 685 } 686 687 out_pm: 688 pm_runtime_put(mas->dev); 689 return ret; 690 } 691 692 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 693 { 694 /* 695 * Calculate how many bytes we'll put in each FIFO word. If the 696 * transfer words don't pack cleanly into a FIFO word we'll just put 697 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 698 */ 699 if (mas->fifo_width_bits % mas->cur_bits_per_word) 700 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 701 BITS_PER_BYTE)); 702 703 return mas->fifo_width_bits / BITS_PER_BYTE; 704 } 705 706 static bool geni_spi_handle_tx(struct spi_geni_master *mas) 707 { 708 struct geni_se *se = &mas->se; 709 unsigned int max_bytes; 710 const u8 *tx_buf; 711 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 712 unsigned int i = 0; 713 714 /* Stop the watermark IRQ if nothing to send */ 715 if (!mas->cur_xfer) { 716 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 717 return false; 718 } 719 720 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 721 if (mas->tx_rem_bytes < max_bytes) 722 max_bytes = mas->tx_rem_bytes; 723 724 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 725 while (i < max_bytes) { 726 unsigned int j; 727 unsigned int bytes_to_write; 728 u32 fifo_word = 0; 729 u8 *fifo_byte = (u8 *)&fifo_word; 730 731 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 732 for (j = 0; j < bytes_to_write; j++) 733 fifo_byte[j] = tx_buf[i++]; 734 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 735 } 736 mas->tx_rem_bytes -= max_bytes; 737 if (!mas->tx_rem_bytes) { 738 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 739 return false; 740 } 741 return true; 742 } 743 744 static void geni_spi_handle_rx(struct spi_geni_master *mas) 745 { 746 struct geni_se *se = &mas->se; 747 u32 rx_fifo_status; 748 unsigned int rx_bytes; 749 unsigned int rx_last_byte_valid; 750 u8 *rx_buf; 751 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 752 unsigned int i = 0; 753 754 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 755 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 756 if (rx_fifo_status & RX_LAST) { 757 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 758 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 759 if (rx_last_byte_valid && rx_last_byte_valid < 4) 760 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 761 } 762 763 /* Clear out the FIFO and bail if nowhere to put it */ 764 if (!mas->cur_xfer) { 765 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 766 readl(se->base + SE_GENI_RX_FIFOn); 767 return; 768 } 769 770 if (mas->rx_rem_bytes < rx_bytes) 771 rx_bytes = mas->rx_rem_bytes; 772 773 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 774 while (i < rx_bytes) { 775 u32 fifo_word = 0; 776 u8 *fifo_byte = (u8 *)&fifo_word; 777 unsigned int bytes_to_read; 778 unsigned int j; 779 780 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 781 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 782 for (j = 0; j < bytes_to_read; j++) 783 rx_buf[i++] = fifo_byte[j]; 784 } 785 mas->rx_rem_bytes -= rx_bytes; 786 } 787 788 static int setup_se_xfer(struct spi_transfer *xfer, 789 struct spi_geni_master *mas, 790 u16 mode, struct spi_controller *spi) 791 { 792 u32 m_cmd = 0; 793 u32 m_params = 0; 794 u32 len; 795 struct geni_se *se = &mas->se; 796 int ret; 797 798 /* 799 * Ensure that our interrupt handler isn't still running from some 800 * prior command before we start messing with the hardware behind 801 * its back. We don't need to _keep_ the lock here since we're only 802 * worried about racing with out interrupt handler. The SPI core 803 * already handles making sure that we're not trying to do two 804 * transfers at once or setting a chip select and doing a transfer 805 * concurrently. 806 * 807 * NOTE: we actually _can't_ hold the lock here because possibly we 808 * might call clk_set_rate() which needs to be able to sleep. 809 */ 810 spin_lock_irq(&mas->lock); 811 spin_unlock_irq(&mas->lock); 812 813 if (xfer->bits_per_word != mas->cur_bits_per_word) { 814 spi_setup_word_len(mas, mode, xfer->bits_per_word); 815 mas->cur_bits_per_word = xfer->bits_per_word; 816 } 817 818 /* Speed and bits per word can be overridden per transfer */ 819 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 820 if (ret) 821 return ret; 822 823 mas->tx_rem_bytes = 0; 824 mas->rx_rem_bytes = 0; 825 826 len = get_xfer_len_in_words(xfer, mas); 827 828 mas->cur_xfer = xfer; 829 if (xfer->tx_buf) { 830 m_cmd |= SPI_TX_ONLY; 831 mas->tx_rem_bytes = xfer->len; 832 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 833 } 834 835 if (xfer->rx_buf) { 836 m_cmd |= SPI_RX_ONLY; 837 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 838 mas->rx_rem_bytes = xfer->len; 839 } 840 841 /* 842 * Select DMA mode if sgt are present; and with only 1 entry 843 * This is not a serious limitation because the xfer buffers are 844 * expected to fit into in 1 entry almost always, and if any 845 * doesn't for any reason we fall back to FIFO mode anyway 846 */ 847 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents) 848 mas->cur_xfer_mode = GENI_SE_FIFO; 849 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) { 850 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n", 851 xfer->tx_sg.nents, xfer->rx_sg.nents); 852 mas->cur_xfer_mode = GENI_SE_FIFO; 853 } else 854 mas->cur_xfer_mode = GENI_SE_DMA; 855 geni_se_select_mode(se, mas->cur_xfer_mode); 856 857 /* 858 * Set FRAGMENTATION to keep CS asserted after this transfer when: 859 * - non-last transfer with cs_change=0: keep CS asserted between chained transfers 860 * - last transfer with cs_change=1: keep CS asserted after the message 861 * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to 862 * keep CS asserted across header, wait-state and data phases) 863 */ 864 if (list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ? 865 xfer->cs_change : !xfer->cs_change) 866 m_params = FRAGMENTATION; 867 868 /* 869 * Lock around right before we start the transfer since our 870 * interrupt could come in at any time now. 871 */ 872 spin_lock_irq(&mas->lock); 873 geni_se_setup_m_cmd(se, m_cmd, m_params); 874 875 if (mas->cur_xfer_mode == GENI_SE_DMA) { 876 if (m_cmd & SPI_RX_ONLY) 877 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl), 878 sg_dma_len(xfer->rx_sg.sgl)); 879 if (m_cmd & SPI_TX_ONLY) 880 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl), 881 sg_dma_len(xfer->tx_sg.sgl)); 882 } else if (m_cmd & SPI_TX_ONLY) { 883 if (geni_spi_handle_tx(mas)) 884 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 885 } 886 887 spin_unlock_irq(&mas->lock); 888 return ret; 889 } 890 891 static int spi_geni_transfer_one(struct spi_controller *spi, 892 struct spi_device *slv, 893 struct spi_transfer *xfer) 894 { 895 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 896 int ret; 897 898 if (spi_geni_is_abort_still_pending(mas)) 899 return -EBUSY; 900 901 /* Terminate and return success for 0 byte length transfer */ 902 if (!xfer->len) 903 return 0; 904 905 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { 906 ret = setup_se_xfer(xfer, mas, slv->mode, spi); 907 /* SPI framework expects +ve ret code to wait for transfer complete */ 908 if (!ret) 909 ret = 1; 910 return ret; 911 } 912 return setup_gsi_xfer(xfer, mas, slv, spi); 913 } 914 915 static irqreturn_t geni_spi_isr(int irq, void *data) 916 { 917 struct spi_controller *spi = data; 918 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 919 struct geni_se *se = &mas->se; 920 u32 m_irq, dma_tx_status, dma_rx_status; 921 922 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 923 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); 924 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); 925 926 if (!m_irq && !dma_tx_status && !dma_rx_status) 927 return IRQ_NONE; 928 929 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 930 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 931 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 932 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 933 934 spin_lock(&mas->lock); 935 936 if (mas->cur_xfer_mode == GENI_SE_FIFO) { 937 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 938 geni_spi_handle_rx(mas); 939 940 if (m_irq & M_TX_FIFO_WATERMARK_EN) 941 geni_spi_handle_tx(mas); 942 943 if (m_irq & M_CMD_DONE_EN) { 944 if (mas->cur_xfer) { 945 spi_finalize_current_transfer(spi); 946 mas->cur_xfer = NULL; 947 /* 948 * If this happens, then a CMD_DONE came before all the 949 * Tx buffer bytes were sent out. This is unusual, log 950 * this condition and disable the WM interrupt to 951 * prevent the system from stalling due an interrupt 952 * storm. 953 * 954 * If this happens when all Rx bytes haven't been 955 * received, log the condition. The only known time 956 * this can happen is if bits_per_word != 8 and some 957 * registers that expect xfer lengths in num spi_words 958 * weren't written correctly. 959 */ 960 if (mas->tx_rem_bytes) { 961 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 962 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 963 mas->tx_rem_bytes, mas->cur_bits_per_word); 964 } 965 if (mas->rx_rem_bytes) 966 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 967 mas->rx_rem_bytes, mas->cur_bits_per_word); 968 } else { 969 complete(&mas->cs_done); 970 } 971 } 972 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { 973 const struct spi_transfer *xfer = mas->cur_xfer; 974 975 if (dma_tx_status) 976 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); 977 if (dma_rx_status) 978 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); 979 if (dma_tx_status & TX_DMA_DONE) 980 mas->tx_rem_bytes = 0; 981 if (dma_rx_status & RX_DMA_DONE) 982 mas->rx_rem_bytes = 0; 983 if (dma_tx_status & TX_RESET_DONE) 984 complete(&mas->tx_reset_done); 985 if (dma_rx_status & RX_RESET_DONE) 986 complete(&mas->rx_reset_done); 987 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { 988 spi_finalize_current_transfer(spi); 989 mas->cur_xfer = NULL; 990 } 991 } 992 993 if (m_irq & M_CMD_CANCEL_EN) 994 complete(&mas->cancel_done); 995 if (m_irq & M_CMD_ABORT_EN) 996 complete(&mas->abort_done); 997 998 /* 999 * It's safe or a good idea to Ack all of our interrupts at the end 1000 * of the function. Specifically: 1001 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 1002 * clearing Acks. Clearing at the end relies on nobody else having 1003 * started a new transfer yet or else we could be clearing _their_ 1004 * done bit, but everyone grabs the spinlock before starting a new 1005 * transfer. 1006 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 1007 * to be "latched level" interrupts so it's important to clear them 1008 * _after_ you've handled the condition and always safe to do so 1009 * since they'll re-assert if they're still happening. 1010 */ 1011 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 1012 1013 spin_unlock(&mas->lock); 1014 1015 return IRQ_HANDLED; 1016 } 1017 1018 static int spi_geni_target_abort(struct spi_controller *spi) 1019 { 1020 if (!spi->cur_msg) 1021 return 0; 1022 1023 handle_se_timeout(spi); 1024 spi_finalize_current_transfer(spi); 1025 1026 return 0; 1027 } 1028 1029 static int spi_geni_probe(struct platform_device *pdev) 1030 { 1031 int ret, irq; 1032 struct spi_controller *spi; 1033 struct spi_geni_master *mas; 1034 void __iomem *base; 1035 struct clk *clk; 1036 struct device *dev = &pdev->dev; 1037 1038 irq = platform_get_irq(pdev, 0); 1039 if (irq < 0) 1040 return irq; 1041 1042 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1043 if (ret) 1044 return dev_err_probe(dev, ret, "could not set DMA mask\n"); 1045 1046 base = devm_platform_ioremap_resource(pdev, 0); 1047 if (IS_ERR(base)) 1048 return PTR_ERR(base); 1049 1050 clk = devm_clk_get(dev, "se"); 1051 if (IS_ERR(clk)) 1052 return PTR_ERR(clk); 1053 1054 if (device_property_read_bool(dev, "spi-slave")) 1055 spi = devm_spi_alloc_target(dev, sizeof(*mas)); 1056 else 1057 spi = devm_spi_alloc_host(dev, sizeof(*mas)); 1058 1059 if (!spi) 1060 return -ENOMEM; 1061 1062 platform_set_drvdata(pdev, spi); 1063 mas = spi_controller_get_devdata(spi); 1064 mas->irq = irq; 1065 mas->dev = dev; 1066 mas->se.dev = dev; 1067 mas->se.wrapper = dev_get_drvdata(dev->parent); 1068 mas->se.base = base; 1069 mas->se.clk = clk; 1070 1071 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1072 if (ret) 1073 return ret; 1074 /* OPP table is optional */ 1075 ret = devm_pm_opp_of_add_table(&pdev->dev); 1076 if (ret && ret != -ENODEV) { 1077 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1078 return ret; 1079 } 1080 1081 spi->bus_num = -1; 1082 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 1083 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1084 spi->num_chipselect = 4; 1085 spi->max_speed_hz = 50000000; 1086 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */ 1087 spi->prepare_message = spi_geni_prepare_message; 1088 spi->transfer_one = spi_geni_transfer_one; 1089 spi->can_dma = geni_can_dma; 1090 spi->dma_map_dev = dev->parent; 1091 spi->auto_runtime_pm = true; 1092 spi->handle_err = spi_geni_handle_err; 1093 spi->use_gpio_descriptors = true; 1094 1095 init_completion(&mas->cs_done); 1096 init_completion(&mas->cancel_done); 1097 init_completion(&mas->abort_done); 1098 init_completion(&mas->tx_reset_done); 1099 init_completion(&mas->rx_reset_done); 1100 spin_lock_init(&mas->lock); 1101 1102 if (spi->target) 1103 spi->target_abort = spi_geni_target_abort; 1104 1105 ret = geni_icc_get(&mas->se, NULL); 1106 if (ret) 1107 return ret; 1108 1109 pm_runtime_use_autosuspend(&pdev->dev); 1110 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 1111 ret = devm_pm_runtime_enable(dev); 1112 if (ret) 1113 return ret; 1114 1115 /* Set the bus quota to a reasonable value for register access */ 1116 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 1117 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1118 1119 ret = geni_icc_set_bw(&mas->se); 1120 if (ret) 1121 return ret; 1122 1123 ret = spi_geni_init(mas); 1124 if (ret) 1125 return ret; 1126 1127 /* 1128 * TX is required per GSI spec, see setup_gsi_xfer(). 1129 */ 1130 if (mas->cur_xfer_mode == GENI_GPI_DMA) 1131 spi->flags = SPI_CONTROLLER_MUST_TX; 1132 1133 ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 1134 if (ret) 1135 return ret; 1136 1137 return devm_spi_register_controller(dev, spi); 1138 } 1139 1140 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 1141 { 1142 struct spi_controller *spi = dev_get_drvdata(dev); 1143 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 1144 int ret; 1145 1146 /* Drop the performance state vote */ 1147 dev_pm_opp_set_rate(dev, 0); 1148 1149 ret = geni_se_resources_off(&mas->se); 1150 if (ret) 1151 return ret; 1152 1153 return geni_icc_disable(&mas->se); 1154 } 1155 1156 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1157 { 1158 struct spi_controller *spi = dev_get_drvdata(dev); 1159 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 1160 int ret; 1161 1162 ret = geni_icc_enable(&mas->se); 1163 if (ret) 1164 return ret; 1165 1166 ret = geni_se_resources_on(&mas->se); 1167 if (ret) 1168 return ret; 1169 1170 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1171 } 1172 1173 static int __maybe_unused spi_geni_suspend(struct device *dev) 1174 { 1175 struct spi_controller *spi = dev_get_drvdata(dev); 1176 int ret; 1177 1178 ret = spi_controller_suspend(spi); 1179 if (ret) 1180 return ret; 1181 1182 ret = pm_runtime_force_suspend(dev); 1183 if (ret) 1184 spi_controller_resume(spi); 1185 1186 return ret; 1187 } 1188 1189 static int __maybe_unused spi_geni_resume(struct device *dev) 1190 { 1191 struct spi_controller *spi = dev_get_drvdata(dev); 1192 int ret; 1193 1194 ret = pm_runtime_force_resume(dev); 1195 if (ret) 1196 return ret; 1197 1198 ret = spi_controller_resume(spi); 1199 if (ret) 1200 pm_runtime_force_suspend(dev); 1201 1202 return ret; 1203 } 1204 1205 static const struct dev_pm_ops spi_geni_pm_ops = { 1206 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1207 spi_geni_runtime_resume, NULL) 1208 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1209 }; 1210 1211 static const struct of_device_id spi_geni_dt_match[] = { 1212 { .compatible = "qcom,geni-spi" }, 1213 {} 1214 }; 1215 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1216 1217 static struct platform_driver spi_geni_driver = { 1218 .probe = spi_geni_probe, 1219 .driver = { 1220 .name = "geni_spi", 1221 .pm = &spi_geni_pm_ops, 1222 .of_match_table = spi_geni_dt_match, 1223 }, 1224 }; 1225 module_platform_driver(spi_geni_driver); 1226 1227 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1228 MODULE_LICENSE("GPL v2"); 1229