1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * MT regs definitions, follows on from mipsregs.h 4 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. 5 * Elizabeth Clarke et. al. 6 * 7 */ 8 #ifndef _ASM_MIPSMTREGS_H 9 #define _ASM_MIPSMTREGS_H 10 11 #include <asm/mipsregs.h> 12 13 #ifndef __ASSEMBLY__ 14 15 /* 16 * C macros 17 */ 18 19 #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1) 20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) 21 22 #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2) 23 #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3) 24 25 #define read_c0_vpecontrol() __read_32bit_c0_register($1, 1) 26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) 27 28 #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) 29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) 30 31 #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) 32 #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) 33 34 #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) 35 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) 36 37 #define read_c0_tcbind() __read_32bit_c0_register($2, 2) 38 39 #define write_c0_tchalt(val) __write_32bit_c0_register($2, 4, val) 40 41 #define read_c0_tccontext() __read_32bit_c0_register($2, 5) 42 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) 43 44 #else /* Assembly */ 45 /* 46 * Macros for use in assembly language code 47 */ 48 49 #define CP0_MVPCONTROL $0, 1 50 #define CP0_MVPCONF0 $0, 2 51 #define CP0_MVPCONF1 $0, 3 52 #define CP0_VPECONTROL $1, 1 53 #define CP0_VPECONF0 $1, 2 54 #define CP0_VPECONF1 $1, 3 55 #define CP0_YQMASK $1, 4 56 #define CP0_VPESCHEDULE $1, 5 57 #define CP0_VPESCHEFBK $1, 6 58 #define CP0_TCSTATUS $2, 1 59 #define CP0_TCBIND $2, 2 60 #define CP0_TCRESTART $2, 3 61 #define CP0_TCHALT $2, 4 62 #define CP0_TCCONTEXT $2, 5 63 #define CP0_TCSCHEDULE $2, 6 64 #define CP0_TCSCHEFBK $2, 7 65 #define CP0_SRSCONF0 $6, 1 66 #define CP0_SRSCONF1 $6, 2 67 #define CP0_SRSCONF2 $6, 3 68 #define CP0_SRSCONF3 $6, 4 69 #define CP0_SRSCONF4 $6, 5 70 71 #endif 72 73 /* MVPControl fields */ 74 #define MVPCONTROL_EVP (_ULCAST_(1)) 75 76 #define MVPCONTROL_VPC_SHIFT 1 77 #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) 78 79 #define MVPCONTROL_STLB_SHIFT 2 80 #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) 81 82 83 /* MVPConf0 fields */ 84 #define MVPCONF0_PTC_SHIFT 0 85 #define MVPCONF0_PTC ( _ULCAST_(0xff)) 86 #define MVPCONF0_PVPE_SHIFT 10 87 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) 88 #define MVPCONF0_TCA_SHIFT 15 89 #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) 90 #define MVPCONF0_PTLBE_SHIFT 16 91 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) 92 #define MVPCONF0_TLBS_SHIFT 29 93 #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) 94 #define MVPCONF0_M_SHIFT 31 95 #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) 96 97 98 /* config3 fields */ 99 #define CONFIG3_MT_SHIFT 2 100 #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) 101 102 103 /* VPEControl fields (per VPE) */ 104 #define VPECONTROL_TARGTC (_ULCAST_(0xff)) 105 106 #define VPECONTROL_TE_SHIFT 15 107 #define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) 108 #define VPECONTROL_EXCPT_SHIFT 16 109 #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) 110 111 /* Thread Exception Codes for EXCPT field */ 112 #define THREX_TU 0 113 #define THREX_TO 1 114 #define THREX_IYQ 2 115 #define THREX_GSX 3 116 #define THREX_YSCH 4 117 #define THREX_GSSCH 5 118 119 #define VPECONTROL_GSI_SHIFT 20 120 #define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) 121 #define VPECONTROL_YSI_SHIFT 21 122 #define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) 123 124 /* VPEConf0 fields (per VPE) */ 125 #define VPECONF0_VPA_SHIFT 0 126 #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) 127 #define VPECONF0_MVP_SHIFT 1 128 #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) 129 #define VPECONF0_XTC_SHIFT 21 130 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) 131 132 /* VPEConf1 fields (per VPE) */ 133 #define VPECONF1_NCP1_SHIFT 0 134 #define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT) 135 #define VPECONF1_NCP2_SHIFT 10 136 #define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT) 137 #define VPECONF1_NCX_SHIFT 20 138 #define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT) 139 140 /* TCStatus fields (per TC) */ 141 #define TCSTATUS_TASID (_ULCAST_(0xff)) 142 #define TCSTATUS_IXMT_SHIFT 10 143 #define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) 144 #define TCSTATUS_TKSU_SHIFT 11 145 #define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) 146 #define TCSTATUS_A_SHIFT 13 147 #define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) 148 #define TCSTATUS_DA_SHIFT 15 149 #define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) 150 #define TCSTATUS_DT_SHIFT 20 151 #define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) 152 #define TCSTATUS_TDS_SHIFT 21 153 #define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) 154 #define TCSTATUS_TSST_SHIFT 22 155 #define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) 156 #define TCSTATUS_RNST_SHIFT 23 157 #define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) 158 /* Codes for RNST */ 159 #define TC_RUNNING 0 160 #define TC_WAITING 1 161 #define TC_YIELDING 2 162 #define TC_GATED 3 163 164 #define TCSTATUS_TMX_SHIFT 27 165 #define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) 166 /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */ 167 168 /* TCBind */ 169 #define TCBIND_CURVPE_SHIFT 0 170 #define TCBIND_CURVPE (_ULCAST_(0xf)) 171 172 #define TCBIND_CURTC_SHIFT 21 173 174 #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) 175 176 /* TCHalt */ 177 #define TCHALT_H (_ULCAST_(1)) 178 179 #ifndef __ASSEMBLY__ 180 core_nvpes(void)181 static inline unsigned core_nvpes(void) 182 { 183 unsigned conf0; 184 185 if (!cpu_has_mipsmt) 186 return 1; 187 188 conf0 = read_c0_mvpconf0(); 189 return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 190 } 191 192 #define _ASM_SET_DVPE \ 193 _ASM_MACRO_1R(dvpe, rt, \ 194 _ASM_INSN_IF_MIPS(0x41600001 | __rt << 16) \ 195 _ASM_INSN32_IF_MM(0x0000157C | __rt << 21)) 196 #define _ASM_UNSET_DVPE ".purgem dvpe\n\t" 197 dvpe(void)198 static inline unsigned int dvpe(void) 199 { 200 int res = 0; 201 202 __asm__ __volatile__( 203 " .set push \n" 204 " .set "MIPS_ISA_LEVEL" \n" 205 _ASM_SET_DVPE 206 " dvpe %0 \n" 207 " ehb \n" 208 _ASM_UNSET_DVPE 209 " .set pop \n" 210 : "=r" (res)); 211 212 instruction_hazard(); 213 214 return res; 215 } 216 217 #define _ASM_SET_EVPE \ 218 _ASM_MACRO_1R(evpe, rt, \ 219 _ASM_INSN_IF_MIPS(0x41600021 | __rt << 16) \ 220 _ASM_INSN32_IF_MM(0x0000357C | __rt << 21)) 221 #define _ASM_UNSET_EVPE ".purgem evpe\n\t" 222 __raw_evpe(void)223 static inline void __raw_evpe(void) 224 { 225 __asm__ __volatile__( 226 " .set push \n" 227 " .set "MIPS_ISA_LEVEL" \n" 228 _ASM_SET_EVPE 229 " evpe $0 \n" 230 " ehb \n" 231 _ASM_UNSET_EVPE 232 " .set pop \n"); 233 } 234 235 /* Enable virtual processor execution if previous suggested it should be. 236 EVPE_ENABLE to force */ 237 238 #define EVPE_ENABLE MVPCONTROL_EVP 239 evpe(int previous)240 static inline void evpe(int previous) 241 { 242 if ((previous & MVPCONTROL_EVP)) 243 __raw_evpe(); 244 } 245 246 #define _ASM_SET_DMT \ 247 _ASM_MACRO_1R(dmt, rt, \ 248 _ASM_INSN_IF_MIPS(0x41600bc1 | __rt << 16) \ 249 _ASM_INSN32_IF_MM(0x0000057C | __rt << 21)) 250 #define _ASM_UNSET_DMT ".purgem dmt\n\t" 251 dmt(void)252 static inline unsigned int dmt(void) 253 { 254 int res; 255 256 __asm__ __volatile__( 257 " .set push \n" 258 " .set "MIPS_ISA_LEVEL" \n" 259 _ASM_SET_DMT 260 " dmt %0 \n" 261 " ehb \n" 262 _ASM_UNSET_DMT 263 " .set pop \n" 264 : "=r" (res)); 265 266 instruction_hazard(); 267 268 return res; 269 } 270 271 #define _ASM_SET_EMT \ 272 _ASM_MACRO_1R(emt, rt, \ 273 _ASM_INSN_IF_MIPS(0x41600be1 | __rt << 16) \ 274 _ASM_INSN32_IF_MM(0x0000257C | __rt << 21)) 275 #define _ASM_UNSET_EMT ".purgem emt\n\t" 276 __raw_emt(void)277 static inline void __raw_emt(void) 278 { 279 __asm__ __volatile__( 280 " .set push \n" 281 " .set "MIPS_ISA_LEVEL" \n" 282 _ASM_SET_EMT 283 " emt $0 \n" 284 _ASM_UNSET_EMT 285 " ehb \n" 286 " .set pop"); 287 } 288 289 /* enable multi-threaded execution if previous suggested it should be. 290 EMT_ENABLE to force */ 291 292 #define EMT_ENABLE VPECONTROL_TE 293 emt(int previous)294 static inline void emt(int previous) 295 { 296 if ((previous & EMT_ENABLE)) 297 __raw_emt(); 298 } 299 ehb(void)300 static inline void ehb(void) 301 { 302 __asm__ __volatile__( 303 " .set push \n" 304 " .set "MIPS_ISA_LEVEL" \n" 305 " ehb \n" 306 " .set pop \n"); 307 } 308 309 #define _ASM_SET_MFTC0 \ 310 _ASM_MACRO_2R_1S(mftc0, rs, rt, sel, \ 311 _ASM_INSN_IF_MIPS(0x41000000 | __rt << 16 | \ 312 __rs << 11 | \\sel) \ 313 _ASM_INSN32_IF_MM(0x0000000E | __rt << 21 | \ 314 __rs << 16 | \\sel << 4)) 315 #define _ASM_UNSET_MFTC0 ".purgem mftc0\n\t" 316 317 #define mftc0(rt, sel) \ 318 ({ \ 319 unsigned long __res; \ 320 \ 321 __asm__ __volatile__( \ 322 " .set push \n" \ 323 " .set "MIPS_ISA_LEVEL" \n" \ 324 _ASM_SET_MFTC0 \ 325 " mftc0 %0, " #rt ", " #sel " \n" \ 326 _ASM_UNSET_MFTC0 \ 327 " .set pop \n" \ 328 : "=r" (__res)); \ 329 \ 330 __res; \ 331 }) 332 333 #define _ASM_SET_MFTGPR \ 334 _ASM_MACRO_2R(mftgpr, rs, rt, \ 335 _ASM_INSN_IF_MIPS(0x41000020 | __rt << 16 | \ 336 __rs << 11) \ 337 _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \ 338 __rs << 16)) 339 #define _ASM_UNSET_MFTGPR ".purgem mftgpr\n\t" 340 341 #define mftgpr(rt) \ 342 ({ \ 343 unsigned long __res; \ 344 \ 345 __asm__ __volatile__( \ 346 " .set push \n" \ 347 " .set "MIPS_ISA_LEVEL" \n" \ 348 _ASM_SET_MFTGPR \ 349 " mftgpr %0," #rt " \n" \ 350 _ASM_UNSET_MFTGPR \ 351 " .set pop \n" \ 352 : "=r" (__res)); \ 353 \ 354 __res; \ 355 }) 356 357 #define mftr(rt, u, sel) \ 358 ({ \ 359 unsigned long __res; \ 360 \ 361 __asm__ __volatile__( \ 362 " mftr %0, " #rt ", " #u ", " #sel " \n" \ 363 : "=r" (__res)); \ 364 \ 365 __res; \ 366 }) 367 368 #define _ASM_SET_MTTGPR \ 369 _ASM_MACRO_2R(mttgpr, rt, rs, \ 370 _ASM_INSN_IF_MIPS(0x41800020 | __rt << 16 | \ 371 __rs << 11) \ 372 _ASM_INSN32_IF_MM(0x00000406 | __rt << 21 | \ 373 __rs << 16)) 374 #define _ASM_UNSET_MTTGPR ".purgem mttgpr\n\t" 375 376 #define mttgpr(rs, v) \ 377 do { \ 378 __asm__ __volatile__( \ 379 " .set push \n" \ 380 " .set "MIPS_ISA_LEVEL" \n" \ 381 _ASM_SET_MTTGPR \ 382 " mttgpr %0, " #rs " \n" \ 383 _ASM_UNSET_MTTGPR \ 384 " .set pop \n" \ 385 : : "r" (v)); \ 386 } while (0) 387 388 #define _ASM_SET_MTTC0 \ 389 _ASM_MACRO_2R_1S(mttc0, rt, rs, sel, \ 390 _ASM_INSN_IF_MIPS(0x41800000 | __rt << 16 | \ 391 __rs << 11 | \\sel) \ 392 _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \ 393 __rs << 16 | \\sel << 4)) 394 #define _ASM_UNSET_MTTC0 ".purgem mttc0\n\t" 395 396 #define mttc0(rs, sel, v) \ 397 ({ \ 398 __asm__ __volatile__( \ 399 " .set push \n" \ 400 " .set "MIPS_ISA_LEVEL" \n" \ 401 _ASM_SET_MTTC0 \ 402 " mttc0 %0," #rs ", " #sel " \n" \ 403 _ASM_UNSET_MTTC0 \ 404 " .set pop \n" \ 405 : \ 406 : "r" (v)); \ 407 }) 408 409 410 #define mttr(rd, u, sel, v) \ 411 ({ \ 412 __asm__ __volatile__( \ 413 "mttr %0," #rd ", " #u ", " #sel \ 414 : : "r" (v)); \ 415 }) 416 417 418 #define settc(tc) \ 419 do { \ 420 write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \ 421 ehb(); \ 422 } while (0) 423 424 425 /* you *must* set the target tc (settc) before trying to use these */ 426 #define read_vpe_c0_vpecontrol() mftc0($1, 1) 427 #define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val) 428 #define read_vpe_c0_vpeconf0() mftc0($1, 2) 429 #define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val) 430 #define read_vpe_c0_vpeconf1() mftc0($1, 3) 431 #define write_vpe_c0_vpeconf1(val) mttc0($1, 3, val) 432 #define read_vpe_c0_count() mftc0($9, 0) 433 #define write_vpe_c0_count(val) mttc0($9, 0, val) 434 #define read_vpe_c0_status() mftc0($12, 0) 435 #define write_vpe_c0_status(val) mttc0($12, 0, val) 436 #define read_vpe_c0_cause() mftc0($13, 0) 437 #define write_vpe_c0_cause(val) mttc0($13, 0, val) 438 #define read_vpe_c0_config() mftc0($16, 0) 439 #define write_vpe_c0_config(val) mttc0($16, 0, val) 440 #define read_vpe_c0_config1() mftc0($16, 1) 441 #define write_vpe_c0_config1(val) mttc0($16, 1, val) 442 #define read_vpe_c0_config7() mftc0($16, 7) 443 #define write_vpe_c0_config7(val) mttc0($16, 7, val) 444 #define read_vpe_c0_ebase() mftc0($15, 1) 445 #define write_vpe_c0_ebase(val) mttc0($15, 1, val) 446 #define write_vpe_c0_compare(val) mttc0($11, 0, val) 447 #define read_vpe_c0_badvaddr() mftc0($8, 0) 448 #define read_vpe_c0_epc() mftc0($14, 0) 449 #define write_vpe_c0_epc(val) mttc0($14, 0, val) 450 451 452 /* TC */ 453 #define read_tc_c0_tcstatus() mftc0($2, 1) 454 #define write_tc_c0_tcstatus(val) mttc0($2, 1, val) 455 #define read_tc_c0_tcbind() mftc0($2, 2) 456 #define write_tc_c0_tcbind(val) mttc0($2, 2, val) 457 #define read_tc_c0_tcrestart() mftc0($2, 3) 458 #define write_tc_c0_tcrestart(val) mttc0($2, 3, val) 459 #define read_tc_c0_tchalt() mftc0($2, 4) 460 #define write_tc_c0_tchalt(val) mttc0($2, 4, val) 461 #define read_tc_c0_tccontext() mftc0($2, 5) 462 #define write_tc_c0_tccontext(val) mttc0($2, 5, val) 463 464 /* GPR */ 465 #define read_tc_gpr_sp() mftgpr($29) 466 #define write_tc_gpr_sp(val) mttgpr($29, val) 467 #define read_tc_gpr_gp() mftgpr($28) 468 #define write_tc_gpr_gp(val) mttgpr($28, val) 469 470 __BUILD_SET_C0(mvpcontrol) 471 472 #endif /* Not __ASSEMBLY__ */ 473 474 #endif 475