1 /**************************************************************************** 2 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004 4 All rights reserved 5 www.echoaudio.com 6 7 This file is part of Echo Digital Audio's generic driver library. 8 9 Echo Digital Audio's generic driver library is free software; 10 you can redistribute it and/or modify it under the terms of 11 the GNU General Public License as published by the Free Software 12 Foundation. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, 22 MA 02111-1307, USA. 23 24 ************************************************************************* 25 26 Translation from C++ and adaptation for use in ALSA-Driver 27 were made by Giuliano Pochini <pochini@shiny.it> 28 29 ****************************************************************************/ 30 31 32 33 /* These functions are common for all "3G" cards */ 34 35 36 static int check_asic_status(struct echoaudio *chip) 37 { 38 u32 box_status; 39 40 if (wait_handshake(chip)) 41 return -EIO; 42 43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); 44 chip->asic_loaded = false; 45 clear_handshake(chip); 46 send_vector(chip, DSP_VC_TEST_ASIC); 47 48 if (wait_handshake(chip)) { 49 chip->dsp_code = NULL; 50 return -EIO; 51 } 52 53 box_status = le32_to_cpu(chip->comm_page->ext_box_status); 54 dev_dbg(chip->card->dev, "box_status=%x\n", box_status); 55 if (box_status == E3G_ASIC_NOT_LOADED) 56 return -ENODEV; 57 58 chip->asic_loaded = true; 59 return box_status & E3G_BOX_TYPE_MASK; 60 } 61 62 63 64 static inline u32 get_frq_reg(struct echoaudio *chip) 65 { 66 return le32_to_cpu(chip->comm_page->e3g_frq_register); 67 } 68 69 70 71 /* Most configuration of 3G cards is accomplished by writing the control 72 register. write_control_reg sends the new control register value to the DSP. */ 73 static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq, 74 char force) 75 { 76 __le32 ctl_reg, frq_reg; 77 78 if (wait_handshake(chip)) 79 return -EIO; 80 81 dev_dbg(chip->card->dev, 82 "WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq); 83 84 ctl_reg = cpu_to_le32(ctl); 85 frq_reg = cpu_to_le32(frq); 86 87 if (ctl_reg != chip->comm_page->control_register || 88 frq_reg != chip->comm_page->e3g_frq_register || force) { 89 chip->comm_page->e3g_frq_register = frq_reg; 90 chip->comm_page->control_register = ctl_reg; 91 clear_handshake(chip); 92 return send_vector(chip, DSP_VC_WRITE_CONTROL_REG); 93 } 94 95 dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n"); 96 return 0; 97 } 98 99 100 101 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */ 102 static int set_digital_mode(struct echoaudio *chip, u8 mode) 103 { 104 u8 previous_mode; 105 int err, i, o; 106 107 /* All audio channels must be closed before changing the digital mode */ 108 if (snd_BUG_ON(chip->pipe_alloc_mask)) 109 return -EAGAIN; 110 111 if (snd_BUG_ON(!(chip->digital_modes & (1 << mode)))) 112 return -EINVAL; 113 114 previous_mode = chip->digital_mode; 115 err = dsp_set_digital_mode(chip, mode); 116 117 /* If we successfully changed the digital mode from or to ADAT, 118 * then make sure all output, input and monitor levels are 119 * updated by the DSP comm object. */ 120 if (err >= 0 && previous_mode != mode && 121 (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) { 122 guard(spinlock_irq)(&chip->lock); 123 for (o = 0; o < num_busses_out(chip); o++) 124 for (i = 0; i < num_busses_in(chip); i++) 125 set_monitor_gain(chip, o, i, 126 chip->monitor_gain[o][i]); 127 128 #ifdef ECHOCARD_HAS_INPUT_GAIN 129 for (i = 0; i < num_busses_in(chip); i++) 130 set_input_gain(chip, i, chip->input_gain[i]); 131 update_input_line_level(chip); 132 #endif 133 134 for (o = 0; o < num_busses_out(chip); o++) 135 set_output_gain(chip, o, chip->output_gain[o]); 136 update_output_line_level(chip); 137 } 138 139 return err; 140 } 141 142 143 144 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) 145 { 146 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; 147 148 switch (rate) { 149 case 32000 : 150 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; 151 break; 152 case 44100 : 153 if (chip->professional_spdif) 154 control_reg |= E3G_SPDIF_SAMPLE_RATE0; 155 break; 156 case 48000 : 157 control_reg |= E3G_SPDIF_SAMPLE_RATE1; 158 break; 159 } 160 161 if (chip->professional_spdif) 162 control_reg |= E3G_SPDIF_PRO_MODE; 163 164 if (chip->non_audio_spdif) 165 control_reg |= E3G_SPDIF_NOT_AUDIO; 166 167 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | 168 E3G_SPDIF_COPY_PERMIT; 169 170 return control_reg; 171 } 172 173 174 175 /* Set the S/PDIF output format */ 176 static int set_professional_spdif(struct echoaudio *chip, char prof) 177 { 178 u32 control_reg; 179 180 control_reg = le32_to_cpu(chip->comm_page->control_register); 181 chip->professional_spdif = prof; 182 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); 183 return write_control_reg(chip, control_reg, get_frq_reg(chip), 0); 184 } 185 186 187 188 /* detect_input_clocks() returns a bitmask consisting of all the input clocks 189 currently connected to the hardware; this changes as the user connects and 190 disconnects clock inputs. You should use this information to determine which 191 clocks the user is allowed to select. */ 192 static u32 detect_input_clocks(const struct echoaudio *chip) 193 { 194 u32 clocks_from_dsp, clock_bits; 195 196 /* Map the DSP clock detect bits to the generic driver clock 197 * detect bits */ 198 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); 199 200 clock_bits = ECHO_CLOCK_BIT_INTERNAL; 201 202 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD) 203 clock_bits |= ECHO_CLOCK_BIT_WORD; 204 205 switch(chip->digital_mode) { 206 case DIGITAL_MODE_SPDIF_RCA: 207 case DIGITAL_MODE_SPDIF_OPTICAL: 208 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF) 209 clock_bits |= ECHO_CLOCK_BIT_SPDIF; 210 break; 211 case DIGITAL_MODE_ADAT: 212 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT) 213 clock_bits |= ECHO_CLOCK_BIT_ADAT; 214 break; 215 } 216 217 return clock_bits; 218 } 219 220 221 222 static int load_asic(struct echoaudio *chip) 223 { 224 int box_type, err; 225 226 if (chip->asic_loaded) 227 return 0; 228 229 /* Give the DSP a few milliseconds to settle down */ 230 mdelay(2); 231 232 err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC); 233 if (err < 0) 234 return err; 235 236 chip->asic_code = FW_3G_ASIC; 237 238 /* Now give the new ASIC some time to set up */ 239 msleep(1000); 240 /* See if it worked */ 241 box_type = check_asic_status(chip); 242 243 /* Set up the control register if the load succeeded - 244 * 48 kHz, internal clock, S/PDIF RCA mode */ 245 if (box_type >= 0) { 246 err = write_control_reg(chip, E3G_48KHZ, 247 E3G_FREQ_REG_DEFAULT, true); 248 if (err < 0) 249 return err; 250 } 251 252 return box_type; 253 } 254 255 256 257 static int set_sample_rate(struct echoaudio *chip, u32 rate) 258 { 259 u32 control_reg, clock, base_rate, frq_reg; 260 261 /* Only set the clock for internal mode. */ 262 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { 263 dev_warn(chip->card->dev, 264 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); 265 /* Save the rate anyhow */ 266 chip->comm_page->sample_rate = cpu_to_le32(rate); 267 chip->sample_rate = rate; 268 set_input_clock(chip, chip->input_clock); 269 return 0; 270 } 271 272 if (snd_BUG_ON(rate >= 50000 && 273 chip->digital_mode == DIGITAL_MODE_ADAT)) 274 return -EINVAL; 275 276 control_reg = le32_to_cpu(chip->comm_page->control_register); 277 control_reg &= E3G_CLOCK_CLEAR_MASK; 278 279 switch (rate) { 280 case 96000: 281 clock = E3G_96KHZ; 282 break; 283 case 88200: 284 clock = E3G_88KHZ; 285 break; 286 case 48000: 287 clock = E3G_48KHZ; 288 break; 289 case 44100: 290 clock = E3G_44KHZ; 291 break; 292 case 32000: 293 clock = E3G_32KHZ; 294 break; 295 default: 296 clock = E3G_CONTINUOUS_CLOCK; 297 if (rate > 50000) 298 clock |= E3G_DOUBLE_SPEED_MODE; 299 break; 300 } 301 302 control_reg |= clock; 303 control_reg = set_spdif_bits(chip, control_reg, rate); 304 305 base_rate = rate; 306 if (base_rate > 50000) 307 base_rate /= 2; 308 if (base_rate < 32000) 309 base_rate = 32000; 310 311 frq_reg = E3G_MAGIC_NUMBER / base_rate - 2; 312 if (frq_reg > E3G_FREQ_REG_MAX) 313 frq_reg = E3G_FREQ_REG_MAX; 314 315 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ 316 chip->sample_rate = rate; 317 dev_dbg(chip->card->dev, 318 "SetSampleRate: %d clock %x\n", rate, control_reg); 319 320 /* Tell the DSP about it - DSP reads both control reg & freq reg */ 321 return write_control_reg(chip, control_reg, frq_reg, 0); 322 } 323 324 325 326 /* Set the sample clock source to internal, S/PDIF, ADAT */ 327 static int set_input_clock(struct echoaudio *chip, u16 clock) 328 { 329 u32 control_reg, clocks_from_dsp; 330 331 332 /* Mask off the clock select bits */ 333 control_reg = le32_to_cpu(chip->comm_page->control_register) & 334 E3G_CLOCK_CLEAR_MASK; 335 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); 336 337 switch (clock) { 338 case ECHO_CLOCK_INTERNAL: 339 chip->input_clock = ECHO_CLOCK_INTERNAL; 340 return set_sample_rate(chip, chip->sample_rate); 341 case ECHO_CLOCK_SPDIF: 342 if (chip->digital_mode == DIGITAL_MODE_ADAT) 343 return -EAGAIN; 344 control_reg |= E3G_SPDIF_CLOCK; 345 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96) 346 control_reg |= E3G_DOUBLE_SPEED_MODE; 347 else 348 control_reg &= ~E3G_DOUBLE_SPEED_MODE; 349 break; 350 case ECHO_CLOCK_ADAT: 351 if (chip->digital_mode != DIGITAL_MODE_ADAT) 352 return -EAGAIN; 353 control_reg |= E3G_ADAT_CLOCK; 354 control_reg &= ~E3G_DOUBLE_SPEED_MODE; 355 break; 356 case ECHO_CLOCK_WORD: 357 control_reg |= E3G_WORD_CLOCK; 358 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96) 359 control_reg |= E3G_DOUBLE_SPEED_MODE; 360 else 361 control_reg &= ~E3G_DOUBLE_SPEED_MODE; 362 break; 363 default: 364 dev_err(chip->card->dev, 365 "Input clock 0x%x not supported for Echo3G\n", clock); 366 return -EINVAL; 367 } 368 369 chip->input_clock = clock; 370 return write_control_reg(chip, control_reg, get_frq_reg(chip), 1); 371 } 372 373 374 375 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) 376 { 377 u32 control_reg; 378 int err, incompatible_clock; 379 380 /* Set clock to "internal" if it's not compatible with the new mode */ 381 incompatible_clock = false; 382 switch (mode) { 383 case DIGITAL_MODE_SPDIF_OPTICAL: 384 case DIGITAL_MODE_SPDIF_RCA: 385 if (chip->input_clock == ECHO_CLOCK_ADAT) 386 incompatible_clock = true; 387 break; 388 case DIGITAL_MODE_ADAT: 389 if (chip->input_clock == ECHO_CLOCK_SPDIF) 390 incompatible_clock = true; 391 break; 392 default: 393 dev_err(chip->card->dev, 394 "Digital mode not supported: %d\n", mode); 395 return -EINVAL; 396 } 397 398 guard(spinlock_irq)(&chip->lock); 399 400 if (incompatible_clock) { 401 chip->sample_rate = 48000; 402 set_input_clock(chip, ECHO_CLOCK_INTERNAL); 403 } 404 405 /* Clear the current digital mode */ 406 control_reg = le32_to_cpu(chip->comm_page->control_register); 407 control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK; 408 409 /* Tweak the control reg */ 410 switch (mode) { 411 case DIGITAL_MODE_SPDIF_OPTICAL: 412 control_reg |= E3G_SPDIF_OPTICAL_MODE; 413 break; 414 case DIGITAL_MODE_SPDIF_RCA: 415 /* E3G_SPDIF_OPTICAL_MODE bit cleared */ 416 break; 417 case DIGITAL_MODE_ADAT: 418 control_reg |= E3G_ADAT_MODE; 419 control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */ 420 break; 421 } 422 423 err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1); 424 if (err < 0) 425 return err; 426 chip->digital_mode = mode; 427 428 dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode); 429 return incompatible_clock; 430 } 431