1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5 6 #include <linux/module.h> 7 #include <linux/types.h> 8 #include <linux/init.h> 9 #include <linux/bitops.h> 10 #include <linux/vmalloc.h> 11 #include <linux/pagemap.h> 12 #include <linux/netdevice.h> 13 #include <linux/ipv6.h> 14 #include <linux/slab.h> 15 #include <net/checksum.h> 16 #include <net/ip6_checksum.h> 17 #include <net/pkt_sched.h> 18 #include <net/pkt_cls.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/sctp.h> 30 #include <linux/if_ether.h> 31 #include <linux/prefetch.h> 32 #include <linux/bpf.h> 33 #include <linux/bpf_trace.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/etherdevice.h> 36 #ifdef CONFIG_IGB_DCA 37 #include <linux/dca.h> 38 #endif 39 #include <linux/i2c.h> 40 #include "igb.h" 41 42 enum queue_mode { 43 QUEUE_MODE_STRICT_PRIORITY, 44 QUEUE_MODE_STREAM_RESERVATION, 45 }; 46 47 enum tx_queue_prio { 48 TX_QUEUE_PRIO_HIGH, 49 TX_QUEUE_PRIO_LOW, 50 }; 51 52 char igb_driver_name[] = "igb"; 53 static const char igb_driver_string[] = 54 "Intel(R) Gigabit Ethernet Network Driver"; 55 static const char igb_copyright[] = 56 "Copyright (c) 2007-2014 Intel Corporation."; 57 58 static const struct e1000_info *igb_info_tbl[] = { 59 [board_82575] = &e1000_82575_info, 60 }; 61 62 static const struct pci_device_id igb_pci_tbl[] = { 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 98 /* required last entry */ 99 {0, } 100 }; 101 102 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 103 104 static int igb_setup_all_tx_resources(struct igb_adapter *); 105 static int igb_setup_all_rx_resources(struct igb_adapter *); 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 static void igb_setup_mrqc(struct igb_adapter *); 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 110 static int igb_sw_init(struct igb_adapter *); 111 int igb_open(struct net_device *); 112 int igb_close(struct net_device *); 113 static void igb_configure(struct igb_adapter *); 114 static void igb_configure_tx(struct igb_adapter *); 115 static void igb_configure_rx(struct igb_adapter *); 116 static void igb_clean_all_tx_rings(struct igb_adapter *); 117 static void igb_clean_all_rx_rings(struct igb_adapter *); 118 static void igb_set_rx_mode(struct net_device *); 119 static void igb_update_phy_info(struct timer_list *); 120 static void igb_watchdog(struct timer_list *); 121 static void igb_watchdog_task(struct work_struct *); 122 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 123 static void igb_get_stats64(struct net_device *dev, 124 struct rtnl_link_stats64 *stats); 125 static int igb_change_mtu(struct net_device *, int); 126 static int igb_set_mac(struct net_device *, void *); 127 static void igb_set_uta(struct igb_adapter *adapter, bool set); 128 static irqreturn_t igb_intr(int irq, void *); 129 static irqreturn_t igb_intr_msi(int irq, void *); 130 static irqreturn_t igb_msix_other(int irq, void *); 131 static irqreturn_t igb_msix_ring(int irq, void *); 132 #ifdef CONFIG_IGB_DCA 133 static void igb_update_dca(struct igb_q_vector *); 134 static void igb_setup_dca(struct igb_adapter *); 135 #endif /* CONFIG_IGB_DCA */ 136 static int igb_poll(struct napi_struct *, int); 137 static bool igb_clean_tx_irq(struct igb_q_vector *, int); 138 static int igb_clean_rx_irq(struct igb_q_vector *, int); 139 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 140 static void igb_tx_timeout(struct net_device *, unsigned int txqueue); 141 static void igb_reset_task(struct work_struct *); 142 static void igb_vlan_mode(struct net_device *netdev, 143 netdev_features_t features); 144 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 145 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 146 static void igb_restore_vlan(struct igb_adapter *); 147 static void igb_rar_set_index(struct igb_adapter *, u32); 148 static void igb_ping_all_vfs(struct igb_adapter *); 149 static void igb_msg_task(struct igb_adapter *); 150 static void igb_vmm_control(struct igb_adapter *); 151 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 152 static void igb_flush_mac_table(struct igb_adapter *); 153 static int igb_available_rars(struct igb_adapter *, u8); 154 static void igb_set_default_mac_filter(struct igb_adapter *); 155 static int igb_uc_sync(struct net_device *, const unsigned char *); 156 static int igb_uc_unsync(struct net_device *, const unsigned char *); 157 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 158 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 159 static int igb_ndo_set_vf_vlan(struct net_device *netdev, 160 int vf, u16 vlan, u8 qos, __be16 vlan_proto); 161 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); 162 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 163 bool setting); 164 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, 165 bool setting); 166 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 167 struct ifla_vf_info *ivi); 168 static void igb_check_vf_rate_limit(struct igb_adapter *); 169 static void igb_nfc_filter_exit(struct igb_adapter *adapter); 170 static void igb_nfc_filter_restore(struct igb_adapter *adapter); 171 172 #ifdef CONFIG_PCI_IOV 173 static int igb_vf_configure(struct igb_adapter *adapter, int vf); 174 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 175 #endif 176 177 #ifdef CONFIG_IGB_DCA 178 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 179 static struct notifier_block dca_notifier = { 180 .notifier_call = igb_notify_dca, 181 .next = NULL, 182 .priority = 0 183 }; 184 #endif 185 #ifdef CONFIG_PCI_IOV 186 static unsigned int max_vfs; 187 module_param(max_vfs, uint, 0444); 188 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 189 #endif /* CONFIG_PCI_IOV */ 190 191 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 192 pci_channel_state_t); 193 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 194 static void igb_io_resume(struct pci_dev *); 195 196 static const struct pci_error_handlers igb_err_handler = { 197 .error_detected = igb_io_error_detected, 198 .slot_reset = igb_io_slot_reset, 199 .resume = igb_io_resume, 200 }; 201 202 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 203 204 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 205 MODULE_LICENSE("GPL v2"); 206 207 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 208 static int debug = -1; 209 module_param(debug, int, 0); 210 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 211 212 struct igb_reg_info { 213 u32 ofs; 214 char *name; 215 }; 216 217 static const struct igb_reg_info igb_reg_info_tbl[] = { 218 219 /* General Registers */ 220 {E1000_CTRL, "CTRL"}, 221 {E1000_STATUS, "STATUS"}, 222 {E1000_CTRL_EXT, "CTRL_EXT"}, 223 224 /* Interrupt Registers */ 225 {E1000_ICR, "ICR"}, 226 227 /* RX Registers */ 228 {E1000_RCTL, "RCTL"}, 229 {E1000_RDLEN(0), "RDLEN"}, 230 {E1000_RDH(0), "RDH"}, 231 {E1000_RDT(0), "RDT"}, 232 {E1000_RXDCTL(0), "RXDCTL"}, 233 {E1000_RDBAL(0), "RDBAL"}, 234 {E1000_RDBAH(0), "RDBAH"}, 235 236 /* TX Registers */ 237 {E1000_TCTL, "TCTL"}, 238 {E1000_TDBAL(0), "TDBAL"}, 239 {E1000_TDBAH(0), "TDBAH"}, 240 {E1000_TDLEN(0), "TDLEN"}, 241 {E1000_TDH(0), "TDH"}, 242 {E1000_TDT(0), "TDT"}, 243 {E1000_TXDCTL(0), "TXDCTL"}, 244 {E1000_TDFH, "TDFH"}, 245 {E1000_TDFT, "TDFT"}, 246 {E1000_TDFHS, "TDFHS"}, 247 {E1000_TDFPC, "TDFPC"}, 248 249 /* List Terminator */ 250 {} 251 }; 252 253 /* igb_regdump - register printout routine */ 254 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 255 { 256 int n = 0; 257 char rname[16]; 258 u32 regs[8]; 259 260 switch (reginfo->ofs) { 261 case E1000_RDLEN(0): 262 for (n = 0; n < 4; n++) 263 regs[n] = rd32(E1000_RDLEN(n)); 264 break; 265 case E1000_RDH(0): 266 for (n = 0; n < 4; n++) 267 regs[n] = rd32(E1000_RDH(n)); 268 break; 269 case E1000_RDT(0): 270 for (n = 0; n < 4; n++) 271 regs[n] = rd32(E1000_RDT(n)); 272 break; 273 case E1000_RXDCTL(0): 274 for (n = 0; n < 4; n++) 275 regs[n] = rd32(E1000_RXDCTL(n)); 276 break; 277 case E1000_RDBAL(0): 278 for (n = 0; n < 4; n++) 279 regs[n] = rd32(E1000_RDBAL(n)); 280 break; 281 case E1000_RDBAH(0): 282 for (n = 0; n < 4; n++) 283 regs[n] = rd32(E1000_RDBAH(n)); 284 break; 285 case E1000_TDBAL(0): 286 for (n = 0; n < 4; n++) 287 regs[n] = rd32(E1000_TDBAL(n)); 288 break; 289 case E1000_TDBAH(0): 290 for (n = 0; n < 4; n++) 291 regs[n] = rd32(E1000_TDBAH(n)); 292 break; 293 case E1000_TDLEN(0): 294 for (n = 0; n < 4; n++) 295 regs[n] = rd32(E1000_TDLEN(n)); 296 break; 297 case E1000_TDH(0): 298 for (n = 0; n < 4; n++) 299 regs[n] = rd32(E1000_TDH(n)); 300 break; 301 case E1000_TDT(0): 302 for (n = 0; n < 4; n++) 303 regs[n] = rd32(E1000_TDT(n)); 304 break; 305 case E1000_TXDCTL(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_TXDCTL(n)); 308 break; 309 default: 310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 311 return; 312 } 313 314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 316 regs[2], regs[3]); 317 } 318 319 /* igb_dump - Print registers, Tx-rings and Rx-rings */ 320 static void igb_dump(struct igb_adapter *adapter) 321 { 322 struct net_device *netdev = adapter->netdev; 323 struct e1000_hw *hw = &adapter->hw; 324 struct igb_reg_info *reginfo; 325 struct igb_ring *tx_ring; 326 union e1000_adv_tx_desc *tx_desc; 327 struct my_u0 { __le64 a; __le64 b; } *u0; 328 struct igb_ring *rx_ring; 329 union e1000_adv_rx_desc *rx_desc; 330 u32 staterr; 331 u16 i, n; 332 333 if (!netif_msg_hw(adapter)) 334 return; 335 336 /* Print netdevice Info */ 337 if (netdev) { 338 dev_info(&adapter->pdev->dev, "Net device Info\n"); 339 pr_info("Device Name state trans_start\n"); 340 pr_info("%-15s %016lX %016lX\n", netdev->name, 341 netdev->state, dev_trans_start(netdev)); 342 } 343 344 /* Print Registers */ 345 dev_info(&adapter->pdev->dev, "Register Dump\n"); 346 pr_info(" Register Name Value\n"); 347 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 348 reginfo->name; reginfo++) { 349 igb_regdump(hw, reginfo); 350 } 351 352 /* Print TX Ring Summary */ 353 if (!netdev || !netif_running(netdev)) 354 goto exit; 355 356 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 357 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 358 for (n = 0; n < adapter->num_tx_queues; n++) { 359 struct igb_tx_buffer *buffer_info; 360 tx_ring = adapter->tx_ring[n]; 361 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 362 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 363 n, tx_ring->next_to_use, tx_ring->next_to_clean, 364 (u64)dma_unmap_addr(buffer_info, dma), 365 dma_unmap_len(buffer_info, len), 366 buffer_info->next_to_watch, 367 (u64)buffer_info->time_stamp); 368 } 369 370 /* Print TX Rings */ 371 if (!netif_msg_tx_done(adapter)) 372 goto rx_ring_summary; 373 374 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 375 376 /* Transmit Descriptor Formats 377 * 378 * Advanced Transmit Descriptor 379 * +--------------------------------------------------------------+ 380 * 0 | Buffer Address [63:0] | 381 * +--------------------------------------------------------------+ 382 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 383 * +--------------------------------------------------------------+ 384 * 63 46 45 40 39 38 36 35 32 31 24 15 0 385 */ 386 387 for (n = 0; n < adapter->num_tx_queues; n++) { 388 tx_ring = adapter->tx_ring[n]; 389 pr_info("------------------------------------\n"); 390 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 391 pr_info("------------------------------------\n"); 392 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 393 394 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 395 const char *next_desc; 396 struct igb_tx_buffer *buffer_info; 397 tx_desc = IGB_TX_DESC(tx_ring, i); 398 buffer_info = &tx_ring->tx_buffer_info[i]; 399 u0 = (struct my_u0 *)tx_desc; 400 if (i == tx_ring->next_to_use && 401 i == tx_ring->next_to_clean) 402 next_desc = " NTC/U"; 403 else if (i == tx_ring->next_to_use) 404 next_desc = " NTU"; 405 else if (i == tx_ring->next_to_clean) 406 next_desc = " NTC"; 407 else 408 next_desc = ""; 409 410 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 411 i, le64_to_cpu(u0->a), 412 le64_to_cpu(u0->b), 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp, 417 buffer_info->skb, next_desc); 418 419 if (netif_msg_pktdata(adapter) && buffer_info->skb) 420 print_hex_dump(KERN_INFO, "", 421 DUMP_PREFIX_ADDRESS, 422 16, 1, buffer_info->skb->data, 423 dma_unmap_len(buffer_info, len), 424 true); 425 } 426 } 427 428 /* Print RX Rings Summary */ 429 rx_ring_summary: 430 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 431 pr_info("Queue [NTU] [NTC]\n"); 432 for (n = 0; n < adapter->num_rx_queues; n++) { 433 rx_ring = adapter->rx_ring[n]; 434 pr_info(" %5d %5X %5X\n", 435 n, rx_ring->next_to_use, rx_ring->next_to_clean); 436 } 437 438 /* Print RX Rings */ 439 if (!netif_msg_rx_status(adapter)) 440 goto exit; 441 442 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 443 444 /* Advanced Receive Descriptor (Read) Format 445 * 63 1 0 446 * +-----------------------------------------------------+ 447 * 0 | Packet Buffer Address [63:1] |A0/NSE| 448 * +----------------------------------------------+------+ 449 * 8 | Header Buffer Address [63:1] | DD | 450 * +-----------------------------------------------------+ 451 * 452 * 453 * Advanced Receive Descriptor (Write-Back) Format 454 * 455 * 63 48 47 32 31 30 21 20 17 16 4 3 0 456 * +------------------------------------------------------+ 457 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 458 * | Checksum Ident | | | | Type | Type | 459 * +------------------------------------------------------+ 460 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 461 * +------------------------------------------------------+ 462 * 63 48 47 32 31 20 19 0 463 */ 464 465 for (n = 0; n < adapter->num_rx_queues; n++) { 466 rx_ring = adapter->rx_ring[n]; 467 pr_info("------------------------------------\n"); 468 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 469 pr_info("------------------------------------\n"); 470 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 471 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 472 473 for (i = 0; i < rx_ring->count; i++) { 474 const char *next_desc; 475 dma_addr_t dma = (dma_addr_t)0; 476 struct igb_rx_buffer *buffer_info = NULL; 477 rx_desc = IGB_RX_DESC(rx_ring, i); 478 u0 = (struct my_u0 *)rx_desc; 479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 480 481 if (!rx_ring->xsk_pool) { 482 buffer_info = &rx_ring->rx_buffer_info[i]; 483 dma = buffer_info->dma; 484 } 485 486 if (i == rx_ring->next_to_use) 487 next_desc = " NTU"; 488 else if (i == rx_ring->next_to_clean) 489 next_desc = " NTC"; 490 else 491 next_desc = ""; 492 493 if (staterr & E1000_RXD_STAT_DD) { 494 /* Descriptor Done */ 495 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 496 "RWB", i, 497 le64_to_cpu(u0->a), 498 le64_to_cpu(u0->b), 499 next_desc); 500 } else { 501 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 502 "R ", i, 503 le64_to_cpu(u0->a), 504 le64_to_cpu(u0->b), 505 (u64)dma, 506 next_desc); 507 508 if (netif_msg_pktdata(adapter) && 509 buffer_info && dma && buffer_info->page) { 510 print_hex_dump(KERN_INFO, "", 511 DUMP_PREFIX_ADDRESS, 512 16, 1, 513 page_address(buffer_info->page) + 514 buffer_info->page_offset, 515 igb_rx_bufsz(rx_ring), true); 516 } 517 } 518 } 519 } 520 521 exit: 522 return; 523 } 524 525 /** 526 * igb_get_i2c_data - Reads the I2C SDA data bit 527 * @data: opaque pointer to adapter struct 528 * 529 * Returns the I2C data bit value 530 **/ 531 static int igb_get_i2c_data(void *data) 532 { 533 struct igb_adapter *adapter = (struct igb_adapter *)data; 534 struct e1000_hw *hw = &adapter->hw; 535 s32 i2cctl = rd32(E1000_I2CPARAMS); 536 537 return !!(i2cctl & E1000_I2C_DATA_IN); 538 } 539 540 /** 541 * igb_set_i2c_data - Sets the I2C data bit 542 * @data: pointer to hardware structure 543 * @state: I2C data value (0 or 1) to set 544 * 545 * Sets the I2C data bit 546 **/ 547 static void igb_set_i2c_data(void *data, int state) 548 { 549 struct igb_adapter *adapter = (struct igb_adapter *)data; 550 struct e1000_hw *hw = &adapter->hw; 551 s32 i2cctl = rd32(E1000_I2CPARAMS); 552 553 if (state) { 554 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N; 555 } else { 556 i2cctl &= ~E1000_I2C_DATA_OE_N; 557 i2cctl &= ~E1000_I2C_DATA_OUT; 558 } 559 560 wr32(E1000_I2CPARAMS, i2cctl); 561 wrfl(); 562 } 563 564 /** 565 * igb_set_i2c_clk - Sets the I2C SCL clock 566 * @data: pointer to hardware structure 567 * @state: state to set clock 568 * 569 * Sets the I2C clock line to state 570 **/ 571 static void igb_set_i2c_clk(void *data, int state) 572 { 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 if (state) { 578 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N; 579 } else { 580 i2cctl &= ~E1000_I2C_CLK_OUT; 581 i2cctl &= ~E1000_I2C_CLK_OE_N; 582 } 583 wr32(E1000_I2CPARAMS, i2cctl); 584 wrfl(); 585 } 586 587 /** 588 * igb_get_i2c_clk - Gets the I2C SCL clock state 589 * @data: pointer to hardware structure 590 * 591 * Gets the I2C clock state 592 **/ 593 static int igb_get_i2c_clk(void *data) 594 { 595 struct igb_adapter *adapter = (struct igb_adapter *)data; 596 struct e1000_hw *hw = &adapter->hw; 597 s32 i2cctl = rd32(E1000_I2CPARAMS); 598 599 return !!(i2cctl & E1000_I2C_CLK_IN); 600 } 601 602 static const struct i2c_algo_bit_data igb_i2c_algo = { 603 .setsda = igb_set_i2c_data, 604 .setscl = igb_set_i2c_clk, 605 .getsda = igb_get_i2c_data, 606 .getscl = igb_get_i2c_clk, 607 .udelay = 5, 608 .timeout = 20, 609 }; 610 611 /** 612 * igb_get_hw_dev - return device 613 * @hw: pointer to hardware structure 614 * 615 * used by hardware layer to print debugging information 616 **/ 617 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 618 { 619 struct igb_adapter *adapter = hw->back; 620 return adapter->netdev; 621 } 622 623 static struct pci_driver igb_driver; 624 625 /** 626 * igb_init_module - Driver Registration Routine 627 * 628 * igb_init_module is the first routine called when the driver is 629 * loaded. All it does is register with the PCI subsystem. 630 **/ 631 static int __init igb_init_module(void) 632 { 633 int ret; 634 635 pr_info("%s\n", igb_driver_string); 636 pr_info("%s\n", igb_copyright); 637 638 #ifdef CONFIG_IGB_DCA 639 dca_register_notify(&dca_notifier); 640 #endif 641 ret = pci_register_driver(&igb_driver); 642 #ifdef CONFIG_IGB_DCA 643 if (ret) 644 dca_unregister_notify(&dca_notifier); 645 #endif 646 return ret; 647 } 648 649 module_init(igb_init_module); 650 651 /** 652 * igb_exit_module - Driver Exit Cleanup Routine 653 * 654 * igb_exit_module is called just before the driver is removed 655 * from memory. 656 **/ 657 static void __exit igb_exit_module(void) 658 { 659 #ifdef CONFIG_IGB_DCA 660 dca_unregister_notify(&dca_notifier); 661 #endif 662 pci_unregister_driver(&igb_driver); 663 } 664 665 module_exit(igb_exit_module); 666 667 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 668 /** 669 * igb_cache_ring_register - Descriptor ring to register mapping 670 * @adapter: board private structure to initialize 671 * 672 * Once we know the feature-set enabled for the device, we'll cache 673 * the register offset the descriptor ring is assigned to. 674 **/ 675 static void igb_cache_ring_register(struct igb_adapter *adapter) 676 { 677 int i = 0, j = 0; 678 u32 rbase_offset = adapter->vfs_allocated_count; 679 680 switch (adapter->hw.mac.type) { 681 case e1000_82576: 682 /* The queues are allocated for virtualization such that VF 0 683 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 684 * In order to avoid collision we start at the first free queue 685 * and continue consuming queues in the same sequence 686 */ 687 if (adapter->vfs_allocated_count) { 688 for (; i < adapter->rss_queues; i++) 689 adapter->rx_ring[i]->reg_idx = rbase_offset + 690 Q_IDX_82576(i); 691 } 692 fallthrough; 693 case e1000_82575: 694 case e1000_82580: 695 case e1000_i350: 696 case e1000_i354: 697 case e1000_i210: 698 case e1000_i211: 699 default: 700 for (; i < adapter->num_rx_queues; i++) 701 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 702 for (; j < adapter->num_tx_queues; j++) 703 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 704 break; 705 } 706 } 707 708 u32 igb_rd32(struct e1000_hw *hw, u32 reg) 709 { 710 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 711 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 712 u32 value = 0; 713 714 if (E1000_REMOVED(hw_addr)) 715 return ~value; 716 717 value = readl(&hw_addr[reg]); 718 719 /* reads should not return all F's */ 720 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 721 struct net_device *netdev = igb->netdev; 722 hw->hw_addr = NULL; 723 netdev_err(netdev, "PCIe link lost\n"); 724 WARN(pci_device_is_present(igb->pdev), 725 "igb: Failed to read reg 0x%x!\n", reg); 726 } 727 728 return value; 729 } 730 731 /** 732 * igb_write_ivar - configure ivar for given MSI-X vector 733 * @hw: pointer to the HW structure 734 * @msix_vector: vector number we are allocating to a given ring 735 * @index: row index of IVAR register to write within IVAR table 736 * @offset: column offset of in IVAR, should be multiple of 8 737 * 738 * This function is intended to handle the writing of the IVAR register 739 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 740 * each containing an cause allocation for an Rx and Tx ring, and a 741 * variable number of rows depending on the number of queues supported. 742 **/ 743 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 744 int index, int offset) 745 { 746 u32 ivar = array_rd32(E1000_IVAR0, index); 747 748 /* clear any bits that are currently set */ 749 ivar &= ~((u32)0xFF << offset); 750 751 /* write vector and valid bit */ 752 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 753 754 array_wr32(E1000_IVAR0, index, ivar); 755 } 756 757 #define IGB_N0_QUEUE -1 758 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 759 { 760 struct igb_adapter *adapter = q_vector->adapter; 761 struct e1000_hw *hw = &adapter->hw; 762 int rx_queue = IGB_N0_QUEUE; 763 int tx_queue = IGB_N0_QUEUE; 764 u32 msixbm = 0; 765 766 if (q_vector->rx.ring) 767 rx_queue = q_vector->rx.ring->reg_idx; 768 if (q_vector->tx.ring) 769 tx_queue = q_vector->tx.ring->reg_idx; 770 771 switch (hw->mac.type) { 772 case e1000_82575: 773 /* The 82575 assigns vectors using a bitmask, which matches the 774 * bitmask for the EICR/EIMS/EIMC registers. To assign one 775 * or more queues to a vector, we write the appropriate bits 776 * into the MSIXBM register for that vector. 777 */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 82576 uses a table that essentially consists of 2 columns 789 * with 8 rows. The ordering is column-major so we use the 790 * lower 3 bits as the row index, and the 4th bit as the 791 * column offset. 792 */ 793 if (rx_queue > IGB_N0_QUEUE) 794 igb_write_ivar(hw, msix_vector, 795 rx_queue & 0x7, 796 (rx_queue & 0x8) << 1); 797 if (tx_queue > IGB_N0_QUEUE) 798 igb_write_ivar(hw, msix_vector, 799 tx_queue & 0x7, 800 ((tx_queue & 0x8) << 1) + 8); 801 q_vector->eims_value = BIT(msix_vector); 802 break; 803 case e1000_82580: 804 case e1000_i350: 805 case e1000_i354: 806 case e1000_i210: 807 case e1000_i211: 808 /* On 82580 and newer adapters the scheme is similar to 82576 809 * however instead of ordering column-major we have things 810 * ordered row-major. So we traverse the table by using 811 * bit 0 as the column offset, and the remaining bits as the 812 * row index. 813 */ 814 if (rx_queue > IGB_N0_QUEUE) 815 igb_write_ivar(hw, msix_vector, 816 rx_queue >> 1, 817 (rx_queue & 0x1) << 4); 818 if (tx_queue > IGB_N0_QUEUE) 819 igb_write_ivar(hw, msix_vector, 820 tx_queue >> 1, 821 ((tx_queue & 0x1) << 4) + 8); 822 q_vector->eims_value = BIT(msix_vector); 823 break; 824 default: 825 BUG(); 826 break; 827 } 828 829 /* add q_vector eims value to global eims_enable_mask */ 830 adapter->eims_enable_mask |= q_vector->eims_value; 831 832 /* configure q_vector to set itr on first interrupt */ 833 q_vector->set_itr = 1; 834 } 835 836 /** 837 * igb_configure_msix - Configure MSI-X hardware 838 * @adapter: board private structure to initialize 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843 static void igb_configure_msix(struct igb_adapter *adapter) 844 { 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 866 adapter->eims_other = E1000_EIMS_OTHER; 867 868 break; 869 870 case e1000_82576: 871 case e1000_82580: 872 case e1000_i350: 873 case e1000_i354: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. 878 */ 879 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 880 E1000_GPIE_PBA | E1000_GPIE_EIAME | 881 E1000_GPIE_NSICR); 882 883 /* enable msix_other interrupt */ 884 adapter->eims_other = BIT(vector); 885 tmp = (vector++ | E1000_IVAR_VALID) << 8; 886 887 wr32(E1000_IVAR_MISC, tmp); 888 break; 889 default: 890 /* do nothing, since nothing else supports MSI-X */ 891 break; 892 } /* switch (hw->mac.type) */ 893 894 adapter->eims_enable_mask |= adapter->eims_other; 895 896 for (i = 0; i < adapter->num_q_vectors; i++) 897 igb_assign_vector(adapter->q_vector[i], vector++); 898 899 wrfl(); 900 } 901 902 /** 903 * igb_request_msix - Initialize MSI-X interrupts 904 * @adapter: board private structure to initialize 905 * 906 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 907 * kernel. 908 **/ 909 static int igb_request_msix(struct igb_adapter *adapter) 910 { 911 unsigned int num_q_vectors = adapter->num_q_vectors; 912 struct net_device *netdev = adapter->netdev; 913 int i, err = 0, vector = 0, free_vector = 0; 914 915 err = request_irq(adapter->msix_entries[vector].vector, 916 igb_msix_other, 0, netdev->name, adapter); 917 if (err) 918 goto err_out; 919 920 if (num_q_vectors > MAX_Q_VECTORS) { 921 num_q_vectors = MAX_Q_VECTORS; 922 dev_warn(&adapter->pdev->dev, 923 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 924 adapter->num_q_vectors, MAX_Q_VECTORS); 925 } 926 for (i = 0; i < num_q_vectors; i++) { 927 struct igb_q_vector *q_vector = adapter->q_vector[i]; 928 929 vector++; 930 931 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector); 932 933 if (q_vector->rx.ring && q_vector->tx.ring) 934 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 935 q_vector->rx.ring->queue_index); 936 else if (q_vector->tx.ring) 937 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 938 q_vector->tx.ring->queue_index); 939 else if (q_vector->rx.ring) 940 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 941 q_vector->rx.ring->queue_index); 942 else 943 sprintf(q_vector->name, "%s-unused", netdev->name); 944 945 err = request_irq(adapter->msix_entries[vector].vector, 946 igb_msix_ring, 0, q_vector->name, 947 q_vector); 948 if (err) 949 goto err_free; 950 951 netif_napi_set_irq(&q_vector->napi, 952 adapter->msix_entries[vector].vector); 953 } 954 955 igb_configure_msix(adapter); 956 return 0; 957 958 err_free: 959 /* free already assigned IRQs */ 960 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 961 962 vector--; 963 for (i = 0; i < vector; i++) { 964 free_irq(adapter->msix_entries[free_vector++].vector, 965 adapter->q_vector[i]); 966 } 967 err_out: 968 return err; 969 } 970 971 /** 972 * igb_free_q_vector - Free memory allocated for specific interrupt vector 973 * @adapter: board private structure to initialize 974 * @v_idx: Index of vector to be freed 975 * 976 * This function frees the memory allocated to the q_vector. 977 **/ 978 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 979 { 980 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 981 982 adapter->q_vector[v_idx] = NULL; 983 984 /* igb_get_stats64() might access the rings on this vector, 985 * we must wait a grace period before freeing it. 986 */ 987 if (q_vector) 988 kfree_rcu(q_vector, rcu); 989 } 990 991 /** 992 * igb_reset_q_vector - Reset config for interrupt vector 993 * @adapter: board private structure to initialize 994 * @v_idx: Index of vector to be reset 995 * 996 * If NAPI is enabled it will delete any references to the 997 * NAPI struct. This is preparation for igb_free_q_vector. 998 **/ 999 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1000 { 1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1002 1003 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1004 * allocated. So, q_vector is NULL so we should stop here. 1005 */ 1006 if (!q_vector) 1007 return; 1008 1009 if (q_vector->tx.ring) 1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1011 1012 if (q_vector->rx.ring) 1013 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 1014 1015 netif_napi_del(&q_vector->napi); 1016 1017 } 1018 1019 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1020 { 1021 int v_idx = adapter->num_q_vectors; 1022 1023 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1024 pci_disable_msix(adapter->pdev); 1025 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1026 pci_disable_msi(adapter->pdev); 1027 1028 while (v_idx--) 1029 igb_reset_q_vector(adapter, v_idx); 1030 } 1031 1032 /** 1033 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1034 * @adapter: board private structure to initialize 1035 * 1036 * This function frees the memory allocated to the q_vectors. In addition if 1037 * NAPI is enabled it will delete any references to the NAPI struct prior 1038 * to freeing the q_vector. 1039 **/ 1040 static void igb_free_q_vectors(struct igb_adapter *adapter) 1041 { 1042 int v_idx = adapter->num_q_vectors; 1043 1044 adapter->num_tx_queues = 0; 1045 adapter->num_rx_queues = 0; 1046 adapter->num_q_vectors = 0; 1047 1048 while (v_idx--) { 1049 igb_reset_q_vector(adapter, v_idx); 1050 igb_free_q_vector(adapter, v_idx); 1051 } 1052 } 1053 1054 /** 1055 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1056 * @adapter: board private structure to initialize 1057 * 1058 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1059 * MSI-X interrupts allocated. 1060 */ 1061 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1062 { 1063 igb_free_q_vectors(adapter); 1064 igb_reset_interrupt_capability(adapter); 1065 } 1066 1067 /** 1068 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1069 * @adapter: board private structure to initialize 1070 * @msix: boolean value of MSIX capability 1071 * 1072 * Attempt to configure interrupts using the best available 1073 * capabilities of the hardware and kernel. 1074 **/ 1075 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1076 { 1077 int err; 1078 int numvecs, i; 1079 1080 if (!msix) 1081 goto msi_only; 1082 adapter->flags |= IGB_FLAG_HAS_MSIX; 1083 1084 /* Number of supported queues. */ 1085 adapter->num_rx_queues = adapter->rss_queues; 1086 if (adapter->vfs_allocated_count) 1087 adapter->num_tx_queues = 1; 1088 else 1089 adapter->num_tx_queues = adapter->rss_queues; 1090 1091 /* start with one vector for every Rx queue */ 1092 numvecs = adapter->num_rx_queues; 1093 1094 /* if Tx handler is separate add 1 for every Tx queue */ 1095 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1096 numvecs += adapter->num_tx_queues; 1097 1098 /* store the number of vectors reserved for queues */ 1099 adapter->num_q_vectors = numvecs; 1100 1101 /* add 1 vector for link status interrupts */ 1102 numvecs++; 1103 for (i = 0; i < numvecs; i++) 1104 adapter->msix_entries[i].entry = i; 1105 1106 err = pci_enable_msix_range(adapter->pdev, 1107 adapter->msix_entries, 1108 numvecs, 1109 numvecs); 1110 if (err > 0) 1111 return; 1112 1113 igb_reset_interrupt_capability(adapter); 1114 1115 /* If we can't do MSI-X, try MSI */ 1116 msi_only: 1117 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1118 #ifdef CONFIG_PCI_IOV 1119 /* disable SR-IOV for non MSI-X configurations */ 1120 if (adapter->vf_data) { 1121 struct e1000_hw *hw = &adapter->hw; 1122 /* disable iov and allow time for transactions to clear */ 1123 pci_disable_sriov(adapter->pdev); 1124 msleep(500); 1125 1126 kfree(adapter->vf_mac_list); 1127 adapter->vf_mac_list = NULL; 1128 kfree(adapter->vf_data); 1129 adapter->vf_data = NULL; 1130 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1131 wrfl(); 1132 msleep(100); 1133 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1134 } 1135 #endif 1136 adapter->vfs_allocated_count = 0; 1137 adapter->rss_queues = 1; 1138 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1139 adapter->num_rx_queues = 1; 1140 adapter->num_tx_queues = 1; 1141 adapter->num_q_vectors = 1; 1142 if (!pci_enable_msi(adapter->pdev)) 1143 adapter->flags |= IGB_FLAG_HAS_MSI; 1144 } 1145 1146 static void igb_add_ring(struct igb_ring *ring, 1147 struct igb_ring_container *head) 1148 { 1149 head->ring = ring; 1150 head->count++; 1151 } 1152 1153 /** 1154 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1155 * @adapter: board private structure to initialize 1156 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1157 * @v_idx: index of vector in adapter struct 1158 * @txr_count: total number of Tx rings to allocate 1159 * @txr_idx: index of first Tx ring to allocate 1160 * @rxr_count: total number of Rx rings to allocate 1161 * @rxr_idx: index of first Rx ring to allocate 1162 * 1163 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1164 **/ 1165 static int igb_alloc_q_vector(struct igb_adapter *adapter, 1166 int v_count, int v_idx, 1167 int txr_count, int txr_idx, 1168 int rxr_count, int rxr_idx) 1169 { 1170 struct igb_q_vector *q_vector; 1171 struct igb_ring *ring; 1172 int ring_count; 1173 size_t size; 1174 1175 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1176 if (txr_count > 1 || rxr_count > 1) 1177 return -ENOMEM; 1178 1179 ring_count = txr_count + rxr_count; 1180 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count)); 1181 1182 /* allocate q_vector and rings */ 1183 q_vector = adapter->q_vector[v_idx]; 1184 if (!q_vector) { 1185 q_vector = kzalloc(size, GFP_KERNEL); 1186 } else if (size > ksize(q_vector)) { 1187 struct igb_q_vector *new_q_vector; 1188 1189 new_q_vector = kzalloc(size, GFP_KERNEL); 1190 if (new_q_vector) 1191 kfree_rcu(q_vector, rcu); 1192 q_vector = new_q_vector; 1193 } else { 1194 memset(q_vector, 0, size); 1195 } 1196 if (!q_vector) 1197 return -ENOMEM; 1198 1199 /* initialize NAPI */ 1200 netif_napi_add_config(adapter->netdev, &q_vector->napi, igb_poll, 1201 v_idx); 1202 1203 /* tie q_vector and adapter together */ 1204 adapter->q_vector[v_idx] = q_vector; 1205 q_vector->adapter = adapter; 1206 1207 /* initialize work limits */ 1208 q_vector->tx.work_limit = adapter->tx_work_limit; 1209 1210 /* initialize ITR configuration */ 1211 q_vector->itr_register = adapter->io_addr + E1000_EITR(0); 1212 q_vector->itr_val = IGB_START_ITR; 1213 1214 /* initialize pointer to rings */ 1215 ring = q_vector->ring; 1216 1217 /* initialize ITR */ 1218 if (rxr_count) { 1219 /* rx or rx/tx vector */ 1220 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1221 q_vector->itr_val = adapter->rx_itr_setting; 1222 } else { 1223 /* tx only vector */ 1224 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1225 q_vector->itr_val = adapter->tx_itr_setting; 1226 } 1227 1228 if (txr_count) { 1229 /* assign generic ring traits */ 1230 ring->dev = &adapter->pdev->dev; 1231 ring->netdev = adapter->netdev; 1232 1233 /* configure backlink on ring */ 1234 ring->q_vector = q_vector; 1235 1236 /* update q_vector Tx values */ 1237 igb_add_ring(ring, &q_vector->tx); 1238 1239 /* For 82575, context index must be unique per ring. */ 1240 if (adapter->hw.mac.type == e1000_82575) 1241 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1242 1243 /* apply Tx specific ring traits */ 1244 ring->count = adapter->tx_ring_count; 1245 ring->queue_index = txr_idx; 1246 1247 ring->cbs_enable = false; 1248 ring->idleslope = 0; 1249 ring->sendslope = 0; 1250 ring->hicredit = 0; 1251 ring->locredit = 0; 1252 1253 u64_stats_init(&ring->tx_syncp); 1254 u64_stats_init(&ring->tx_syncp2); 1255 1256 /* assign ring to adapter */ 1257 adapter->tx_ring[txr_idx] = ring; 1258 1259 /* push pointer to next ring */ 1260 ring++; 1261 } 1262 1263 if (rxr_count) { 1264 /* assign generic ring traits */ 1265 ring->dev = &adapter->pdev->dev; 1266 ring->netdev = adapter->netdev; 1267 1268 /* configure backlink on ring */ 1269 ring->q_vector = q_vector; 1270 1271 /* update q_vector Rx values */ 1272 igb_add_ring(ring, &q_vector->rx); 1273 1274 /* set flag indicating ring supports SCTP checksum offload */ 1275 if (adapter->hw.mac.type >= e1000_82576) 1276 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1277 1278 /* On i350, i354, i210, and i211, loopback VLAN packets 1279 * have the tag byte-swapped. 1280 */ 1281 if (adapter->hw.mac.type >= e1000_i350) 1282 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1283 1284 /* apply Rx specific ring traits */ 1285 ring->count = adapter->rx_ring_count; 1286 ring->queue_index = rxr_idx; 1287 1288 u64_stats_init(&ring->rx_syncp); 1289 1290 /* assign ring to adapter */ 1291 adapter->rx_ring[rxr_idx] = ring; 1292 } 1293 1294 return 0; 1295 } 1296 1297 1298 /** 1299 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1300 * @adapter: board private structure to initialize 1301 * 1302 * We allocate one q_vector per queue interrupt. If allocation fails we 1303 * return -ENOMEM. 1304 **/ 1305 static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1306 { 1307 int q_vectors = adapter->num_q_vectors; 1308 int rxr_remaining = adapter->num_rx_queues; 1309 int txr_remaining = adapter->num_tx_queues; 1310 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1311 int err; 1312 1313 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1314 for (; rxr_remaining; v_idx++) { 1315 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1316 0, 0, 1, rxr_idx); 1317 1318 if (err) 1319 goto err_out; 1320 1321 /* update counts and index */ 1322 rxr_remaining--; 1323 rxr_idx++; 1324 } 1325 } 1326 1327 for (; v_idx < q_vectors; v_idx++) { 1328 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1329 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1330 1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1332 tqpv, txr_idx, rqpv, rxr_idx); 1333 1334 if (err) 1335 goto err_out; 1336 1337 /* update counts and index */ 1338 rxr_remaining -= rqpv; 1339 txr_remaining -= tqpv; 1340 rxr_idx++; 1341 txr_idx++; 1342 } 1343 1344 return 0; 1345 1346 err_out: 1347 adapter->num_tx_queues = 0; 1348 adapter->num_rx_queues = 0; 1349 adapter->num_q_vectors = 0; 1350 1351 while (v_idx--) 1352 igb_free_q_vector(adapter, v_idx); 1353 1354 return -ENOMEM; 1355 } 1356 1357 /** 1358 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1359 * @adapter: board private structure to initialize 1360 * @msix: boolean value of MSIX capability 1361 * 1362 * This function initializes the interrupts and allocates all of the queues. 1363 **/ 1364 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1365 { 1366 struct pci_dev *pdev = adapter->pdev; 1367 int err; 1368 1369 igb_set_interrupt_capability(adapter, msix); 1370 1371 err = igb_alloc_q_vectors(adapter); 1372 if (err) { 1373 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1374 goto err_alloc_q_vectors; 1375 } 1376 1377 igb_cache_ring_register(adapter); 1378 1379 return 0; 1380 1381 err_alloc_q_vectors: 1382 igb_reset_interrupt_capability(adapter); 1383 return err; 1384 } 1385 1386 /** 1387 * igb_request_irq - initialize interrupts 1388 * @adapter: board private structure to initialize 1389 * 1390 * Attempts to configure interrupts using the best available 1391 * capabilities of the hardware and kernel. 1392 **/ 1393 static int igb_request_irq(struct igb_adapter *adapter) 1394 { 1395 struct net_device *netdev = adapter->netdev; 1396 struct pci_dev *pdev = adapter->pdev; 1397 int err = 0; 1398 1399 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1400 err = igb_request_msix(adapter); 1401 if (!err) 1402 goto request_done; 1403 /* fall back to MSI */ 1404 igb_free_all_tx_resources(adapter); 1405 igb_free_all_rx_resources(adapter); 1406 1407 igb_clear_interrupt_scheme(adapter); 1408 err = igb_init_interrupt_scheme(adapter, false); 1409 if (err) 1410 goto request_done; 1411 1412 igb_setup_all_tx_resources(adapter); 1413 igb_setup_all_rx_resources(adapter); 1414 igb_configure(adapter); 1415 } 1416 1417 igb_assign_vector(adapter->q_vector[0], 0); 1418 1419 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1420 err = request_irq(pdev->irq, igb_intr_msi, 0, 1421 netdev->name, adapter); 1422 if (!err) 1423 goto request_done; 1424 1425 /* fall back to legacy interrupts */ 1426 igb_reset_interrupt_capability(adapter); 1427 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1428 } 1429 1430 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1431 netdev->name, adapter); 1432 1433 if (err) 1434 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1435 err); 1436 1437 request_done: 1438 return err; 1439 } 1440 1441 static void igb_free_irq(struct igb_adapter *adapter) 1442 { 1443 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1444 int vector = 0, i; 1445 1446 free_irq(adapter->msix_entries[vector++].vector, adapter); 1447 1448 for (i = 0; i < adapter->num_q_vectors; i++) 1449 free_irq(adapter->msix_entries[vector++].vector, 1450 adapter->q_vector[i]); 1451 } else { 1452 free_irq(adapter->pdev->irq, adapter); 1453 } 1454 } 1455 1456 /** 1457 * igb_irq_disable - Mask off interrupt generation on the NIC 1458 * @adapter: board private structure 1459 **/ 1460 static void igb_irq_disable(struct igb_adapter *adapter) 1461 { 1462 struct e1000_hw *hw = &adapter->hw; 1463 1464 /* we need to be careful when disabling interrupts. The VFs are also 1465 * mapped into these registers and so clearing the bits can cause 1466 * issues on the VF drivers so we only need to clear what we set 1467 */ 1468 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1469 u32 regval = rd32(E1000_EIAM); 1470 1471 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1472 wr32(E1000_EIMC, adapter->eims_enable_mask); 1473 regval = rd32(E1000_EIAC); 1474 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1475 } 1476 1477 wr32(E1000_IAM, 0); 1478 wr32(E1000_IMC, ~0); 1479 wrfl(); 1480 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1481 int i; 1482 1483 for (i = 0; i < adapter->num_q_vectors; i++) 1484 synchronize_irq(adapter->msix_entries[i].vector); 1485 } else { 1486 synchronize_irq(adapter->pdev->irq); 1487 } 1488 } 1489 1490 /** 1491 * igb_irq_enable - Enable default interrupt generation settings 1492 * @adapter: board private structure 1493 **/ 1494 static void igb_irq_enable(struct igb_adapter *adapter) 1495 { 1496 struct e1000_hw *hw = &adapter->hw; 1497 1498 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1499 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1500 u32 regval = rd32(E1000_EIAC); 1501 1502 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1503 regval = rd32(E1000_EIAM); 1504 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1505 wr32(E1000_EIMS, adapter->eims_enable_mask); 1506 if (adapter->vfs_allocated_count) { 1507 wr32(E1000_MBVFIMR, 0xFF); 1508 ims |= E1000_IMS_VMMB; 1509 } 1510 wr32(E1000_IMS, ims); 1511 } else { 1512 wr32(E1000_IMS, IMS_ENABLE_MASK | 1513 E1000_IMS_DRSTA); 1514 wr32(E1000_IAM, IMS_ENABLE_MASK | 1515 E1000_IMS_DRSTA); 1516 } 1517 } 1518 1519 static void igb_update_mng_vlan(struct igb_adapter *adapter) 1520 { 1521 struct e1000_hw *hw = &adapter->hw; 1522 u16 pf_id = adapter->vfs_allocated_count; 1523 u16 vid = adapter->hw.mng_cookie.vlan_id; 1524 u16 old_vid = adapter->mng_vlan_id; 1525 1526 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1527 /* add VID to filter table */ 1528 igb_vfta_set(hw, vid, pf_id, true, true); 1529 adapter->mng_vlan_id = vid; 1530 } else { 1531 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1532 } 1533 1534 if (old_vid != IGB_MNG_VLAN_NONE && vid != old_vid && 1535 !test_bit(old_vid, adapter->active_vlans)) { 1536 /* remove VID from filter table */ 1537 igb_vfta_set(hw, vid, pf_id, false, true); 1538 } 1539 } 1540 1541 /** 1542 * igb_release_hw_control - release control of the h/w to f/w 1543 * @adapter: address of board private structure 1544 * 1545 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1546 * For ASF and Pass Through versions of f/w this means that the 1547 * driver is no longer loaded. 1548 **/ 1549 static void igb_release_hw_control(struct igb_adapter *adapter) 1550 { 1551 struct e1000_hw *hw = &adapter->hw; 1552 u32 ctrl_ext; 1553 1554 /* Let firmware take over control of h/w */ 1555 ctrl_ext = rd32(E1000_CTRL_EXT); 1556 wr32(E1000_CTRL_EXT, 1557 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1558 } 1559 1560 /** 1561 * igb_get_hw_control - get control of the h/w from f/w 1562 * @adapter: address of board private structure 1563 * 1564 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1565 * For ASF and Pass Through versions of f/w this means that 1566 * the driver is loaded. 1567 **/ 1568 static void igb_get_hw_control(struct igb_adapter *adapter) 1569 { 1570 struct e1000_hw *hw = &adapter->hw; 1571 u32 ctrl_ext; 1572 1573 /* Let firmware know the driver has taken over */ 1574 ctrl_ext = rd32(E1000_CTRL_EXT); 1575 wr32(E1000_CTRL_EXT, 1576 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1577 } 1578 1579 static void enable_fqtss(struct igb_adapter *adapter, bool enable) 1580 { 1581 struct net_device *netdev = adapter->netdev; 1582 struct e1000_hw *hw = &adapter->hw; 1583 1584 WARN_ON(hw->mac.type != e1000_i210); 1585 1586 if (enable) 1587 adapter->flags |= IGB_FLAG_FQTSS; 1588 else 1589 adapter->flags &= ~IGB_FLAG_FQTSS; 1590 1591 if (netif_running(netdev)) 1592 schedule_work(&adapter->reset_task); 1593 } 1594 1595 static bool is_fqtss_enabled(struct igb_adapter *adapter) 1596 { 1597 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false; 1598 } 1599 1600 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue, 1601 enum tx_queue_prio prio) 1602 { 1603 u32 val; 1604 1605 WARN_ON(hw->mac.type != e1000_i210); 1606 WARN_ON(queue < 0 || queue > 4); 1607 1608 val = rd32(E1000_I210_TXDCTL(queue)); 1609 1610 if (prio == TX_QUEUE_PRIO_HIGH) 1611 val |= E1000_TXDCTL_PRIORITY; 1612 else 1613 val &= ~E1000_TXDCTL_PRIORITY; 1614 1615 wr32(E1000_I210_TXDCTL(queue), val); 1616 } 1617 1618 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode) 1619 { 1620 u32 val; 1621 1622 WARN_ON(hw->mac.type != e1000_i210); 1623 WARN_ON(queue < 0 || queue > 1); 1624 1625 val = rd32(E1000_I210_TQAVCC(queue)); 1626 1627 if (mode == QUEUE_MODE_STREAM_RESERVATION) 1628 val |= E1000_TQAVCC_QUEUEMODE; 1629 else 1630 val &= ~E1000_TQAVCC_QUEUEMODE; 1631 1632 wr32(E1000_I210_TQAVCC(queue), val); 1633 } 1634 1635 static bool is_any_cbs_enabled(struct igb_adapter *adapter) 1636 { 1637 int i; 1638 1639 for (i = 0; i < adapter->num_tx_queues; i++) { 1640 if (adapter->tx_ring[i]->cbs_enable) 1641 return true; 1642 } 1643 1644 return false; 1645 } 1646 1647 static bool is_any_txtime_enabled(struct igb_adapter *adapter) 1648 { 1649 int i; 1650 1651 for (i = 0; i < adapter->num_tx_queues; i++) { 1652 if (adapter->tx_ring[i]->launchtime_enable) 1653 return true; 1654 } 1655 1656 return false; 1657 } 1658 1659 /** 1660 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1661 * @adapter: pointer to adapter struct 1662 * @queue: queue number 1663 * 1664 * Configure CBS and Launchtime for a given hardware queue. 1665 * Parameters are retrieved from the correct Tx ring, so 1666 * igb_save_cbs_params() and igb_save_txtime_params() should be used 1667 * for setting those correctly prior to this function being called. 1668 **/ 1669 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1670 { 1671 struct net_device *netdev = adapter->netdev; 1672 struct e1000_hw *hw = &adapter->hw; 1673 struct igb_ring *ring; 1674 u32 tqavcc, tqavctrl; 1675 u16 value; 1676 1677 WARN_ON(hw->mac.type != e1000_i210); 1678 WARN_ON(queue < 0 || queue > 1); 1679 ring = adapter->tx_ring[queue]; 1680 1681 /* If any of the Qav features is enabled, configure queues as SR and 1682 * with HIGH PRIO. If none is, then configure them with LOW PRIO and 1683 * as SP. 1684 */ 1685 if (ring->cbs_enable || ring->launchtime_enable) { 1686 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH); 1687 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION); 1688 } else { 1689 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW); 1690 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY); 1691 } 1692 1693 /* If CBS is enabled, set DataTranARB and config its parameters. */ 1694 if (ring->cbs_enable || queue == 0) { 1695 /* i210 does not allow the queue 0 to be in the Strict 1696 * Priority mode while the Qav mode is enabled, so, 1697 * instead of disabling strict priority mode, we give 1698 * queue 0 the maximum of credits possible. 1699 * 1700 * See section 8.12.19 of the i210 datasheet, "Note: 1701 * Queue0 QueueMode must be set to 1b when 1702 * TransmitMode is set to Qav." 1703 */ 1704 if (queue == 0 && !ring->cbs_enable) { 1705 /* max "linkspeed" idleslope in kbps */ 1706 ring->idleslope = 1000000; 1707 ring->hicredit = ETH_FRAME_LEN; 1708 } 1709 1710 /* Always set data transfer arbitration to credit-based 1711 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1712 * the queues. 1713 */ 1714 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1715 tqavctrl |= E1000_TQAVCTRL_DATATRANARB; 1716 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1717 1718 /* According to i210 datasheet section 7.2.7.7, we should set 1719 * the 'idleSlope' field from TQAVCC register following the 1720 * equation: 1721 * 1722 * For 100 Mbps link speed: 1723 * 1724 * value = BW * 0x7735 * 0.2 (E1) 1725 * 1726 * For 1000Mbps link speed: 1727 * 1728 * value = BW * 0x7735 * 2 (E2) 1729 * 1730 * E1 and E2 can be merged into one equation as shown below. 1731 * Note that 'link-speed' is in Mbps. 1732 * 1733 * value = BW * 0x7735 * 2 * link-speed 1734 * -------------- (E3) 1735 * 1000 1736 * 1737 * 'BW' is the percentage bandwidth out of full link speed 1738 * which can be found with the following equation. Note that 1739 * idleSlope here is the parameter from this function which 1740 * is in kbps. 1741 * 1742 * BW = idleSlope 1743 * ----------------- (E4) 1744 * link-speed * 1000 1745 * 1746 * That said, we can come up with a generic equation to 1747 * calculate the value we should set it TQAVCC register by 1748 * replacing 'BW' in E3 by E4. The resulting equation is: 1749 * 1750 * value = idleSlope * 0x7735 * 2 * link-speed 1751 * ----------------- -------------- (E5) 1752 * link-speed * 1000 1000 1753 * 1754 * 'link-speed' is present in both sides of the fraction so 1755 * it is canceled out. The final equation is the following: 1756 * 1757 * value = idleSlope * 61034 1758 * ----------------- (E6) 1759 * 1000000 1760 * 1761 * NOTE: For i210, given the above, we can see that idleslope 1762 * is represented in 16.38431 kbps units by the value at 1763 * the TQAVCC register (1Gbps / 61034), which reduces 1764 * the granularity for idleslope increments. 1765 * For instance, if you want to configure a 2576kbps 1766 * idleslope, the value to be written on the register 1767 * would have to be 157.23. If rounded down, you end 1768 * up with less bandwidth available than originally 1769 * required (~2572 kbps). If rounded up, you end up 1770 * with a higher bandwidth (~2589 kbps). Below the 1771 * approach we take is to always round up the 1772 * calculated value, so the resulting bandwidth might 1773 * be slightly higher for some configurations. 1774 */ 1775 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000); 1776 1777 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1778 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1779 tqavcc |= value; 1780 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1781 1782 wr32(E1000_I210_TQAVHC(queue), 1783 0x80000000 + ring->hicredit * 0x7735); 1784 } else { 1785 1786 /* Set idleSlope to zero. */ 1787 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1788 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK; 1789 wr32(E1000_I210_TQAVCC(queue), tqavcc); 1790 1791 /* Set hiCredit to zero. */ 1792 wr32(E1000_I210_TQAVHC(queue), 0); 1793 1794 /* If CBS is not enabled for any queues anymore, then return to 1795 * the default state of Data Transmission Arbitration on 1796 * TQAVCTRL. 1797 */ 1798 if (!is_any_cbs_enabled(adapter)) { 1799 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1800 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB; 1801 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1802 } 1803 } 1804 1805 /* If LaunchTime is enabled, set DataTranTIM. */ 1806 if (ring->launchtime_enable) { 1807 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled 1808 * for any of the SR queues, and configure fetchtime delta. 1809 * XXX NOTE: 1810 * - LaunchTime will be enabled for all SR queues. 1811 * - A fixed offset can be added relative to the launch 1812 * time of all packets if configured at reg LAUNCH_OS0. 1813 * We are keeping it as 0 for now (default value). 1814 */ 1815 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1816 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM | 1817 E1000_TQAVCTRL_FETCHTIME_DELTA; 1818 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1819 } else { 1820 /* If Launchtime is not enabled for any SR queues anymore, 1821 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta, 1822 * effectively disabling Launchtime. 1823 */ 1824 if (!is_any_txtime_enabled(adapter)) { 1825 tqavctrl = rd32(E1000_I210_TQAVCTRL); 1826 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM; 1827 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA; 1828 wr32(E1000_I210_TQAVCTRL, tqavctrl); 1829 } 1830 } 1831 1832 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1833 * CBS are not configurable by software so we don't do any 'controller 1834 * configuration' in respect to these parameters. 1835 */ 1836 1837 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1838 ring->cbs_enable ? "enabled" : "disabled", 1839 ring->launchtime_enable ? "enabled" : "disabled", 1840 queue, 1841 ring->idleslope, ring->sendslope, 1842 ring->hicredit, ring->locredit); 1843 } 1844 1845 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue, 1846 bool enable) 1847 { 1848 struct igb_ring *ring; 1849 1850 if (queue < 0 || queue > adapter->num_tx_queues) 1851 return -EINVAL; 1852 1853 ring = adapter->tx_ring[queue]; 1854 ring->launchtime_enable = enable; 1855 1856 return 0; 1857 } 1858 1859 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1860 bool enable, int idleslope, int sendslope, 1861 int hicredit, int locredit) 1862 { 1863 struct igb_ring *ring; 1864 1865 if (queue < 0 || queue > adapter->num_tx_queues) 1866 return -EINVAL; 1867 1868 ring = adapter->tx_ring[queue]; 1869 1870 ring->cbs_enable = enable; 1871 ring->idleslope = idleslope; 1872 ring->sendslope = sendslope; 1873 ring->hicredit = hicredit; 1874 ring->locredit = locredit; 1875 1876 return 0; 1877 } 1878 1879 /** 1880 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable 1881 * @adapter: pointer to adapter struct 1882 * 1883 * Configure TQAVCTRL register switching the controller's Tx mode 1884 * if FQTSS mode is enabled or disabled. Additionally, will issue 1885 * a call to igb_config_tx_modes() per queue so any previously saved 1886 * Tx parameters are applied. 1887 **/ 1888 static void igb_setup_tx_mode(struct igb_adapter *adapter) 1889 { 1890 struct net_device *netdev = adapter->netdev; 1891 struct e1000_hw *hw = &adapter->hw; 1892 u32 val; 1893 1894 /* Only i210 controller supports changing the transmission mode. */ 1895 if (hw->mac.type != e1000_i210) 1896 return; 1897 1898 if (is_fqtss_enabled(adapter)) { 1899 int i, max_queue; 1900 1901 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1902 * set data fetch arbitration to 'round robin', set SP_WAIT_SR 1903 * so SP queues wait for SR ones. 1904 */ 1905 val = rd32(E1000_I210_TQAVCTRL); 1906 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR; 1907 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1908 wr32(E1000_I210_TQAVCTRL, val); 1909 1910 /* Configure Tx and Rx packet buffers sizes as described in 1911 * i210 datasheet section 7.2.7.7. 1912 */ 1913 val = rd32(E1000_TXPBS); 1914 val &= ~I210_TXPBSIZE_MASK; 1915 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB | 1916 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB; 1917 wr32(E1000_TXPBS, val); 1918 1919 val = rd32(E1000_RXPBS); 1920 val &= ~I210_RXPBSIZE_MASK; 1921 val |= I210_RXPBSIZE_PB_30KB; 1922 wr32(E1000_RXPBS, val); 1923 1924 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ 1925 * register should not exceed the buffer size programmed in 1926 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB 1927 * so according to the datasheet we should set MAX_TPKT_SIZE to 1928 * 4kB / 64. 1929 * 1930 * However, when we do so, no frame from queue 2 and 3 are 1931 * transmitted. It seems the MAX_TPKT_SIZE should not be great 1932 * or _equal_ to the buffer size programmed in TXPBS. For this 1933 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64. 1934 */ 1935 val = (4096 - 1) / 64; 1936 wr32(E1000_I210_DTXMXPKTSZ, val); 1937 1938 /* Since FQTSS mode is enabled, apply any CBS configuration 1939 * previously set. If no previous CBS configuration has been 1940 * done, then the initial configuration is applied, which means 1941 * CBS is disabled. 1942 */ 1943 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ? 1944 adapter->num_tx_queues : I210_SR_QUEUES_NUM; 1945 1946 for (i = 0; i < max_queue; i++) { 1947 igb_config_tx_modes(adapter, i); 1948 } 1949 } else { 1950 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 1951 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 1952 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); 1953 1954 val = rd32(E1000_I210_TQAVCTRL); 1955 /* According to Section 8.12.21, the other flags we've set when 1956 * enabling FQTSS are not relevant when disabling FQTSS so we 1957 * don't set they here. 1958 */ 1959 val &= ~E1000_TQAVCTRL_XMIT_MODE; 1960 wr32(E1000_I210_TQAVCTRL, val); 1961 } 1962 1963 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ? 1964 "enabled" : "disabled"); 1965 } 1966 1967 /** 1968 * igb_configure - configure the hardware for RX and TX 1969 * @adapter: private board structure 1970 **/ 1971 static void igb_configure(struct igb_adapter *adapter) 1972 { 1973 struct net_device *netdev = adapter->netdev; 1974 int i; 1975 1976 igb_get_hw_control(adapter); 1977 igb_set_rx_mode(netdev); 1978 igb_setup_tx_mode(adapter); 1979 1980 igb_restore_vlan(adapter); 1981 1982 igb_setup_tctl(adapter); 1983 igb_setup_mrqc(adapter); 1984 igb_setup_rctl(adapter); 1985 1986 igb_nfc_filter_restore(adapter); 1987 igb_configure_tx(adapter); 1988 igb_configure_rx(adapter); 1989 1990 igb_rx_fifo_flush_82575(&adapter->hw); 1991 1992 /* call igb_desc_unused which always leaves 1993 * at least 1 descriptor unused to make sure 1994 * next_to_use != next_to_clean 1995 */ 1996 for (i = 0; i < adapter->num_rx_queues; i++) { 1997 struct igb_ring *ring = adapter->rx_ring[i]; 1998 if (ring->xsk_pool) 1999 igb_alloc_rx_buffers_zc(ring, ring->xsk_pool, 2000 igb_desc_unused(ring)); 2001 else 2002 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 2003 } 2004 } 2005 2006 /** 2007 * igb_power_up_link - Power up the phy/serdes link 2008 * @adapter: address of board private structure 2009 **/ 2010 void igb_power_up_link(struct igb_adapter *adapter) 2011 { 2012 igb_reset_phy(&adapter->hw); 2013 2014 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2015 igb_power_up_phy_copper(&adapter->hw); 2016 else 2017 igb_power_up_serdes_link_82575(&adapter->hw); 2018 2019 igb_setup_link(&adapter->hw); 2020 } 2021 2022 /** 2023 * igb_power_down_link - Power down the phy/serdes link 2024 * @adapter: address of board private structure 2025 */ 2026 static void igb_power_down_link(struct igb_adapter *adapter) 2027 { 2028 if (adapter->hw.phy.media_type == e1000_media_type_copper) 2029 igb_power_down_phy_copper_82575(&adapter->hw); 2030 else 2031 igb_shutdown_serdes_link_82575(&adapter->hw); 2032 } 2033 2034 /** 2035 * igb_check_swap_media - Detect and switch function for Media Auto Sense 2036 * @adapter: address of the board private structure 2037 **/ 2038 static void igb_check_swap_media(struct igb_adapter *adapter) 2039 { 2040 struct e1000_hw *hw = &adapter->hw; 2041 u32 ctrl_ext, connsw; 2042 bool swap_now = false; 2043 2044 ctrl_ext = rd32(E1000_CTRL_EXT); 2045 connsw = rd32(E1000_CONNSW); 2046 2047 /* need to live swap if current media is copper and we have fiber/serdes 2048 * to go to. 2049 */ 2050 2051 if ((hw->phy.media_type == e1000_media_type_copper) && 2052 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 2053 swap_now = true; 2054 } else if ((hw->phy.media_type != e1000_media_type_copper) && 2055 !(connsw & E1000_CONNSW_SERDESD)) { 2056 /* copper signal takes time to appear */ 2057 if (adapter->copper_tries < 4) { 2058 adapter->copper_tries++; 2059 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 2060 wr32(E1000_CONNSW, connsw); 2061 return; 2062 } else { 2063 adapter->copper_tries = 0; 2064 if ((connsw & E1000_CONNSW_PHYSD) && 2065 (!(connsw & E1000_CONNSW_PHY_PDN))) { 2066 swap_now = true; 2067 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 2068 wr32(E1000_CONNSW, connsw); 2069 } 2070 } 2071 } 2072 2073 if (!swap_now) 2074 return; 2075 2076 switch (hw->phy.media_type) { 2077 case e1000_media_type_copper: 2078 netdev_info(adapter->netdev, 2079 "MAS: changing media to fiber/serdes\n"); 2080 ctrl_ext |= 2081 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2082 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2083 adapter->copper_tries = 0; 2084 break; 2085 case e1000_media_type_internal_serdes: 2086 case e1000_media_type_fiber: 2087 netdev_info(adapter->netdev, 2088 "MAS: changing media to copper\n"); 2089 ctrl_ext &= 2090 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2091 adapter->flags |= IGB_FLAG_MEDIA_RESET; 2092 break; 2093 default: 2094 /* shouldn't get here during regular operation */ 2095 netdev_err(adapter->netdev, 2096 "AMS: Invalid media type found, returning\n"); 2097 break; 2098 } 2099 wr32(E1000_CTRL_EXT, ctrl_ext); 2100 } 2101 2102 void igb_set_queue_napi(struct igb_adapter *adapter, int vector, 2103 struct napi_struct *napi) 2104 { 2105 struct igb_q_vector *q_vector = adapter->q_vector[vector]; 2106 2107 if (q_vector->rx.ring) 2108 netif_queue_set_napi(adapter->netdev, 2109 q_vector->rx.ring->queue_index, 2110 NETDEV_QUEUE_TYPE_RX, napi); 2111 2112 if (q_vector->tx.ring) 2113 netif_queue_set_napi(adapter->netdev, 2114 q_vector->tx.ring->queue_index, 2115 NETDEV_QUEUE_TYPE_TX, napi); 2116 } 2117 2118 /** 2119 * igb_up - Open the interface and prepare it to handle traffic 2120 * @adapter: board private structure 2121 **/ 2122 int igb_up(struct igb_adapter *adapter) 2123 { 2124 struct e1000_hw *hw = &adapter->hw; 2125 struct napi_struct *napi; 2126 int i; 2127 2128 /* hardware has been reset, we need to reload some things */ 2129 igb_configure(adapter); 2130 2131 clear_bit(__IGB_DOWN, &adapter->state); 2132 2133 for (i = 0; i < adapter->num_q_vectors; i++) { 2134 napi = &adapter->q_vector[i]->napi; 2135 napi_enable(napi); 2136 igb_set_queue_napi(adapter, i, napi); 2137 } 2138 2139 if (adapter->flags & IGB_FLAG_HAS_MSIX) 2140 igb_configure_msix(adapter); 2141 else 2142 igb_assign_vector(adapter->q_vector[0], 0); 2143 2144 /* Clear any pending interrupts. */ 2145 rd32(E1000_TSICR); 2146 rd32(E1000_ICR); 2147 igb_irq_enable(adapter); 2148 2149 /* notify VFs that reset has been completed */ 2150 if (adapter->vfs_allocated_count) { 2151 u32 reg_data = rd32(E1000_CTRL_EXT); 2152 2153 reg_data |= E1000_CTRL_EXT_PFRSTD; 2154 wr32(E1000_CTRL_EXT, reg_data); 2155 } 2156 2157 netif_tx_start_all_queues(adapter->netdev); 2158 2159 /* start the watchdog. */ 2160 hw->mac.get_link_status = 1; 2161 schedule_work(&adapter->watchdog_task); 2162 2163 if ((adapter->flags & IGB_FLAG_EEE) && 2164 (!hw->dev_spec._82575.eee_disable)) 2165 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 2166 2167 return 0; 2168 } 2169 2170 void igb_down(struct igb_adapter *adapter) 2171 { 2172 struct net_device *netdev = adapter->netdev; 2173 struct e1000_hw *hw = &adapter->hw; 2174 u32 tctl, rctl; 2175 int i; 2176 2177 /* signal that we're down so the interrupt handler does not 2178 * reschedule our watchdog timer 2179 */ 2180 set_bit(__IGB_DOWN, &adapter->state); 2181 2182 /* disable receives in the hardware */ 2183 rctl = rd32(E1000_RCTL); 2184 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 2185 /* flush and sleep below */ 2186 2187 igb_nfc_filter_exit(adapter); 2188 2189 netif_carrier_off(netdev); 2190 netif_tx_stop_all_queues(netdev); 2191 2192 /* disable transmits in the hardware */ 2193 tctl = rd32(E1000_TCTL); 2194 tctl &= ~E1000_TCTL_EN; 2195 wr32(E1000_TCTL, tctl); 2196 /* flush both disables and wait for them to finish */ 2197 wrfl(); 2198 usleep_range(10000, 11000); 2199 2200 igb_irq_disable(adapter); 2201 2202 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 2203 2204 for (i = 0; i < adapter->num_q_vectors; i++) { 2205 if (adapter->q_vector[i]) { 2206 napi_synchronize(&adapter->q_vector[i]->napi); 2207 igb_set_queue_napi(adapter, i, NULL); 2208 napi_disable(&adapter->q_vector[i]->napi); 2209 } 2210 } 2211 2212 timer_delete_sync(&adapter->watchdog_timer); 2213 timer_delete_sync(&adapter->phy_info_timer); 2214 2215 /* record the stats before reset*/ 2216 spin_lock(&adapter->stats64_lock); 2217 igb_update_stats(adapter); 2218 spin_unlock(&adapter->stats64_lock); 2219 2220 adapter->link_speed = 0; 2221 adapter->link_duplex = 0; 2222 2223 if (!pci_channel_offline(adapter->pdev)) 2224 igb_reset(adapter); 2225 2226 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2227 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 2228 2229 igb_clean_all_tx_rings(adapter); 2230 igb_clean_all_rx_rings(adapter); 2231 #ifdef CONFIG_IGB_DCA 2232 2233 /* since we reset the hardware DCA settings were cleared */ 2234 igb_setup_dca(adapter); 2235 #endif 2236 } 2237 2238 void igb_reinit_locked(struct igb_adapter *adapter) 2239 { 2240 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 2241 usleep_range(1000, 2000); 2242 igb_down(adapter); 2243 igb_up(adapter); 2244 clear_bit(__IGB_RESETTING, &adapter->state); 2245 } 2246 2247 /** igb_enable_mas - Media Autosense re-enable after swap 2248 * 2249 * @adapter: adapter struct 2250 **/ 2251 static void igb_enable_mas(struct igb_adapter *adapter) 2252 { 2253 struct e1000_hw *hw = &adapter->hw; 2254 u32 connsw = rd32(E1000_CONNSW); 2255 2256 /* configure for SerDes media detect */ 2257 if ((hw->phy.media_type == e1000_media_type_copper) && 2258 (!(connsw & E1000_CONNSW_SERDESD))) { 2259 connsw |= E1000_CONNSW_ENRGSRC; 2260 connsw |= E1000_CONNSW_AUTOSENSE_EN; 2261 wr32(E1000_CONNSW, connsw); 2262 wrfl(); 2263 } 2264 } 2265 2266 #ifdef CONFIG_IGB_HWMON 2267 /** 2268 * igb_set_i2c_bb - Init I2C interface 2269 * @hw: pointer to hardware structure 2270 **/ 2271 static void igb_set_i2c_bb(struct e1000_hw *hw) 2272 { 2273 u32 ctrl_ext; 2274 s32 i2cctl; 2275 2276 ctrl_ext = rd32(E1000_CTRL_EXT); 2277 ctrl_ext |= E1000_CTRL_I2C_ENA; 2278 wr32(E1000_CTRL_EXT, ctrl_ext); 2279 wrfl(); 2280 2281 i2cctl = rd32(E1000_I2CPARAMS); 2282 i2cctl |= E1000_I2CBB_EN 2283 | E1000_I2C_CLK_OE_N 2284 | E1000_I2C_DATA_OE_N; 2285 wr32(E1000_I2CPARAMS, i2cctl); 2286 wrfl(); 2287 } 2288 #endif 2289 2290 void igb_reset(struct igb_adapter *adapter) 2291 { 2292 struct pci_dev *pdev = adapter->pdev; 2293 struct e1000_hw *hw = &adapter->hw; 2294 struct e1000_mac_info *mac = &hw->mac; 2295 struct e1000_fc_info *fc = &hw->fc; 2296 u32 pba, hwm; 2297 2298 /* Repartition Pba for greater than 9k mtu 2299 * To take effect CTRL.RST is required. 2300 */ 2301 switch (mac->type) { 2302 case e1000_i350: 2303 case e1000_i354: 2304 case e1000_82580: 2305 pba = rd32(E1000_RXPBS); 2306 pba = igb_rxpbs_adjust_82580(pba); 2307 break; 2308 case e1000_82576: 2309 pba = rd32(E1000_RXPBS); 2310 pba &= E1000_RXPBS_SIZE_MASK_82576; 2311 break; 2312 case e1000_82575: 2313 case e1000_i210: 2314 case e1000_i211: 2315 default: 2316 pba = E1000_PBA_34K; 2317 break; 2318 } 2319 2320 if (mac->type == e1000_82575) { 2321 u32 min_rx_space, min_tx_space, needed_tx_space; 2322 2323 /* write Rx PBA so that hardware can report correct Tx PBA */ 2324 wr32(E1000_PBA, pba); 2325 2326 /* To maintain wire speed transmits, the Tx FIFO should be 2327 * large enough to accommodate two full transmit packets, 2328 * rounded up to the next 1KB and expressed in KB. Likewise, 2329 * the Rx FIFO should be large enough to accommodate at least 2330 * one full receive packet and is similarly rounded up and 2331 * expressed in KB. 2332 */ 2333 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024); 2334 2335 /* The Tx FIFO also stores 16 bytes of information about the Tx 2336 * but don't include Ethernet FCS because hardware appends it. 2337 * We only need to round down to the nearest 512 byte block 2338 * count since the value we care about is 2 frames, not 1. 2339 */ 2340 min_tx_space = adapter->max_frame_size; 2341 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN; 2342 min_tx_space = DIV_ROUND_UP(min_tx_space, 512); 2343 2344 /* upper 16 bits has Tx packet buffer allocation size in KB */ 2345 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16); 2346 2347 /* If current Tx allocation is less than the min Tx FIFO size, 2348 * and the min Tx FIFO size is less than the current Rx FIFO 2349 * allocation, take space away from current Rx allocation. 2350 */ 2351 if (needed_tx_space < pba) { 2352 pba -= needed_tx_space; 2353 2354 /* if short on Rx space, Rx wins and must trump Tx 2355 * adjustment 2356 */ 2357 if (pba < min_rx_space) 2358 pba = min_rx_space; 2359 } 2360 2361 /* adjust PBA for jumbo frames */ 2362 wr32(E1000_PBA, pba); 2363 } 2364 2365 /* flow control settings 2366 * The high water mark must be low enough to fit one full frame 2367 * after transmitting the pause frame. As such we must have enough 2368 * space to allow for us to complete our current transmit and then 2369 * receive the frame that is in progress from the link partner. 2370 * Set it to: 2371 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 2372 */ 2373 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 2374 2375 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 2376 fc->low_water = fc->high_water - 16; 2377 fc->pause_time = 0xFFFF; 2378 fc->send_xon = 1; 2379 fc->current_mode = fc->requested_mode; 2380 2381 /* disable receive for all VFs and wait one second */ 2382 if (adapter->vfs_allocated_count) { 2383 int i; 2384 2385 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 2386 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 2387 2388 /* ping all the active vfs to let them know we are going down */ 2389 igb_ping_all_vfs(adapter); 2390 2391 /* disable transmits and receives */ 2392 wr32(E1000_VFRE, 0); 2393 wr32(E1000_VFTE, 0); 2394 } 2395 2396 /* Allow time for pending master requests to run */ 2397 hw->mac.ops.reset_hw(hw); 2398 wr32(E1000_WUC, 0); 2399 2400 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 2401 /* need to resetup here after media swap */ 2402 adapter->ei.get_invariants(hw); 2403 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 2404 } 2405 if ((mac->type == e1000_82575 || mac->type == e1000_i350) && 2406 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 2407 igb_enable_mas(adapter); 2408 } 2409 if (hw->mac.ops.init_hw(hw)) 2410 dev_err(&pdev->dev, "Hardware Error\n"); 2411 2412 /* RAR registers were cleared during init_hw, clear mac table */ 2413 igb_flush_mac_table(adapter); 2414 __dev_uc_unsync(adapter->netdev, NULL); 2415 2416 /* Recover default RAR entry */ 2417 igb_set_default_mac_filter(adapter); 2418 2419 /* Flow control settings reset on hardware reset, so guarantee flow 2420 * control is off when forcing speed. 2421 */ 2422 if (!hw->mac.autoneg) 2423 igb_force_mac_fc(hw); 2424 2425 igb_init_dmac(adapter, pba); 2426 #ifdef CONFIG_IGB_HWMON 2427 /* Re-initialize the thermal sensor on i350 devices. */ 2428 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2429 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2430 /* If present, re-initialize the external thermal sensor 2431 * interface. 2432 */ 2433 if (adapter->ets) 2434 igb_set_i2c_bb(hw); 2435 mac->ops.init_thermal_sensor_thresh(hw); 2436 } 2437 } 2438 #endif 2439 /* Re-establish EEE setting */ 2440 if (hw->phy.media_type == e1000_media_type_copper) { 2441 switch (mac->type) { 2442 case e1000_i350: 2443 case e1000_i210: 2444 case e1000_i211: 2445 igb_set_eee_i350(hw, true, true); 2446 break; 2447 case e1000_i354: 2448 igb_set_eee_i354(hw, true, true); 2449 break; 2450 default: 2451 break; 2452 } 2453 } 2454 if (!netif_running(adapter->netdev)) 2455 igb_power_down_link(adapter); 2456 2457 igb_update_mng_vlan(adapter); 2458 2459 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2460 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2461 2462 /* Re-enable PTP, where applicable. */ 2463 if (adapter->ptp_flags & IGB_PTP_ENABLED) 2464 igb_ptp_reset(adapter); 2465 2466 igb_get_phy_info(hw); 2467 } 2468 2469 static netdev_features_t igb_fix_features(struct net_device *netdev, 2470 netdev_features_t features) 2471 { 2472 /* Since there is no support for separate Rx/Tx vlan accel 2473 * enable/disable make sure Tx flag is always in same state as Rx. 2474 */ 2475 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2476 features |= NETIF_F_HW_VLAN_CTAG_TX; 2477 else 2478 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2479 2480 return features; 2481 } 2482 2483 static int igb_set_features(struct net_device *netdev, 2484 netdev_features_t features) 2485 { 2486 netdev_features_t changed = netdev->features ^ features; 2487 struct igb_adapter *adapter = netdev_priv(netdev); 2488 2489 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2490 igb_vlan_mode(netdev, features); 2491 2492 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2493 return 0; 2494 2495 if (!(features & NETIF_F_NTUPLE)) { 2496 struct hlist_node *node2; 2497 struct igb_nfc_filter *rule; 2498 2499 spin_lock(&adapter->nfc_lock); 2500 hlist_for_each_entry_safe(rule, node2, 2501 &adapter->nfc_filter_list, nfc_node) { 2502 igb_erase_filter(adapter, rule); 2503 hlist_del(&rule->nfc_node); 2504 kfree(rule); 2505 } 2506 spin_unlock(&adapter->nfc_lock); 2507 adapter->nfc_filter_count = 0; 2508 } 2509 2510 netdev->features = features; 2511 2512 if (netif_running(netdev)) 2513 igb_reinit_locked(adapter); 2514 else 2515 igb_reset(adapter); 2516 2517 return 1; 2518 } 2519 2520 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 2521 struct net_device *dev, 2522 const unsigned char *addr, u16 vid, 2523 u16 flags, bool *notified, 2524 struct netlink_ext_ack *extack) 2525 { 2526 /* guarantee we can provide a unique filter for the unicast address */ 2527 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 2528 struct igb_adapter *adapter = netdev_priv(dev); 2529 int vfn = adapter->vfs_allocated_count; 2530 2531 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn)) 2532 return -ENOMEM; 2533 } 2534 2535 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 2536 } 2537 2538 #define IGB_MAX_MAC_HDR_LEN 127 2539 #define IGB_MAX_NETWORK_HDR_LEN 511 2540 2541 static netdev_features_t 2542 igb_features_check(struct sk_buff *skb, struct net_device *dev, 2543 netdev_features_t features) 2544 { 2545 unsigned int network_hdr_len, mac_hdr_len; 2546 2547 /* Make certain the headers can be described by a context descriptor */ 2548 mac_hdr_len = skb_network_offset(skb); 2549 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) 2550 return features & ~(NETIF_F_HW_CSUM | 2551 NETIF_F_SCTP_CRC | 2552 NETIF_F_GSO_UDP_L4 | 2553 NETIF_F_HW_VLAN_CTAG_TX | 2554 NETIF_F_TSO | 2555 NETIF_F_TSO6); 2556 2557 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2558 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN)) 2559 return features & ~(NETIF_F_HW_CSUM | 2560 NETIF_F_SCTP_CRC | 2561 NETIF_F_GSO_UDP_L4 | 2562 NETIF_F_TSO | 2563 NETIF_F_TSO6); 2564 2565 /* We can only support IPV4 TSO in tunnels if we can mangle the 2566 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2567 */ 2568 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2569 features &= ~NETIF_F_TSO; 2570 2571 return features; 2572 } 2573 2574 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue) 2575 { 2576 if (!is_fqtss_enabled(adapter)) { 2577 enable_fqtss(adapter, true); 2578 return; 2579 } 2580 2581 igb_config_tx_modes(adapter, queue); 2582 2583 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter)) 2584 enable_fqtss(adapter, false); 2585 } 2586 2587 static int igb_offload_cbs(struct igb_adapter *adapter, 2588 struct tc_cbs_qopt_offload *qopt) 2589 { 2590 struct e1000_hw *hw = &adapter->hw; 2591 int err; 2592 2593 /* CBS offloading is only supported by i210 controller. */ 2594 if (hw->mac.type != e1000_i210) 2595 return -EOPNOTSUPP; 2596 2597 /* CBS offloading is only supported by queue 0 and queue 1. */ 2598 if (qopt->queue < 0 || qopt->queue > 1) 2599 return -EINVAL; 2600 2601 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable, 2602 qopt->idleslope, qopt->sendslope, 2603 qopt->hicredit, qopt->locredit); 2604 if (err) 2605 return err; 2606 2607 igb_offload_apply(adapter, qopt->queue); 2608 2609 return 0; 2610 } 2611 2612 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2613 #define VLAN_PRIO_FULL_MASK (0x07) 2614 2615 static int igb_parse_cls_flower(struct igb_adapter *adapter, 2616 struct flow_cls_offload *f, 2617 int traffic_class, 2618 struct igb_nfc_filter *input) 2619 { 2620 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2621 struct flow_dissector *dissector = rule->match.dissector; 2622 struct netlink_ext_ack *extack = f->common.extack; 2623 2624 if (dissector->used_keys & 2625 ~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 2626 BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 2627 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 2628 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) { 2629 NL_SET_ERR_MSG_MOD(extack, 2630 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); 2631 return -EOPNOTSUPP; 2632 } 2633 2634 if (flow_rule_match_has_control_flags(rule, extack)) 2635 return -EOPNOTSUPP; 2636 2637 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2638 struct flow_match_eth_addrs match; 2639 2640 flow_rule_match_eth_addrs(rule, &match); 2641 if (!is_zero_ether_addr(match.mask->dst)) { 2642 if (!is_broadcast_ether_addr(match.mask->dst)) { 2643 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); 2644 return -EINVAL; 2645 } 2646 2647 input->filter.match_flags |= 2648 IGB_FILTER_FLAG_DST_MAC_ADDR; 2649 ether_addr_copy(input->filter.dst_addr, match.key->dst); 2650 } 2651 2652 if (!is_zero_ether_addr(match.mask->src)) { 2653 if (!is_broadcast_ether_addr(match.mask->src)) { 2654 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); 2655 return -EINVAL; 2656 } 2657 2658 input->filter.match_flags |= 2659 IGB_FILTER_FLAG_SRC_MAC_ADDR; 2660 ether_addr_copy(input->filter.src_addr, match.key->src); 2661 } 2662 } 2663 2664 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { 2665 struct flow_match_basic match; 2666 2667 flow_rule_match_basic(rule, &match); 2668 if (match.mask->n_proto) { 2669 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 2670 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); 2671 return -EINVAL; 2672 } 2673 2674 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE; 2675 input->filter.etype = match.key->n_proto; 2676 } 2677 } 2678 2679 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2680 struct flow_match_vlan match; 2681 2682 flow_rule_match_vlan(rule, &match); 2683 if (match.mask->vlan_priority) { 2684 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 2685 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); 2686 return -EINVAL; 2687 } 2688 2689 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2690 input->filter.vlan_tci = 2691 (__force __be16)match.key->vlan_priority; 2692 } 2693 } 2694 2695 input->action = traffic_class; 2696 input->cookie = f->cookie; 2697 2698 return 0; 2699 } 2700 2701 static int igb_configure_clsflower(struct igb_adapter *adapter, 2702 struct flow_cls_offload *cls_flower) 2703 { 2704 struct netlink_ext_ack *extack = cls_flower->common.extack; 2705 struct igb_nfc_filter *filter, *f; 2706 int err, tc; 2707 2708 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid); 2709 if (tc < 0) { 2710 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class"); 2711 return -EINVAL; 2712 } 2713 2714 filter = kzalloc_obj(*filter); 2715 if (!filter) 2716 return -ENOMEM; 2717 2718 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter); 2719 if (err < 0) 2720 goto err_parse; 2721 2722 spin_lock(&adapter->nfc_lock); 2723 2724 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) { 2725 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2726 err = -EEXIST; 2727 NL_SET_ERR_MSG_MOD(extack, 2728 "This filter is already set in ethtool"); 2729 goto err_locked; 2730 } 2731 } 2732 2733 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) { 2734 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) { 2735 err = -EEXIST; 2736 NL_SET_ERR_MSG_MOD(extack, 2737 "This filter is already set in cls_flower"); 2738 goto err_locked; 2739 } 2740 } 2741 2742 err = igb_add_filter(adapter, filter); 2743 if (err < 0) { 2744 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter"); 2745 goto err_locked; 2746 } 2747 2748 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list); 2749 2750 spin_unlock(&adapter->nfc_lock); 2751 2752 return 0; 2753 2754 err_locked: 2755 spin_unlock(&adapter->nfc_lock); 2756 2757 err_parse: 2758 kfree(filter); 2759 2760 return err; 2761 } 2762 2763 static int igb_delete_clsflower(struct igb_adapter *adapter, 2764 struct flow_cls_offload *cls_flower) 2765 { 2766 struct igb_nfc_filter *filter; 2767 int err; 2768 2769 spin_lock(&adapter->nfc_lock); 2770 2771 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node) 2772 if (filter->cookie == cls_flower->cookie) 2773 break; 2774 2775 if (!filter) { 2776 err = -ENOENT; 2777 goto out; 2778 } 2779 2780 err = igb_erase_filter(adapter, filter); 2781 if (err < 0) 2782 goto out; 2783 2784 hlist_del(&filter->nfc_node); 2785 kfree(filter); 2786 2787 out: 2788 spin_unlock(&adapter->nfc_lock); 2789 2790 return err; 2791 } 2792 2793 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter, 2794 struct flow_cls_offload *cls_flower) 2795 { 2796 switch (cls_flower->command) { 2797 case FLOW_CLS_REPLACE: 2798 return igb_configure_clsflower(adapter, cls_flower); 2799 case FLOW_CLS_DESTROY: 2800 return igb_delete_clsflower(adapter, cls_flower); 2801 case FLOW_CLS_STATS: 2802 return -EOPNOTSUPP; 2803 default: 2804 return -EOPNOTSUPP; 2805 } 2806 } 2807 2808 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2809 void *cb_priv) 2810 { 2811 struct igb_adapter *adapter = cb_priv; 2812 2813 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 2814 return -EOPNOTSUPP; 2815 2816 switch (type) { 2817 case TC_SETUP_CLSFLOWER: 2818 return igb_setup_tc_cls_flower(adapter, type_data); 2819 2820 default: 2821 return -EOPNOTSUPP; 2822 } 2823 } 2824 2825 static int igb_offload_txtime(struct igb_adapter *adapter, 2826 struct tc_etf_qopt_offload *qopt) 2827 { 2828 struct e1000_hw *hw = &adapter->hw; 2829 int err; 2830 2831 /* Launchtime offloading is only supported by i210 controller. */ 2832 if (hw->mac.type != e1000_i210) 2833 return -EOPNOTSUPP; 2834 2835 /* Launchtime offloading is only supported by queues 0 and 1. */ 2836 if (qopt->queue < 0 || qopt->queue > 1) 2837 return -EINVAL; 2838 2839 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable); 2840 if (err) 2841 return err; 2842 2843 igb_offload_apply(adapter, qopt->queue); 2844 2845 return 0; 2846 } 2847 2848 static int igb_tc_query_caps(struct igb_adapter *adapter, 2849 struct tc_query_caps_base *base) 2850 { 2851 switch (base->type) { 2852 case TC_SETUP_QDISC_TAPRIO: { 2853 struct tc_taprio_caps *caps = base->caps; 2854 2855 caps->broken_mqprio = true; 2856 2857 return 0; 2858 } 2859 default: 2860 return -EOPNOTSUPP; 2861 } 2862 } 2863 2864 static LIST_HEAD(igb_block_cb_list); 2865 2866 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2867 void *type_data) 2868 { 2869 struct igb_adapter *adapter = netdev_priv(dev); 2870 2871 switch (type) { 2872 case TC_QUERY_CAPS: 2873 return igb_tc_query_caps(adapter, type_data); 2874 case TC_SETUP_QDISC_CBS: 2875 return igb_offload_cbs(adapter, type_data); 2876 case TC_SETUP_BLOCK: 2877 return flow_block_cb_setup_simple(type_data, 2878 &igb_block_cb_list, 2879 igb_setup_tc_block_cb, 2880 adapter, adapter, true); 2881 2882 case TC_SETUP_QDISC_ETF: 2883 return igb_offload_txtime(adapter, type_data); 2884 2885 default: 2886 return -EOPNOTSUPP; 2887 } 2888 } 2889 2890 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf) 2891 { 2892 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD; 2893 struct igb_adapter *adapter = netdev_priv(dev); 2894 struct bpf_prog *prog = bpf->prog, *old_prog; 2895 bool running = netif_running(dev); 2896 bool need_reset; 2897 2898 /* verify igb ring attributes are sufficient for XDP */ 2899 for (i = 0; i < adapter->num_rx_queues; i++) { 2900 struct igb_ring *ring = adapter->rx_ring[i]; 2901 2902 if (frame_size > igb_rx_bufsz(ring)) { 2903 NL_SET_ERR_MSG_MOD(bpf->extack, 2904 "The RX buffer size is too small for the frame size"); 2905 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n", 2906 igb_rx_bufsz(ring), frame_size); 2907 return -EINVAL; 2908 } 2909 } 2910 2911 old_prog = xchg(&adapter->xdp_prog, prog); 2912 need_reset = (!!prog != !!old_prog); 2913 2914 /* device is up and bpf is added/removed, must setup the RX queues */ 2915 if (need_reset && running) { 2916 igb_close(dev); 2917 } else { 2918 for (i = 0; i < adapter->num_rx_queues; i++) 2919 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 2920 adapter->xdp_prog); 2921 } 2922 2923 if (old_prog) 2924 bpf_prog_put(old_prog); 2925 2926 /* bpf is just replaced, RXQ and MTU are already setup */ 2927 if (!need_reset) { 2928 return 0; 2929 } else { 2930 if (prog) 2931 xdp_features_set_redirect_target(dev, true); 2932 else 2933 xdp_features_clear_redirect_target(dev); 2934 } 2935 2936 if (running) 2937 igb_open(dev); 2938 2939 return 0; 2940 } 2941 2942 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp) 2943 { 2944 struct igb_adapter *adapter = netdev_priv(dev); 2945 2946 switch (xdp->command) { 2947 case XDP_SETUP_PROG: 2948 return igb_xdp_setup(dev, xdp); 2949 case XDP_SETUP_XSK_POOL: 2950 return igb_xsk_pool_setup(adapter, xdp->xsk.pool, 2951 xdp->xsk.queue_id); 2952 default: 2953 return -EINVAL; 2954 } 2955 } 2956 2957 int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp) 2958 { 2959 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2960 int cpu = smp_processor_id(); 2961 struct igb_ring *tx_ring; 2962 struct netdev_queue *nq; 2963 u32 ret; 2964 2965 if (unlikely(!xdpf)) 2966 return IGB_XDP_CONSUMED; 2967 2968 /* During program transitions its possible adapter->xdp_prog is assigned 2969 * but ring has not been configured yet. In this case simply abort xmit. 2970 */ 2971 tx_ring = igb_xdp_is_enabled(adapter) ? 2972 igb_xdp_tx_queue_mapping(adapter) : NULL; 2973 if (unlikely(!tx_ring)) 2974 return IGB_XDP_CONSUMED; 2975 2976 nq = txring_txq(tx_ring); 2977 __netif_tx_lock(nq, cpu); 2978 /* Avoid transmit queue timeout since we share it with the slow path */ 2979 txq_trans_cond_update(nq); 2980 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 2981 __netif_tx_unlock(nq); 2982 2983 return ret; 2984 } 2985 2986 static int igb_xdp_xmit(struct net_device *dev, int n, 2987 struct xdp_frame **frames, u32 flags) 2988 { 2989 struct igb_adapter *adapter = netdev_priv(dev); 2990 int cpu = smp_processor_id(); 2991 struct igb_ring *tx_ring; 2992 struct netdev_queue *nq; 2993 int nxmit = 0; 2994 int i; 2995 2996 if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) 2997 return -ENETDOWN; 2998 2999 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3000 return -EINVAL; 3001 3002 /* During program transitions its possible adapter->xdp_prog is assigned 3003 * but ring has not been configured yet. In this case simply abort xmit. 3004 */ 3005 tx_ring = igb_xdp_is_enabled(adapter) ? 3006 igb_xdp_tx_queue_mapping(adapter) : NULL; 3007 if (unlikely(!tx_ring)) 3008 return -ENXIO; 3009 3010 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 3011 return -ENXIO; 3012 3013 nq = txring_txq(tx_ring); 3014 __netif_tx_lock(nq, cpu); 3015 3016 /* Avoid transmit queue timeout since we share it with the slow path */ 3017 txq_trans_cond_update(nq); 3018 3019 for (i = 0; i < n; i++) { 3020 struct xdp_frame *xdpf = frames[i]; 3021 int err; 3022 3023 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf); 3024 if (err != IGB_XDP_TX) 3025 break; 3026 nxmit++; 3027 } 3028 3029 if (unlikely(flags & XDP_XMIT_FLUSH)) 3030 igb_xdp_ring_update_tail(tx_ring); 3031 3032 __netif_tx_unlock(nq); 3033 3034 return nxmit; 3035 } 3036 3037 static const struct net_device_ops igb_netdev_ops = { 3038 .ndo_open = igb_open, 3039 .ndo_stop = igb_close, 3040 .ndo_start_xmit = igb_xmit_frame, 3041 .ndo_get_stats64 = igb_get_stats64, 3042 .ndo_set_rx_mode = igb_set_rx_mode, 3043 .ndo_set_mac_address = igb_set_mac, 3044 .ndo_change_mtu = igb_change_mtu, 3045 .ndo_eth_ioctl = igb_ioctl, 3046 .ndo_tx_timeout = igb_tx_timeout, 3047 .ndo_validate_addr = eth_validate_addr, 3048 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 3049 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 3050 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 3051 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 3052 .ndo_set_vf_rate = igb_ndo_set_vf_bw, 3053 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 3054 .ndo_set_vf_trust = igb_ndo_set_vf_trust, 3055 .ndo_get_vf_config = igb_ndo_get_vf_config, 3056 .ndo_fix_features = igb_fix_features, 3057 .ndo_set_features = igb_set_features, 3058 .ndo_fdb_add = igb_ndo_fdb_add, 3059 .ndo_features_check = igb_features_check, 3060 .ndo_setup_tc = igb_setup_tc, 3061 .ndo_bpf = igb_xdp, 3062 .ndo_xdp_xmit = igb_xdp_xmit, 3063 .ndo_xsk_wakeup = igb_xsk_wakeup, 3064 .ndo_hwtstamp_get = igb_ptp_hwtstamp_get, 3065 .ndo_hwtstamp_set = igb_ptp_hwtstamp_set, 3066 }; 3067 3068 /** 3069 * igb_set_fw_version - Configure version string for ethtool 3070 * @adapter: adapter struct 3071 **/ 3072 void igb_set_fw_version(struct igb_adapter *adapter) 3073 { 3074 struct e1000_hw *hw = &adapter->hw; 3075 struct e1000_fw_version fw; 3076 3077 igb_get_fw_version(hw, &fw); 3078 3079 switch (hw->mac.type) { 3080 case e1000_i210: 3081 case e1000_i211: 3082 if (!(igb_get_flash_presence_i210(hw))) { 3083 snprintf(adapter->fw_version, 3084 sizeof(adapter->fw_version), 3085 "%2d.%2d-%d", 3086 fw.invm_major, fw.invm_minor, 3087 fw.invm_img_type); 3088 break; 3089 } 3090 fallthrough; 3091 default: 3092 /* if option rom is valid, display its version too */ 3093 if (fw.or_valid) { 3094 snprintf(adapter->fw_version, 3095 sizeof(adapter->fw_version), 3096 "%d.%d, 0x%08x, %d.%d.%d", 3097 fw.eep_major, fw.eep_minor, fw.etrack_id, 3098 fw.or_major, fw.or_build, fw.or_patch); 3099 /* no option rom */ 3100 } else if (fw.etrack_id != 0X0000) { 3101 snprintf(adapter->fw_version, 3102 sizeof(adapter->fw_version), 3103 "%d.%d, 0x%08x", 3104 fw.eep_major, fw.eep_minor, fw.etrack_id); 3105 } else { 3106 snprintf(adapter->fw_version, 3107 sizeof(adapter->fw_version), 3108 "%d.%d.%d", 3109 fw.eep_major, fw.eep_minor, fw.eep_build); 3110 } 3111 break; 3112 } 3113 } 3114 3115 /** 3116 * igb_init_mas - init Media Autosense feature if enabled in the NVM 3117 * 3118 * @adapter: adapter struct 3119 **/ 3120 static void igb_init_mas(struct igb_adapter *adapter) 3121 { 3122 struct e1000_hw *hw = &adapter->hw; 3123 u16 eeprom_data; 3124 3125 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 3126 switch (hw->bus.func) { 3127 case E1000_FUNC_0: 3128 if (eeprom_data & IGB_MAS_ENABLE_0) { 3129 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3130 netdev_info(adapter->netdev, 3131 "MAS: Enabling Media Autosense for port %d\n", 3132 hw->bus.func); 3133 } 3134 break; 3135 case E1000_FUNC_1: 3136 if (eeprom_data & IGB_MAS_ENABLE_1) { 3137 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3138 netdev_info(adapter->netdev, 3139 "MAS: Enabling Media Autosense for port %d\n", 3140 hw->bus.func); 3141 } 3142 break; 3143 case E1000_FUNC_2: 3144 if (eeprom_data & IGB_MAS_ENABLE_2) { 3145 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3146 netdev_info(adapter->netdev, 3147 "MAS: Enabling Media Autosense for port %d\n", 3148 hw->bus.func); 3149 } 3150 break; 3151 case E1000_FUNC_3: 3152 if (eeprom_data & IGB_MAS_ENABLE_3) { 3153 adapter->flags |= IGB_FLAG_MAS_ENABLE; 3154 netdev_info(adapter->netdev, 3155 "MAS: Enabling Media Autosense for port %d\n", 3156 hw->bus.func); 3157 } 3158 break; 3159 default: 3160 /* Shouldn't get here */ 3161 netdev_err(adapter->netdev, 3162 "MAS: Invalid port configuration, returning\n"); 3163 break; 3164 } 3165 } 3166 3167 /** 3168 * igb_init_i2c - Init I2C interface 3169 * @adapter: pointer to adapter structure 3170 **/ 3171 static s32 igb_init_i2c(struct igb_adapter *adapter) 3172 { 3173 s32 status = 0; 3174 3175 /* I2C interface supported on i350 devices */ 3176 if (adapter->hw.mac.type != e1000_i350) 3177 return 0; 3178 3179 /* Initialize the i2c bus which is controlled by the registers. 3180 * This bus will use the i2c_algo_bit structure that implements 3181 * the protocol through toggling of the 4 bits in the register. 3182 */ 3183 adapter->i2c_adap.owner = THIS_MODULE; 3184 adapter->i2c_algo = igb_i2c_algo; 3185 adapter->i2c_algo.data = adapter; 3186 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 3187 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 3188 strscpy(adapter->i2c_adap.name, "igb BB", 3189 sizeof(adapter->i2c_adap.name)); 3190 status = i2c_bit_add_bus(&adapter->i2c_adap); 3191 return status; 3192 } 3193 3194 /** 3195 * igb_probe - Device Initialization Routine 3196 * @pdev: PCI device information struct 3197 * @ent: entry in igb_pci_tbl 3198 * 3199 * Returns 0 on success, negative on failure 3200 * 3201 * igb_probe initializes an adapter identified by a pci_dev structure. 3202 * The OS initialization, configuring of the adapter private structure, 3203 * and a hardware reset occur. 3204 **/ 3205 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3206 { 3207 struct net_device *netdev; 3208 struct igb_adapter *adapter; 3209 struct e1000_hw *hw; 3210 u16 eeprom_data = 0; 3211 s32 ret_val; 3212 static int global_quad_port_a; /* global quad port a indication */ 3213 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 3214 u8 part_str[E1000_PBANUM_LENGTH]; 3215 int err; 3216 3217 /* Catch broken hardware that put the wrong VF device ID in 3218 * the PCIe SR-IOV capability. 3219 */ 3220 if (pdev->is_virtfn) { 3221 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n", 3222 pci_name(pdev), pdev->vendor, pdev->device); 3223 return -EINVAL; 3224 } 3225 3226 err = pci_enable_device_mem(pdev); 3227 if (err) 3228 return err; 3229 3230 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3231 if (err) { 3232 dev_err(&pdev->dev, 3233 "No usable DMA configuration, aborting\n"); 3234 goto err_dma; 3235 } 3236 3237 err = pci_request_mem_regions(pdev, igb_driver_name); 3238 if (err) 3239 goto err_pci_reg; 3240 3241 pci_set_master(pdev); 3242 pci_save_state(pdev); 3243 3244 err = -ENOMEM; 3245 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 3246 IGB_MAX_TX_QUEUES); 3247 if (!netdev) 3248 goto err_alloc_etherdev; 3249 3250 SET_NETDEV_DEV(netdev, &pdev->dev); 3251 3252 pci_set_drvdata(pdev, netdev); 3253 adapter = netdev_priv(netdev); 3254 adapter->netdev = netdev; 3255 adapter->pdev = pdev; 3256 hw = &adapter->hw; 3257 hw->back = adapter; 3258 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3259 3260 err = -EIO; 3261 adapter->io_addr = pci_iomap(pdev, 0, 0); 3262 if (!adapter->io_addr) 3263 goto err_ioremap; 3264 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */ 3265 hw->hw_addr = adapter->io_addr; 3266 3267 netdev->netdev_ops = &igb_netdev_ops; 3268 igb_set_ethtool_ops(netdev); 3269 netdev->watchdog_timeo = 5 * HZ; 3270 3271 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 3272 3273 netdev->mem_start = pci_resource_start(pdev, 0); 3274 netdev->mem_end = pci_resource_end(pdev, 0); 3275 3276 /* PCI config space info */ 3277 hw->vendor_id = pdev->vendor; 3278 hw->device_id = pdev->device; 3279 hw->revision_id = pdev->revision; 3280 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3281 hw->subsystem_device_id = pdev->subsystem_device; 3282 3283 /* Copy the default MAC, PHY and NVM function pointers */ 3284 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3285 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3286 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 3287 /* Initialize skew-specific constants */ 3288 err = ei->get_invariants(hw); 3289 if (err) 3290 goto err_sw_init; 3291 3292 /* setup the private structure */ 3293 err = igb_sw_init(adapter); 3294 if (err) 3295 goto err_sw_init; 3296 3297 igb_get_bus_info_pcie(hw); 3298 3299 hw->phy.autoneg_wait_to_complete = false; 3300 3301 /* Copper options */ 3302 if (hw->phy.media_type == e1000_media_type_copper) { 3303 hw->phy.mdix = AUTO_ALL_MODES; 3304 hw->phy.disable_polarity_correction = false; 3305 hw->phy.ms_type = e1000_ms_hw_default; 3306 } 3307 3308 if (igb_check_reset_block(hw)) 3309 dev_info(&pdev->dev, 3310 "PHY reset is blocked due to SOL/IDER session.\n"); 3311 3312 /* features is initialized to 0 in allocation, it might have bits 3313 * set by igb_sw_init so we should use an or instead of an 3314 * assignment. 3315 */ 3316 netdev->features |= NETIF_F_SG | 3317 NETIF_F_TSO | 3318 NETIF_F_TSO6 | 3319 NETIF_F_RXHASH | 3320 NETIF_F_RXCSUM | 3321 NETIF_F_HW_CSUM; 3322 3323 if (hw->mac.type >= e1000_82576) 3324 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 3325 3326 if (hw->mac.type >= e1000_i350) 3327 netdev->features |= NETIF_F_HW_TC; 3328 3329 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 3330 NETIF_F_GSO_GRE_CSUM | \ 3331 NETIF_F_GSO_IPXIP4 | \ 3332 NETIF_F_GSO_IPXIP6 | \ 3333 NETIF_F_GSO_UDP_TUNNEL | \ 3334 NETIF_F_GSO_UDP_TUNNEL_CSUM) 3335 3336 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES; 3337 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES; 3338 3339 /* copy netdev features into list of user selectable features */ 3340 netdev->hw_features |= netdev->features | 3341 NETIF_F_HW_VLAN_CTAG_RX | 3342 NETIF_F_HW_VLAN_CTAG_TX | 3343 NETIF_F_RXALL; 3344 3345 if (hw->mac.type >= e1000_i350) 3346 netdev->hw_features |= NETIF_F_NTUPLE; 3347 3348 netdev->features |= NETIF_F_HIGHDMA; 3349 3350 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 3351 netdev->mpls_features |= NETIF_F_HW_CSUM; 3352 netdev->hw_enc_features |= netdev->vlan_features; 3353 3354 /* set this bit last since it cannot be part of vlan_features */ 3355 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3356 NETIF_F_HW_VLAN_CTAG_RX | 3357 NETIF_F_HW_VLAN_CTAG_TX; 3358 3359 netdev->priv_flags |= IFF_SUPP_NOFCS; 3360 3361 netdev->priv_flags |= IFF_UNICAST_FLT; 3362 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3363 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3364 3365 /* MTU range: 68 - 9216 */ 3366 netdev->min_mtu = ETH_MIN_MTU; 3367 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3368 3369 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 3370 3371 /* before reading the NVM, reset the controller to put the device in a 3372 * known good starting state 3373 */ 3374 hw->mac.ops.reset_hw(hw); 3375 3376 /* make sure the NVM is good , i211/i210 parts can have special NVM 3377 * that doesn't contain a checksum 3378 */ 3379 switch (hw->mac.type) { 3380 case e1000_i210: 3381 case e1000_i211: 3382 if (igb_get_flash_presence_i210(hw)) { 3383 if (hw->nvm.ops.validate(hw) < 0) { 3384 dev_err(&pdev->dev, 3385 "The NVM Checksum Is Not Valid\n"); 3386 err = -EIO; 3387 goto err_eeprom; 3388 } 3389 } 3390 break; 3391 default: 3392 if (hw->nvm.ops.validate(hw) < 0) { 3393 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 3394 err = -EIO; 3395 goto err_eeprom; 3396 } 3397 break; 3398 } 3399 3400 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3401 /* copy the MAC address out of the NVM */ 3402 if (hw->mac.ops.read_mac_addr(hw)) 3403 dev_err(&pdev->dev, "NVM Read Error\n"); 3404 } 3405 3406 eth_hw_addr_set(netdev, hw->mac.addr); 3407 3408 if (!is_valid_ether_addr(netdev->dev_addr)) { 3409 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3410 err = -EIO; 3411 goto err_eeprom; 3412 } 3413 3414 igb_set_default_mac_filter(adapter); 3415 3416 /* get firmware version for ethtool -i */ 3417 igb_set_fw_version(adapter); 3418 3419 /* configure RXPBSIZE and TXPBSIZE */ 3420 if (hw->mac.type == e1000_i210) { 3421 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); 3422 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); 3423 } 3424 3425 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0); 3426 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0); 3427 3428 INIT_WORK(&adapter->reset_task, igb_reset_task); 3429 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 3430 3431 /* Initialize link properties that are user-changeable */ 3432 adapter->fc_autoneg = true; 3433 hw->mac.autoneg = true; 3434 hw->phy.autoneg_advertised = 0x2f; 3435 3436 hw->fc.requested_mode = e1000_fc_default; 3437 hw->fc.current_mode = e1000_fc_default; 3438 3439 igb_validate_mdi_setting(hw); 3440 3441 /* By default, support wake on port A */ 3442 if (hw->bus.func == 0) 3443 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3444 3445 /* Check the NVM for wake support on non-port A ports */ 3446 if (hw->mac.type >= e1000_82580) 3447 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 3448 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 3449 &eeprom_data); 3450 else if (hw->bus.func == 1) 3451 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3452 3453 if (eeprom_data & IGB_EEPROM_APME) 3454 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3455 3456 /* now that we have the eeprom settings, apply the special cases where 3457 * the eeprom may be wrong or the board simply won't support wake on 3458 * lan on a particular port 3459 */ 3460 switch (pdev->device) { 3461 case E1000_DEV_ID_82575GB_QUAD_COPPER: 3462 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3463 break; 3464 case E1000_DEV_ID_82575EB_FIBER_SERDES: 3465 case E1000_DEV_ID_82576_FIBER: 3466 case E1000_DEV_ID_82576_SERDES: 3467 /* Wake events only supported on port A for dual fiber 3468 * regardless of eeprom setting 3469 */ 3470 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 3471 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3472 break; 3473 case E1000_DEV_ID_82576_QUAD_COPPER: 3474 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 3475 /* if quad port adapter, disable WoL on all but port A */ 3476 if (global_quad_port_a != 0) 3477 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3478 else 3479 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 3480 /* Reset for multiple quad port adapters */ 3481 if (++global_quad_port_a == 4) 3482 global_quad_port_a = 0; 3483 break; 3484 default: 3485 /* If the device can't wake, don't set software support */ 3486 if (!device_can_wakeup(&adapter->pdev->dev)) 3487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 3488 } 3489 3490 /* initialize the wol settings based on the eeprom settings */ 3491 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 3492 adapter->wol |= E1000_WUFC_MAG; 3493 3494 /* Some vendors want WoL disabled by default, but still supported */ 3495 if ((hw->mac.type == e1000_i350) && 3496 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 3497 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3498 adapter->wol = 0; 3499 } 3500 3501 /* Some vendors want the ability to Use the EEPROM setting as 3502 * enable/disable only, and not for capability 3503 */ 3504 if (((hw->mac.type == e1000_i350) || 3505 (hw->mac.type == e1000_i354)) && 3506 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) { 3507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3508 adapter->wol = 0; 3509 } 3510 if (hw->mac.type == e1000_i350) { 3511 if (((pdev->subsystem_device == 0x5001) || 3512 (pdev->subsystem_device == 0x5002)) && 3513 (hw->bus.func == 0)) { 3514 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3515 adapter->wol = 0; 3516 } 3517 if (pdev->subsystem_device == 0x1F52) 3518 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 3519 } 3520 3521 device_set_wakeup_enable(&adapter->pdev->dev, 3522 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 3523 3524 /* reset the hardware with the new settings */ 3525 igb_reset(adapter); 3526 3527 /* Init the I2C interface */ 3528 err = igb_init_i2c(adapter); 3529 if (err) { 3530 dev_err(&pdev->dev, "failed to init i2c interface\n"); 3531 goto err_eeprom; 3532 } 3533 3534 /* let the f/w know that the h/w is now under the control of the 3535 * driver. 3536 */ 3537 igb_get_hw_control(adapter); 3538 3539 strcpy(netdev->name, "eth%d"); 3540 err = register_netdev(netdev); 3541 if (err) 3542 goto err_register; 3543 3544 /* carrier off reporting is important to ethtool even BEFORE open */ 3545 netif_carrier_off(netdev); 3546 3547 #ifdef CONFIG_IGB_DCA 3548 if (dca_add_requester(&pdev->dev) == 0) { 3549 adapter->flags |= IGB_FLAG_DCA_ENABLED; 3550 dev_info(&pdev->dev, "DCA enabled\n"); 3551 igb_setup_dca(adapter); 3552 } 3553 3554 #endif 3555 #ifdef CONFIG_IGB_HWMON 3556 /* Initialize the thermal sensor on i350 devices. */ 3557 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 3558 u16 ets_word; 3559 3560 /* Read the NVM to determine if this i350 device supports an 3561 * external thermal sensor. 3562 */ 3563 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 3564 if (ets_word != 0x0000 && ets_word != 0xFFFF) 3565 adapter->ets = true; 3566 else 3567 adapter->ets = false; 3568 /* Only enable I2C bit banging if an external thermal 3569 * sensor is supported. 3570 */ 3571 if (adapter->ets) 3572 igb_set_i2c_bb(hw); 3573 hw->mac.ops.init_thermal_sensor_thresh(hw); 3574 if (igb_sysfs_init(adapter)) 3575 dev_err(&pdev->dev, 3576 "failed to allocate sysfs resources\n"); 3577 } else { 3578 adapter->ets = false; 3579 } 3580 #endif 3581 /* Check if Media Autosense is enabled */ 3582 adapter->ei = *ei; 3583 if (hw->dev_spec._82575.mas_capable) 3584 igb_init_mas(adapter); 3585 3586 /* do hw tstamp init after resetting */ 3587 igb_ptp_init(adapter); 3588 3589 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 3590 /* print bus type/speed/width info, not applicable to i354 */ 3591 if (hw->mac.type != e1000_i354) { 3592 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 3593 netdev->name, 3594 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 3595 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 3596 "unknown"), 3597 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 3598 "Width x4" : 3599 (hw->bus.width == e1000_bus_width_pcie_x2) ? 3600 "Width x2" : 3601 (hw->bus.width == e1000_bus_width_pcie_x1) ? 3602 "Width x1" : "unknown"), netdev->dev_addr); 3603 } 3604 3605 if ((hw->mac.type == e1000_82576 && 3606 rd32(E1000_EECD) & E1000_EECD_PRES) || 3607 (hw->mac.type >= e1000_i210 || 3608 igb_get_flash_presence_i210(hw))) { 3609 ret_val = igb_read_part_string(hw, part_str, 3610 E1000_PBANUM_LENGTH); 3611 } else { 3612 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 3613 } 3614 3615 if (ret_val) 3616 strcpy(part_str, "Unknown"); 3617 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 3618 dev_info(&pdev->dev, 3619 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 3620 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 3621 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 3622 adapter->num_rx_queues, adapter->num_tx_queues); 3623 if (hw->phy.media_type == e1000_media_type_copper) { 3624 switch (hw->mac.type) { 3625 case e1000_i350: 3626 case e1000_i210: 3627 case e1000_i211: 3628 /* Enable EEE for internal copper PHY devices */ 3629 err = igb_set_eee_i350(hw, true, true); 3630 if ((!err) && 3631 (!hw->dev_spec._82575.eee_disable)) { 3632 adapter->eee_advert = 3633 MDIO_EEE_100TX | MDIO_EEE_1000T; 3634 adapter->flags |= IGB_FLAG_EEE; 3635 } 3636 break; 3637 case e1000_i354: 3638 if ((rd32(E1000_CTRL_EXT) & 3639 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3640 err = igb_set_eee_i354(hw, true, true); 3641 if ((!err) && 3642 (!hw->dev_spec._82575.eee_disable)) { 3643 adapter->eee_advert = 3644 MDIO_EEE_100TX | MDIO_EEE_1000T; 3645 adapter->flags |= IGB_FLAG_EEE; 3646 } 3647 } 3648 break; 3649 default: 3650 break; 3651 } 3652 } 3653 3654 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 3655 3656 pm_runtime_put_noidle(&pdev->dev); 3657 return 0; 3658 3659 err_register: 3660 igb_release_hw_control(adapter); 3661 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 3662 err_eeprom: 3663 if (!igb_check_reset_block(hw)) 3664 igb_reset_phy(hw); 3665 3666 if (hw->flash_address) 3667 iounmap(hw->flash_address); 3668 err_sw_init: 3669 kfree(adapter->mac_table); 3670 kfree(adapter->shadow_vfta); 3671 igb_clear_interrupt_scheme(adapter); 3672 #ifdef CONFIG_PCI_IOV 3673 igb_disable_sriov(pdev, false); 3674 #endif 3675 pci_iounmap(pdev, adapter->io_addr); 3676 err_ioremap: 3677 free_netdev(netdev); 3678 err_alloc_etherdev: 3679 pci_release_mem_regions(pdev); 3680 err_pci_reg: 3681 err_dma: 3682 pci_disable_device(pdev); 3683 return err; 3684 } 3685 3686 #ifdef CONFIG_PCI_IOV 3687 static int igb_sriov_reinit(struct pci_dev *dev) 3688 { 3689 struct net_device *netdev = pci_get_drvdata(dev); 3690 struct igb_adapter *adapter = netdev_priv(netdev); 3691 struct pci_dev *pdev = adapter->pdev; 3692 3693 rtnl_lock(); 3694 3695 if (netif_running(netdev)) 3696 igb_close(netdev); 3697 else 3698 igb_reset(adapter); 3699 3700 igb_clear_interrupt_scheme(adapter); 3701 3702 igb_init_queue_configuration(adapter); 3703 3704 if (igb_init_interrupt_scheme(adapter, true)) { 3705 rtnl_unlock(); 3706 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3707 return -ENOMEM; 3708 } 3709 3710 if (netif_running(netdev)) 3711 igb_open(netdev); 3712 3713 rtnl_unlock(); 3714 3715 return 0; 3716 } 3717 3718 static int igb_disable_sriov(struct pci_dev *pdev, bool reinit) 3719 { 3720 struct net_device *netdev = pci_get_drvdata(pdev); 3721 struct igb_adapter *adapter = netdev_priv(netdev); 3722 struct e1000_hw *hw = &adapter->hw; 3723 unsigned long flags; 3724 3725 /* reclaim resources allocated to VFs */ 3726 if (adapter->vf_data) { 3727 /* disable iov and allow time for transactions to clear */ 3728 if (pci_vfs_assigned(pdev)) { 3729 dev_warn(&pdev->dev, 3730 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 3731 return -EPERM; 3732 } else { 3733 pci_disable_sriov(pdev); 3734 msleep(500); 3735 } 3736 spin_lock_irqsave(&adapter->vfs_lock, flags); 3737 kfree(adapter->vf_mac_list); 3738 adapter->vf_mac_list = NULL; 3739 kfree(adapter->vf_data); 3740 adapter->vf_data = NULL; 3741 adapter->vfs_allocated_count = 0; 3742 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 3743 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 3744 wrfl(); 3745 msleep(100); 3746 dev_info(&pdev->dev, "IOV Disabled\n"); 3747 3748 /* Re-enable DMA Coalescing flag since IOV is turned off */ 3749 adapter->flags |= IGB_FLAG_DMAC; 3750 } 3751 3752 return reinit ? igb_sriov_reinit(pdev) : 0; 3753 } 3754 3755 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs, bool reinit) 3756 { 3757 struct net_device *netdev = pci_get_drvdata(pdev); 3758 struct igb_adapter *adapter = netdev_priv(netdev); 3759 int old_vfs = pci_num_vf(pdev); 3760 struct vf_mac_filter *mac_list; 3761 int err = 0; 3762 int num_vf_mac_filters, i; 3763 3764 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 3765 err = -EPERM; 3766 goto out; 3767 } 3768 if (!num_vfs) 3769 goto out; 3770 3771 if (old_vfs) { 3772 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 3773 old_vfs, max_vfs); 3774 adapter->vfs_allocated_count = old_vfs; 3775 } else 3776 adapter->vfs_allocated_count = num_vfs; 3777 3778 adapter->vf_data = kzalloc_objs(struct vf_data_storage, 3779 adapter->vfs_allocated_count); 3780 3781 /* if allocation failed then we do not support SR-IOV */ 3782 if (!adapter->vf_data) { 3783 adapter->vfs_allocated_count = 0; 3784 err = -ENOMEM; 3785 goto out; 3786 } 3787 3788 /* Due to the limited number of RAR entries calculate potential 3789 * number of MAC filters available for the VFs. Reserve entries 3790 * for PF default MAC, PF MAC filters and at least one RAR entry 3791 * for each VF for VF MAC. 3792 */ 3793 num_vf_mac_filters = adapter->hw.mac.rar_entry_count - 3794 (1 + IGB_PF_MAC_FILTERS_RESERVED + 3795 adapter->vfs_allocated_count); 3796 3797 adapter->vf_mac_list = kzalloc_objs(struct vf_mac_filter, 3798 num_vf_mac_filters); 3799 3800 mac_list = adapter->vf_mac_list; 3801 INIT_LIST_HEAD(&adapter->vf_macs.l); 3802 3803 if (adapter->vf_mac_list) { 3804 /* Initialize list of VF MAC filters */ 3805 for (i = 0; i < num_vf_mac_filters; i++) { 3806 mac_list->vf = -1; 3807 mac_list->free = true; 3808 list_add(&mac_list->l, &adapter->vf_macs.l); 3809 mac_list++; 3810 } 3811 } else { 3812 /* If we could not allocate memory for the VF MAC filters 3813 * we can continue without this feature but warn user. 3814 */ 3815 dev_err(&pdev->dev, 3816 "Unable to allocate memory for VF MAC filter list\n"); 3817 } 3818 3819 dev_info(&pdev->dev, "%d VFs allocated\n", 3820 adapter->vfs_allocated_count); 3821 for (i = 0; i < adapter->vfs_allocated_count; i++) 3822 igb_vf_configure(adapter, i); 3823 3824 /* DMA Coalescing is not supported in IOV mode. */ 3825 adapter->flags &= ~IGB_FLAG_DMAC; 3826 3827 if (reinit) { 3828 err = igb_sriov_reinit(pdev); 3829 if (err) 3830 goto err_out; 3831 } 3832 3833 /* only call pci_enable_sriov() if no VFs are allocated already */ 3834 if (!old_vfs) { 3835 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 3836 if (err) 3837 goto err_out; 3838 } 3839 3840 goto out; 3841 3842 err_out: 3843 kfree(adapter->vf_mac_list); 3844 adapter->vf_mac_list = NULL; 3845 kfree(adapter->vf_data); 3846 adapter->vf_data = NULL; 3847 adapter->vfs_allocated_count = 0; 3848 out: 3849 return err; 3850 } 3851 3852 #endif 3853 /** 3854 * igb_remove_i2c - Cleanup I2C interface 3855 * @adapter: pointer to adapter structure 3856 **/ 3857 static void igb_remove_i2c(struct igb_adapter *adapter) 3858 { 3859 /* free the adapter bus structure */ 3860 i2c_del_adapter(&adapter->i2c_adap); 3861 } 3862 3863 /** 3864 * igb_remove - Device Removal Routine 3865 * @pdev: PCI device information struct 3866 * 3867 * igb_remove is called by the PCI subsystem to alert the driver 3868 * that it should release a PCI device. The could be caused by a 3869 * Hot-Plug event, or because the driver is going to be removed from 3870 * memory. 3871 **/ 3872 static void igb_remove(struct pci_dev *pdev) 3873 { 3874 struct net_device *netdev = pci_get_drvdata(pdev); 3875 struct igb_adapter *adapter = netdev_priv(netdev); 3876 struct e1000_hw *hw = &adapter->hw; 3877 3878 pm_runtime_get_noresume(&pdev->dev); 3879 #ifdef CONFIG_IGB_HWMON 3880 igb_sysfs_exit(adapter); 3881 #endif 3882 igb_remove_i2c(adapter); 3883 igb_ptp_stop(adapter); 3884 /* The watchdog timer may be rescheduled, so explicitly 3885 * disable watchdog from being rescheduled. 3886 */ 3887 set_bit(__IGB_DOWN, &adapter->state); 3888 timer_delete_sync(&adapter->watchdog_timer); 3889 timer_delete_sync(&adapter->phy_info_timer); 3890 3891 cancel_work_sync(&adapter->reset_task); 3892 cancel_work_sync(&adapter->watchdog_task); 3893 3894 #ifdef CONFIG_IGB_DCA 3895 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 3896 dev_info(&pdev->dev, "DCA disabled\n"); 3897 dca_remove_requester(&pdev->dev); 3898 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 3899 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 3900 } 3901 #endif 3902 3903 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3904 * would have already happened in close and is redundant. 3905 */ 3906 igb_release_hw_control(adapter); 3907 3908 #ifdef CONFIG_PCI_IOV 3909 igb_disable_sriov(pdev, false); 3910 #endif 3911 3912 unregister_netdev(netdev); 3913 3914 igb_clear_interrupt_scheme(adapter); 3915 3916 pci_iounmap(pdev, adapter->io_addr); 3917 if (hw->flash_address) 3918 iounmap(hw->flash_address); 3919 pci_release_mem_regions(pdev); 3920 3921 kfree(adapter->mac_table); 3922 kfree(adapter->shadow_vfta); 3923 free_netdev(netdev); 3924 3925 pci_disable_device(pdev); 3926 } 3927 3928 /** 3929 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 3930 * @adapter: board private structure to initialize 3931 * 3932 * This function initializes the vf specific data storage and then attempts to 3933 * allocate the VFs. The reason for ordering it this way is because it is much 3934 * more expensive time wise to disable SR-IOV than it is to allocate and free 3935 * the memory for the VFs. 3936 **/ 3937 static void igb_probe_vfs(struct igb_adapter *adapter) 3938 { 3939 #ifdef CONFIG_PCI_IOV 3940 struct pci_dev *pdev = adapter->pdev; 3941 struct e1000_hw *hw = &adapter->hw; 3942 3943 /* Virtualization features not supported on i210 and 82580 family. */ 3944 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || 3945 (hw->mac.type == e1000_82580)) 3946 return; 3947 3948 /* Of the below we really only want the effect of getting 3949 * IGB_FLAG_HAS_MSIX set (if available), without which 3950 * igb_enable_sriov() has no effect. 3951 */ 3952 igb_set_interrupt_capability(adapter, true); 3953 igb_reset_interrupt_capability(adapter); 3954 3955 pci_sriov_set_totalvfs(pdev, 7); 3956 igb_enable_sriov(pdev, max_vfs, false); 3957 3958 #endif /* CONFIG_PCI_IOV */ 3959 } 3960 3961 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter) 3962 { 3963 struct e1000_hw *hw = &adapter->hw; 3964 unsigned int max_rss_queues; 3965 3966 /* Determine the maximum number of RSS queues supported. */ 3967 switch (hw->mac.type) { 3968 case e1000_i211: 3969 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 3970 break; 3971 case e1000_82575: 3972 case e1000_i210: 3973 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 3974 break; 3975 case e1000_i350: 3976 /* I350 cannot do RSS and SR-IOV at the same time */ 3977 if (!!adapter->vfs_allocated_count) { 3978 max_rss_queues = 1; 3979 break; 3980 } 3981 fallthrough; 3982 case e1000_82576: 3983 if (!!adapter->vfs_allocated_count) { 3984 max_rss_queues = 2; 3985 break; 3986 } 3987 fallthrough; 3988 case e1000_82580: 3989 case e1000_i354: 3990 default: 3991 max_rss_queues = IGB_MAX_RX_QUEUES; 3992 break; 3993 } 3994 3995 return max_rss_queues; 3996 } 3997 3998 static void igb_init_queue_configuration(struct igb_adapter *adapter) 3999 { 4000 u32 max_rss_queues; 4001 4002 max_rss_queues = igb_get_max_rss_queues(adapter); 4003 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4004 4005 igb_set_flag_queue_pairs(adapter, max_rss_queues); 4006 } 4007 4008 void igb_set_flag_queue_pairs(struct igb_adapter *adapter, 4009 const u32 max_rss_queues) 4010 { 4011 struct e1000_hw *hw = &adapter->hw; 4012 4013 /* Determine if we need to pair queues. */ 4014 switch (hw->mac.type) { 4015 case e1000_82575: 4016 case e1000_i211: 4017 /* Device supports enough interrupts without queue pairing. */ 4018 break; 4019 case e1000_82576: 4020 case e1000_82580: 4021 case e1000_i350: 4022 case e1000_i354: 4023 case e1000_i210: 4024 default: 4025 /* If rss_queues > half of max_rss_queues, pair the queues in 4026 * order to conserve interrupts due to limited supply. 4027 */ 4028 if (adapter->rss_queues > (max_rss_queues / 2)) 4029 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 4030 else 4031 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS; 4032 break; 4033 } 4034 } 4035 4036 /** 4037 * igb_sw_init - Initialize general software structures (struct igb_adapter) 4038 * @adapter: board private structure to initialize 4039 * 4040 * igb_sw_init initializes the Adapter private data structure. 4041 * Fields are initialized based on PCI device information and 4042 * OS network device settings (MTU size). 4043 **/ 4044 static int igb_sw_init(struct igb_adapter *adapter) 4045 { 4046 struct e1000_hw *hw = &adapter->hw; 4047 struct net_device *netdev = adapter->netdev; 4048 struct pci_dev *pdev = adapter->pdev; 4049 4050 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4051 4052 /* set default ring sizes */ 4053 adapter->tx_ring_count = IGB_DEFAULT_TXD; 4054 adapter->rx_ring_count = IGB_DEFAULT_RXD; 4055 4056 /* set default ITR values */ 4057 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 4058 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 4059 4060 /* set default work limits */ 4061 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 4062 4063 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD; 4064 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4065 4066 spin_lock_init(&adapter->nfc_lock); 4067 spin_lock_init(&adapter->stats64_lock); 4068 4069 /* init spinlock to avoid concurrency of VF resources */ 4070 spin_lock_init(&adapter->vfs_lock); 4071 #ifdef CONFIG_PCI_IOV 4072 switch (hw->mac.type) { 4073 case e1000_82576: 4074 case e1000_i350: 4075 if (max_vfs > 7) { 4076 dev_warn(&pdev->dev, 4077 "Maximum of 7 VFs per PF, using max\n"); 4078 max_vfs = adapter->vfs_allocated_count = 7; 4079 } else 4080 adapter->vfs_allocated_count = max_vfs; 4081 if (adapter->vfs_allocated_count) 4082 dev_warn(&pdev->dev, 4083 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 4084 break; 4085 default: 4086 break; 4087 } 4088 #endif /* CONFIG_PCI_IOV */ 4089 4090 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4091 adapter->flags |= IGB_FLAG_HAS_MSIX; 4092 4093 adapter->mac_table = kzalloc_objs(struct igb_mac_addr, 4094 hw->mac.rar_entry_count); 4095 if (!adapter->mac_table) 4096 return -ENOMEM; 4097 4098 igb_probe_vfs(adapter); 4099 4100 igb_init_queue_configuration(adapter); 4101 4102 /* Setup and initialize a copy of the hw vlan table array */ 4103 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 4104 GFP_KERNEL); 4105 if (!adapter->shadow_vfta) 4106 return -ENOMEM; 4107 4108 /* This call may decrease the number of queues */ 4109 if (igb_init_interrupt_scheme(adapter, true)) { 4110 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4111 return -ENOMEM; 4112 } 4113 4114 /* Explicitly disable IRQ since the NIC can be in any state. */ 4115 igb_irq_disable(adapter); 4116 4117 if (hw->mac.type >= e1000_i350) 4118 adapter->flags &= ~IGB_FLAG_DMAC; 4119 4120 set_bit(__IGB_DOWN, &adapter->state); 4121 return 0; 4122 } 4123 4124 /** 4125 * __igb_open - Called when a network interface is made active 4126 * @netdev: network interface device structure 4127 * @resuming: indicates whether we are in a resume call 4128 * 4129 * Returns 0 on success, negative value on failure 4130 * 4131 * The open entry point is called when a network interface is made 4132 * active by the system (IFF_UP). At this point all resources needed 4133 * for transmit and receive operations are allocated, the interrupt 4134 * handler is registered with the OS, the watchdog timer is started, 4135 * and the stack is notified that the interface is ready. 4136 **/ 4137 static int __igb_open(struct net_device *netdev, bool resuming) 4138 { 4139 struct igb_adapter *adapter = netdev_priv(netdev); 4140 struct pci_dev *pdev = adapter->pdev; 4141 struct e1000_hw *hw = &adapter->hw; 4142 struct napi_struct *napi; 4143 int err; 4144 int i; 4145 4146 /* disallow open during test */ 4147 if (test_bit(__IGB_TESTING, &adapter->state)) { 4148 WARN_ON(resuming); 4149 return -EBUSY; 4150 } 4151 4152 if (!resuming) 4153 pm_runtime_get_sync(&pdev->dev); 4154 4155 netif_carrier_off(netdev); 4156 4157 /* allocate transmit descriptors */ 4158 err = igb_setup_all_tx_resources(adapter); 4159 if (err) 4160 goto err_setup_tx; 4161 4162 /* allocate receive descriptors */ 4163 err = igb_setup_all_rx_resources(adapter); 4164 if (err) 4165 goto err_setup_rx; 4166 4167 igb_power_up_link(adapter); 4168 4169 /* before we allocate an interrupt, we must be ready to handle it. 4170 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 4171 * as soon as we call pci_request_irq, so we have to setup our 4172 * clean_rx handler before we do so. 4173 */ 4174 igb_configure(adapter); 4175 4176 err = igb_request_irq(adapter); 4177 if (err) 4178 goto err_req_irq; 4179 4180 /* Notify the stack of the actual queue counts. */ 4181 err = netif_set_real_num_tx_queues(adapter->netdev, 4182 adapter->num_tx_queues); 4183 if (err) 4184 goto err_set_queues; 4185 4186 err = netif_set_real_num_rx_queues(adapter->netdev, 4187 adapter->num_rx_queues); 4188 if (err) 4189 goto err_set_queues; 4190 4191 /* From here on the code is the same as igb_up() */ 4192 clear_bit(__IGB_DOWN, &adapter->state); 4193 4194 for (i = 0; i < adapter->num_q_vectors; i++) { 4195 napi = &adapter->q_vector[i]->napi; 4196 napi_enable(napi); 4197 igb_set_queue_napi(adapter, i, napi); 4198 } 4199 4200 /* Clear any pending interrupts. */ 4201 rd32(E1000_TSICR); 4202 rd32(E1000_ICR); 4203 4204 igb_irq_enable(adapter); 4205 4206 /* notify VFs that reset has been completed */ 4207 if (adapter->vfs_allocated_count) { 4208 u32 reg_data = rd32(E1000_CTRL_EXT); 4209 4210 reg_data |= E1000_CTRL_EXT_PFRSTD; 4211 wr32(E1000_CTRL_EXT, reg_data); 4212 } 4213 4214 netif_tx_start_all_queues(netdev); 4215 4216 if (!resuming) 4217 pm_runtime_put(&pdev->dev); 4218 4219 /* start the watchdog. */ 4220 hw->mac.get_link_status = 1; 4221 schedule_work(&adapter->watchdog_task); 4222 4223 return 0; 4224 4225 err_set_queues: 4226 igb_free_irq(adapter); 4227 err_req_irq: 4228 igb_release_hw_control(adapter); 4229 igb_power_down_link(adapter); 4230 igb_free_all_rx_resources(adapter); 4231 err_setup_rx: 4232 igb_free_all_tx_resources(adapter); 4233 err_setup_tx: 4234 igb_reset(adapter); 4235 if (!resuming) 4236 pm_runtime_put(&pdev->dev); 4237 4238 return err; 4239 } 4240 4241 int igb_open(struct net_device *netdev) 4242 { 4243 return __igb_open(netdev, false); 4244 } 4245 4246 /** 4247 * __igb_close - Disables a network interface 4248 * @netdev: network interface device structure 4249 * @suspending: indicates we are in a suspend call 4250 * 4251 * Returns 0, this is not allowed to fail 4252 * 4253 * The close entry point is called when an interface is de-activated 4254 * by the OS. The hardware is still under the driver's control, but 4255 * needs to be disabled. A global MAC reset is issued to stop the 4256 * hardware, and all transmit and receive resources are freed. 4257 **/ 4258 static int __igb_close(struct net_device *netdev, bool suspending) 4259 { 4260 struct igb_adapter *adapter = netdev_priv(netdev); 4261 struct pci_dev *pdev = adapter->pdev; 4262 4263 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 4264 4265 if (!suspending) 4266 pm_runtime_get_sync(&pdev->dev); 4267 4268 igb_down(adapter); 4269 igb_free_irq(adapter); 4270 4271 igb_free_all_tx_resources(adapter); 4272 igb_free_all_rx_resources(adapter); 4273 4274 if (!suspending) 4275 pm_runtime_put_sync(&pdev->dev); 4276 return 0; 4277 } 4278 4279 int igb_close(struct net_device *netdev) 4280 { 4281 if (netif_device_present(netdev) || netdev->dismantle) 4282 return __igb_close(netdev, false); 4283 return 0; 4284 } 4285 4286 /** 4287 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 4288 * @tx_ring: tx descriptor ring (for a specific queue) to setup 4289 * 4290 * Return 0 on success, negative on failure 4291 **/ 4292 int igb_setup_tx_resources(struct igb_ring *tx_ring) 4293 { 4294 struct device *dev = tx_ring->dev; 4295 int size; 4296 4297 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 4298 4299 tx_ring->tx_buffer_info = vmalloc(size); 4300 if (!tx_ring->tx_buffer_info) 4301 goto err; 4302 4303 /* round up to nearest 4K */ 4304 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 4305 tx_ring->size = ALIGN(tx_ring->size, 4096); 4306 4307 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 4308 &tx_ring->dma, GFP_KERNEL); 4309 if (!tx_ring->desc) 4310 goto err; 4311 4312 tx_ring->next_to_use = 0; 4313 tx_ring->next_to_clean = 0; 4314 4315 return 0; 4316 4317 err: 4318 vfree(tx_ring->tx_buffer_info); 4319 tx_ring->tx_buffer_info = NULL; 4320 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 4321 return -ENOMEM; 4322 } 4323 4324 /** 4325 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 4326 * (Descriptors) for all queues 4327 * @adapter: board private structure 4328 * 4329 * Return 0 on success, negative on failure 4330 **/ 4331 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 4332 { 4333 struct pci_dev *pdev = adapter->pdev; 4334 int i, err = 0; 4335 4336 for (i = 0; i < adapter->num_tx_queues; i++) { 4337 err = igb_setup_tx_resources(adapter->tx_ring[i]); 4338 if (err) { 4339 dev_err(&pdev->dev, 4340 "Allocation for Tx Queue %u failed\n", i); 4341 for (i--; i >= 0; i--) 4342 igb_free_tx_resources(adapter->tx_ring[i]); 4343 break; 4344 } 4345 } 4346 4347 return err; 4348 } 4349 4350 /** 4351 * igb_setup_tctl - configure the transmit control registers 4352 * @adapter: Board private structure 4353 **/ 4354 void igb_setup_tctl(struct igb_adapter *adapter) 4355 { 4356 struct e1000_hw *hw = &adapter->hw; 4357 u32 tctl; 4358 4359 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 4360 wr32(E1000_TXDCTL(0), 0); 4361 4362 /* Program the Transmit Control Register */ 4363 tctl = rd32(E1000_TCTL); 4364 tctl &= ~E1000_TCTL_CT; 4365 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 4366 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 4367 4368 igb_config_collision_dist(hw); 4369 4370 /* Enable transmits */ 4371 tctl |= E1000_TCTL_EN; 4372 4373 wr32(E1000_TCTL, tctl); 4374 } 4375 4376 /** 4377 * igb_configure_tx_ring - Configure transmit ring after Reset 4378 * @adapter: board private structure 4379 * @ring: tx ring to configure 4380 * 4381 * Configure a transmit ring after a reset. 4382 **/ 4383 void igb_configure_tx_ring(struct igb_adapter *adapter, 4384 struct igb_ring *ring) 4385 { 4386 struct e1000_hw *hw = &adapter->hw; 4387 u32 txdctl = 0; 4388 u64 tdba = ring->dma; 4389 int reg_idx = ring->reg_idx; 4390 4391 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4392 4393 wr32(E1000_TDLEN(reg_idx), 4394 ring->count * sizeof(union e1000_adv_tx_desc)); 4395 wr32(E1000_TDBAL(reg_idx), 4396 tdba & 0x00000000ffffffffULL); 4397 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 4398 4399 ring->tail = adapter->io_addr + E1000_TDT(reg_idx); 4400 wr32(E1000_TDH(reg_idx), 0); 4401 writel(0, ring->tail); 4402 4403 txdctl |= IGB_TX_PTHRESH; 4404 txdctl |= IGB_TX_HTHRESH << 8; 4405 txdctl |= IGB_TX_WTHRESH << 16; 4406 4407 /* reinitialize tx_buffer_info */ 4408 memset(ring->tx_buffer_info, 0, 4409 sizeof(struct igb_tx_buffer) * ring->count); 4410 4411 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 4412 wr32(E1000_TXDCTL(reg_idx), txdctl); 4413 } 4414 4415 /** 4416 * igb_configure_tx - Configure transmit Unit after Reset 4417 * @adapter: board private structure 4418 * 4419 * Configure the Tx unit of the MAC after a reset. 4420 **/ 4421 static void igb_configure_tx(struct igb_adapter *adapter) 4422 { 4423 struct e1000_hw *hw = &adapter->hw; 4424 int i; 4425 4426 /* disable the queues */ 4427 for (i = 0; i < adapter->num_tx_queues; i++) 4428 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); 4429 4430 wrfl(); 4431 usleep_range(10000, 20000); 4432 4433 for (i = 0; i < adapter->num_tx_queues; i++) 4434 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 4435 } 4436 4437 /** 4438 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 4439 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 4440 * 4441 * Returns 0 on success, negative on failure 4442 **/ 4443 int igb_setup_rx_resources(struct igb_ring *rx_ring) 4444 { 4445 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev); 4446 struct device *dev = rx_ring->dev; 4447 int size, res; 4448 4449 /* XDP RX-queue info */ 4450 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 4451 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4452 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 4453 rx_ring->queue_index, 0); 4454 if (res < 0) { 4455 dev_err(dev, "Failed to register xdp_rxq index %u\n", 4456 rx_ring->queue_index); 4457 return res; 4458 } 4459 4460 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 4461 4462 rx_ring->rx_buffer_info = vmalloc(size); 4463 if (!rx_ring->rx_buffer_info) 4464 goto err; 4465 4466 /* Round up to nearest 4K */ 4467 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 4468 rx_ring->size = ALIGN(rx_ring->size, 4096); 4469 4470 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 4471 &rx_ring->dma, GFP_KERNEL); 4472 if (!rx_ring->desc) 4473 goto err; 4474 4475 rx_ring->next_to_alloc = 0; 4476 rx_ring->next_to_clean = 0; 4477 rx_ring->next_to_use = 0; 4478 4479 rx_ring->xdp_prog = adapter->xdp_prog; 4480 4481 return 0; 4482 4483 err: 4484 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 4485 vfree(rx_ring->rx_buffer_info); 4486 rx_ring->rx_buffer_info = NULL; 4487 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 4488 return -ENOMEM; 4489 } 4490 4491 /** 4492 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 4493 * (Descriptors) for all queues 4494 * @adapter: board private structure 4495 * 4496 * Return 0 on success, negative on failure 4497 **/ 4498 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 4499 { 4500 struct pci_dev *pdev = adapter->pdev; 4501 int i, err = 0; 4502 4503 for (i = 0; i < adapter->num_rx_queues; i++) { 4504 err = igb_setup_rx_resources(adapter->rx_ring[i]); 4505 if (err) { 4506 dev_err(&pdev->dev, 4507 "Allocation for Rx Queue %u failed\n", i); 4508 for (i--; i >= 0; i--) 4509 igb_free_rx_resources(adapter->rx_ring[i]); 4510 break; 4511 } 4512 } 4513 4514 return err; 4515 } 4516 4517 /** 4518 * igb_setup_mrqc - configure the multiple receive queue control registers 4519 * @adapter: Board private structure 4520 **/ 4521 static void igb_setup_mrqc(struct igb_adapter *adapter) 4522 { 4523 struct e1000_hw *hw = &adapter->hw; 4524 u32 mrqc, rxcsum; 4525 u32 j, num_rx_queues; 4526 u32 rss_key[10]; 4527 4528 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 4529 for (j = 0; j < 10; j++) 4530 wr32(E1000_RSSRK(j), rss_key[j]); 4531 4532 num_rx_queues = adapter->rss_queues; 4533 4534 switch (hw->mac.type) { 4535 case e1000_82576: 4536 /* 82576 supports 2 RSS queues for SR-IOV */ 4537 if (adapter->vfs_allocated_count) 4538 num_rx_queues = 2; 4539 break; 4540 default: 4541 break; 4542 } 4543 4544 if (adapter->rss_indir_tbl_init != num_rx_queues) { 4545 for (j = 0; j < IGB_RETA_SIZE; j++) 4546 adapter->rss_indir_tbl[j] = 4547 (j * num_rx_queues) / IGB_RETA_SIZE; 4548 adapter->rss_indir_tbl_init = num_rx_queues; 4549 } 4550 igb_write_rss_indir_tbl(adapter); 4551 4552 /* Disable raw packet checksumming so that RSS hash is placed in 4553 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 4554 * offloads as they are enabled by default 4555 */ 4556 rxcsum = rd32(E1000_RXCSUM); 4557 rxcsum |= E1000_RXCSUM_PCSD; 4558 4559 if (adapter->hw.mac.type >= e1000_82576) 4560 /* Enable Receive Checksum Offload for SCTP */ 4561 rxcsum |= E1000_RXCSUM_CRCOFL; 4562 4563 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 4564 wr32(E1000_RXCSUM, rxcsum); 4565 4566 /* Generate RSS hash based on packet types, TCP/UDP 4567 * port numbers and/or IPv4/v6 src and dst addresses 4568 */ 4569 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 4570 E1000_MRQC_RSS_FIELD_IPV4_TCP | 4571 E1000_MRQC_RSS_FIELD_IPV6 | 4572 E1000_MRQC_RSS_FIELD_IPV6_TCP | 4573 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 4574 4575 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 4576 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 4577 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 4578 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 4579 4580 /* If VMDq is enabled then we set the appropriate mode for that, else 4581 * we default to RSS so that an RSS hash is calculated per packet even 4582 * if we are only using one queue 4583 */ 4584 if (adapter->vfs_allocated_count) { 4585 if (hw->mac.type > e1000_82575) { 4586 /* Set the default pool for the PF's first queue */ 4587 u32 vtctl = rd32(E1000_VT_CTL); 4588 4589 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 4590 E1000_VT_CTL_DISABLE_DEF_POOL); 4591 vtctl |= adapter->vfs_allocated_count << 4592 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 4593 wr32(E1000_VT_CTL, vtctl); 4594 } 4595 if (adapter->rss_queues > 1) 4596 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ; 4597 else 4598 mrqc |= E1000_MRQC_ENABLE_VMDQ; 4599 } else { 4600 mrqc |= E1000_MRQC_ENABLE_RSS_MQ; 4601 } 4602 igb_vmm_control(adapter); 4603 4604 wr32(E1000_MRQC, mrqc); 4605 } 4606 4607 /** 4608 * igb_setup_rctl - configure the receive control registers 4609 * @adapter: Board private structure 4610 **/ 4611 void igb_setup_rctl(struct igb_adapter *adapter) 4612 { 4613 struct e1000_hw *hw = &adapter->hw; 4614 u32 rctl; 4615 4616 rctl = rd32(E1000_RCTL); 4617 4618 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4619 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 4620 4621 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 4622 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4623 4624 /* enable stripping of CRC. It's unlikely this will break BMC 4625 * redirection as it did with e1000. Newer features require 4626 * that the HW strips the CRC. 4627 */ 4628 rctl |= E1000_RCTL_SECRC; 4629 4630 /* disable store bad packets and clear size bits. */ 4631 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 4632 4633 /* enable LPE to allow for reception of jumbo frames */ 4634 rctl |= E1000_RCTL_LPE; 4635 4636 /* disable queue 0 to prevent tail write w/o re-config */ 4637 wr32(E1000_RXDCTL(0), 0); 4638 4639 /* Attention!!! For SR-IOV PF driver operations you must enable 4640 * queue drop for all VF and PF queues to prevent head of line blocking 4641 * if an un-trusted VF does not provide descriptors to hardware. 4642 */ 4643 if (adapter->vfs_allocated_count) { 4644 /* set all queue drop enable bits */ 4645 wr32(E1000_QDE, ALL_QUEUES); 4646 } 4647 4648 /* This is useful for sniffing bad packets. */ 4649 if (adapter->netdev->features & NETIF_F_RXALL) { 4650 /* UPE and MPE will be handled by normal PROMISC logic 4651 * in e1000e_set_rx_mode 4652 */ 4653 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 4654 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 4655 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 4656 4657 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */ 4658 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 4659 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 4660 * and that breaks VLANs. 4661 */ 4662 } 4663 4664 wr32(E1000_RCTL, rctl); 4665 } 4666 4667 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 4668 int vfn) 4669 { 4670 struct e1000_hw *hw = &adapter->hw; 4671 u32 vmolr; 4672 4673 if (size > MAX_JUMBO_FRAME_SIZE) 4674 size = MAX_JUMBO_FRAME_SIZE; 4675 4676 vmolr = rd32(E1000_VMOLR(vfn)); 4677 vmolr &= ~E1000_VMOLR_RLPML_MASK; 4678 vmolr |= size | E1000_VMOLR_LPE; 4679 wr32(E1000_VMOLR(vfn), vmolr); 4680 4681 return 0; 4682 } 4683 4684 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter, 4685 int vfn, bool enable) 4686 { 4687 struct e1000_hw *hw = &adapter->hw; 4688 u32 val, reg; 4689 4690 if (hw->mac.type < e1000_82576) 4691 return; 4692 4693 if (hw->mac.type == e1000_i350) 4694 reg = E1000_DVMOLR(vfn); 4695 else 4696 reg = E1000_VMOLR(vfn); 4697 4698 val = rd32(reg); 4699 if (enable) 4700 val |= E1000_VMOLR_STRVLAN; 4701 else 4702 val &= ~(E1000_VMOLR_STRVLAN); 4703 wr32(reg, val); 4704 } 4705 4706 static inline void igb_set_vmolr(struct igb_adapter *adapter, 4707 int vfn, bool aupe) 4708 { 4709 struct e1000_hw *hw = &adapter->hw; 4710 u32 vmolr; 4711 4712 /* This register exists only on 82576 and newer so if we are older then 4713 * we should exit and do nothing 4714 */ 4715 if (hw->mac.type < e1000_82576) 4716 return; 4717 4718 vmolr = rd32(E1000_VMOLR(vfn)); 4719 if (aupe) 4720 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 4721 else 4722 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 4723 4724 /* clear all bits that might not be set */ 4725 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 4726 4727 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 4728 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 4729 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 4730 * multicast packets 4731 */ 4732 if (vfn <= adapter->vfs_allocated_count) 4733 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 4734 4735 wr32(E1000_VMOLR(vfn), vmolr); 4736 } 4737 4738 /** 4739 * igb_setup_srrctl - configure the split and replication receive control 4740 * registers 4741 * @adapter: Board private structure 4742 * @ring: receive ring to be configured 4743 **/ 4744 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring) 4745 { 4746 struct e1000_hw *hw = &adapter->hw; 4747 int reg_idx = ring->reg_idx; 4748 u32 srrctl = 0; 4749 u32 buf_size; 4750 4751 if (ring->xsk_pool) 4752 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4753 else if (ring_uses_large_buffer(ring)) 4754 buf_size = IGB_RXBUFFER_3072; 4755 else 4756 buf_size = IGB_RXBUFFER_2048; 4757 4758 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 4759 srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT; 4760 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 4761 if (hw->mac.type >= e1000_82580) 4762 srrctl |= E1000_SRRCTL_TIMESTAMP; 4763 /* Only set Drop Enable if VFs allocated, or we are supporting multiple 4764 * queues and rx flow control is disabled 4765 */ 4766 if (adapter->vfs_allocated_count || 4767 (!(hw->fc.current_mode & e1000_fc_rx_pause) && 4768 adapter->num_rx_queues > 1)) 4769 srrctl |= E1000_SRRCTL_DROP_EN; 4770 4771 wr32(E1000_SRRCTL(reg_idx), srrctl); 4772 } 4773 4774 /** 4775 * igb_configure_rx_ring - Configure a receive ring after Reset 4776 * @adapter: board private structure 4777 * @ring: receive ring to be configured 4778 * 4779 * Configure the Rx unit of the MAC after a reset. 4780 **/ 4781 void igb_configure_rx_ring(struct igb_adapter *adapter, 4782 struct igb_ring *ring) 4783 { 4784 struct e1000_hw *hw = &adapter->hw; 4785 union e1000_adv_rx_desc *rx_desc; 4786 u64 rdba = ring->dma; 4787 int reg_idx = ring->reg_idx; 4788 u32 rxdctl = 0; 4789 4790 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4791 WRITE_ONCE(ring->xsk_pool, igb_xsk_pool(adapter, ring)); 4792 if (ring->xsk_pool) { 4793 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4794 MEM_TYPE_XSK_BUFF_POOL, 4795 NULL)); 4796 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4797 } else { 4798 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4799 MEM_TYPE_PAGE_SHARED, 4800 NULL)); 4801 } 4802 4803 /* disable the queue */ 4804 wr32(E1000_RXDCTL(reg_idx), 0); 4805 4806 /* Set DMA base address registers */ 4807 wr32(E1000_RDBAL(reg_idx), 4808 rdba & 0x00000000ffffffffULL); 4809 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 4810 wr32(E1000_RDLEN(reg_idx), 4811 ring->count * sizeof(union e1000_adv_rx_desc)); 4812 4813 /* initialize head and tail */ 4814 ring->tail = adapter->io_addr + E1000_RDT(reg_idx); 4815 wr32(E1000_RDH(reg_idx), 0); 4816 writel(0, ring->tail); 4817 4818 /* set descriptor configuration */ 4819 igb_setup_srrctl(adapter, ring); 4820 4821 /* set filtering for VMDQ pools */ 4822 igb_set_vmolr(adapter, reg_idx & 0x7, true); 4823 4824 rxdctl |= IGB_RX_PTHRESH; 4825 rxdctl |= IGB_RX_HTHRESH << 8; 4826 rxdctl |= IGB_RX_WTHRESH << 16; 4827 4828 if (ring->xsk_pool) 4829 memset(ring->rx_buffer_info_zc, 0, 4830 sizeof(*ring->rx_buffer_info_zc) * ring->count); 4831 else 4832 memset(ring->rx_buffer_info, 0, 4833 sizeof(*ring->rx_buffer_info) * ring->count); 4834 4835 /* initialize Rx descriptor 0 */ 4836 rx_desc = IGB_RX_DESC(ring, 0); 4837 rx_desc->wb.upper.length = 0; 4838 4839 /* enable receive descriptor fetching */ 4840 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 4841 wr32(E1000_RXDCTL(reg_idx), rxdctl); 4842 } 4843 4844 static void igb_set_rx_buffer_len(struct igb_adapter *adapter, 4845 struct igb_ring *rx_ring) 4846 { 4847 #if (PAGE_SIZE < 8192) 4848 struct e1000_hw *hw = &adapter->hw; 4849 #endif 4850 4851 /* set build_skb and buffer size flags */ 4852 clear_ring_build_skb_enabled(rx_ring); 4853 clear_ring_uses_large_buffer(rx_ring); 4854 4855 if (adapter->flags & IGB_FLAG_RX_LEGACY) 4856 return; 4857 4858 set_ring_build_skb_enabled(rx_ring); 4859 4860 #if (PAGE_SIZE < 8192) 4861 if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || 4862 IGB_2K_TOO_SMALL_WITH_PADDING || 4863 rd32(E1000_RCTL) & E1000_RCTL_SBP) 4864 set_ring_uses_large_buffer(rx_ring); 4865 #endif 4866 } 4867 4868 /** 4869 * igb_configure_rx - Configure receive Unit after Reset 4870 * @adapter: board private structure 4871 * 4872 * Configure the Rx unit of the MAC after a reset. 4873 **/ 4874 static void igb_configure_rx(struct igb_adapter *adapter) 4875 { 4876 int i; 4877 4878 /* set the correct pool for the PF default MAC address in entry 0 */ 4879 igb_set_default_mac_filter(adapter); 4880 4881 /* Setup the HW Rx Head and Tail Descriptor Pointers and 4882 * the Base and Length of the Rx Descriptor Ring 4883 */ 4884 for (i = 0; i < adapter->num_rx_queues; i++) { 4885 struct igb_ring *rx_ring = adapter->rx_ring[i]; 4886 4887 igb_set_rx_buffer_len(adapter, rx_ring); 4888 igb_configure_rx_ring(adapter, rx_ring); 4889 } 4890 } 4891 4892 /** 4893 * igb_free_tx_resources - Free Tx Resources per Queue 4894 * @tx_ring: Tx descriptor ring for a specific queue 4895 * 4896 * Free all transmit software resources 4897 **/ 4898 void igb_free_tx_resources(struct igb_ring *tx_ring) 4899 { 4900 igb_clean_tx_ring(tx_ring); 4901 4902 vfree(tx_ring->tx_buffer_info); 4903 tx_ring->tx_buffer_info = NULL; 4904 4905 /* if not set, then don't free */ 4906 if (!tx_ring->desc) 4907 return; 4908 4909 dma_free_coherent(tx_ring->dev, tx_ring->size, 4910 tx_ring->desc, tx_ring->dma); 4911 4912 tx_ring->desc = NULL; 4913 } 4914 4915 /** 4916 * igb_free_all_tx_resources - Free Tx Resources for All Queues 4917 * @adapter: board private structure 4918 * 4919 * Free all transmit software resources 4920 **/ 4921 static void igb_free_all_tx_resources(struct igb_adapter *adapter) 4922 { 4923 int i; 4924 4925 for (i = 0; i < adapter->num_tx_queues; i++) 4926 if (adapter->tx_ring[i]) 4927 igb_free_tx_resources(adapter->tx_ring[i]); 4928 } 4929 4930 /** 4931 * igb_clean_tx_ring - Free Tx Buffers 4932 * @tx_ring: ring to be cleaned 4933 **/ 4934 void igb_clean_tx_ring(struct igb_ring *tx_ring) 4935 { 4936 u16 i = tx_ring->next_to_clean; 4937 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 4938 u32 xsk_frames = 0; 4939 4940 while (i != tx_ring->next_to_use) { 4941 union e1000_adv_tx_desc *eop_desc, *tx_desc; 4942 4943 /* Free all the Tx ring sk_buffs or xdp frames */ 4944 if (tx_buffer->type == IGB_TYPE_SKB) { 4945 dev_kfree_skb_any(tx_buffer->skb); 4946 } else if (tx_buffer->type == IGB_TYPE_XDP) { 4947 xdp_return_frame(tx_buffer->xdpf); 4948 } else if (tx_buffer->type == IGB_TYPE_XSK) { 4949 xsk_frames++; 4950 goto skip_for_xsk; 4951 } 4952 4953 /* unmap skb header data */ 4954 dma_unmap_single(tx_ring->dev, 4955 dma_unmap_addr(tx_buffer, dma), 4956 dma_unmap_len(tx_buffer, len), 4957 DMA_TO_DEVICE); 4958 4959 /* check for eop_desc to determine the end of the packet */ 4960 eop_desc = tx_buffer->next_to_watch; 4961 tx_desc = IGB_TX_DESC(tx_ring, i); 4962 4963 /* unmap remaining buffers */ 4964 while (tx_desc != eop_desc) { 4965 tx_buffer++; 4966 tx_desc++; 4967 i++; 4968 if (unlikely(i == tx_ring->count)) { 4969 i = 0; 4970 tx_buffer = tx_ring->tx_buffer_info; 4971 tx_desc = IGB_TX_DESC(tx_ring, 0); 4972 } 4973 4974 /* unmap any remaining paged data */ 4975 if (dma_unmap_len(tx_buffer, len)) 4976 dma_unmap_page(tx_ring->dev, 4977 dma_unmap_addr(tx_buffer, dma), 4978 dma_unmap_len(tx_buffer, len), 4979 DMA_TO_DEVICE); 4980 } 4981 4982 skip_for_xsk: 4983 tx_buffer->next_to_watch = NULL; 4984 4985 /* move us one more past the eop_desc for start of next pkt */ 4986 tx_buffer++; 4987 i++; 4988 if (unlikely(i == tx_ring->count)) { 4989 i = 0; 4990 tx_buffer = tx_ring->tx_buffer_info; 4991 } 4992 } 4993 4994 /* reset BQL for queue */ 4995 netdev_tx_reset_queue(txring_txq(tx_ring)); 4996 4997 if (tx_ring->xsk_pool && xsk_frames) 4998 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 4999 5000 /* reset next_to_use and next_to_clean */ 5001 tx_ring->next_to_use = 0; 5002 tx_ring->next_to_clean = 0; 5003 } 5004 5005 /** 5006 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 5007 * @adapter: board private structure 5008 **/ 5009 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 5010 { 5011 int i; 5012 5013 for (i = 0; i < adapter->num_tx_queues; i++) 5014 if (adapter->tx_ring[i]) 5015 igb_clean_tx_ring(adapter->tx_ring[i]); 5016 } 5017 5018 /** 5019 * igb_free_rx_resources - Free Rx Resources 5020 * @rx_ring: ring to clean the resources from 5021 * 5022 * Free all receive software resources 5023 **/ 5024 void igb_free_rx_resources(struct igb_ring *rx_ring) 5025 { 5026 igb_clean_rx_ring(rx_ring); 5027 5028 rx_ring->xdp_prog = NULL; 5029 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 5030 if (rx_ring->xsk_pool) { 5031 vfree(rx_ring->rx_buffer_info_zc); 5032 rx_ring->rx_buffer_info_zc = NULL; 5033 } else { 5034 vfree(rx_ring->rx_buffer_info); 5035 rx_ring->rx_buffer_info = NULL; 5036 } 5037 5038 /* if not set, then don't free */ 5039 if (!rx_ring->desc) 5040 return; 5041 5042 dma_free_coherent(rx_ring->dev, rx_ring->size, 5043 rx_ring->desc, rx_ring->dma); 5044 5045 rx_ring->desc = NULL; 5046 } 5047 5048 /** 5049 * igb_free_all_rx_resources - Free Rx Resources for All Queues 5050 * @adapter: board private structure 5051 * 5052 * Free all receive software resources 5053 **/ 5054 static void igb_free_all_rx_resources(struct igb_adapter *adapter) 5055 { 5056 int i; 5057 5058 for (i = 0; i < adapter->num_rx_queues; i++) 5059 if (adapter->rx_ring[i]) 5060 igb_free_rx_resources(adapter->rx_ring[i]); 5061 } 5062 5063 /** 5064 * igb_clean_rx_ring - Free Rx Buffers per Queue 5065 * @rx_ring: ring to free buffers from 5066 **/ 5067 void igb_clean_rx_ring(struct igb_ring *rx_ring) 5068 { 5069 u16 i = rx_ring->next_to_clean; 5070 5071 dev_kfree_skb(rx_ring->skb); 5072 rx_ring->skb = NULL; 5073 5074 if (rx_ring->xsk_pool) { 5075 igb_clean_rx_ring_zc(rx_ring); 5076 goto skip_for_xsk; 5077 } 5078 5079 /* Free all the Rx ring sk_buffs */ 5080 while (i != rx_ring->next_to_alloc) { 5081 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5082 5083 /* Invalidate cache lines that may have been written to by 5084 * device so that we avoid corrupting memory. 5085 */ 5086 dma_sync_single_range_for_cpu(rx_ring->dev, 5087 buffer_info->dma, 5088 buffer_info->page_offset, 5089 igb_rx_bufsz(rx_ring), 5090 DMA_FROM_DEVICE); 5091 5092 /* free resources associated with mapping */ 5093 dma_unmap_page_attrs(rx_ring->dev, 5094 buffer_info->dma, 5095 igb_rx_pg_size(rx_ring), 5096 DMA_FROM_DEVICE, 5097 IGB_RX_DMA_ATTR); 5098 __page_frag_cache_drain(buffer_info->page, 5099 buffer_info->pagecnt_bias); 5100 5101 i++; 5102 if (i == rx_ring->count) 5103 i = 0; 5104 } 5105 5106 skip_for_xsk: 5107 rx_ring->next_to_alloc = 0; 5108 rx_ring->next_to_clean = 0; 5109 rx_ring->next_to_use = 0; 5110 } 5111 5112 /** 5113 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 5114 * @adapter: board private structure 5115 **/ 5116 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 5117 { 5118 int i; 5119 5120 for (i = 0; i < adapter->num_rx_queues; i++) 5121 if (adapter->rx_ring[i]) 5122 igb_clean_rx_ring(adapter->rx_ring[i]); 5123 } 5124 5125 /** 5126 * igb_set_mac - Change the Ethernet Address of the NIC 5127 * @netdev: network interface device structure 5128 * @p: pointer to an address structure 5129 * 5130 * Returns 0 on success, negative on failure 5131 **/ 5132 static int igb_set_mac(struct net_device *netdev, void *p) 5133 { 5134 struct igb_adapter *adapter = netdev_priv(netdev); 5135 struct e1000_hw *hw = &adapter->hw; 5136 struct sockaddr *addr = p; 5137 5138 if (!is_valid_ether_addr(addr->sa_data)) 5139 return -EADDRNOTAVAIL; 5140 5141 eth_hw_addr_set(netdev, addr->sa_data); 5142 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 5143 5144 /* set the correct pool for the new PF MAC address in entry 0 */ 5145 igb_set_default_mac_filter(adapter); 5146 5147 return 0; 5148 } 5149 5150 /** 5151 * igb_write_mc_addr_list - write multicast addresses to MTA 5152 * @netdev: network interface device structure 5153 * 5154 * Writes multicast address list to the MTA hash table. 5155 * Returns: -ENOMEM on failure 5156 * 0 on no addresses written 5157 * X on writing X addresses to MTA 5158 **/ 5159 static int igb_write_mc_addr_list(struct net_device *netdev) 5160 { 5161 struct igb_adapter *adapter = netdev_priv(netdev); 5162 struct e1000_hw *hw = &adapter->hw; 5163 struct netdev_hw_addr *ha; 5164 u8 *mta_list; 5165 int i; 5166 5167 if (netdev_mc_empty(netdev)) { 5168 /* nothing to program, so clear mc list */ 5169 igb_update_mc_addr_list(hw, NULL, 0); 5170 igb_restore_vf_multicasts(adapter); 5171 return 0; 5172 } 5173 5174 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 5175 if (!mta_list) 5176 return -ENOMEM; 5177 5178 /* The shared function expects a packed array of only addresses. */ 5179 i = 0; 5180 netdev_for_each_mc_addr(ha, netdev) 5181 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 5182 5183 igb_update_mc_addr_list(hw, mta_list, i); 5184 kfree(mta_list); 5185 5186 return netdev_mc_count(netdev); 5187 } 5188 5189 static int igb_vlan_promisc_enable(struct igb_adapter *adapter) 5190 { 5191 struct e1000_hw *hw = &adapter->hw; 5192 u32 i, pf_id; 5193 5194 switch (hw->mac.type) { 5195 case e1000_i210: 5196 case e1000_i211: 5197 case e1000_i350: 5198 /* VLAN filtering needed for VLAN prio filter */ 5199 if (adapter->netdev->features & NETIF_F_NTUPLE) 5200 break; 5201 fallthrough; 5202 case e1000_82576: 5203 case e1000_82580: 5204 case e1000_i354: 5205 /* VLAN filtering needed for pool filtering */ 5206 if (adapter->vfs_allocated_count) 5207 break; 5208 fallthrough; 5209 default: 5210 return 1; 5211 } 5212 5213 /* We are already in VLAN promisc, nothing to do */ 5214 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 5215 return 0; 5216 5217 if (!adapter->vfs_allocated_count) 5218 goto set_vfta; 5219 5220 /* Add PF to all active pools */ 5221 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5222 5223 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5224 u32 vlvf = rd32(E1000_VLVF(i)); 5225 5226 vlvf |= BIT(pf_id); 5227 wr32(E1000_VLVF(i), vlvf); 5228 } 5229 5230 set_vfta: 5231 /* Set all bits in the VLAN filter table array */ 5232 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;) 5233 hw->mac.ops.write_vfta(hw, i, ~0U); 5234 5235 /* Set flag so we don't redo unnecessary work */ 5236 adapter->flags |= IGB_FLAG_VLAN_PROMISC; 5237 5238 return 0; 5239 } 5240 5241 #define VFTA_BLOCK_SIZE 8 5242 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset) 5243 { 5244 struct e1000_hw *hw = &adapter->hw; 5245 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5246 u32 vid_start = vfta_offset * 32; 5247 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5248 u32 i, vid, word, bits, pf_id; 5249 5250 /* guarantee that we don't scrub out management VLAN */ 5251 vid = adapter->mng_vlan_id; 5252 if (vid >= vid_start && vid < vid_end) 5253 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5254 5255 if (!adapter->vfs_allocated_count) 5256 goto set_vfta; 5257 5258 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 5259 5260 for (i = E1000_VLVF_ARRAY_SIZE; --i;) { 5261 u32 vlvf = rd32(E1000_VLVF(i)); 5262 5263 /* pull VLAN ID from VLVF */ 5264 vid = vlvf & VLAN_VID_MASK; 5265 5266 /* only concern ourselves with a certain range */ 5267 if (vid < vid_start || vid >= vid_end) 5268 continue; 5269 5270 if (vlvf & E1000_VLVF_VLANID_ENABLE) { 5271 /* record VLAN ID in VFTA */ 5272 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5273 5274 /* if PF is part of this then continue */ 5275 if (test_bit(vid, adapter->active_vlans)) 5276 continue; 5277 } 5278 5279 /* remove PF from the pool */ 5280 bits = ~BIT(pf_id); 5281 bits &= rd32(E1000_VLVF(i)); 5282 wr32(E1000_VLVF(i), bits); 5283 } 5284 5285 set_vfta: 5286 /* extract values from active_vlans and write back to VFTA */ 5287 for (i = VFTA_BLOCK_SIZE; i--;) { 5288 vid = (vfta_offset + i) * 32; 5289 word = vid / BITS_PER_LONG; 5290 bits = vid % BITS_PER_LONG; 5291 5292 vfta[i] |= adapter->active_vlans[word] >> bits; 5293 5294 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]); 5295 } 5296 } 5297 5298 static void igb_vlan_promisc_disable(struct igb_adapter *adapter) 5299 { 5300 u32 i; 5301 5302 /* We are not in VLAN promisc, nothing to do */ 5303 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 5304 return; 5305 5306 /* Set flag so we don't redo unnecessary work */ 5307 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC; 5308 5309 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE) 5310 igb_scrub_vfta(adapter, i); 5311 } 5312 5313 /** 5314 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 5315 * @netdev: network interface device structure 5316 * 5317 * The set_rx_mode entry point is called whenever the unicast or multicast 5318 * address lists or the network interface flags are updated. This routine is 5319 * responsible for configuring the hardware for proper unicast, multicast, 5320 * promiscuous mode, and all-multi behavior. 5321 **/ 5322 static void igb_set_rx_mode(struct net_device *netdev) 5323 { 5324 struct igb_adapter *adapter = netdev_priv(netdev); 5325 struct e1000_hw *hw = &adapter->hw; 5326 unsigned int vfn = adapter->vfs_allocated_count; 5327 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 5328 int count; 5329 5330 /* Check for Promiscuous and All Multicast modes */ 5331 if (netdev->flags & IFF_PROMISC) { 5332 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE; 5333 vmolr |= E1000_VMOLR_MPME; 5334 5335 /* enable use of UTA filter to force packets to default pool */ 5336 if (hw->mac.type == e1000_82576) 5337 vmolr |= E1000_VMOLR_ROPE; 5338 } else { 5339 if (netdev->flags & IFF_ALLMULTI) { 5340 rctl |= E1000_RCTL_MPE; 5341 vmolr |= E1000_VMOLR_MPME; 5342 } else { 5343 /* Write addresses to the MTA, if the attempt fails 5344 * then we should just turn on promiscuous mode so 5345 * that we can at least receive multicast traffic 5346 */ 5347 count = igb_write_mc_addr_list(netdev); 5348 if (count < 0) { 5349 rctl |= E1000_RCTL_MPE; 5350 vmolr |= E1000_VMOLR_MPME; 5351 } else if (count) { 5352 vmolr |= E1000_VMOLR_ROMPE; 5353 } 5354 } 5355 } 5356 5357 /* Write addresses to available RAR registers, if there is not 5358 * sufficient space to store all the addresses then enable 5359 * unicast promiscuous mode 5360 */ 5361 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) { 5362 rctl |= E1000_RCTL_UPE; 5363 vmolr |= E1000_VMOLR_ROPE; 5364 } 5365 5366 /* enable VLAN filtering by default */ 5367 rctl |= E1000_RCTL_VFE; 5368 5369 /* disable VLAN filtering for modes that require it */ 5370 if ((netdev->flags & IFF_PROMISC) || 5371 (netdev->features & NETIF_F_RXALL)) { 5372 /* if we fail to set all rules then just clear VFE */ 5373 if (igb_vlan_promisc_enable(adapter)) 5374 rctl &= ~E1000_RCTL_VFE; 5375 } else { 5376 igb_vlan_promisc_disable(adapter); 5377 } 5378 5379 /* update state of unicast, multicast, and VLAN filtering modes */ 5380 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE | 5381 E1000_RCTL_VFE); 5382 wr32(E1000_RCTL, rctl); 5383 5384 #if (PAGE_SIZE < 8192) 5385 if (!adapter->vfs_allocated_count) { 5386 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5387 rlpml = IGB_MAX_FRAME_BUILD_SKB; 5388 } 5389 #endif 5390 wr32(E1000_RLPML, rlpml); 5391 5392 /* In order to support SR-IOV and eventually VMDq it is necessary to set 5393 * the VMOLR to enable the appropriate modes. Without this workaround 5394 * we will have issues with VLAN tag stripping not being done for frames 5395 * that are only arriving because we are the default pool 5396 */ 5397 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 5398 return; 5399 5400 /* set UTA to appropriate mode */ 5401 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE)); 5402 5403 vmolr |= rd32(E1000_VMOLR(vfn)) & 5404 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 5405 5406 /* enable Rx jumbo frames, restrict as needed to support build_skb */ 5407 vmolr &= ~E1000_VMOLR_RLPML_MASK; 5408 #if (PAGE_SIZE < 8192) 5409 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) 5410 vmolr |= IGB_MAX_FRAME_BUILD_SKB; 5411 else 5412 #endif 5413 vmolr |= MAX_JUMBO_FRAME_SIZE; 5414 vmolr |= E1000_VMOLR_LPE; 5415 5416 wr32(E1000_VMOLR(vfn), vmolr); 5417 5418 igb_restore_vf_multicasts(adapter); 5419 } 5420 5421 static void igb_check_wvbr(struct igb_adapter *adapter) 5422 { 5423 struct e1000_hw *hw = &adapter->hw; 5424 u32 wvbr = 0; 5425 5426 switch (hw->mac.type) { 5427 case e1000_82576: 5428 case e1000_i350: 5429 wvbr = rd32(E1000_WVBR); 5430 if (!wvbr) 5431 return; 5432 break; 5433 default: 5434 break; 5435 } 5436 5437 adapter->wvbr |= wvbr; 5438 } 5439 5440 #define IGB_STAGGERED_QUEUE_OFFSET 8 5441 5442 static void igb_spoof_check(struct igb_adapter *adapter) 5443 { 5444 int j; 5445 5446 if (!adapter->wvbr) 5447 return; 5448 5449 for (j = 0; j < adapter->vfs_allocated_count; j++) { 5450 if (adapter->wvbr & BIT(j) || 5451 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) { 5452 dev_warn(&adapter->pdev->dev, 5453 "Spoof event(s) detected on VF %d\n", j); 5454 adapter->wvbr &= 5455 ~(BIT(j) | 5456 BIT(j + IGB_STAGGERED_QUEUE_OFFSET)); 5457 } 5458 } 5459 } 5460 5461 /* Need to wait a few seconds after link up to get diagnostic information from 5462 * the phy 5463 */ 5464 static void igb_update_phy_info(struct timer_list *t) 5465 { 5466 struct igb_adapter *adapter = timer_container_of(adapter, t, 5467 phy_info_timer); 5468 igb_get_phy_info(&adapter->hw); 5469 } 5470 5471 /** 5472 * igb_has_link - check shared code for link and determine up/down 5473 * @adapter: pointer to driver private info 5474 **/ 5475 bool igb_has_link(struct igb_adapter *adapter) 5476 { 5477 struct e1000_hw *hw = &adapter->hw; 5478 bool link_active = false; 5479 5480 /* get_link_status is set on LSC (link status) interrupt or 5481 * rx sequence error interrupt. get_link_status will stay 5482 * false until the e1000_check_for_link establishes link 5483 * for copper adapters ONLY 5484 */ 5485 switch (hw->phy.media_type) { 5486 case e1000_media_type_copper: 5487 if (!hw->mac.get_link_status) 5488 return true; 5489 fallthrough; 5490 case e1000_media_type_internal_serdes: 5491 hw->mac.ops.check_for_link(hw); 5492 link_active = !hw->mac.get_link_status; 5493 break; 5494 default: 5495 case e1000_media_type_unknown: 5496 break; 5497 } 5498 5499 if (((hw->mac.type == e1000_i210) || 5500 (hw->mac.type == e1000_i211)) && 5501 (hw->phy.id == I210_I_PHY_ID)) { 5502 if (!netif_carrier_ok(adapter->netdev)) { 5503 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5504 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 5505 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 5506 adapter->link_check_timeout = jiffies; 5507 } 5508 } 5509 5510 return link_active; 5511 } 5512 5513 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 5514 { 5515 bool ret = false; 5516 u32 ctrl_ext, thstat; 5517 5518 /* check for thermal sensor event on i350 copper only */ 5519 if (hw->mac.type == e1000_i350) { 5520 thstat = rd32(E1000_THSTAT); 5521 ctrl_ext = rd32(E1000_CTRL_EXT); 5522 5523 if ((hw->phy.media_type == e1000_media_type_copper) && 5524 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 5525 ret = !!(thstat & event); 5526 } 5527 5528 return ret; 5529 } 5530 5531 /** 5532 * igb_check_lvmmc - check for malformed packets received 5533 * and indicated in LVMMC register 5534 * @adapter: pointer to adapter 5535 **/ 5536 static void igb_check_lvmmc(struct igb_adapter *adapter) 5537 { 5538 struct e1000_hw *hw = &adapter->hw; 5539 u32 lvmmc; 5540 5541 lvmmc = rd32(E1000_LVMMC); 5542 if (lvmmc) { 5543 if (unlikely(net_ratelimit())) { 5544 netdev_warn(adapter->netdev, 5545 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", 5546 lvmmc); 5547 } 5548 } 5549 } 5550 5551 /** 5552 * igb_watchdog - Timer Call-back 5553 * @t: pointer to timer_list containing our private info pointer 5554 **/ 5555 static void igb_watchdog(struct timer_list *t) 5556 { 5557 struct igb_adapter *adapter = timer_container_of(adapter, t, 5558 watchdog_timer); 5559 /* Do the rest outside of interrupt context */ 5560 schedule_work(&adapter->watchdog_task); 5561 } 5562 5563 static void igb_watchdog_task(struct work_struct *work) 5564 { 5565 struct igb_adapter *adapter = container_of(work, 5566 struct igb_adapter, 5567 watchdog_task); 5568 struct e1000_hw *hw = &adapter->hw; 5569 struct e1000_phy_info *phy = &hw->phy; 5570 struct net_device *netdev = adapter->netdev; 5571 u32 link; 5572 int i; 5573 u32 connsw; 5574 u16 phy_data, retry_count = 20; 5575 5576 link = igb_has_link(adapter); 5577 5578 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 5579 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5580 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 5581 else 5582 link = false; 5583 } 5584 5585 /* Force link down if we have fiber to swap to */ 5586 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5587 if (hw->phy.media_type == e1000_media_type_copper) { 5588 connsw = rd32(E1000_CONNSW); 5589 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 5590 link = 0; 5591 } 5592 } 5593 if (link) { 5594 /* Perform a reset if the media type changed. */ 5595 if (hw->dev_spec._82575.media_changed) { 5596 hw->dev_spec._82575.media_changed = false; 5597 adapter->flags |= IGB_FLAG_MEDIA_RESET; 5598 igb_reset(adapter); 5599 } 5600 /* Cancel scheduled suspend requests. */ 5601 pm_runtime_resume(netdev->dev.parent); 5602 5603 if (!netif_carrier_ok(netdev)) { 5604 u32 ctrl; 5605 5606 hw->mac.ops.get_speed_and_duplex(hw, 5607 &adapter->link_speed, 5608 &adapter->link_duplex); 5609 5610 ctrl = rd32(E1000_CTRL); 5611 /* Links status message must follow this format */ 5612 netdev_info(netdev, 5613 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5614 netdev->name, 5615 adapter->link_speed, 5616 adapter->link_duplex == FULL_DUPLEX ? 5617 "Full" : "Half", 5618 (ctrl & E1000_CTRL_TFCE) && 5619 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 5620 (ctrl & E1000_CTRL_RFCE) ? "RX" : 5621 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 5622 5623 /* disable EEE if enabled */ 5624 if ((adapter->flags & IGB_FLAG_EEE) && 5625 (adapter->link_duplex == HALF_DUPLEX)) { 5626 dev_info(&adapter->pdev->dev, 5627 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 5628 adapter->hw.dev_spec._82575.eee_disable = true; 5629 adapter->flags &= ~IGB_FLAG_EEE; 5630 } 5631 5632 /* check if SmartSpeed worked */ 5633 igb_check_downshift(hw); 5634 if (phy->speed_downgraded) 5635 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5636 5637 /* check for thermal sensor event */ 5638 if (igb_thermal_sensor_event(hw, 5639 E1000_THSTAT_LINK_THROTTLE)) 5640 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 5641 5642 /* adjust timeout factor according to speed/duplex */ 5643 adapter->tx_timeout_factor = 1; 5644 switch (adapter->link_speed) { 5645 case SPEED_10: 5646 adapter->tx_timeout_factor = 14; 5647 break; 5648 case SPEED_100: 5649 /* maybe add some timeout factor ? */ 5650 break; 5651 } 5652 5653 if (adapter->link_speed != SPEED_1000 || 5654 !hw->phy.ops.read_reg) 5655 goto no_wait; 5656 5657 /* wait for Remote receiver status OK */ 5658 retry_read_status: 5659 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS, 5660 &phy_data)) { 5661 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5662 retry_count) { 5663 msleep(100); 5664 retry_count--; 5665 goto retry_read_status; 5666 } else if (!retry_count) { 5667 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 5668 } 5669 } else { 5670 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 5671 } 5672 no_wait: 5673 netif_carrier_on(netdev); 5674 5675 igb_ping_all_vfs(adapter); 5676 igb_check_vf_rate_limit(adapter); 5677 5678 /* link state has changed, schedule phy info update */ 5679 if (!test_bit(__IGB_DOWN, &adapter->state)) 5680 mod_timer(&adapter->phy_info_timer, 5681 round_jiffies(jiffies + 2 * HZ)); 5682 } 5683 } else { 5684 if (netif_carrier_ok(netdev)) { 5685 adapter->link_speed = 0; 5686 adapter->link_duplex = 0; 5687 5688 /* check for thermal sensor event */ 5689 if (igb_thermal_sensor_event(hw, 5690 E1000_THSTAT_PWR_DOWN)) { 5691 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 5692 } 5693 5694 /* Links status message must follow this format */ 5695 netdev_info(netdev, "igb: %s NIC Link is Down\n", 5696 netdev->name); 5697 netif_carrier_off(netdev); 5698 5699 igb_ping_all_vfs(adapter); 5700 5701 /* link state has changed, schedule phy info update */ 5702 if (!test_bit(__IGB_DOWN, &adapter->state)) 5703 mod_timer(&adapter->phy_info_timer, 5704 round_jiffies(jiffies + 2 * HZ)); 5705 5706 /* link is down, time to check for alternate media */ 5707 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 5708 igb_check_swap_media(adapter); 5709 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5710 schedule_work(&adapter->reset_task); 5711 /* return immediately */ 5712 return; 5713 } 5714 } 5715 pm_schedule_suspend(netdev->dev.parent, 5716 MSEC_PER_SEC * 5); 5717 5718 /* also check for alternate media here */ 5719 } else if (!netif_carrier_ok(netdev) && 5720 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 5721 igb_check_swap_media(adapter); 5722 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 5723 schedule_work(&adapter->reset_task); 5724 /* return immediately */ 5725 return; 5726 } 5727 } 5728 } 5729 5730 spin_lock(&adapter->stats64_lock); 5731 igb_update_stats(adapter); 5732 spin_unlock(&adapter->stats64_lock); 5733 5734 for (i = 0; i < adapter->num_tx_queues; i++) { 5735 struct igb_ring *tx_ring = adapter->tx_ring[i]; 5736 if (!netif_carrier_ok(netdev)) { 5737 /* We've lost link, so the controller stops DMA, 5738 * but we've got queued Tx work that's never going 5739 * to get done, so reset controller to flush Tx. 5740 * (Do the reset outside of interrupt context). 5741 */ 5742 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 5743 adapter->tx_timeout_count++; 5744 schedule_work(&adapter->reset_task); 5745 /* return immediately since reset is imminent */ 5746 return; 5747 } 5748 } 5749 5750 /* Force detection of hung controller every watchdog period */ 5751 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5752 } 5753 5754 /* Cause software interrupt to ensure Rx ring is cleaned */ 5755 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 5756 u32 eics = 0; 5757 5758 for (i = 0; i < adapter->num_q_vectors; i++) { 5759 struct igb_q_vector *q_vector = adapter->q_vector[i]; 5760 struct igb_ring *rx_ring; 5761 5762 if (!q_vector->rx.ring) 5763 continue; 5764 5765 rx_ring = adapter->rx_ring[q_vector->rx.ring->queue_index]; 5766 5767 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5768 eics |= q_vector->eims_value; 5769 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5770 } 5771 } 5772 if (eics) 5773 wr32(E1000_EICS, eics); 5774 } else { 5775 struct igb_ring *rx_ring = adapter->rx_ring[0]; 5776 5777 if (test_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags)) { 5778 clear_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 5779 wr32(E1000_ICS, E1000_ICS_RXDMT0); 5780 } 5781 } 5782 5783 igb_spoof_check(adapter); 5784 igb_ptp_rx_hang(adapter); 5785 igb_ptp_tx_hang(adapter); 5786 5787 /* Check LVMMC register on i350/i354 only */ 5788 if ((adapter->hw.mac.type == e1000_i350) || 5789 (adapter->hw.mac.type == e1000_i354)) 5790 igb_check_lvmmc(adapter); 5791 5792 /* Reset the timer */ 5793 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5794 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 5795 mod_timer(&adapter->watchdog_timer, 5796 round_jiffies(jiffies + HZ)); 5797 else 5798 mod_timer(&adapter->watchdog_timer, 5799 round_jiffies(jiffies + 2 * HZ)); 5800 } 5801 } 5802 5803 enum latency_range { 5804 lowest_latency = 0, 5805 low_latency = 1, 5806 bulk_latency = 2, 5807 latency_invalid = 255 5808 }; 5809 5810 /** 5811 * igb_update_ring_itr - update the dynamic ITR value based on packet size 5812 * @q_vector: pointer to q_vector 5813 * 5814 * Stores a new ITR value based on strictly on packet size. This 5815 * algorithm is less sophisticated than that used in igb_update_itr, 5816 * due to the difficulty of synchronizing statistics across multiple 5817 * receive rings. The divisors and thresholds used by this function 5818 * were determined based on theoretical maximum wire speed and testing 5819 * data, in order to minimize response time while increasing bulk 5820 * throughput. 5821 * This functionality is controlled by ethtool's coalescing settings. 5822 * NOTE: This function is called only when operating in a multiqueue 5823 * receive environment. 5824 **/ 5825 static void igb_update_ring_itr(struct igb_q_vector *q_vector) 5826 { 5827 int new_val = q_vector->itr_val; 5828 int avg_wire_size = 0; 5829 struct igb_adapter *adapter = q_vector->adapter; 5830 unsigned int packets; 5831 5832 /* For non-gigabit speeds, just fix the interrupt rate at 4000 5833 * ints/sec - ITR timer value of 120 ticks. 5834 */ 5835 if (adapter->link_speed != SPEED_1000) { 5836 new_val = IGB_4K_ITR; 5837 goto set_itr_val; 5838 } 5839 5840 packets = q_vector->rx.total_packets; 5841 if (packets) 5842 avg_wire_size = q_vector->rx.total_bytes / packets; 5843 5844 packets = q_vector->tx.total_packets; 5845 if (packets) 5846 avg_wire_size = max_t(u32, avg_wire_size, 5847 q_vector->tx.total_bytes / packets); 5848 5849 /* if avg_wire_size isn't set no work was done */ 5850 if (!avg_wire_size) 5851 goto clear_counts; 5852 5853 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 5854 avg_wire_size += 24; 5855 5856 /* Don't starve jumbo frames */ 5857 avg_wire_size = min(avg_wire_size, 3000); 5858 5859 /* Give a little boost to mid-size frames */ 5860 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 5861 new_val = avg_wire_size / 3; 5862 else 5863 new_val = avg_wire_size / 2; 5864 5865 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5866 if (new_val < IGB_20K_ITR && 5867 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5868 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5869 new_val = IGB_20K_ITR; 5870 5871 set_itr_val: 5872 if (new_val != q_vector->itr_val) { 5873 q_vector->itr_val = new_val; 5874 q_vector->set_itr = 1; 5875 } 5876 clear_counts: 5877 q_vector->rx.total_bytes = 0; 5878 q_vector->rx.total_packets = 0; 5879 q_vector->tx.total_bytes = 0; 5880 q_vector->tx.total_packets = 0; 5881 } 5882 5883 /** 5884 * igb_update_itr - update the dynamic ITR value based on statistics 5885 * @q_vector: pointer to q_vector 5886 * @ring_container: ring info to update the itr for 5887 * 5888 * Stores a new ITR value based on packets and byte 5889 * counts during the last interrupt. The advantage of per interrupt 5890 * computation is faster updates and more accurate ITR for the current 5891 * traffic pattern. Constants in this function were computed 5892 * based on theoretical maximum wire speed and thresholds were set based 5893 * on testing data as well as attempting to minimize response time 5894 * while increasing bulk throughput. 5895 * This functionality is controlled by ethtool's coalescing settings. 5896 * NOTE: These calculations are only valid when operating in a single- 5897 * queue environment. 5898 **/ 5899 static void igb_update_itr(struct igb_q_vector *q_vector, 5900 struct igb_ring_container *ring_container) 5901 { 5902 unsigned int packets = ring_container->total_packets; 5903 unsigned int bytes = ring_container->total_bytes; 5904 u8 itrval = ring_container->itr; 5905 5906 /* no packets, exit with status unchanged */ 5907 if (packets == 0) 5908 return; 5909 5910 switch (itrval) { 5911 case lowest_latency: 5912 /* handle TSO and jumbo frames */ 5913 if (bytes/packets > 8000) 5914 itrval = bulk_latency; 5915 else if ((packets < 5) && (bytes > 512)) 5916 itrval = low_latency; 5917 break; 5918 case low_latency: /* 50 usec aka 20000 ints/s */ 5919 if (bytes > 10000) { 5920 /* this if handles the TSO accounting */ 5921 if (bytes/packets > 8000) 5922 itrval = bulk_latency; 5923 else if ((packets < 10) || ((bytes/packets) > 1200)) 5924 itrval = bulk_latency; 5925 else if ((packets > 35)) 5926 itrval = lowest_latency; 5927 } else if (bytes/packets > 2000) { 5928 itrval = bulk_latency; 5929 } else if (packets <= 2 && bytes < 512) { 5930 itrval = lowest_latency; 5931 } 5932 break; 5933 case bulk_latency: /* 250 usec aka 4000 ints/s */ 5934 if (bytes > 25000) { 5935 if (packets > 35) 5936 itrval = low_latency; 5937 } else if (bytes < 1500) { 5938 itrval = low_latency; 5939 } 5940 break; 5941 } 5942 5943 /* clear work counters since we have the values we need */ 5944 ring_container->total_bytes = 0; 5945 ring_container->total_packets = 0; 5946 5947 /* write updated itr to ring container */ 5948 ring_container->itr = itrval; 5949 } 5950 5951 static void igb_set_itr(struct igb_q_vector *q_vector) 5952 { 5953 struct igb_adapter *adapter = q_vector->adapter; 5954 u32 new_itr = q_vector->itr_val; 5955 u8 current_itr = 0; 5956 5957 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 5958 if (adapter->link_speed != SPEED_1000) { 5959 current_itr = 0; 5960 new_itr = IGB_4K_ITR; 5961 goto set_itr_now; 5962 } 5963 5964 igb_update_itr(q_vector, &q_vector->tx); 5965 igb_update_itr(q_vector, &q_vector->rx); 5966 5967 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 5968 5969 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 5970 if (current_itr == lowest_latency && 5971 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 5972 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 5973 current_itr = low_latency; 5974 5975 switch (current_itr) { 5976 /* counts and packets in update_itr are dependent on these numbers */ 5977 case lowest_latency: 5978 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 5979 break; 5980 case low_latency: 5981 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 5982 break; 5983 case bulk_latency: 5984 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 5985 break; 5986 default: 5987 break; 5988 } 5989 5990 set_itr_now: 5991 if (new_itr != q_vector->itr_val) { 5992 /* this attempts to bias the interrupt rate towards Bulk 5993 * by adding intermediate steps when interrupt rate is 5994 * increasing 5995 */ 5996 new_itr = new_itr > q_vector->itr_val ? 5997 max((new_itr * q_vector->itr_val) / 5998 (new_itr + (q_vector->itr_val >> 2)), 5999 new_itr) : new_itr; 6000 /* Don't write the value here; it resets the adapter's 6001 * internal timer, and causes us to delay far longer than 6002 * we should between interrupts. Instead, we write the ITR 6003 * value at the beginning of the next interrupt so the timing 6004 * ends up being correct. 6005 */ 6006 q_vector->itr_val = new_itr; 6007 q_vector->set_itr = 1; 6008 } 6009 } 6010 6011 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, 6012 struct igb_tx_buffer *first, 6013 u32 vlan_macip_lens, u32 type_tucmd, 6014 u32 mss_l4len_idx) 6015 { 6016 struct e1000_adv_tx_context_desc *context_desc; 6017 u16 i = tx_ring->next_to_use; 6018 struct timespec64 ts; 6019 6020 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 6021 6022 i++; 6023 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 6024 6025 /* set bits to identify this as an advanced context descriptor */ 6026 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 6027 6028 /* For 82575, context index must be unique per ring. */ 6029 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6030 mss_l4len_idx |= tx_ring->reg_idx << 4; 6031 6032 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 6033 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 6034 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 6035 6036 /* We assume there is always a valid tx time available. Invalid times 6037 * should have been handled by the upper layers. 6038 */ 6039 if (tx_ring->launchtime_enable) { 6040 ts = ktime_to_timespec64(first->skb->tstamp); 6041 skb_txtime_consumed(first->skb); 6042 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32); 6043 } else { 6044 context_desc->seqnum_seed = 0; 6045 } 6046 } 6047 6048 static int igb_tso(struct igb_ring *tx_ring, 6049 struct igb_tx_buffer *first, 6050 u8 *hdr_len) 6051 { 6052 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 6053 struct sk_buff *skb = first->skb; 6054 union { 6055 struct iphdr *v4; 6056 struct ipv6hdr *v6; 6057 unsigned char *hdr; 6058 } ip; 6059 union { 6060 struct tcphdr *tcp; 6061 struct udphdr *udp; 6062 unsigned char *hdr; 6063 } l4; 6064 u32 paylen, l4_offset; 6065 int err; 6066 6067 if (skb->ip_summed != CHECKSUM_PARTIAL) 6068 return 0; 6069 6070 if (!skb_is_gso(skb)) 6071 return 0; 6072 6073 err = skb_cow_head(skb, 0); 6074 if (err < 0) 6075 return err; 6076 6077 ip.hdr = skb_network_header(skb); 6078 l4.hdr = skb_checksum_start(skb); 6079 6080 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6081 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 6082 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP; 6083 6084 /* initialize outer IP header fields */ 6085 if (ip.v4->version == 4) { 6086 unsigned char *csum_start = skb_checksum_start(skb); 6087 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 6088 6089 /* IP header will have to cancel out any data that 6090 * is not a part of the outer IP header 6091 */ 6092 ip.v4->check = csum_fold(csum_partial(trans_start, 6093 csum_start - trans_start, 6094 0)); 6095 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 6096 6097 ip.v4->tot_len = 0; 6098 first->tx_flags |= IGB_TX_FLAGS_TSO | 6099 IGB_TX_FLAGS_CSUM | 6100 IGB_TX_FLAGS_IPV4; 6101 } else { 6102 ip.v6->payload_len = 0; 6103 first->tx_flags |= IGB_TX_FLAGS_TSO | 6104 IGB_TX_FLAGS_CSUM; 6105 } 6106 6107 /* determine offset of inner transport header */ 6108 l4_offset = l4.hdr - skb->data; 6109 6110 /* remove payload length from inner checksum */ 6111 paylen = skb->len - l4_offset; 6112 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) { 6113 /* compute length of segmentation header */ 6114 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 6115 csum_replace_by_diff(&l4.tcp->check, 6116 (__force __wsum)htonl(paylen)); 6117 } else { 6118 /* compute length of segmentation header */ 6119 *hdr_len = sizeof(*l4.udp) + l4_offset; 6120 csum_replace_by_diff(&l4.udp->check, 6121 (__force __wsum)htonl(paylen)); 6122 } 6123 6124 /* update gso size and bytecount with header size */ 6125 first->gso_segs = skb_shinfo(skb)->gso_segs; 6126 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6127 6128 /* MSS L4LEN IDX */ 6129 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT; 6130 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 6131 6132 /* VLAN MACLEN IPLEN */ 6133 vlan_macip_lens = l4.hdr - ip.hdr; 6134 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 6135 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6136 6137 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, 6138 type_tucmd, mss_l4len_idx); 6139 6140 return 1; 6141 } 6142 6143 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 6144 { 6145 struct sk_buff *skb = first->skb; 6146 u32 vlan_macip_lens = 0; 6147 u32 type_tucmd = 0; 6148 6149 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6150 csum_failed: 6151 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) && 6152 !tx_ring->launchtime_enable) 6153 return; 6154 goto no_csum; 6155 } 6156 6157 switch (skb->csum_offset) { 6158 case offsetof(struct tcphdr, check): 6159 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 6160 fallthrough; 6161 case offsetof(struct udphdr, check): 6162 break; 6163 case offsetof(struct sctphdr, checksum): 6164 /* validate that this is actually an SCTP request */ 6165 if (skb_csum_is_sctp(skb)) { 6166 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP; 6167 break; 6168 } 6169 fallthrough; 6170 default: 6171 skb_checksum_help(skb); 6172 goto csum_failed; 6173 } 6174 6175 /* update TX checksum flag */ 6176 first->tx_flags |= IGB_TX_FLAGS_CSUM; 6177 vlan_macip_lens = skb_checksum_start_offset(skb) - 6178 skb_network_offset(skb); 6179 no_csum: 6180 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 6181 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 6182 6183 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0); 6184 } 6185 6186 #define IGB_SET_FLAG(_input, _flag, _result) \ 6187 ((_flag <= _result) ? \ 6188 ((u32)(_input & _flag) * (_result / _flag)) : \ 6189 ((u32)(_input & _flag) / (_flag / _result))) 6190 6191 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6192 { 6193 /* set type for advanced descriptor with frame checksum insertion */ 6194 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 6195 E1000_ADVTXD_DCMD_DEXT | 6196 E1000_ADVTXD_DCMD_IFCS; 6197 6198 /* set HW vlan bit if vlan is present */ 6199 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 6200 (E1000_ADVTXD_DCMD_VLE)); 6201 6202 /* set segmentation bits for TSO */ 6203 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 6204 (E1000_ADVTXD_DCMD_TSE)); 6205 6206 /* set timestamp bit if present */ 6207 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 6208 (E1000_ADVTXD_MAC_TSTAMP)); 6209 6210 /* insert frame checksum */ 6211 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 6212 6213 return cmd_type; 6214 } 6215 6216 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 6217 union e1000_adv_tx_desc *tx_desc, 6218 u32 tx_flags, unsigned int paylen) 6219 { 6220 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 6221 6222 /* 82575 requires a unique index per ring */ 6223 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6224 olinfo_status |= tx_ring->reg_idx << 4; 6225 6226 /* insert L4 checksum */ 6227 olinfo_status |= IGB_SET_FLAG(tx_flags, 6228 IGB_TX_FLAGS_CSUM, 6229 (E1000_TXD_POPTS_TXSM << 8)); 6230 6231 /* insert IPv4 checksum */ 6232 olinfo_status |= IGB_SET_FLAG(tx_flags, 6233 IGB_TX_FLAGS_IPV4, 6234 (E1000_TXD_POPTS_IXSM << 8)); 6235 6236 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6237 } 6238 6239 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6240 { 6241 struct net_device *netdev = tx_ring->netdev; 6242 6243 netif_stop_subqueue(netdev, tx_ring->queue_index); 6244 6245 /* Herbert's original patch had: 6246 * smp_mb__after_netif_stop_queue(); 6247 * but since that doesn't exist yet, just open code it. 6248 */ 6249 smp_mb(); 6250 6251 /* We need to check again in a case another CPU has just 6252 * made room available. 6253 */ 6254 if (igb_desc_unused(tx_ring) < size) 6255 return -EBUSY; 6256 6257 /* A reprieve! */ 6258 netif_wake_subqueue(netdev, tx_ring->queue_index); 6259 6260 u64_stats_update_begin(&tx_ring->tx_syncp2); 6261 tx_ring->tx_stats.restart_queue2++; 6262 u64_stats_update_end(&tx_ring->tx_syncp2); 6263 6264 return 0; 6265 } 6266 6267 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 6268 { 6269 if (igb_desc_unused(tx_ring) >= size) 6270 return 0; 6271 return __igb_maybe_stop_tx(tx_ring, size); 6272 } 6273 6274 static int igb_tx_map(struct igb_ring *tx_ring, 6275 struct igb_tx_buffer *first, 6276 const u8 hdr_len) 6277 { 6278 struct sk_buff *skb = first->skb; 6279 struct igb_tx_buffer *tx_buffer; 6280 union e1000_adv_tx_desc *tx_desc; 6281 skb_frag_t *frag; 6282 dma_addr_t dma; 6283 unsigned int data_len, size; 6284 u32 tx_flags = first->tx_flags; 6285 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 6286 u16 i = tx_ring->next_to_use; 6287 6288 tx_desc = IGB_TX_DESC(tx_ring, i); 6289 6290 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 6291 6292 size = skb_headlen(skb); 6293 data_len = skb->data_len; 6294 6295 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6296 6297 tx_buffer = first; 6298 6299 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6300 if (dma_mapping_error(tx_ring->dev, dma)) 6301 goto dma_error; 6302 6303 /* record length, and DMA address */ 6304 dma_unmap_len_set(tx_buffer, len, size); 6305 dma_unmap_addr_set(tx_buffer, dma, dma); 6306 6307 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6308 6309 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 6310 tx_desc->read.cmd_type_len = 6311 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 6312 6313 i++; 6314 tx_desc++; 6315 if (i == tx_ring->count) { 6316 tx_desc = IGB_TX_DESC(tx_ring, 0); 6317 i = 0; 6318 } 6319 tx_desc->read.olinfo_status = 0; 6320 6321 dma += IGB_MAX_DATA_PER_TXD; 6322 size -= IGB_MAX_DATA_PER_TXD; 6323 6324 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6325 } 6326 6327 if (likely(!data_len)) 6328 break; 6329 6330 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 6331 6332 i++; 6333 tx_desc++; 6334 if (i == tx_ring->count) { 6335 tx_desc = IGB_TX_DESC(tx_ring, 0); 6336 i = 0; 6337 } 6338 tx_desc->read.olinfo_status = 0; 6339 6340 size = skb_frag_size(frag); 6341 data_len -= size; 6342 6343 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 6344 size, DMA_TO_DEVICE); 6345 6346 tx_buffer = &tx_ring->tx_buffer_info[i]; 6347 } 6348 6349 /* write last descriptor with RS and EOP bits */ 6350 cmd_type |= size | IGB_TXD_DCMD; 6351 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6352 6353 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 6354 6355 /* set the timestamp */ 6356 first->time_stamp = jiffies; 6357 6358 skb_tx_timestamp(skb); 6359 6360 /* Force memory writes to complete before letting h/w know there 6361 * are new descriptors to fetch. (Only applicable for weak-ordered 6362 * memory model archs, such as IA-64). 6363 * 6364 * We also need this memory barrier to make certain all of the 6365 * status bits have been updated before next_to_watch is written. 6366 */ 6367 dma_wmb(); 6368 6369 /* set next_to_watch value indicating a packet is present */ 6370 first->next_to_watch = tx_desc; 6371 6372 i++; 6373 if (i == tx_ring->count) 6374 i = 0; 6375 6376 tx_ring->next_to_use = i; 6377 6378 /* Make sure there is space in the ring for the next send. */ 6379 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6380 6381 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 6382 writel(i, tx_ring->tail); 6383 } 6384 return 0; 6385 6386 dma_error: 6387 dev_err(tx_ring->dev, "TX DMA map failed\n"); 6388 tx_buffer = &tx_ring->tx_buffer_info[i]; 6389 6390 /* clear dma mappings for failed tx_buffer_info map */ 6391 while (tx_buffer != first) { 6392 if (dma_unmap_len(tx_buffer, len)) 6393 dma_unmap_page(tx_ring->dev, 6394 dma_unmap_addr(tx_buffer, dma), 6395 dma_unmap_len(tx_buffer, len), 6396 DMA_TO_DEVICE); 6397 dma_unmap_len_set(tx_buffer, len, 0); 6398 6399 if (i-- == 0) 6400 i += tx_ring->count; 6401 tx_buffer = &tx_ring->tx_buffer_info[i]; 6402 } 6403 6404 if (dma_unmap_len(tx_buffer, len)) 6405 dma_unmap_single(tx_ring->dev, 6406 dma_unmap_addr(tx_buffer, dma), 6407 dma_unmap_len(tx_buffer, len), 6408 DMA_TO_DEVICE); 6409 dma_unmap_len_set(tx_buffer, len, 0); 6410 6411 dev_kfree_skb_any(tx_buffer->skb); 6412 tx_buffer->skb = NULL; 6413 6414 tx_ring->next_to_use = i; 6415 6416 return -1; 6417 } 6418 6419 int igb_xmit_xdp_ring(struct igb_adapter *adapter, 6420 struct igb_ring *tx_ring, 6421 struct xdp_frame *xdpf) 6422 { 6423 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 6424 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 6425 u16 count, i, index = tx_ring->next_to_use; 6426 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index]; 6427 struct igb_tx_buffer *tx_buffer = tx_head; 6428 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index); 6429 u32 len = xdpf->len, cmd_type, olinfo_status; 6430 void *data = xdpf->data; 6431 6432 count = TXD_USE_COUNT(len); 6433 for (i = 0; i < nr_frags; i++) 6434 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 6435 6436 if (igb_maybe_stop_tx(tx_ring, count + 3)) 6437 return IGB_XDP_CONSUMED; 6438 6439 i = 0; 6440 /* record the location of the first descriptor for this packet */ 6441 tx_head->bytecount = xdp_get_frame_len(xdpf); 6442 tx_head->type = IGB_TYPE_XDP; 6443 tx_head->gso_segs = 1; 6444 tx_head->xdpf = xdpf; 6445 6446 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT; 6447 /* 82575 requires a unique index per ring */ 6448 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 6449 olinfo_status |= tx_ring->reg_idx << 4; 6450 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6451 6452 for (;;) { 6453 dma_addr_t dma; 6454 6455 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE); 6456 if (dma_mapping_error(tx_ring->dev, dma)) 6457 goto unmap; 6458 6459 /* record length, and DMA address */ 6460 dma_unmap_len_set(tx_buffer, len, len); 6461 dma_unmap_addr_set(tx_buffer, dma, dma); 6462 6463 /* put descriptor type bits */ 6464 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT | 6465 E1000_ADVTXD_DCMD_IFCS | len; 6466 6467 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 6468 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6469 6470 tx_buffer->protocol = 0; 6471 6472 if (++index == tx_ring->count) 6473 index = 0; 6474 6475 if (i == nr_frags) 6476 break; 6477 6478 tx_buffer = &tx_ring->tx_buffer_info[index]; 6479 tx_desc = IGB_TX_DESC(tx_ring, index); 6480 tx_desc->read.olinfo_status = 0; 6481 6482 data = skb_frag_address(&sinfo->frags[i]); 6483 len = skb_frag_size(&sinfo->frags[i]); 6484 i++; 6485 } 6486 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD); 6487 6488 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount); 6489 /* set the timestamp */ 6490 tx_head->time_stamp = jiffies; 6491 6492 /* Avoid any potential race with xdp_xmit and cleanup */ 6493 smp_wmb(); 6494 6495 /* set next_to_watch value indicating a packet is present */ 6496 tx_head->next_to_watch = tx_desc; 6497 tx_ring->next_to_use = index; 6498 6499 /* Make sure there is space in the ring for the next send. */ 6500 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 6501 6502 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) 6503 writel(index, tx_ring->tail); 6504 6505 return IGB_XDP_TX; 6506 6507 unmap: 6508 for (;;) { 6509 tx_buffer = &tx_ring->tx_buffer_info[index]; 6510 if (dma_unmap_len(tx_buffer, len)) 6511 dma_unmap_page(tx_ring->dev, 6512 dma_unmap_addr(tx_buffer, dma), 6513 dma_unmap_len(tx_buffer, len), 6514 DMA_TO_DEVICE); 6515 dma_unmap_len_set(tx_buffer, len, 0); 6516 if (tx_buffer == tx_head) 6517 break; 6518 6519 if (!index) 6520 index += tx_ring->count; 6521 index--; 6522 } 6523 6524 return IGB_XDP_CONSUMED; 6525 } 6526 6527 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 6528 struct igb_ring *tx_ring) 6529 { 6530 struct igb_tx_buffer *first; 6531 int tso; 6532 u32 tx_flags = 0; 6533 unsigned short f; 6534 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 6535 __be16 protocol = vlan_get_protocol(skb); 6536 u8 hdr_len = 0; 6537 6538 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 6539 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 6540 * + 2 desc gap to keep tail from touching head, 6541 * + 1 desc for context descriptor, 6542 * otherwise try next time 6543 */ 6544 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 6545 count += TXD_USE_COUNT(skb_frag_size( 6546 &skb_shinfo(skb)->frags[f])); 6547 6548 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 6549 /* this is a hard error */ 6550 return NETDEV_TX_BUSY; 6551 } 6552 6553 if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) 6554 return NETDEV_TX_BUSY; 6555 6556 /* record the location of the first descriptor for this packet */ 6557 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 6558 first->type = IGB_TYPE_SKB; 6559 first->skb = skb; 6560 first->bytecount = skb->len; 6561 first->gso_segs = 1; 6562 6563 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 6564 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6565 6566 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 6567 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 6568 &adapter->state)) { 6569 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 6570 tx_flags |= IGB_TX_FLAGS_TSTAMP; 6571 6572 adapter->ptp_tx_skb = skb_get(skb); 6573 adapter->ptp_tx_start = jiffies; 6574 if (adapter->hw.mac.type == e1000_82576) 6575 schedule_work(&adapter->ptp_tx_work); 6576 } else { 6577 adapter->tx_hwtstamp_skipped++; 6578 } 6579 } 6580 6581 if (skb_vlan_tag_present(skb)) { 6582 tx_flags |= IGB_TX_FLAGS_VLAN; 6583 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 6584 } 6585 6586 /* record initial flags and protocol */ 6587 first->tx_flags = tx_flags; 6588 first->protocol = protocol; 6589 6590 tso = igb_tso(tx_ring, first, &hdr_len); 6591 if (tso < 0) 6592 goto out_drop; 6593 else if (!tso) 6594 igb_tx_csum(tx_ring, first); 6595 6596 if (igb_tx_map(tx_ring, first, hdr_len)) 6597 goto cleanup_tx_tstamp; 6598 6599 return NETDEV_TX_OK; 6600 6601 out_drop: 6602 dev_kfree_skb_any(first->skb); 6603 first->skb = NULL; 6604 cleanup_tx_tstamp: 6605 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) { 6606 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 6607 6608 dev_kfree_skb_any(adapter->ptp_tx_skb); 6609 adapter->ptp_tx_skb = NULL; 6610 if (adapter->hw.mac.type == e1000_82576) 6611 cancel_work_sync(&adapter->ptp_tx_work); 6612 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); 6613 } 6614 6615 return NETDEV_TX_OK; 6616 } 6617 6618 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 6619 struct sk_buff *skb) 6620 { 6621 unsigned int r_idx = skb->queue_mapping; 6622 6623 if (r_idx >= adapter->num_tx_queues) 6624 r_idx = r_idx % adapter->num_tx_queues; 6625 6626 return adapter->tx_ring[r_idx]; 6627 } 6628 6629 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 6630 struct net_device *netdev) 6631 { 6632 struct igb_adapter *adapter = netdev_priv(netdev); 6633 6634 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 6635 * in order to meet this minimum size requirement. 6636 */ 6637 if (skb_put_padto(skb, 17)) 6638 return NETDEV_TX_OK; 6639 6640 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 6641 } 6642 6643 /** 6644 * igb_tx_timeout - Respond to a Tx Hang 6645 * @netdev: network interface device structure 6646 * @txqueue: number of the Tx queue that hung (unused) 6647 **/ 6648 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6649 { 6650 struct igb_adapter *adapter = netdev_priv(netdev); 6651 struct e1000_hw *hw = &adapter->hw; 6652 6653 /* Do the reset outside of interrupt context */ 6654 adapter->tx_timeout_count++; 6655 6656 if (hw->mac.type >= e1000_82580) 6657 hw->dev_spec._82575.global_device_reset = true; 6658 6659 schedule_work(&adapter->reset_task); 6660 wr32(E1000_EICS, 6661 (adapter->eims_enable_mask & ~adapter->eims_other)); 6662 } 6663 6664 static void igb_reset_task(struct work_struct *work) 6665 { 6666 struct igb_adapter *adapter; 6667 adapter = container_of(work, struct igb_adapter, reset_task); 6668 6669 rtnl_lock(); 6670 /* If we're already down or resetting, just bail */ 6671 if (test_bit(__IGB_DOWN, &adapter->state) || 6672 test_bit(__IGB_RESETTING, &adapter->state)) { 6673 rtnl_unlock(); 6674 return; 6675 } 6676 6677 igb_dump(adapter); 6678 netdev_err(adapter->netdev, "Reset adapter\n"); 6679 igb_reinit_locked(adapter); 6680 rtnl_unlock(); 6681 } 6682 6683 /** 6684 * igb_get_stats64 - Get System Network Statistics 6685 * @netdev: network interface device structure 6686 * @stats: rtnl_link_stats64 pointer 6687 **/ 6688 static void igb_get_stats64(struct net_device *netdev, 6689 struct rtnl_link_stats64 *stats) 6690 { 6691 struct igb_adapter *adapter = netdev_priv(netdev); 6692 6693 spin_lock(&adapter->stats64_lock); 6694 igb_update_stats(adapter); 6695 memcpy(stats, &adapter->stats64, sizeof(*stats)); 6696 spin_unlock(&adapter->stats64_lock); 6697 } 6698 6699 /** 6700 * igb_change_mtu - Change the Maximum Transfer Unit 6701 * @netdev: network interface device structure 6702 * @new_mtu: new value for maximum frame size 6703 * 6704 * Returns 0 on success, negative on failure 6705 **/ 6706 static int igb_change_mtu(struct net_device *netdev, int new_mtu) 6707 { 6708 struct igb_adapter *adapter = netdev_priv(netdev); 6709 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD; 6710 6711 if (igb_xdp_is_enabled(adapter)) { 6712 int i; 6713 6714 for (i = 0; i < adapter->num_rx_queues; i++) { 6715 struct igb_ring *ring = adapter->rx_ring[i]; 6716 6717 if (max_frame > igb_rx_bufsz(ring)) { 6718 netdev_warn(adapter->netdev, 6719 "Requested MTU size is not supported with XDP. Max frame size is %d\n", 6720 max_frame); 6721 return -EINVAL; 6722 } 6723 } 6724 } 6725 6726 /* adjust max frame to be at least the size of a standard frame */ 6727 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 6728 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 6729 6730 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 6731 usleep_range(1000, 2000); 6732 6733 /* igb_down has a dependency on max_frame_size */ 6734 adapter->max_frame_size = max_frame; 6735 6736 if (netif_running(netdev)) 6737 igb_down(adapter); 6738 6739 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6740 netdev->mtu, new_mtu); 6741 WRITE_ONCE(netdev->mtu, new_mtu); 6742 6743 if (netif_running(netdev)) 6744 igb_up(adapter); 6745 else 6746 igb_reset(adapter); 6747 6748 clear_bit(__IGB_RESETTING, &adapter->state); 6749 6750 return 0; 6751 } 6752 6753 /** 6754 * igb_update_stats - Update the board statistics counters 6755 * @adapter: board private structure 6756 **/ 6757 void igb_update_stats(struct igb_adapter *adapter) 6758 { 6759 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 6760 struct e1000_hw *hw = &adapter->hw; 6761 struct pci_dev *pdev = adapter->pdev; 6762 u32 reg, mpc; 6763 int i; 6764 u64 bytes, packets; 6765 unsigned int start; 6766 u64 _bytes, _packets; 6767 6768 /* Prevent stats update while adapter is being reset, or if the pci 6769 * connection is down. 6770 */ 6771 if (adapter->link_speed == 0) 6772 return; 6773 if (pci_channel_offline(pdev)) 6774 return; 6775 6776 bytes = 0; 6777 packets = 0; 6778 6779 rcu_read_lock(); 6780 for (i = 0; i < adapter->num_rx_queues; i++) { 6781 struct igb_ring *ring = adapter->rx_ring[i]; 6782 u32 rqdpc = rd32(E1000_RQDPC(i)); 6783 if (hw->mac.type >= e1000_i210) 6784 wr32(E1000_RQDPC(i), 0); 6785 6786 if (rqdpc) { 6787 ring->rx_stats.drops += rqdpc; 6788 net_stats->rx_fifo_errors += rqdpc; 6789 } 6790 6791 do { 6792 start = u64_stats_fetch_begin(&ring->rx_syncp); 6793 _bytes = ring->rx_stats.bytes; 6794 _packets = ring->rx_stats.packets; 6795 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 6796 bytes += _bytes; 6797 packets += _packets; 6798 } 6799 6800 net_stats->rx_bytes = bytes; 6801 net_stats->rx_packets = packets; 6802 6803 bytes = 0; 6804 packets = 0; 6805 for (i = 0; i < adapter->num_tx_queues; i++) { 6806 struct igb_ring *ring = adapter->tx_ring[i]; 6807 do { 6808 start = u64_stats_fetch_begin(&ring->tx_syncp); 6809 _bytes = ring->tx_stats.bytes; 6810 _packets = ring->tx_stats.packets; 6811 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 6812 bytes += _bytes; 6813 packets += _packets; 6814 } 6815 net_stats->tx_bytes = bytes; 6816 net_stats->tx_packets = packets; 6817 rcu_read_unlock(); 6818 6819 /* read stats registers */ 6820 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 6821 adapter->stats.gprc += rd32(E1000_GPRC); 6822 adapter->stats.gorc += rd32(E1000_GORCL); 6823 rd32(E1000_GORCH); /* clear GORCL */ 6824 adapter->stats.bprc += rd32(E1000_BPRC); 6825 adapter->stats.mprc += rd32(E1000_MPRC); 6826 adapter->stats.roc += rd32(E1000_ROC); 6827 6828 adapter->stats.prc64 += rd32(E1000_PRC64); 6829 adapter->stats.prc127 += rd32(E1000_PRC127); 6830 adapter->stats.prc255 += rd32(E1000_PRC255); 6831 adapter->stats.prc511 += rd32(E1000_PRC511); 6832 adapter->stats.prc1023 += rd32(E1000_PRC1023); 6833 adapter->stats.prc1522 += rd32(E1000_PRC1522); 6834 adapter->stats.symerrs += rd32(E1000_SYMERRS); 6835 adapter->stats.sec += rd32(E1000_SEC); 6836 6837 mpc = rd32(E1000_MPC); 6838 adapter->stats.mpc += mpc; 6839 net_stats->rx_fifo_errors += mpc; 6840 adapter->stats.scc += rd32(E1000_SCC); 6841 adapter->stats.ecol += rd32(E1000_ECOL); 6842 adapter->stats.mcc += rd32(E1000_MCC); 6843 adapter->stats.latecol += rd32(E1000_LATECOL); 6844 adapter->stats.dc += rd32(E1000_DC); 6845 adapter->stats.rlec += rd32(E1000_RLEC); 6846 adapter->stats.xonrxc += rd32(E1000_XONRXC); 6847 adapter->stats.xontxc += rd32(E1000_XONTXC); 6848 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 6849 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 6850 adapter->stats.fcruc += rd32(E1000_FCRUC); 6851 adapter->stats.gptc += rd32(E1000_GPTC); 6852 adapter->stats.gotc += rd32(E1000_GOTCL); 6853 rd32(E1000_GOTCH); /* clear GOTCL */ 6854 adapter->stats.rnbc += rd32(E1000_RNBC); 6855 adapter->stats.ruc += rd32(E1000_RUC); 6856 adapter->stats.rfc += rd32(E1000_RFC); 6857 adapter->stats.rjc += rd32(E1000_RJC); 6858 adapter->stats.tor += rd32(E1000_TORH); 6859 adapter->stats.tot += rd32(E1000_TOTH); 6860 adapter->stats.tpr += rd32(E1000_TPR); 6861 6862 adapter->stats.ptc64 += rd32(E1000_PTC64); 6863 adapter->stats.ptc127 += rd32(E1000_PTC127); 6864 adapter->stats.ptc255 += rd32(E1000_PTC255); 6865 adapter->stats.ptc511 += rd32(E1000_PTC511); 6866 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 6867 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 6868 6869 adapter->stats.mptc += rd32(E1000_MPTC); 6870 adapter->stats.bptc += rd32(E1000_BPTC); 6871 6872 adapter->stats.tpt += rd32(E1000_TPT); 6873 adapter->stats.colc += rd32(E1000_COLC); 6874 6875 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 6876 /* read internal phy specific stats */ 6877 reg = rd32(E1000_CTRL_EXT); 6878 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 6879 adapter->stats.rxerrc += rd32(E1000_RXERRC); 6880 6881 /* this stat has invalid values on i210/i211 */ 6882 if ((hw->mac.type != e1000_i210) && 6883 (hw->mac.type != e1000_i211)) 6884 adapter->stats.tncrs += rd32(E1000_TNCRS); 6885 } 6886 6887 adapter->stats.tsctc += rd32(E1000_TSCTC); 6888 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 6889 6890 adapter->stats.iac += rd32(E1000_IAC); 6891 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 6892 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 6893 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 6894 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 6895 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 6896 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 6897 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 6898 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 6899 6900 /* Fill out the OS statistics structure */ 6901 net_stats->multicast = adapter->stats.mprc; 6902 net_stats->collisions = adapter->stats.colc; 6903 6904 /* Rx Errors */ 6905 6906 /* RLEC on some newer hardware can be incorrect so build 6907 * our own version based on RUC and ROC 6908 */ 6909 net_stats->rx_errors = adapter->stats.rxerrc + 6910 adapter->stats.crcerrs + adapter->stats.algnerrc + 6911 adapter->stats.ruc + adapter->stats.roc + 6912 adapter->stats.cexterr; 6913 net_stats->rx_length_errors = adapter->stats.ruc + 6914 adapter->stats.roc; 6915 net_stats->rx_crc_errors = adapter->stats.crcerrs; 6916 net_stats->rx_frame_errors = adapter->stats.algnerrc; 6917 net_stats->rx_missed_errors = adapter->stats.mpc; 6918 6919 /* Tx Errors */ 6920 net_stats->tx_errors = adapter->stats.ecol + 6921 adapter->stats.latecol; 6922 net_stats->tx_aborted_errors = adapter->stats.ecol; 6923 net_stats->tx_window_errors = adapter->stats.latecol; 6924 net_stats->tx_carrier_errors = adapter->stats.tncrs; 6925 6926 /* Tx Dropped needs to be maintained elsewhere */ 6927 6928 /* Management Stats */ 6929 adapter->stats.mgptc += rd32(E1000_MGTPTC); 6930 adapter->stats.mgprc += rd32(E1000_MGTPRC); 6931 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 6932 6933 /* OS2BMC Stats */ 6934 reg = rd32(E1000_MANC); 6935 if (reg & E1000_MANC_EN_BMC2OS) { 6936 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 6937 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 6938 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 6939 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 6940 } 6941 } 6942 6943 static void igb_perout(struct igb_adapter *adapter, int tsintr_tt) 6944 { 6945 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt); 6946 struct e1000_hw *hw = &adapter->hw; 6947 struct timespec64 ts; 6948 u32 tsauxc; 6949 6950 if (pin < 0 || pin >= IGB_N_SDP) 6951 return; 6952 6953 spin_lock(&adapter->tmreg_lock); 6954 6955 if (hw->mac.type == e1000_82580 || 6956 hw->mac.type == e1000_i354 || 6957 hw->mac.type == e1000_i350) { 6958 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period); 6959 u32 systiml, systimh, level_mask, level, rem; 6960 u64 systim, now; 6961 6962 /* read systim registers in sequence */ 6963 rd32(E1000_SYSTIMR); 6964 systiml = rd32(E1000_SYSTIML); 6965 systimh = rd32(E1000_SYSTIMH); 6966 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml); 6967 now = timecounter_cyc2time(&adapter->tc, systim); 6968 6969 if (pin < 2) { 6970 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000; 6971 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0; 6972 } else { 6973 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40; 6974 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0; 6975 } 6976 6977 div_u64_rem(now, ns, &rem); 6978 systim = systim + (ns - rem); 6979 6980 /* synchronize pin level with rising/falling edges */ 6981 div_u64_rem(now, ns << 1, &rem); 6982 if (rem < ns) { 6983 /* first half of period */ 6984 if (level == 0) { 6985 /* output is already low, skip this period */ 6986 systim += ns; 6987 pr_notice("igb: periodic output on %s missed falling edge\n", 6988 adapter->sdp_config[pin].name); 6989 } 6990 } else { 6991 /* second half of period */ 6992 if (level == 1) { 6993 /* output is already high, skip this period */ 6994 systim += ns; 6995 pr_notice("igb: periodic output on %s missed rising edge\n", 6996 adapter->sdp_config[pin].name); 6997 } 6998 } 6999 7000 /* for this chip family tv_sec is the upper part of the binary value, 7001 * so not seconds 7002 */ 7003 ts.tv_nsec = (u32)systim; 7004 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF; 7005 } else { 7006 ts = timespec64_add(adapter->perout[tsintr_tt].start, 7007 adapter->perout[tsintr_tt].period); 7008 } 7009 7010 /* u32 conversion of tv_sec is safe until y2106 */ 7011 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); 7012 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); 7013 tsauxc = rd32(E1000_TSAUXC); 7014 tsauxc |= TSAUXC_EN_TT0; 7015 wr32(E1000_TSAUXC, tsauxc); 7016 adapter->perout[tsintr_tt].start = ts; 7017 7018 spin_unlock(&adapter->tmreg_lock); 7019 } 7020 7021 static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) 7022 { 7023 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt); 7024 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0; 7025 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0; 7026 struct e1000_hw *hw = &adapter->hw; 7027 struct ptp_clock_event event; 7028 struct timespec64 ts; 7029 unsigned long flags; 7030 7031 if (pin < 0 || pin >= IGB_N_SDP) 7032 return; 7033 7034 if (hw->mac.type == e1000_82580 || 7035 hw->mac.type == e1000_i354 || 7036 hw->mac.type == e1000_i350) { 7037 u64 ns = rd32(auxstmpl); 7038 7039 ns += ((u64)(rd32(auxstmph) & 0xFF)) << 32; 7040 spin_lock_irqsave(&adapter->tmreg_lock, flags); 7041 ns = timecounter_cyc2time(&adapter->tc, ns); 7042 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 7043 ts = ns_to_timespec64(ns); 7044 } else { 7045 ts.tv_nsec = rd32(auxstmpl); 7046 ts.tv_sec = rd32(auxstmph); 7047 } 7048 7049 event.type = PTP_CLOCK_EXTTS; 7050 event.index = tsintr_tt; 7051 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec; 7052 ptp_clock_event(adapter->ptp_clock, &event); 7053 } 7054 7055 static void igb_tsync_interrupt(struct igb_adapter *adapter) 7056 { 7057 const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | 7058 TSINTR_TT0 | TSINTR_TT1 | 7059 TSINTR_AUTT0 | TSINTR_AUTT1); 7060 struct e1000_hw *hw = &adapter->hw; 7061 u32 tsicr = rd32(E1000_TSICR); 7062 struct ptp_clock_event event; 7063 7064 if (hw->mac.type == e1000_82580) { 7065 /* 82580 has a hardware bug that requires an explicit 7066 * write to clear the TimeSync interrupt cause. 7067 */ 7068 wr32(E1000_TSICR, tsicr & mask); 7069 } 7070 7071 if (tsicr & TSINTR_SYS_WRAP) { 7072 event.type = PTP_CLOCK_PPS; 7073 if (adapter->ptp_caps.pps) 7074 ptp_clock_event(adapter->ptp_clock, &event); 7075 } 7076 7077 if (tsicr & E1000_TSICR_TXTS) { 7078 /* retrieve hardware timestamp */ 7079 schedule_work(&adapter->ptp_tx_work); 7080 } 7081 7082 if (tsicr & TSINTR_TT0) 7083 igb_perout(adapter, 0); 7084 7085 if (tsicr & TSINTR_TT1) 7086 igb_perout(adapter, 1); 7087 7088 if (tsicr & TSINTR_AUTT0) 7089 igb_extts(adapter, 0); 7090 7091 if (tsicr & TSINTR_AUTT1) 7092 igb_extts(adapter, 1); 7093 } 7094 7095 static irqreturn_t igb_msix_other(int irq, void *data) 7096 { 7097 struct igb_adapter *adapter = data; 7098 struct e1000_hw *hw = &adapter->hw; 7099 u32 icr = rd32(E1000_ICR); 7100 /* reading ICR causes bit 31 of EICR to be cleared */ 7101 7102 if (icr & E1000_ICR_DRSTA) 7103 schedule_work(&adapter->reset_task); 7104 7105 if (icr & E1000_ICR_DOUTSYNC) { 7106 /* HW is reporting DMA is out of sync */ 7107 adapter->stats.doosync++; 7108 /* The DMA Out of Sync is also indication of a spoof event 7109 * in IOV mode. Check the Wrong VM Behavior register to 7110 * see if it is really a spoof event. 7111 */ 7112 igb_check_wvbr(adapter); 7113 } 7114 7115 /* Check for a mailbox event */ 7116 if (icr & E1000_ICR_VMMB) 7117 igb_msg_task(adapter); 7118 7119 if (icr & E1000_ICR_LSC) { 7120 hw->mac.get_link_status = 1; 7121 /* guard against interrupt when we're going down */ 7122 if (!test_bit(__IGB_DOWN, &adapter->state)) 7123 mod_timer(&adapter->watchdog_timer, jiffies + 1); 7124 } 7125 7126 if (icr & E1000_ICR_TS) 7127 igb_tsync_interrupt(adapter); 7128 7129 wr32(E1000_EIMS, adapter->eims_other); 7130 7131 return IRQ_HANDLED; 7132 } 7133 7134 static void igb_write_itr(struct igb_q_vector *q_vector) 7135 { 7136 struct igb_adapter *adapter = q_vector->adapter; 7137 u32 itr_val = q_vector->itr_val & 0x7FFC; 7138 7139 if (!q_vector->set_itr) 7140 return; 7141 7142 if (!itr_val) 7143 itr_val = 0x4; 7144 7145 if (adapter->hw.mac.type == e1000_82575) 7146 itr_val |= itr_val << 16; 7147 else 7148 itr_val |= E1000_EITR_CNT_IGNR; 7149 7150 writel(itr_val, q_vector->itr_register); 7151 q_vector->set_itr = 0; 7152 } 7153 7154 static irqreturn_t igb_msix_ring(int irq, void *data) 7155 { 7156 struct igb_q_vector *q_vector = data; 7157 7158 /* Write the ITR value calculated from the previous interrupt. */ 7159 igb_write_itr(q_vector); 7160 7161 napi_schedule(&q_vector->napi); 7162 7163 return IRQ_HANDLED; 7164 } 7165 7166 #ifdef CONFIG_IGB_DCA 7167 static void igb_update_tx_dca(struct igb_adapter *adapter, 7168 struct igb_ring *tx_ring, 7169 int cpu) 7170 { 7171 struct e1000_hw *hw = &adapter->hw; 7172 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 7173 7174 if (hw->mac.type != e1000_82575) 7175 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 7176 7177 /* We can enable relaxed ordering for reads, but not writes when 7178 * DCA is enabled. This is due to a known issue in some chipsets 7179 * which will cause the DCA tag to be cleared. 7180 */ 7181 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 7182 E1000_DCA_TXCTRL_DATA_RRO_EN | 7183 E1000_DCA_TXCTRL_DESC_DCA_EN; 7184 7185 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 7186 } 7187 7188 static void igb_update_rx_dca(struct igb_adapter *adapter, 7189 struct igb_ring *rx_ring, 7190 int cpu) 7191 { 7192 struct e1000_hw *hw = &adapter->hw; 7193 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 7194 7195 if (hw->mac.type != e1000_82575) 7196 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 7197 7198 /* We can enable relaxed ordering for reads, but not writes when 7199 * DCA is enabled. This is due to a known issue in some chipsets 7200 * which will cause the DCA tag to be cleared. 7201 */ 7202 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 7203 E1000_DCA_RXCTRL_DESC_DCA_EN; 7204 7205 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 7206 } 7207 7208 static void igb_update_dca(struct igb_q_vector *q_vector) 7209 { 7210 struct igb_adapter *adapter = q_vector->adapter; 7211 int cpu = get_cpu(); 7212 7213 if (q_vector->cpu == cpu) 7214 goto out_no_update; 7215 7216 if (q_vector->tx.ring) 7217 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 7218 7219 if (q_vector->rx.ring) 7220 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 7221 7222 q_vector->cpu = cpu; 7223 out_no_update: 7224 put_cpu(); 7225 } 7226 7227 static void igb_setup_dca(struct igb_adapter *adapter) 7228 { 7229 struct e1000_hw *hw = &adapter->hw; 7230 int i; 7231 7232 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 7233 return; 7234 7235 /* Always use CB2 mode, difference is masked in the CB driver. */ 7236 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 7237 7238 for (i = 0; i < adapter->num_q_vectors; i++) { 7239 adapter->q_vector[i]->cpu = -1; 7240 igb_update_dca(adapter->q_vector[i]); 7241 } 7242 } 7243 7244 static int __igb_notify_dca(struct device *dev, void *data) 7245 { 7246 struct net_device *netdev = dev_get_drvdata(dev); 7247 struct igb_adapter *adapter = netdev_priv(netdev); 7248 struct pci_dev *pdev = adapter->pdev; 7249 struct e1000_hw *hw = &adapter->hw; 7250 unsigned long event = *(unsigned long *)data; 7251 7252 switch (event) { 7253 case DCA_PROVIDER_ADD: 7254 /* if already enabled, don't do it again */ 7255 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 7256 break; 7257 if (dca_add_requester(dev) == 0) { 7258 adapter->flags |= IGB_FLAG_DCA_ENABLED; 7259 dev_info(&pdev->dev, "DCA enabled\n"); 7260 igb_setup_dca(adapter); 7261 break; 7262 } 7263 fallthrough; /* since DCA is disabled. */ 7264 case DCA_PROVIDER_REMOVE: 7265 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 7266 /* without this a class_device is left 7267 * hanging around in the sysfs model 7268 */ 7269 dca_remove_requester(dev); 7270 dev_info(&pdev->dev, "DCA disabled\n"); 7271 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 7272 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 7273 } 7274 break; 7275 } 7276 7277 return 0; 7278 } 7279 7280 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 7281 void *p) 7282 { 7283 int ret_val; 7284 7285 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 7286 __igb_notify_dca); 7287 7288 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 7289 } 7290 #endif /* CONFIG_IGB_DCA */ 7291 7292 #ifdef CONFIG_PCI_IOV 7293 static int igb_vf_configure(struct igb_adapter *adapter, int vf) 7294 { 7295 unsigned char mac_addr[ETH_ALEN]; 7296 7297 eth_zero_addr(mac_addr); 7298 igb_set_vf_mac(adapter, vf, mac_addr); 7299 7300 /* By default spoof check is enabled for all VFs */ 7301 adapter->vf_data[vf].spoofchk_enabled = true; 7302 7303 /* By default VFs are not trusted */ 7304 adapter->vf_data[vf].trusted = false; 7305 7306 return 0; 7307 } 7308 7309 #endif 7310 static void igb_ping_all_vfs(struct igb_adapter *adapter) 7311 { 7312 struct e1000_hw *hw = &adapter->hw; 7313 u32 ping; 7314 int i; 7315 7316 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 7317 ping = E1000_PF_CONTROL_MSG; 7318 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 7319 ping |= E1000_VT_MSGTYPE_CTS; 7320 igb_write_mbx(hw, &ping, 1, i); 7321 } 7322 } 7323 7324 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7325 { 7326 struct e1000_hw *hw = &adapter->hw; 7327 u32 vmolr = rd32(E1000_VMOLR(vf)); 7328 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7329 7330 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 7331 IGB_VF_FLAG_MULTI_PROMISC); 7332 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7333 7334 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 7335 vmolr |= E1000_VMOLR_MPME; 7336 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 7337 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 7338 } else { 7339 /* if we have hashes and we are clearing a multicast promisc 7340 * flag we need to write the hashes to the MTA as this step 7341 * was previously skipped 7342 */ 7343 if (vf_data->num_vf_mc_hashes > 30) { 7344 vmolr |= E1000_VMOLR_MPME; 7345 } else if (vf_data->num_vf_mc_hashes) { 7346 int j; 7347 7348 vmolr |= E1000_VMOLR_ROMPE; 7349 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7350 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7351 } 7352 } 7353 7354 wr32(E1000_VMOLR(vf), vmolr); 7355 7356 /* there are flags left unprocessed, likely not supported */ 7357 if (*msgbuf & E1000_VT_MSGINFO_MASK) 7358 return -EINVAL; 7359 7360 return 0; 7361 } 7362 7363 static int igb_set_vf_multicasts(struct igb_adapter *adapter, 7364 u32 *msgbuf, u32 vf) 7365 { 7366 int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7367 u16 *hash_list = (u16 *)&msgbuf[1]; 7368 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7369 int i; 7370 7371 /* salt away the number of multicast addresses assigned 7372 * to this VF for later use to restore when the PF multi cast 7373 * list changes 7374 */ 7375 vf_data->num_vf_mc_hashes = n; 7376 7377 /* only up to 30 hash values supported */ 7378 if (n > 30) 7379 n = 30; 7380 7381 /* store the hashes for later use */ 7382 for (i = 0; i < n; i++) 7383 vf_data->vf_mc_hashes[i] = hash_list[i]; 7384 7385 /* Flush and reset the mta with the new values */ 7386 igb_set_rx_mode(adapter->netdev); 7387 7388 return 0; 7389 } 7390 7391 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 7392 { 7393 struct e1000_hw *hw = &adapter->hw; 7394 struct vf_data_storage *vf_data; 7395 int i, j; 7396 7397 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7398 u32 vmolr = rd32(E1000_VMOLR(i)); 7399 7400 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 7401 7402 vf_data = &adapter->vf_data[i]; 7403 7404 if ((vf_data->num_vf_mc_hashes > 30) || 7405 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 7406 vmolr |= E1000_VMOLR_MPME; 7407 } else if (vf_data->num_vf_mc_hashes) { 7408 vmolr |= E1000_VMOLR_ROMPE; 7409 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 7410 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 7411 } 7412 wr32(E1000_VMOLR(i), vmolr); 7413 } 7414 } 7415 7416 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 7417 { 7418 struct e1000_hw *hw = &adapter->hw; 7419 u32 pool_mask, vlvf_mask, i; 7420 7421 /* create mask for VF and other pools */ 7422 pool_mask = E1000_VLVF_POOLSEL_MASK; 7423 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf); 7424 7425 /* drop PF from pool bits */ 7426 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT + 7427 adapter->vfs_allocated_count); 7428 7429 /* Find the vlan filter for this id */ 7430 for (i = E1000_VLVF_ARRAY_SIZE; i--;) { 7431 u32 vlvf = rd32(E1000_VLVF(i)); 7432 u32 vfta_mask, vid, vfta; 7433 7434 /* remove the vf from the pool */ 7435 if (!(vlvf & vlvf_mask)) 7436 continue; 7437 7438 /* clear out bit from VLVF */ 7439 vlvf ^= vlvf_mask; 7440 7441 /* if other pools are present, just remove ourselves */ 7442 if (vlvf & pool_mask) 7443 goto update_vlvfb; 7444 7445 /* if PF is present, leave VFTA */ 7446 if (vlvf & E1000_VLVF_POOLSEL_MASK) 7447 goto update_vlvf; 7448 7449 vid = vlvf & E1000_VLVF_VLANID_MASK; 7450 vfta_mask = BIT(vid % 32); 7451 7452 /* clear bit from VFTA */ 7453 vfta = adapter->shadow_vfta[vid / 32]; 7454 if (vfta & vfta_mask) 7455 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask); 7456 update_vlvf: 7457 /* clear pool selection enable */ 7458 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7459 vlvf &= E1000_VLVF_POOLSEL_MASK; 7460 else 7461 vlvf = 0; 7462 update_vlvfb: 7463 /* clear pool bits */ 7464 wr32(E1000_VLVF(i), vlvf); 7465 } 7466 } 7467 7468 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan) 7469 { 7470 u32 vlvf; 7471 int idx; 7472 7473 /* short cut the special case */ 7474 if (vlan == 0) 7475 return 0; 7476 7477 /* Search for the VLAN id in the VLVF entries */ 7478 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) { 7479 vlvf = rd32(E1000_VLVF(idx)); 7480 if ((vlvf & VLAN_VID_MASK) == vlan) 7481 break; 7482 } 7483 7484 return idx; 7485 } 7486 7487 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid) 7488 { 7489 struct e1000_hw *hw = &adapter->hw; 7490 u32 bits, pf_id; 7491 int idx; 7492 7493 idx = igb_find_vlvf_entry(hw, vid); 7494 if (!idx) 7495 return; 7496 7497 /* See if any other pools are set for this VLAN filter 7498 * entry other than the PF. 7499 */ 7500 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT; 7501 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK; 7502 bits &= rd32(E1000_VLVF(idx)); 7503 7504 /* Disable the filter so this falls into the default pool. */ 7505 if (!bits) { 7506 if (adapter->flags & IGB_FLAG_VLAN_PROMISC) 7507 wr32(E1000_VLVF(idx), BIT(pf_id)); 7508 else 7509 wr32(E1000_VLVF(idx), 0); 7510 } 7511 } 7512 7513 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid, 7514 bool add, u32 vf) 7515 { 7516 int pf_id = adapter->vfs_allocated_count; 7517 struct e1000_hw *hw = &adapter->hw; 7518 int err; 7519 7520 /* If VLAN overlaps with one the PF is currently monitoring make 7521 * sure that we are able to allocate a VLVF entry. This may be 7522 * redundant but it guarantees PF will maintain visibility to 7523 * the VLAN. 7524 */ 7525 if (add && test_bit(vid, adapter->active_vlans)) { 7526 err = igb_vfta_set(hw, vid, pf_id, true, false); 7527 if (err) 7528 return err; 7529 } 7530 7531 err = igb_vfta_set(hw, vid, vf, add, false); 7532 7533 if (add && !err) 7534 return err; 7535 7536 /* If we failed to add the VF VLAN or we are removing the VF VLAN 7537 * we may need to drop the PF pool bit in order to allow us to free 7538 * up the VLVF resources. 7539 */ 7540 if (test_bit(vid, adapter->active_vlans) || 7541 (adapter->flags & IGB_FLAG_VLAN_PROMISC)) 7542 igb_update_pf_vlvf(adapter, vid); 7543 7544 return err; 7545 } 7546 7547 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 7548 { 7549 struct e1000_hw *hw = &adapter->hw; 7550 7551 if (vid) 7552 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 7553 else 7554 wr32(E1000_VMVIR(vf), 0); 7555 } 7556 7557 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf, 7558 u16 vlan, u8 qos) 7559 { 7560 int err; 7561 7562 err = igb_set_vf_vlan(adapter, vlan, true, vf); 7563 if (err) 7564 return err; 7565 7566 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 7567 igb_set_vmolr(adapter, vf, !vlan); 7568 7569 /* revoke access to previous VLAN */ 7570 if (vlan != adapter->vf_data[vf].pf_vlan) 7571 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7572 false, vf); 7573 7574 adapter->vf_data[vf].pf_vlan = vlan; 7575 adapter->vf_data[vf].pf_qos = qos; 7576 igb_set_vf_vlan_strip(adapter, vf, true); 7577 dev_info(&adapter->pdev->dev, 7578 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 7579 if (test_bit(__IGB_DOWN, &adapter->state)) { 7580 dev_warn(&adapter->pdev->dev, 7581 "The VF VLAN has been set, but the PF device is not up.\n"); 7582 dev_warn(&adapter->pdev->dev, 7583 "Bring the PF device up before attempting to use the VF device.\n"); 7584 } 7585 7586 return err; 7587 } 7588 7589 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf) 7590 { 7591 /* Restore tagless access via VLAN 0 */ 7592 igb_set_vf_vlan(adapter, 0, true, vf); 7593 7594 igb_set_vmvir(adapter, 0, vf); 7595 igb_set_vmolr(adapter, vf, true); 7596 7597 /* Remove any PF assigned VLAN */ 7598 if (adapter->vf_data[vf].pf_vlan) 7599 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, 7600 false, vf); 7601 7602 adapter->vf_data[vf].pf_vlan = 0; 7603 adapter->vf_data[vf].pf_qos = 0; 7604 igb_set_vf_vlan_strip(adapter, vf, false); 7605 7606 return 0; 7607 } 7608 7609 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf, 7610 u16 vlan, u8 qos, __be16 vlan_proto) 7611 { 7612 struct igb_adapter *adapter = netdev_priv(netdev); 7613 7614 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 7615 return -EINVAL; 7616 7617 if (vlan_proto != htons(ETH_P_8021Q)) 7618 return -EPROTONOSUPPORT; 7619 7620 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) : 7621 igb_disable_port_vlan(adapter, vf); 7622 } 7623 7624 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 7625 { 7626 int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]); 7627 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 7628 int ret; 7629 7630 if (adapter->vf_data[vf].pf_vlan) 7631 return -1; 7632 7633 /* VLAN 0 is a special case, don't allow it to be removed */ 7634 if (!vid && !add) 7635 return 0; 7636 7637 ret = igb_set_vf_vlan(adapter, vid, !!add, vf); 7638 if (!ret) 7639 igb_set_vf_vlan_strip(adapter, vf, !!vid); 7640 return ret; 7641 } 7642 7643 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 7644 { 7645 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7646 7647 /* clear flags - except flag that indicates PF has set the MAC */ 7648 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC; 7649 vf_data->last_nack = jiffies; 7650 7651 /* reset vlans for device */ 7652 igb_clear_vf_vfta(adapter, vf); 7653 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf); 7654 igb_set_vmvir(adapter, vf_data->pf_vlan | 7655 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf); 7656 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan); 7657 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan)); 7658 7659 /* reset multicast table array for vf */ 7660 adapter->vf_data[vf].num_vf_mc_hashes = 0; 7661 7662 /* Flush and reset the mta with the new values */ 7663 igb_set_rx_mode(adapter->netdev); 7664 } 7665 7666 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 7667 { 7668 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7669 7670 /* clear mac address as we were hotplug removed/added */ 7671 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 7672 eth_zero_addr(vf_mac); 7673 7674 /* process remaining reset events */ 7675 igb_vf_reset(adapter, vf); 7676 } 7677 7678 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 7679 { 7680 struct e1000_hw *hw = &adapter->hw; 7681 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 7682 u32 reg, msgbuf[3] = {}; 7683 u8 *addr = (u8 *)(&msgbuf[1]); 7684 7685 /* process all the same items cleared in a function level reset */ 7686 igb_vf_reset(adapter, vf); 7687 7688 /* set vf mac address */ 7689 igb_set_vf_mac(adapter, vf, vf_mac); 7690 7691 /* enable transmit and receive for vf */ 7692 reg = rd32(E1000_VFTE); 7693 wr32(E1000_VFTE, reg | BIT(vf)); 7694 reg = rd32(E1000_VFRE); 7695 wr32(E1000_VFRE, reg | BIT(vf)); 7696 7697 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 7698 7699 /* reply to reset with ack and vf mac address */ 7700 if (!is_zero_ether_addr(vf_mac)) { 7701 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 7702 memcpy(addr, vf_mac, ETH_ALEN); 7703 } else { 7704 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK; 7705 } 7706 igb_write_mbx(hw, msgbuf, 3, vf); 7707 } 7708 7709 static void igb_flush_mac_table(struct igb_adapter *adapter) 7710 { 7711 struct e1000_hw *hw = &adapter->hw; 7712 int i; 7713 7714 for (i = 0; i < hw->mac.rar_entry_count; i++) { 7715 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE; 7716 eth_zero_addr(adapter->mac_table[i].addr); 7717 adapter->mac_table[i].queue = 0; 7718 igb_rar_set_index(adapter, i); 7719 } 7720 } 7721 7722 static int igb_available_rars(struct igb_adapter *adapter, u8 queue) 7723 { 7724 struct e1000_hw *hw = &adapter->hw; 7725 /* do not count rar entries reserved for VFs MAC addresses */ 7726 int rar_entries = hw->mac.rar_entry_count - 7727 adapter->vfs_allocated_count; 7728 int i, count = 0; 7729 7730 for (i = 0; i < rar_entries; i++) { 7731 /* do not count default entries */ 7732 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) 7733 continue; 7734 7735 /* do not count "in use" entries for different queues */ 7736 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) && 7737 (adapter->mac_table[i].queue != queue)) 7738 continue; 7739 7740 count++; 7741 } 7742 7743 return count; 7744 } 7745 7746 /* Set default MAC address for the PF in the first RAR entry */ 7747 static void igb_set_default_mac_filter(struct igb_adapter *adapter) 7748 { 7749 struct igb_mac_addr *mac_table = &adapter->mac_table[0]; 7750 7751 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 7752 mac_table->queue = adapter->vfs_allocated_count; 7753 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7754 7755 igb_rar_set_index(adapter, 0); 7756 } 7757 7758 /* If the filter to be added and an already existing filter express 7759 * the same address and address type, it should be possible to only 7760 * override the other configurations, for example the queue to steer 7761 * traffic. 7762 */ 7763 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry, 7764 const u8 *addr, const u8 flags) 7765 { 7766 if (!(entry->state & IGB_MAC_STATE_IN_USE)) 7767 return true; 7768 7769 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) != 7770 (flags & IGB_MAC_STATE_SRC_ADDR)) 7771 return false; 7772 7773 if (!ether_addr_equal(addr, entry->addr)) 7774 return false; 7775 7776 return true; 7777 } 7778 7779 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 7780 * 'flags' is used to indicate what kind of match is made, match is by 7781 * default for the destination address, if matching by source address 7782 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used. 7783 */ 7784 static int igb_add_mac_filter_flags(struct igb_adapter *adapter, 7785 const u8 *addr, const u8 queue, 7786 const u8 flags) 7787 { 7788 struct e1000_hw *hw = &adapter->hw; 7789 int rar_entries = hw->mac.rar_entry_count - 7790 adapter->vfs_allocated_count; 7791 int i; 7792 7793 if (is_zero_ether_addr(addr)) 7794 return -EINVAL; 7795 7796 /* Search for the first empty entry in the MAC table. 7797 * Do not touch entries at the end of the table reserved for the VF MAC 7798 * addresses. 7799 */ 7800 for (i = 0; i < rar_entries; i++) { 7801 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i], 7802 addr, flags)) 7803 continue; 7804 7805 ether_addr_copy(adapter->mac_table[i].addr, addr); 7806 adapter->mac_table[i].queue = queue; 7807 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags; 7808 7809 igb_rar_set_index(adapter, i); 7810 return i; 7811 } 7812 7813 return -ENOSPC; 7814 } 7815 7816 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7817 const u8 queue) 7818 { 7819 return igb_add_mac_filter_flags(adapter, addr, queue, 0); 7820 } 7821 7822 /* Remove a MAC filter for 'addr' directing matching traffic to 7823 * 'queue', 'flags' is used to indicate what kind of match need to be 7824 * removed, match is by default for the destination address, if 7825 * matching by source address is to be removed the flag 7826 * IGB_MAC_STATE_SRC_ADDR can be used. 7827 */ 7828 static int igb_del_mac_filter_flags(struct igb_adapter *adapter, 7829 const u8 *addr, const u8 queue, 7830 const u8 flags) 7831 { 7832 struct e1000_hw *hw = &adapter->hw; 7833 int rar_entries = hw->mac.rar_entry_count - 7834 adapter->vfs_allocated_count; 7835 int i; 7836 7837 if (is_zero_ether_addr(addr)) 7838 return -EINVAL; 7839 7840 /* Search for matching entry in the MAC table based on given address 7841 * and queue. Do not touch entries at the end of the table reserved 7842 * for the VF MAC addresses. 7843 */ 7844 for (i = 0; i < rar_entries; i++) { 7845 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) 7846 continue; 7847 if ((adapter->mac_table[i].state & flags) != flags) 7848 continue; 7849 if (adapter->mac_table[i].queue != queue) 7850 continue; 7851 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 7852 continue; 7853 7854 /* When a filter for the default address is "deleted", 7855 * we return it to its initial configuration 7856 */ 7857 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) { 7858 adapter->mac_table[i].state = 7859 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE; 7860 adapter->mac_table[i].queue = 7861 adapter->vfs_allocated_count; 7862 } else { 7863 adapter->mac_table[i].state = 0; 7864 adapter->mac_table[i].queue = 0; 7865 eth_zero_addr(adapter->mac_table[i].addr); 7866 } 7867 7868 igb_rar_set_index(adapter, i); 7869 return 0; 7870 } 7871 7872 return -ENOENT; 7873 } 7874 7875 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr, 7876 const u8 queue) 7877 { 7878 return igb_del_mac_filter_flags(adapter, addr, queue, 0); 7879 } 7880 7881 int igb_add_mac_steering_filter(struct igb_adapter *adapter, 7882 const u8 *addr, u8 queue, u8 flags) 7883 { 7884 struct e1000_hw *hw = &adapter->hw; 7885 7886 /* In theory, this should be supported on 82575 as well, but 7887 * that part wasn't easily accessible during development. 7888 */ 7889 if (hw->mac.type != e1000_i210) 7890 return -EOPNOTSUPP; 7891 7892 return igb_add_mac_filter_flags(adapter, addr, queue, 7893 IGB_MAC_STATE_QUEUE_STEERING | flags); 7894 } 7895 7896 int igb_del_mac_steering_filter(struct igb_adapter *adapter, 7897 const u8 *addr, u8 queue, u8 flags) 7898 { 7899 return igb_del_mac_filter_flags(adapter, addr, queue, 7900 IGB_MAC_STATE_QUEUE_STEERING | flags); 7901 } 7902 7903 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr) 7904 { 7905 struct igb_adapter *adapter = netdev_priv(netdev); 7906 int ret; 7907 7908 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7909 7910 return min_t(int, ret, 0); 7911 } 7912 7913 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr) 7914 { 7915 struct igb_adapter *adapter = netdev_priv(netdev); 7916 7917 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count); 7918 7919 return 0; 7920 } 7921 7922 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf, 7923 const u32 info, const u8 *addr) 7924 { 7925 struct pci_dev *pdev = adapter->pdev; 7926 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7927 struct vf_mac_filter *entry; 7928 bool found = false; 7929 int ret = 0; 7930 7931 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 7932 !vf_data->trusted) { 7933 dev_warn(&pdev->dev, 7934 "VF %d requested MAC filter but is administratively denied\n", 7935 vf); 7936 return -EINVAL; 7937 } 7938 if (!is_valid_ether_addr(addr)) { 7939 dev_warn(&pdev->dev, 7940 "VF %d attempted to set invalid MAC filter\n", 7941 vf); 7942 return -EINVAL; 7943 } 7944 7945 switch (info) { 7946 case E1000_VF_MAC_FILTER_CLR: 7947 /* remove all unicast MAC filters related to the current VF */ 7948 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7949 if (entry->vf == vf) { 7950 entry->vf = -1; 7951 entry->free = true; 7952 igb_del_mac_filter(adapter, entry->vf_mac, vf); 7953 } 7954 } 7955 break; 7956 case E1000_VF_MAC_FILTER_ADD: 7957 /* try to find empty slot in the list */ 7958 list_for_each_entry(entry, &adapter->vf_macs.l, l) { 7959 if (entry->free) { 7960 found = true; 7961 break; 7962 } 7963 } 7964 7965 if (found) { 7966 entry->free = false; 7967 entry->vf = vf; 7968 ether_addr_copy(entry->vf_mac, addr); 7969 7970 ret = igb_add_mac_filter(adapter, addr, vf); 7971 ret = min_t(int, ret, 0); 7972 } else { 7973 ret = -ENOSPC; 7974 } 7975 7976 if (ret == -ENOSPC) 7977 dev_warn(&pdev->dev, 7978 "VF %d has requested MAC filter but there is no space for it\n", 7979 vf); 7980 break; 7981 default: 7982 ret = -EINVAL; 7983 break; 7984 } 7985 7986 return ret; 7987 } 7988 7989 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 7990 { 7991 struct pci_dev *pdev = adapter->pdev; 7992 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 7993 u32 info = msg[0] & E1000_VT_MSGINFO_MASK; 7994 7995 /* The VF MAC Address is stored in a packed array of bytes 7996 * starting at the second 32 bit word of the msg array 7997 */ 7998 unsigned char *addr = (unsigned char *)&msg[1]; 7999 int ret = 0; 8000 8001 if (!info) { 8002 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) && 8003 !vf_data->trusted) { 8004 dev_warn(&pdev->dev, 8005 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 8006 vf); 8007 return -EINVAL; 8008 } 8009 8010 if (!is_valid_ether_addr(addr)) { 8011 dev_warn(&pdev->dev, 8012 "VF %d attempted to set invalid MAC\n", 8013 vf); 8014 return -EINVAL; 8015 } 8016 8017 ret = igb_set_vf_mac(adapter, vf, addr); 8018 } else { 8019 ret = igb_set_vf_mac_filter(adapter, vf, info, addr); 8020 } 8021 8022 return ret; 8023 } 8024 8025 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 8026 { 8027 struct e1000_hw *hw = &adapter->hw; 8028 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8029 u32 msg = E1000_VT_MSGTYPE_NACK; 8030 8031 /* if device isn't clear to send it shouldn't be reading either */ 8032 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 8033 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 8034 igb_write_mbx(hw, &msg, 1, vf); 8035 vf_data->last_nack = jiffies; 8036 } 8037 } 8038 8039 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 8040 { 8041 struct pci_dev *pdev = adapter->pdev; 8042 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 8043 struct e1000_hw *hw = &adapter->hw; 8044 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 8045 s32 retval; 8046 8047 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false); 8048 8049 if (retval) { 8050 /* if receive failed revoke VF CTS stats and restart init */ 8051 dev_err(&pdev->dev, "Error receiving message from VF\n"); 8052 vf_data->flags &= ~IGB_VF_FLAG_CTS; 8053 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8054 goto unlock; 8055 goto out; 8056 } 8057 8058 /* this is a message we already processed, do nothing */ 8059 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 8060 goto unlock; 8061 8062 /* until the vf completes a reset it should not be 8063 * allowed to start any configuration. 8064 */ 8065 if (msgbuf[0] == E1000_VF_RESET) { 8066 /* unlocks mailbox */ 8067 igb_vf_reset_msg(adapter, vf); 8068 return; 8069 } 8070 8071 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 8072 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 8073 goto unlock; 8074 retval = -1; 8075 goto out; 8076 } 8077 8078 switch ((msgbuf[0] & 0xFFFF)) { 8079 case E1000_VF_SET_MAC_ADDR: 8080 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 8081 break; 8082 case E1000_VF_SET_PROMISC: 8083 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 8084 break; 8085 case E1000_VF_SET_MULTICAST: 8086 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 8087 break; 8088 case E1000_VF_SET_LPE: 8089 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 8090 break; 8091 case E1000_VF_SET_VLAN: 8092 retval = -1; 8093 if (vf_data->pf_vlan) 8094 dev_warn(&pdev->dev, 8095 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 8096 vf); 8097 else 8098 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf); 8099 break; 8100 default: 8101 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 8102 retval = -1; 8103 break; 8104 } 8105 8106 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 8107 out: 8108 /* notify the VF of the results of what it sent us */ 8109 if (retval) 8110 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 8111 else 8112 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 8113 8114 /* unlocks mailbox */ 8115 igb_write_mbx(hw, msgbuf, 1, vf); 8116 return; 8117 8118 unlock: 8119 igb_unlock_mbx(hw, vf); 8120 } 8121 8122 static void igb_msg_task(struct igb_adapter *adapter) 8123 { 8124 struct e1000_hw *hw = &adapter->hw; 8125 unsigned long flags; 8126 u32 vf; 8127 8128 spin_lock_irqsave(&adapter->vfs_lock, flags); 8129 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 8130 /* process any reset requests */ 8131 if (!igb_check_for_rst(hw, vf)) 8132 igb_vf_reset_event(adapter, vf); 8133 8134 /* process any messages pending */ 8135 if (!igb_check_for_msg(hw, vf)) 8136 igb_rcv_msg_from_vf(adapter, vf); 8137 8138 /* process any acks */ 8139 if (!igb_check_for_ack(hw, vf)) 8140 igb_rcv_ack_from_vf(adapter, vf); 8141 } 8142 spin_unlock_irqrestore(&adapter->vfs_lock, flags); 8143 } 8144 8145 /** 8146 * igb_set_uta - Set unicast filter table address 8147 * @adapter: board private structure 8148 * @set: boolean indicating if we are setting or clearing bits 8149 * 8150 * The unicast table address is a register array of 32-bit registers. 8151 * The table is meant to be used in a way similar to how the MTA is used 8152 * however due to certain limitations in the hardware it is necessary to 8153 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 8154 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 8155 **/ 8156 static void igb_set_uta(struct igb_adapter *adapter, bool set) 8157 { 8158 struct e1000_hw *hw = &adapter->hw; 8159 u32 uta = set ? ~0 : 0; 8160 int i; 8161 8162 /* we only need to do this if VMDq is enabled */ 8163 if (!adapter->vfs_allocated_count) 8164 return; 8165 8166 for (i = hw->mac.uta_reg_count; i--;) 8167 array_wr32(E1000_UTA, i, uta); 8168 } 8169 8170 /** 8171 * igb_intr_msi - Interrupt Handler 8172 * @irq: interrupt number 8173 * @data: pointer to a network interface device structure 8174 **/ 8175 static irqreturn_t igb_intr_msi(int irq, void *data) 8176 { 8177 struct igb_adapter *adapter = data; 8178 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8179 struct e1000_hw *hw = &adapter->hw; 8180 /* read ICR disables interrupts using IAM */ 8181 u32 icr = rd32(E1000_ICR); 8182 8183 igb_write_itr(q_vector); 8184 8185 if (icr & E1000_ICR_DRSTA) 8186 schedule_work(&adapter->reset_task); 8187 8188 if (icr & E1000_ICR_DOUTSYNC) { 8189 /* HW is reporting DMA is out of sync */ 8190 adapter->stats.doosync++; 8191 } 8192 8193 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8194 hw->mac.get_link_status = 1; 8195 if (!test_bit(__IGB_DOWN, &adapter->state)) 8196 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8197 } 8198 8199 if (icr & E1000_ICR_TS) 8200 igb_tsync_interrupt(adapter); 8201 8202 napi_schedule(&q_vector->napi); 8203 8204 return IRQ_HANDLED; 8205 } 8206 8207 /** 8208 * igb_intr - Legacy Interrupt Handler 8209 * @irq: interrupt number 8210 * @data: pointer to a network interface device structure 8211 **/ 8212 static irqreturn_t igb_intr(int irq, void *data) 8213 { 8214 struct igb_adapter *adapter = data; 8215 struct igb_q_vector *q_vector = adapter->q_vector[0]; 8216 struct e1000_hw *hw = &adapter->hw; 8217 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 8218 * need for the IMC write 8219 */ 8220 u32 icr = rd32(E1000_ICR); 8221 8222 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 8223 * not set, then the adapter didn't send an interrupt 8224 */ 8225 if (!(icr & E1000_ICR_INT_ASSERTED)) 8226 return IRQ_NONE; 8227 8228 igb_write_itr(q_vector); 8229 8230 if (icr & E1000_ICR_DRSTA) 8231 schedule_work(&adapter->reset_task); 8232 8233 if (icr & E1000_ICR_DOUTSYNC) { 8234 /* HW is reporting DMA is out of sync */ 8235 adapter->stats.doosync++; 8236 } 8237 8238 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 8239 hw->mac.get_link_status = 1; 8240 /* guard against interrupt when we're going down */ 8241 if (!test_bit(__IGB_DOWN, &adapter->state)) 8242 mod_timer(&adapter->watchdog_timer, jiffies + 1); 8243 } 8244 8245 if (icr & E1000_ICR_TS) 8246 igb_tsync_interrupt(adapter); 8247 8248 napi_schedule(&q_vector->napi); 8249 8250 return IRQ_HANDLED; 8251 } 8252 8253 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 8254 { 8255 struct igb_adapter *adapter = q_vector->adapter; 8256 struct e1000_hw *hw = &adapter->hw; 8257 8258 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 8259 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 8260 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 8261 igb_set_itr(q_vector); 8262 else 8263 igb_update_ring_itr(q_vector); 8264 } 8265 8266 if (!test_bit(__IGB_DOWN, &adapter->state)) { 8267 if (adapter->flags & IGB_FLAG_HAS_MSIX) 8268 wr32(E1000_EIMS, q_vector->eims_value); 8269 else 8270 igb_irq_enable(adapter); 8271 } 8272 } 8273 8274 /** 8275 * igb_poll - NAPI Rx polling callback 8276 * @napi: napi polling structure 8277 * @budget: count of how many packets we should handle 8278 **/ 8279 static int igb_poll(struct napi_struct *napi, int budget) 8280 { 8281 struct igb_q_vector *q_vector = container_of(napi, 8282 struct igb_q_vector, 8283 napi); 8284 struct xsk_buff_pool *xsk_pool; 8285 bool clean_complete = true; 8286 int work_done = 0; 8287 8288 #ifdef CONFIG_IGB_DCA 8289 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 8290 igb_update_dca(q_vector); 8291 #endif 8292 if (q_vector->tx.ring) 8293 clean_complete = igb_clean_tx_irq(q_vector, budget); 8294 8295 if (q_vector->rx.ring) { 8296 int cleaned; 8297 8298 xsk_pool = READ_ONCE(q_vector->rx.ring->xsk_pool); 8299 cleaned = xsk_pool ? 8300 igb_clean_rx_irq_zc(q_vector, xsk_pool, budget) : 8301 igb_clean_rx_irq(q_vector, budget); 8302 8303 work_done += cleaned; 8304 if (cleaned >= budget) 8305 clean_complete = false; 8306 } 8307 8308 /* If all work not completed, return budget and keep polling */ 8309 if (!clean_complete) 8310 return budget; 8311 8312 /* Exit the polling mode, but don't re-enable interrupts if stack might 8313 * poll us due to busy-polling 8314 */ 8315 if (likely(napi_complete_done(napi, work_done))) 8316 igb_ring_irq_enable(q_vector); 8317 8318 return work_done; 8319 } 8320 8321 /** 8322 * igb_clean_tx_irq - Reclaim resources after transmit completes 8323 * @q_vector: pointer to q_vector containing needed info 8324 * @napi_budget: Used to determine if we are in netpoll 8325 * 8326 * returns true if ring is completely cleaned 8327 **/ 8328 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget) 8329 { 8330 unsigned int total_bytes = 0, total_packets = 0; 8331 struct igb_adapter *adapter = q_vector->adapter; 8332 unsigned int budget = q_vector->tx.work_limit; 8333 struct igb_ring *tx_ring = q_vector->tx.ring; 8334 unsigned int i = tx_ring->next_to_clean; 8335 union e1000_adv_tx_desc *tx_desc; 8336 struct igb_tx_buffer *tx_buffer; 8337 struct xsk_buff_pool *xsk_pool; 8338 int cpu = smp_processor_id(); 8339 bool xsk_xmit_done = true; 8340 struct netdev_queue *nq; 8341 u32 xsk_frames = 0; 8342 8343 if (test_bit(__IGB_DOWN, &adapter->state)) 8344 return true; 8345 8346 tx_buffer = &tx_ring->tx_buffer_info[i]; 8347 tx_desc = IGB_TX_DESC(tx_ring, i); 8348 i -= tx_ring->count; 8349 8350 do { 8351 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 8352 8353 /* if next_to_watch is not set then there is no work pending */ 8354 if (!eop_desc) 8355 break; 8356 8357 /* prevent any other reads prior to eop_desc */ 8358 smp_rmb(); 8359 8360 /* if DD is not set pending work has not been completed */ 8361 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 8362 break; 8363 8364 /* clear next_to_watch to prevent false hangs */ 8365 tx_buffer->next_to_watch = NULL; 8366 8367 /* update the statistics for this packet */ 8368 total_bytes += tx_buffer->bytecount; 8369 total_packets += tx_buffer->gso_segs; 8370 8371 /* free the skb */ 8372 if (tx_buffer->type == IGB_TYPE_SKB) { 8373 napi_consume_skb(tx_buffer->skb, napi_budget); 8374 } else if (tx_buffer->type == IGB_TYPE_XDP) { 8375 xdp_return_frame(tx_buffer->xdpf); 8376 } else if (tx_buffer->type == IGB_TYPE_XSK) { 8377 xsk_frames++; 8378 goto skip_for_xsk; 8379 } 8380 8381 /* unmap skb header data */ 8382 dma_unmap_single(tx_ring->dev, 8383 dma_unmap_addr(tx_buffer, dma), 8384 dma_unmap_len(tx_buffer, len), 8385 DMA_TO_DEVICE); 8386 8387 /* clear tx_buffer data */ 8388 dma_unmap_len_set(tx_buffer, len, 0); 8389 8390 /* clear last DMA location and unmap remaining buffers */ 8391 while (tx_desc != eop_desc) { 8392 tx_buffer++; 8393 tx_desc++; 8394 i++; 8395 if (unlikely(!i)) { 8396 i -= tx_ring->count; 8397 tx_buffer = tx_ring->tx_buffer_info; 8398 tx_desc = IGB_TX_DESC(tx_ring, 0); 8399 } 8400 8401 /* unmap any remaining paged data */ 8402 if (dma_unmap_len(tx_buffer, len)) { 8403 dma_unmap_page(tx_ring->dev, 8404 dma_unmap_addr(tx_buffer, dma), 8405 dma_unmap_len(tx_buffer, len), 8406 DMA_TO_DEVICE); 8407 dma_unmap_len_set(tx_buffer, len, 0); 8408 } 8409 } 8410 8411 skip_for_xsk: 8412 /* move us one more past the eop_desc for start of next pkt */ 8413 tx_buffer++; 8414 tx_desc++; 8415 i++; 8416 if (unlikely(!i)) { 8417 i -= tx_ring->count; 8418 tx_buffer = tx_ring->tx_buffer_info; 8419 tx_desc = IGB_TX_DESC(tx_ring, 0); 8420 } 8421 8422 /* issue prefetch for next Tx descriptor */ 8423 prefetch(tx_desc); 8424 8425 /* update budget accounting */ 8426 budget--; 8427 } while (likely(budget)); 8428 8429 netdev_tx_completed_queue(txring_txq(tx_ring), 8430 total_packets, total_bytes); 8431 i += tx_ring->count; 8432 tx_ring->next_to_clean = i; 8433 u64_stats_update_begin(&tx_ring->tx_syncp); 8434 tx_ring->tx_stats.bytes += total_bytes; 8435 tx_ring->tx_stats.packets += total_packets; 8436 u64_stats_update_end(&tx_ring->tx_syncp); 8437 q_vector->tx.total_bytes += total_bytes; 8438 q_vector->tx.total_packets += total_packets; 8439 8440 xsk_pool = READ_ONCE(tx_ring->xsk_pool); 8441 if (xsk_pool) { 8442 if (xsk_frames) 8443 xsk_tx_completed(xsk_pool, xsk_frames); 8444 if (xsk_uses_need_wakeup(xsk_pool)) 8445 xsk_set_tx_need_wakeup(xsk_pool); 8446 8447 nq = txring_txq(tx_ring); 8448 __netif_tx_lock(nq, cpu); 8449 /* Avoid transmit queue timeout since we share it with the slow path */ 8450 txq_trans_cond_update(nq); 8451 xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool); 8452 __netif_tx_unlock(nq); 8453 } 8454 8455 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 8456 struct e1000_hw *hw = &adapter->hw; 8457 8458 /* Detect a transmit hang in hardware, this serializes the 8459 * check with the clearing of time_stamp and movement of i 8460 */ 8461 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 8462 if (tx_buffer->next_to_watch && 8463 time_after(jiffies, tx_buffer->time_stamp + 8464 (adapter->tx_timeout_factor * HZ)) && 8465 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 8466 8467 /* detected Tx unit hang */ 8468 dev_err(tx_ring->dev, 8469 "Detected Tx Unit Hang\n" 8470 " Tx Queue <%d>\n" 8471 " TDH <%x>\n" 8472 " TDT <%x>\n" 8473 " next_to_use <%x>\n" 8474 " next_to_clean <%x>\n" 8475 "buffer_info[next_to_clean]\n" 8476 " time_stamp <%lx>\n" 8477 " next_to_watch <%p>\n" 8478 " jiffies <%lx>\n" 8479 " desc.status <%x>\n", 8480 tx_ring->queue_index, 8481 rd32(E1000_TDH(tx_ring->reg_idx)), 8482 readl(tx_ring->tail), 8483 tx_ring->next_to_use, 8484 tx_ring->next_to_clean, 8485 tx_buffer->time_stamp, 8486 tx_buffer->next_to_watch, 8487 jiffies, 8488 tx_buffer->next_to_watch->wb.status); 8489 netif_stop_subqueue(tx_ring->netdev, 8490 tx_ring->queue_index); 8491 8492 /* we are about to reset, no point in enabling stuff */ 8493 return true; 8494 } 8495 } 8496 8497 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 8498 if (unlikely(total_packets && 8499 netif_carrier_ok(tx_ring->netdev) && 8500 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 8501 /* Make sure that anybody stopping the queue after this 8502 * sees the new next_to_clean. 8503 */ 8504 smp_mb(); 8505 if (__netif_subqueue_stopped(tx_ring->netdev, 8506 tx_ring->queue_index) && 8507 !(test_bit(__IGB_DOWN, &adapter->state))) { 8508 netif_wake_subqueue(tx_ring->netdev, 8509 tx_ring->queue_index); 8510 8511 u64_stats_update_begin(&tx_ring->tx_syncp); 8512 tx_ring->tx_stats.restart_queue++; 8513 u64_stats_update_end(&tx_ring->tx_syncp); 8514 } 8515 } 8516 8517 return !!budget && xsk_xmit_done; 8518 } 8519 8520 /** 8521 * igb_reuse_rx_page - page flip buffer and store it back on the ring 8522 * @rx_ring: rx descriptor ring to store buffers on 8523 * @old_buff: donor buffer to have page reused 8524 * 8525 * Synchronizes page for reuse by the adapter 8526 **/ 8527 static void igb_reuse_rx_page(struct igb_ring *rx_ring, 8528 struct igb_rx_buffer *old_buff) 8529 { 8530 struct igb_rx_buffer *new_buff; 8531 u16 nta = rx_ring->next_to_alloc; 8532 8533 new_buff = &rx_ring->rx_buffer_info[nta]; 8534 8535 /* update, and store next to alloc */ 8536 nta++; 8537 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 8538 8539 /* Transfer page from old buffer to new buffer. 8540 * Move each member individually to avoid possible store 8541 * forwarding stalls. 8542 */ 8543 new_buff->dma = old_buff->dma; 8544 new_buff->page = old_buff->page; 8545 new_buff->page_offset = old_buff->page_offset; 8546 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 8547 } 8548 8549 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 8550 int rx_buf_pgcnt) 8551 { 8552 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 8553 struct page *page = rx_buffer->page; 8554 8555 /* avoid re-using remote and pfmemalloc pages */ 8556 if (!dev_page_is_reusable(page)) 8557 return false; 8558 8559 #if (PAGE_SIZE < 8192) 8560 /* if we are only owner of page we can reuse it */ 8561 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 8562 return false; 8563 #else 8564 #define IGB_LAST_OFFSET \ 8565 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048) 8566 8567 if (rx_buffer->page_offset > IGB_LAST_OFFSET) 8568 return false; 8569 #endif 8570 8571 /* If we have drained the page fragment pool we need to update 8572 * the pagecnt_bias and page count so that we fully restock the 8573 * number of references the driver holds. 8574 */ 8575 if (unlikely(pagecnt_bias == 1)) { 8576 page_ref_add(page, USHRT_MAX - 1); 8577 rx_buffer->pagecnt_bias = USHRT_MAX; 8578 } 8579 8580 return true; 8581 } 8582 8583 /** 8584 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 8585 * @rx_ring: rx descriptor ring to transact packets on 8586 * @rx_buffer: buffer containing page to add 8587 * @skb: sk_buff to place the data into 8588 * @size: size of buffer to be added 8589 * 8590 * This function will add the data contained in rx_buffer->page to the skb. 8591 **/ 8592 static void igb_add_rx_frag(struct igb_ring *rx_ring, 8593 struct igb_rx_buffer *rx_buffer, 8594 struct sk_buff *skb, 8595 unsigned int size) 8596 { 8597 #if (PAGE_SIZE < 8192) 8598 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8599 #else 8600 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 8601 SKB_DATA_ALIGN(IGB_SKB_PAD + size) : 8602 SKB_DATA_ALIGN(size); 8603 #endif 8604 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 8605 rx_buffer->page_offset, size, truesize); 8606 #if (PAGE_SIZE < 8192) 8607 rx_buffer->page_offset ^= truesize; 8608 #else 8609 rx_buffer->page_offset += truesize; 8610 #endif 8611 } 8612 8613 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring, 8614 struct igb_rx_buffer *rx_buffer, 8615 struct xdp_buff *xdp, 8616 ktime_t timestamp) 8617 { 8618 #if (PAGE_SIZE < 8192) 8619 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8620 #else 8621 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 8622 xdp->data_hard_start); 8623 #endif 8624 unsigned int size = xdp->data_end - xdp->data; 8625 unsigned int headlen; 8626 struct sk_buff *skb; 8627 8628 /* prefetch first cache line of first page */ 8629 net_prefetch(xdp->data); 8630 8631 /* allocate a skb to store the frags */ 8632 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN); 8633 if (unlikely(!skb)) 8634 return NULL; 8635 8636 if (timestamp) 8637 skb_hwtstamps(skb)->hwtstamp = timestamp; 8638 8639 /* Determine available headroom for copy */ 8640 headlen = size; 8641 if (headlen > IGB_RX_HDR_LEN) 8642 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN); 8643 8644 /* align pull length to size of long to optimize memcpy performance */ 8645 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long))); 8646 8647 /* update all of the pointers */ 8648 size -= headlen; 8649 if (size) { 8650 skb_add_rx_frag(skb, 0, rx_buffer->page, 8651 (xdp->data + headlen) - page_address(rx_buffer->page), 8652 size, truesize); 8653 #if (PAGE_SIZE < 8192) 8654 rx_buffer->page_offset ^= truesize; 8655 #else 8656 rx_buffer->page_offset += truesize; 8657 #endif 8658 } else { 8659 rx_buffer->pagecnt_bias++; 8660 } 8661 8662 return skb; 8663 } 8664 8665 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring, 8666 struct igb_rx_buffer *rx_buffer, 8667 struct xdp_buff *xdp, 8668 ktime_t timestamp) 8669 { 8670 #if (PAGE_SIZE < 8192) 8671 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2; 8672 #else 8673 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 8674 SKB_DATA_ALIGN(xdp->data_end - 8675 xdp->data_hard_start); 8676 #endif 8677 unsigned int metasize = xdp->data - xdp->data_meta; 8678 struct sk_buff *skb; 8679 8680 /* prefetch first cache line of first page */ 8681 net_prefetch(xdp->data_meta); 8682 8683 /* build an skb around the page buffer */ 8684 skb = napi_build_skb(xdp->data_hard_start, truesize); 8685 if (unlikely(!skb)) 8686 return NULL; 8687 8688 /* update pointers within the skb to store the data */ 8689 skb_reserve(skb, xdp->data - xdp->data_hard_start); 8690 __skb_put(skb, xdp->data_end - xdp->data); 8691 8692 if (metasize) 8693 skb_metadata_set(skb, metasize); 8694 8695 if (timestamp) 8696 skb_hwtstamps(skb)->hwtstamp = timestamp; 8697 8698 /* update buffer offset */ 8699 #if (PAGE_SIZE < 8192) 8700 rx_buffer->page_offset ^= truesize; 8701 #else 8702 rx_buffer->page_offset += truesize; 8703 #endif 8704 8705 return skb; 8706 } 8707 8708 static int igb_run_xdp(struct igb_adapter *adapter, struct igb_ring *rx_ring, 8709 struct xdp_buff *xdp) 8710 { 8711 int err, result = IGB_XDP_PASS; 8712 struct bpf_prog *xdp_prog; 8713 u32 act; 8714 8715 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 8716 8717 if (!xdp_prog) 8718 goto xdp_out; 8719 8720 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 8721 8722 act = bpf_prog_run_xdp(xdp_prog, xdp); 8723 switch (act) { 8724 case XDP_PASS: 8725 break; 8726 case XDP_TX: 8727 result = igb_xdp_xmit_back(adapter, xdp); 8728 if (result == IGB_XDP_CONSUMED) 8729 goto out_failure; 8730 break; 8731 case XDP_REDIRECT: 8732 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 8733 if (err) 8734 goto out_failure; 8735 result = IGB_XDP_REDIR; 8736 break; 8737 default: 8738 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act); 8739 fallthrough; 8740 case XDP_ABORTED: 8741 out_failure: 8742 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 8743 fallthrough; 8744 case XDP_DROP: 8745 result = IGB_XDP_CONSUMED; 8746 break; 8747 } 8748 xdp_out: 8749 return result; 8750 } 8751 8752 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring, 8753 unsigned int size) 8754 { 8755 unsigned int truesize; 8756 8757 #if (PAGE_SIZE < 8192) 8758 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 8759 #else 8760 truesize = ring_uses_build_skb(rx_ring) ? 8761 SKB_DATA_ALIGN(IGB_SKB_PAD + size) + 8762 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 8763 SKB_DATA_ALIGN(size); 8764 #endif 8765 return truesize; 8766 } 8767 8768 static void igb_rx_buffer_flip(struct igb_ring *rx_ring, 8769 struct igb_rx_buffer *rx_buffer, 8770 unsigned int size) 8771 { 8772 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size); 8773 #if (PAGE_SIZE < 8192) 8774 rx_buffer->page_offset ^= truesize; 8775 #else 8776 rx_buffer->page_offset += truesize; 8777 #endif 8778 } 8779 8780 static inline void igb_rx_checksum(struct igb_ring *ring, 8781 union e1000_adv_rx_desc *rx_desc, 8782 struct sk_buff *skb) 8783 { 8784 skb_checksum_none_assert(skb); 8785 8786 /* Ignore Checksum bit is set */ 8787 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 8788 return; 8789 8790 /* Rx checksum disabled via ethtool */ 8791 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 8792 return; 8793 8794 /* TCP/UDP checksum error bit is set */ 8795 if (igb_test_staterr(rx_desc, 8796 E1000_RXDEXT_STATERR_TCPE | 8797 E1000_RXDEXT_STATERR_IPE)) { 8798 /* work around errata with sctp packets where the TCPE aka 8799 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 8800 * packets, (aka let the stack check the crc32c) 8801 */ 8802 if (!((skb->len == 60) && 8803 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 8804 u64_stats_update_begin(&ring->rx_syncp); 8805 ring->rx_stats.csum_err++; 8806 u64_stats_update_end(&ring->rx_syncp); 8807 } 8808 /* let the stack verify checksum errors */ 8809 return; 8810 } 8811 /* It must be a TCP or UDP packet with a valid checksum */ 8812 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 8813 E1000_RXD_STAT_UDPCS)) 8814 skb->ip_summed = CHECKSUM_UNNECESSARY; 8815 8816 dev_dbg(ring->dev, "cksum success: bits %08X\n", 8817 le32_to_cpu(rx_desc->wb.upper.status_error)); 8818 } 8819 8820 static inline void igb_rx_hash(struct igb_ring *ring, 8821 union e1000_adv_rx_desc *rx_desc, 8822 struct sk_buff *skb) 8823 { 8824 if (ring->netdev->features & NETIF_F_RXHASH) 8825 skb_set_hash(skb, 8826 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 8827 PKT_HASH_TYPE_L3); 8828 } 8829 8830 /** 8831 * igb_is_non_eop - process handling of non-EOP buffers 8832 * @rx_ring: Rx ring being processed 8833 * @rx_desc: Rx descriptor for current buffer 8834 * 8835 * This function updates next to clean. If the buffer is an EOP buffer 8836 * this function exits returning false, otherwise it will place the 8837 * sk_buff in the next buffer to be chained and return true indicating 8838 * that this is in fact a non-EOP buffer. 8839 **/ 8840 static bool igb_is_non_eop(struct igb_ring *rx_ring, 8841 union e1000_adv_rx_desc *rx_desc) 8842 { 8843 u32 ntc = rx_ring->next_to_clean + 1; 8844 8845 /* fetch, update, and store next to clean */ 8846 ntc = (ntc < rx_ring->count) ? ntc : 0; 8847 rx_ring->next_to_clean = ntc; 8848 8849 prefetch(IGB_RX_DESC(rx_ring, ntc)); 8850 8851 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 8852 return false; 8853 8854 return true; 8855 } 8856 8857 /** 8858 * igb_cleanup_headers - Correct corrupted or empty headers 8859 * @rx_ring: rx descriptor ring packet is being transacted on 8860 * @rx_desc: pointer to the EOP Rx descriptor 8861 * @skb: pointer to current skb being fixed 8862 * 8863 * Address the case where we are pulling data in on pages only 8864 * and as such no data is present in the skb header. 8865 * 8866 * In addition if skb is not at least 60 bytes we need to pad it so that 8867 * it is large enough to qualify as a valid Ethernet frame. 8868 * 8869 * Returns true if an error was encountered and skb was freed. 8870 **/ 8871 static bool igb_cleanup_headers(struct igb_ring *rx_ring, 8872 union e1000_adv_rx_desc *rx_desc, 8873 struct sk_buff *skb) 8874 { 8875 if (unlikely((igb_test_staterr(rx_desc, 8876 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 8877 struct net_device *netdev = rx_ring->netdev; 8878 if (!(netdev->features & NETIF_F_RXALL)) { 8879 dev_kfree_skb_any(skb); 8880 return true; 8881 } 8882 } 8883 8884 /* if eth_skb_pad returns an error the skb was freed */ 8885 if (eth_skb_pad(skb)) 8886 return true; 8887 8888 return false; 8889 } 8890 8891 /** 8892 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 8893 * @rx_ring: rx descriptor ring packet is being transacted on 8894 * @rx_desc: pointer to the EOP Rx descriptor 8895 * @skb: pointer to current skb being populated 8896 * 8897 * This function checks the ring, descriptor, and packet information in 8898 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 8899 * other fields within the skb. 8900 **/ 8901 void igb_process_skb_fields(struct igb_ring *rx_ring, 8902 union e1000_adv_rx_desc *rx_desc, 8903 struct sk_buff *skb) 8904 { 8905 struct net_device *dev = rx_ring->netdev; 8906 8907 igb_rx_hash(rx_ring, rx_desc, skb); 8908 8909 igb_rx_checksum(rx_ring, rx_desc, skb); 8910 8911 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 8912 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 8913 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 8914 8915 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 8916 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 8917 u16 vid; 8918 8919 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 8920 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 8921 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 8922 else 8923 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 8924 8925 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 8926 } 8927 8928 skb_record_rx_queue(skb, rx_ring->queue_index); 8929 8930 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 8931 } 8932 8933 static unsigned int igb_rx_offset(struct igb_ring *rx_ring) 8934 { 8935 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0; 8936 } 8937 8938 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring, 8939 const unsigned int size, int *rx_buf_pgcnt) 8940 { 8941 struct igb_rx_buffer *rx_buffer; 8942 8943 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 8944 *rx_buf_pgcnt = 8945 #if (PAGE_SIZE < 8192) 8946 page_count(rx_buffer->page); 8947 #else 8948 0; 8949 #endif 8950 prefetchw(rx_buffer->page); 8951 8952 /* we are reusing so sync this buffer for CPU use */ 8953 dma_sync_single_range_for_cpu(rx_ring->dev, 8954 rx_buffer->dma, 8955 rx_buffer->page_offset, 8956 size, 8957 DMA_FROM_DEVICE); 8958 8959 rx_buffer->pagecnt_bias--; 8960 8961 return rx_buffer; 8962 } 8963 8964 static void igb_put_rx_buffer(struct igb_ring *rx_ring, 8965 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt) 8966 { 8967 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { 8968 /* hand second half of page back to the ring */ 8969 igb_reuse_rx_page(rx_ring, rx_buffer); 8970 } else { 8971 /* We are not reusing the buffer so unmap it and free 8972 * any references we are holding to it 8973 */ 8974 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 8975 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 8976 IGB_RX_DMA_ATTR); 8977 __page_frag_cache_drain(rx_buffer->page, 8978 rx_buffer->pagecnt_bias); 8979 } 8980 8981 /* clear contents of rx_buffer */ 8982 rx_buffer->page = NULL; 8983 } 8984 8985 void igb_finalize_xdp(struct igb_adapter *adapter, unsigned int status) 8986 { 8987 int cpu = smp_processor_id(); 8988 struct netdev_queue *nq; 8989 8990 if (status & IGB_XDP_REDIR) 8991 xdp_do_flush(); 8992 8993 if (status & IGB_XDP_TX) { 8994 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter); 8995 8996 nq = txring_txq(tx_ring); 8997 __netif_tx_lock(nq, cpu); 8998 igb_xdp_ring_update_tail(tx_ring); 8999 __netif_tx_unlock(nq); 9000 } 9001 } 9002 9003 void igb_update_rx_stats(struct igb_q_vector *q_vector, unsigned int packets, 9004 unsigned int bytes) 9005 { 9006 struct igb_ring *ring = q_vector->rx.ring; 9007 9008 u64_stats_update_begin(&ring->rx_syncp); 9009 ring->rx_stats.packets += packets; 9010 ring->rx_stats.bytes += bytes; 9011 u64_stats_update_end(&ring->rx_syncp); 9012 9013 q_vector->rx.total_packets += packets; 9014 q_vector->rx.total_bytes += bytes; 9015 } 9016 9017 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 9018 { 9019 unsigned int total_bytes = 0, total_packets = 0; 9020 struct igb_adapter *adapter = q_vector->adapter; 9021 struct igb_ring *rx_ring = q_vector->rx.ring; 9022 u16 cleaned_count = igb_desc_unused(rx_ring); 9023 struct sk_buff *skb = rx_ring->skb; 9024 unsigned int xdp_xmit = 0; 9025 struct xdp_buff xdp; 9026 u32 frame_sz = 0; 9027 int rx_buf_pgcnt; 9028 int xdp_res = 0; 9029 9030 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 9031 #if (PAGE_SIZE < 8192) 9032 frame_sz = igb_rx_frame_truesize(rx_ring, 0); 9033 #endif 9034 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 9035 9036 while (likely(total_packets < budget)) { 9037 union e1000_adv_rx_desc *rx_desc; 9038 struct igb_rx_buffer *rx_buffer; 9039 ktime_t timestamp = 0; 9040 int pkt_offset = 0; 9041 unsigned int size; 9042 void *pktbuf; 9043 9044 /* return some buffers to hardware, one at a time is too slow */ 9045 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 9046 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9047 cleaned_count = 0; 9048 } 9049 9050 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 9051 size = le16_to_cpu(rx_desc->wb.upper.length); 9052 if (!size) 9053 break; 9054 9055 /* This memory barrier is needed to keep us from reading 9056 * any other fields out of the rx_desc until we know the 9057 * descriptor has been written back 9058 */ 9059 dma_rmb(); 9060 9061 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt); 9062 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 9063 9064 /* pull rx packet timestamp if available and valid */ 9065 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 9066 int ts_hdr_len; 9067 9068 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector, 9069 pktbuf, ×tamp); 9070 9071 pkt_offset += ts_hdr_len; 9072 size -= ts_hdr_len; 9073 } 9074 9075 /* retrieve a buffer from the ring */ 9076 if (!skb) { 9077 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring); 9078 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring); 9079 9080 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 9081 xdp_buff_clear_frags_flag(&xdp); 9082 #if (PAGE_SIZE > 4096) 9083 /* At larger PAGE_SIZE, frame_sz depend on len size */ 9084 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size); 9085 #endif 9086 xdp_res = igb_run_xdp(adapter, rx_ring, &xdp); 9087 } 9088 9089 if (xdp_res) { 9090 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) { 9091 xdp_xmit |= xdp_res; 9092 igb_rx_buffer_flip(rx_ring, rx_buffer, size); 9093 } else { 9094 rx_buffer->pagecnt_bias++; 9095 } 9096 total_packets++; 9097 total_bytes += size; 9098 } else if (skb) 9099 igb_add_rx_frag(rx_ring, rx_buffer, skb, size); 9100 else if (ring_uses_build_skb(rx_ring)) 9101 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, 9102 timestamp); 9103 else 9104 skb = igb_construct_skb(rx_ring, rx_buffer, 9105 &xdp, timestamp); 9106 9107 /* exit if we failed to retrieve a buffer */ 9108 if (!xdp_res && !skb) { 9109 rx_ring->rx_stats.alloc_failed++; 9110 rx_buffer->pagecnt_bias++; 9111 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9112 break; 9113 } 9114 9115 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt); 9116 cleaned_count++; 9117 9118 /* fetch next buffer in frame if non-eop */ 9119 if (igb_is_non_eop(rx_ring, rx_desc)) 9120 continue; 9121 9122 /* verify the packet layout is correct */ 9123 if (xdp_res || igb_cleanup_headers(rx_ring, rx_desc, skb)) { 9124 skb = NULL; 9125 continue; 9126 } 9127 9128 /* probably a little skewed due to removing CRC */ 9129 total_bytes += skb->len; 9130 9131 /* populate checksum, timestamp, VLAN, and protocol */ 9132 igb_process_skb_fields(rx_ring, rx_desc, skb); 9133 9134 napi_gro_receive(&q_vector->napi, skb); 9135 9136 /* reset skb pointer */ 9137 skb = NULL; 9138 9139 /* update budget accounting */ 9140 total_packets++; 9141 } 9142 9143 /* place incomplete frames back on ring for completion */ 9144 rx_ring->skb = skb; 9145 9146 if (xdp_xmit) 9147 igb_finalize_xdp(adapter, xdp_xmit); 9148 9149 igb_update_rx_stats(q_vector, total_packets, total_bytes); 9150 9151 if (cleaned_count) 9152 igb_alloc_rx_buffers(rx_ring, cleaned_count); 9153 9154 return total_packets; 9155 } 9156 9157 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 9158 struct igb_rx_buffer *bi) 9159 { 9160 struct page *page = bi->page; 9161 dma_addr_t dma; 9162 9163 /* since we are recycling buffers we should seldom need to alloc */ 9164 if (likely(page)) 9165 return true; 9166 9167 /* alloc new page for storage */ 9168 page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); 9169 if (unlikely(!page)) { 9170 rx_ring->rx_stats.alloc_failed++; 9171 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9172 return false; 9173 } 9174 9175 /* map page for use */ 9176 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 9177 igb_rx_pg_size(rx_ring), 9178 DMA_FROM_DEVICE, 9179 IGB_RX_DMA_ATTR); 9180 9181 /* if mapping failed free memory back to system since 9182 * there isn't much point in holding memory we can't use 9183 */ 9184 if (dma_mapping_error(rx_ring->dev, dma)) { 9185 __free_pages(page, igb_rx_pg_order(rx_ring)); 9186 9187 rx_ring->rx_stats.alloc_failed++; 9188 set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); 9189 return false; 9190 } 9191 9192 bi->dma = dma; 9193 bi->page = page; 9194 bi->page_offset = igb_rx_offset(rx_ring); 9195 page_ref_add(page, USHRT_MAX - 1); 9196 bi->pagecnt_bias = USHRT_MAX; 9197 9198 return true; 9199 } 9200 9201 /** 9202 * igb_alloc_rx_buffers - Replace used receive buffers 9203 * @rx_ring: rx descriptor ring to allocate new receive buffers 9204 * @cleaned_count: count of buffers to allocate 9205 **/ 9206 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 9207 { 9208 union e1000_adv_rx_desc *rx_desc; 9209 struct igb_rx_buffer *bi; 9210 u16 i = rx_ring->next_to_use; 9211 u16 bufsz; 9212 9213 /* nothing to do */ 9214 if (!cleaned_count) 9215 return; 9216 9217 rx_desc = IGB_RX_DESC(rx_ring, i); 9218 bi = &rx_ring->rx_buffer_info[i]; 9219 i -= rx_ring->count; 9220 9221 bufsz = igb_rx_bufsz(rx_ring); 9222 9223 do { 9224 if (!igb_alloc_mapped_page(rx_ring, bi)) 9225 break; 9226 9227 /* sync the buffer for use by the device */ 9228 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 9229 bi->page_offset, bufsz, 9230 DMA_FROM_DEVICE); 9231 9232 /* Refresh the desc even if buffer_addrs didn't change 9233 * because each write-back erases this info. 9234 */ 9235 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 9236 9237 rx_desc++; 9238 bi++; 9239 i++; 9240 if (unlikely(!i)) { 9241 rx_desc = IGB_RX_DESC(rx_ring, 0); 9242 bi = rx_ring->rx_buffer_info; 9243 i -= rx_ring->count; 9244 } 9245 9246 /* clear the length for the next_to_use descriptor */ 9247 rx_desc->wb.upper.length = 0; 9248 9249 cleaned_count--; 9250 } while (cleaned_count); 9251 9252 i += rx_ring->count; 9253 9254 if (rx_ring->next_to_use != i) { 9255 /* record the next descriptor to use */ 9256 rx_ring->next_to_use = i; 9257 9258 /* update next to alloc since we have filled the ring */ 9259 rx_ring->next_to_alloc = i; 9260 9261 /* Force memory writes to complete before letting h/w 9262 * know there are new descriptors to fetch. (Only 9263 * applicable for weak-ordered memory model archs, 9264 * such as IA-64). 9265 */ 9266 dma_wmb(); 9267 writel(i, rx_ring->tail); 9268 } 9269 } 9270 9271 /** 9272 * igb_mii_ioctl - 9273 * @netdev: pointer to netdev struct 9274 * @ifr: interface structure 9275 * @cmd: ioctl command to execute 9276 **/ 9277 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9278 { 9279 struct igb_adapter *adapter = netdev_priv(netdev); 9280 struct mii_ioctl_data *data = if_mii(ifr); 9281 9282 if (adapter->hw.phy.media_type != e1000_media_type_copper) 9283 return -EOPNOTSUPP; 9284 9285 switch (cmd) { 9286 case SIOCGMIIPHY: 9287 data->phy_id = adapter->hw.phy.addr; 9288 break; 9289 case SIOCGMIIREG: 9290 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9291 &data->val_out)) 9292 return -EIO; 9293 break; 9294 case SIOCSMIIREG: 9295 if (igb_write_phy_reg(&adapter->hw, data->reg_num & 0x1F, 9296 data->val_in)) 9297 return -EIO; 9298 break; 9299 default: 9300 return -EOPNOTSUPP; 9301 } 9302 return 0; 9303 } 9304 9305 /** 9306 * igb_ioctl - 9307 * @netdev: pointer to netdev struct 9308 * @ifr: interface structure 9309 * @cmd: ioctl command to execute 9310 **/ 9311 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 9312 { 9313 switch (cmd) { 9314 case SIOCGMIIPHY: 9315 case SIOCGMIIREG: 9316 case SIOCSMIIREG: 9317 return igb_mii_ioctl(netdev, ifr, cmd); 9318 default: 9319 return -EOPNOTSUPP; 9320 } 9321 } 9322 9323 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9324 { 9325 struct igb_adapter *adapter = hw->back; 9326 9327 pci_read_config_word(adapter->pdev, reg, value); 9328 } 9329 9330 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 9331 { 9332 struct igb_adapter *adapter = hw->back; 9333 9334 pci_write_config_word(adapter->pdev, reg, *value); 9335 } 9336 9337 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9338 { 9339 struct igb_adapter *adapter = hw->back; 9340 9341 if (pcie_capability_read_word(adapter->pdev, reg, value)) 9342 return -E1000_ERR_CONFIG; 9343 9344 return 0; 9345 } 9346 9347 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 9348 { 9349 struct igb_adapter *adapter = hw->back; 9350 9351 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 9352 return -E1000_ERR_CONFIG; 9353 9354 return 0; 9355 } 9356 9357 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 9358 { 9359 struct igb_adapter *adapter = netdev_priv(netdev); 9360 struct e1000_hw *hw = &adapter->hw; 9361 u32 ctrl, rctl; 9362 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 9363 9364 if (enable) { 9365 /* enable VLAN tag insert/strip */ 9366 ctrl = rd32(E1000_CTRL); 9367 ctrl |= E1000_CTRL_VME; 9368 wr32(E1000_CTRL, ctrl); 9369 9370 /* Disable CFI check */ 9371 rctl = rd32(E1000_RCTL); 9372 rctl &= ~E1000_RCTL_CFIEN; 9373 wr32(E1000_RCTL, rctl); 9374 } else { 9375 /* disable VLAN tag insert/strip */ 9376 ctrl = rd32(E1000_CTRL); 9377 ctrl &= ~E1000_CTRL_VME; 9378 wr32(E1000_CTRL, ctrl); 9379 } 9380 9381 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable); 9382 } 9383 9384 static int igb_vlan_rx_add_vid(struct net_device *netdev, 9385 __be16 proto, u16 vid) 9386 { 9387 struct igb_adapter *adapter = netdev_priv(netdev); 9388 struct e1000_hw *hw = &adapter->hw; 9389 int pf_id = adapter->vfs_allocated_count; 9390 9391 /* add the filter since PF can receive vlans w/o entry in vlvf */ 9392 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9393 igb_vfta_set(hw, vid, pf_id, true, !!vid); 9394 9395 set_bit(vid, adapter->active_vlans); 9396 9397 return 0; 9398 } 9399 9400 static int igb_vlan_rx_kill_vid(struct net_device *netdev, 9401 __be16 proto, u16 vid) 9402 { 9403 struct igb_adapter *adapter = netdev_priv(netdev); 9404 int pf_id = adapter->vfs_allocated_count; 9405 struct e1000_hw *hw = &adapter->hw; 9406 9407 /* remove VID from filter table */ 9408 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC)) 9409 igb_vfta_set(hw, vid, pf_id, false, true); 9410 9411 clear_bit(vid, adapter->active_vlans); 9412 9413 return 0; 9414 } 9415 9416 static void igb_restore_vlan(struct igb_adapter *adapter) 9417 { 9418 u16 vid = 1; 9419 9420 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 9421 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 9422 9423 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 9424 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 9425 } 9426 9427 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 9428 { 9429 struct pci_dev *pdev = adapter->pdev; 9430 struct e1000_mac_info *mac = &adapter->hw.mac; 9431 9432 mac->autoneg = 0; 9433 9434 /* Make sure dplx is at most 1 bit and lsb of speed is not set 9435 * for the switch() below to work 9436 */ 9437 if ((spd & 1) || (dplx & ~1)) 9438 goto err_inval; 9439 9440 /* Fiber NIC's only allow 1000 gbps Full duplex 9441 * and 100Mbps Full duplex for 100baseFx sfp 9442 */ 9443 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 9444 switch (spd + dplx) { 9445 case SPEED_10 + DUPLEX_HALF: 9446 case SPEED_10 + DUPLEX_FULL: 9447 case SPEED_100 + DUPLEX_HALF: 9448 goto err_inval; 9449 default: 9450 break; 9451 } 9452 } 9453 9454 switch (spd + dplx) { 9455 case SPEED_10 + DUPLEX_HALF: 9456 mac->forced_speed_duplex = ADVERTISE_10_HALF; 9457 break; 9458 case SPEED_10 + DUPLEX_FULL: 9459 mac->forced_speed_duplex = ADVERTISE_10_FULL; 9460 break; 9461 case SPEED_100 + DUPLEX_HALF: 9462 mac->forced_speed_duplex = ADVERTISE_100_HALF; 9463 break; 9464 case SPEED_100 + DUPLEX_FULL: 9465 mac->forced_speed_duplex = ADVERTISE_100_FULL; 9466 break; 9467 case SPEED_1000 + DUPLEX_FULL: 9468 mac->autoneg = 1; 9469 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 9470 break; 9471 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 9472 default: 9473 goto err_inval; 9474 } 9475 9476 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 9477 adapter->hw.phy.mdix = AUTO_ALL_MODES; 9478 9479 return 0; 9480 9481 err_inval: 9482 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 9483 return -EINVAL; 9484 } 9485 9486 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 9487 bool runtime) 9488 { 9489 struct net_device *netdev = pci_get_drvdata(pdev); 9490 struct igb_adapter *adapter = netdev_priv(netdev); 9491 struct e1000_hw *hw = &adapter->hw; 9492 u32 ctrl, rctl, status; 9493 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 9494 bool wake; 9495 9496 rtnl_lock(); 9497 netif_device_detach(netdev); 9498 9499 if (netif_running(netdev)) 9500 __igb_close(netdev, true); 9501 9502 igb_ptp_suspend(adapter); 9503 9504 igb_clear_interrupt_scheme(adapter); 9505 rtnl_unlock(); 9506 9507 status = rd32(E1000_STATUS); 9508 if (status & E1000_STATUS_LU) 9509 wufc &= ~E1000_WUFC_LNKC; 9510 9511 if (wufc) { 9512 igb_setup_rctl(adapter); 9513 igb_set_rx_mode(netdev); 9514 9515 /* turn on all-multi mode if wake on multicast is enabled */ 9516 if (wufc & E1000_WUFC_MC) { 9517 rctl = rd32(E1000_RCTL); 9518 rctl |= E1000_RCTL_MPE; 9519 wr32(E1000_RCTL, rctl); 9520 } 9521 9522 ctrl = rd32(E1000_CTRL); 9523 ctrl |= E1000_CTRL_ADVD3WUC; 9524 wr32(E1000_CTRL, ctrl); 9525 9526 /* Allow time for pending master requests to run */ 9527 igb_disable_pcie_master(hw); 9528 9529 wr32(E1000_WUC, E1000_WUC_PME_EN); 9530 wr32(E1000_WUFC, wufc); 9531 } else { 9532 wr32(E1000_WUC, 0); 9533 wr32(E1000_WUFC, 0); 9534 } 9535 9536 wake = wufc || adapter->en_mng_pt; 9537 if (!wake) 9538 igb_power_down_link(adapter); 9539 else 9540 igb_power_up_link(adapter); 9541 9542 if (enable_wake) 9543 *enable_wake = wake; 9544 9545 /* Release control of h/w to f/w. If f/w is AMT enabled, this 9546 * would have already happened in close and is redundant. 9547 */ 9548 igb_release_hw_control(adapter); 9549 9550 pci_disable_device(pdev); 9551 9552 return 0; 9553 } 9554 9555 static void igb_deliver_wake_packet(struct net_device *netdev) 9556 { 9557 struct igb_adapter *adapter = netdev_priv(netdev); 9558 struct e1000_hw *hw = &adapter->hw; 9559 struct sk_buff *skb; 9560 u32 wupl; 9561 9562 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK; 9563 9564 /* WUPM stores only the first 128 bytes of the wake packet. 9565 * Read the packet only if we have the whole thing. 9566 */ 9567 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES)) 9568 return; 9569 9570 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES); 9571 if (!skb) 9572 return; 9573 9574 skb_put(skb, wupl); 9575 9576 /* Ensure reads are 32-bit aligned */ 9577 wupl = roundup(wupl, 4); 9578 9579 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl); 9580 9581 skb->protocol = eth_type_trans(skb, netdev); 9582 netif_rx(skb); 9583 } 9584 9585 static int igb_suspend(struct device *dev) 9586 { 9587 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9588 } 9589 9590 static int __igb_resume(struct device *dev, bool rpm) 9591 { 9592 struct pci_dev *pdev = to_pci_dev(dev); 9593 struct net_device *netdev = pci_get_drvdata(pdev); 9594 struct igb_adapter *adapter = netdev_priv(netdev); 9595 struct e1000_hw *hw = &adapter->hw; 9596 u32 err, val; 9597 9598 pci_set_power_state(pdev, PCI_D0); 9599 pci_restore_state(pdev); 9600 9601 if (!pci_device_is_present(pdev)) 9602 return -ENODEV; 9603 err = pci_enable_device_mem(pdev); 9604 if (err) { 9605 dev_err(&pdev->dev, 9606 "igb: Cannot enable PCI device from suspend\n"); 9607 return err; 9608 } 9609 pci_set_master(pdev); 9610 9611 pci_enable_wake(pdev, PCI_D3hot, 0); 9612 pci_enable_wake(pdev, PCI_D3cold, 0); 9613 9614 if (igb_init_interrupt_scheme(adapter, true)) { 9615 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 9616 return -ENOMEM; 9617 } 9618 9619 igb_reset(adapter); 9620 9621 /* let the f/w know that the h/w is now under the control of the 9622 * driver. 9623 */ 9624 igb_get_hw_control(adapter); 9625 9626 val = rd32(E1000_WUS); 9627 if (val & WAKE_PKT_WUS) 9628 igb_deliver_wake_packet(netdev); 9629 9630 wr32(E1000_WUS, ~0); 9631 9632 if (!rpm) 9633 rtnl_lock(); 9634 if (!err && netif_running(netdev)) 9635 err = __igb_open(netdev, true); 9636 9637 if (!err) 9638 netif_device_attach(netdev); 9639 if (!rpm) 9640 rtnl_unlock(); 9641 9642 return err; 9643 } 9644 9645 static int igb_resume(struct device *dev) 9646 { 9647 return __igb_resume(dev, false); 9648 } 9649 9650 static int igb_runtime_idle(struct device *dev) 9651 { 9652 struct net_device *netdev = dev_get_drvdata(dev); 9653 struct igb_adapter *adapter = netdev_priv(netdev); 9654 9655 if (!igb_has_link(adapter)) 9656 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 9657 9658 return -EBUSY; 9659 } 9660 9661 static int igb_runtime_suspend(struct device *dev) 9662 { 9663 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9664 } 9665 9666 static int igb_runtime_resume(struct device *dev) 9667 { 9668 return __igb_resume(dev, true); 9669 } 9670 9671 static void igb_shutdown(struct pci_dev *pdev) 9672 { 9673 bool wake; 9674 9675 __igb_shutdown(pdev, &wake, 0); 9676 9677 if (system_state == SYSTEM_POWER_OFF) { 9678 pci_wake_from_d3(pdev, wake); 9679 pci_set_power_state(pdev, PCI_D3hot); 9680 } 9681 } 9682 9683 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 9684 { 9685 #ifdef CONFIG_PCI_IOV 9686 int err; 9687 9688 if (num_vfs == 0) { 9689 return igb_disable_sriov(dev, true); 9690 } else { 9691 err = igb_enable_sriov(dev, num_vfs, true); 9692 return err ? err : num_vfs; 9693 } 9694 #endif 9695 return 0; 9696 } 9697 9698 /** 9699 * igb_io_error_detected - called when PCI error is detected 9700 * @pdev: Pointer to PCI device 9701 * @state: The current pci connection state 9702 * 9703 * This function is called after a PCI bus error affecting 9704 * this device has been detected. 9705 **/ 9706 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 9707 pci_channel_state_t state) 9708 { 9709 struct net_device *netdev = pci_get_drvdata(pdev); 9710 struct igb_adapter *adapter = netdev_priv(netdev); 9711 9712 if (state == pci_channel_io_normal) { 9713 dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); 9714 return PCI_ERS_RESULT_CAN_RECOVER; 9715 } 9716 9717 netif_device_detach(netdev); 9718 9719 if (state == pci_channel_io_perm_failure) 9720 return PCI_ERS_RESULT_DISCONNECT; 9721 9722 rtnl_lock(); 9723 if (netif_running(netdev)) 9724 igb_down(adapter); 9725 rtnl_unlock(); 9726 9727 pci_disable_device(pdev); 9728 9729 /* Request a slot reset. */ 9730 return PCI_ERS_RESULT_NEED_RESET; 9731 } 9732 9733 /** 9734 * igb_io_slot_reset - called after the pci bus has been reset. 9735 * @pdev: Pointer to PCI device 9736 * 9737 * Restart the card from scratch, as if from a cold-boot. Implementation 9738 * resembles the first-half of the __igb_resume routine. 9739 **/ 9740 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 9741 { 9742 struct net_device *netdev = pci_get_drvdata(pdev); 9743 struct igb_adapter *adapter = netdev_priv(netdev); 9744 struct e1000_hw *hw = &adapter->hw; 9745 pci_ers_result_t result; 9746 9747 if (pci_enable_device_mem(pdev)) { 9748 dev_err(&pdev->dev, 9749 "Cannot re-enable PCI device after reset.\n"); 9750 result = PCI_ERS_RESULT_DISCONNECT; 9751 } else { 9752 pci_set_master(pdev); 9753 pci_restore_state(pdev); 9754 9755 pci_enable_wake(pdev, PCI_D3hot, 0); 9756 pci_enable_wake(pdev, PCI_D3cold, 0); 9757 9758 /* In case of PCI error, adapter lose its HW address 9759 * so we should re-assign it here. 9760 */ 9761 hw->hw_addr = adapter->io_addr; 9762 9763 igb_reset(adapter); 9764 wr32(E1000_WUS, ~0); 9765 result = PCI_ERS_RESULT_RECOVERED; 9766 } 9767 9768 return result; 9769 } 9770 9771 /** 9772 * igb_io_resume - called when traffic can start flowing again. 9773 * @pdev: Pointer to PCI device 9774 * 9775 * This callback is called when the error recovery driver tells us that 9776 * its OK to resume normal operation. Implementation resembles the 9777 * second-half of the __igb_resume routine. 9778 */ 9779 static void igb_io_resume(struct pci_dev *pdev) 9780 { 9781 struct net_device *netdev = pci_get_drvdata(pdev); 9782 struct igb_adapter *adapter = netdev_priv(netdev); 9783 9784 rtnl_lock(); 9785 if (netif_running(netdev)) { 9786 if (!test_bit(__IGB_DOWN, &adapter->state)) { 9787 dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n"); 9788 rtnl_unlock(); 9789 return; 9790 } 9791 9792 if (igb_up(adapter)) { 9793 dev_err(&pdev->dev, "igb_up failed after reset\n"); 9794 rtnl_unlock(); 9795 return; 9796 } 9797 } 9798 rtnl_unlock(); 9799 9800 netif_device_attach(netdev); 9801 9802 /* let the f/w know that the h/w is now under the control of the 9803 * driver. 9804 */ 9805 igb_get_hw_control(adapter); 9806 } 9807 9808 /** 9809 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 9810 * @adapter: Pointer to adapter structure 9811 * @index: Index of the RAR entry which need to be synced with MAC table 9812 **/ 9813 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index) 9814 { 9815 struct e1000_hw *hw = &adapter->hw; 9816 u32 rar_low, rar_high; 9817 u8 *addr = adapter->mac_table[index].addr; 9818 9819 /* HW expects these to be in network order when they are plugged 9820 * into the registers which are little endian. In order to guarantee 9821 * that ordering we need to do an leXX_to_cpup here in order to be 9822 * ready for the byteswap that occurs with writel 9823 */ 9824 rar_low = le32_to_cpup((__le32 *)(addr)); 9825 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 9826 9827 /* Indicate to hardware the Address is Valid. */ 9828 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) { 9829 if (is_valid_ether_addr(addr)) 9830 rar_high |= E1000_RAH_AV; 9831 9832 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR) 9833 rar_high |= E1000_RAH_ASEL_SRC_ADDR; 9834 9835 switch (hw->mac.type) { 9836 case e1000_82575: 9837 case e1000_i210: 9838 if (adapter->mac_table[index].state & 9839 IGB_MAC_STATE_QUEUE_STEERING) 9840 rar_high |= E1000_RAH_QSEL_ENABLE; 9841 9842 rar_high |= E1000_RAH_POOL_1 * 9843 adapter->mac_table[index].queue; 9844 break; 9845 default: 9846 rar_high |= E1000_RAH_POOL_1 << 9847 adapter->mac_table[index].queue; 9848 break; 9849 } 9850 } 9851 9852 wr32(E1000_RAL(index), rar_low); 9853 wrfl(); 9854 wr32(E1000_RAH(index), rar_high); 9855 wrfl(); 9856 } 9857 9858 static int igb_set_vf_mac(struct igb_adapter *adapter, 9859 int vf, unsigned char *mac_addr) 9860 { 9861 struct e1000_hw *hw = &adapter->hw; 9862 /* VF MAC addresses start at end of receive addresses and moves 9863 * towards the first, as a result a collision should not be possible 9864 */ 9865 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 9866 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses; 9867 9868 ether_addr_copy(vf_mac_addr, mac_addr); 9869 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr); 9870 adapter->mac_table[rar_entry].queue = vf; 9871 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE; 9872 igb_rar_set_index(adapter, rar_entry); 9873 9874 return 0; 9875 } 9876 9877 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 9878 { 9879 struct igb_adapter *adapter = netdev_priv(netdev); 9880 9881 if (vf >= adapter->vfs_allocated_count) 9882 return -EINVAL; 9883 9884 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC 9885 * flag and allows to overwrite the MAC via VF netdev. This 9886 * is necessary to allow libvirt a way to restore the original 9887 * MAC after unbinding vfio-pci and reloading igbvf after shutting 9888 * down a VM. 9889 */ 9890 if (is_zero_ether_addr(mac)) { 9891 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC; 9892 dev_info(&adapter->pdev->dev, 9893 "remove administratively set MAC on VF %d\n", 9894 vf); 9895 } else if (is_valid_ether_addr(mac)) { 9896 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 9897 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", 9898 mac, vf); 9899 dev_info(&adapter->pdev->dev, 9900 "Reload the VF driver to make this change effective."); 9901 /* Generate additional warning if PF is down */ 9902 if (test_bit(__IGB_DOWN, &adapter->state)) { 9903 dev_warn(&adapter->pdev->dev, 9904 "The VF MAC address has been set, but the PF device is not up.\n"); 9905 dev_warn(&adapter->pdev->dev, 9906 "Bring the PF device up before attempting to use the VF device.\n"); 9907 } 9908 } else { 9909 return -EINVAL; 9910 } 9911 return igb_set_vf_mac(adapter, vf, mac); 9912 } 9913 9914 static int igb_link_mbps(int internal_link_speed) 9915 { 9916 switch (internal_link_speed) { 9917 case SPEED_100: 9918 return 100; 9919 case SPEED_1000: 9920 return 1000; 9921 default: 9922 return 0; 9923 } 9924 } 9925 9926 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 9927 int link_speed) 9928 { 9929 int rf_dec, rf_int; 9930 u32 bcnrc_val; 9931 9932 if (tx_rate != 0) { 9933 /* Calculate the rate factor values to set */ 9934 rf_int = link_speed / tx_rate; 9935 rf_dec = (link_speed - (rf_int * tx_rate)); 9936 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) / 9937 tx_rate; 9938 9939 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 9940 bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int); 9941 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 9942 } else { 9943 bcnrc_val = 0; 9944 } 9945 9946 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 9947 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 9948 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 9949 */ 9950 wr32(E1000_RTTBCNRM, 0x14); 9951 wr32(E1000_RTTBCNRC, bcnrc_val); 9952 } 9953 9954 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 9955 { 9956 int actual_link_speed, i; 9957 bool reset_rate = false; 9958 9959 /* VF TX rate limit was not set or not supported */ 9960 if ((adapter->vf_rate_link_speed == 0) || 9961 (adapter->hw.mac.type != e1000_82576)) 9962 return; 9963 9964 actual_link_speed = igb_link_mbps(adapter->link_speed); 9965 if (actual_link_speed != adapter->vf_rate_link_speed) { 9966 reset_rate = true; 9967 adapter->vf_rate_link_speed = 0; 9968 dev_info(&adapter->pdev->dev, 9969 "Link speed has been changed. VF Transmit rate is disabled\n"); 9970 } 9971 9972 for (i = 0; i < adapter->vfs_allocated_count; i++) { 9973 if (reset_rate) 9974 adapter->vf_data[i].tx_rate = 0; 9975 9976 igb_set_vf_rate_limit(&adapter->hw, i, 9977 adapter->vf_data[i].tx_rate, 9978 actual_link_speed); 9979 } 9980 } 9981 9982 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, 9983 int min_tx_rate, int max_tx_rate) 9984 { 9985 struct igb_adapter *adapter = netdev_priv(netdev); 9986 struct e1000_hw *hw = &adapter->hw; 9987 int actual_link_speed; 9988 9989 if (hw->mac.type != e1000_82576) 9990 return -EOPNOTSUPP; 9991 9992 if (min_tx_rate) 9993 return -EINVAL; 9994 9995 actual_link_speed = igb_link_mbps(adapter->link_speed); 9996 if ((vf >= adapter->vfs_allocated_count) || 9997 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 9998 (max_tx_rate < 0) || 9999 (max_tx_rate > actual_link_speed)) 10000 return -EINVAL; 10001 10002 adapter->vf_rate_link_speed = actual_link_speed; 10003 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; 10004 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); 10005 10006 return 0; 10007 } 10008 10009 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 10010 bool setting) 10011 { 10012 struct igb_adapter *adapter = netdev_priv(netdev); 10013 struct e1000_hw *hw = &adapter->hw; 10014 u32 reg_val, reg_offset; 10015 10016 if (!adapter->vfs_allocated_count) 10017 return -EOPNOTSUPP; 10018 10019 if (vf >= adapter->vfs_allocated_count) 10020 return -EINVAL; 10021 10022 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 10023 reg_val = rd32(reg_offset); 10024 if (setting) 10025 reg_val |= (BIT(vf) | 10026 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10027 else 10028 reg_val &= ~(BIT(vf) | 10029 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 10030 wr32(reg_offset, reg_val); 10031 10032 adapter->vf_data[vf].spoofchk_enabled = setting; 10033 return 0; 10034 } 10035 10036 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting) 10037 { 10038 struct igb_adapter *adapter = netdev_priv(netdev); 10039 10040 if (vf >= adapter->vfs_allocated_count) 10041 return -EINVAL; 10042 if (adapter->vf_data[vf].trusted == setting) 10043 return 0; 10044 10045 adapter->vf_data[vf].trusted = setting; 10046 10047 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n", 10048 vf, setting ? "" : "not "); 10049 return 0; 10050 } 10051 10052 static int igb_ndo_get_vf_config(struct net_device *netdev, 10053 int vf, struct ifla_vf_info *ivi) 10054 { 10055 struct igb_adapter *adapter = netdev_priv(netdev); 10056 if (vf >= adapter->vfs_allocated_count) 10057 return -EINVAL; 10058 ivi->vf = vf; 10059 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 10060 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; 10061 ivi->min_tx_rate = 0; 10062 ivi->vlan = adapter->vf_data[vf].pf_vlan; 10063 ivi->qos = adapter->vf_data[vf].pf_qos; 10064 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 10065 ivi->trusted = adapter->vf_data[vf].trusted; 10066 return 0; 10067 } 10068 10069 static void igb_vmm_control(struct igb_adapter *adapter) 10070 { 10071 struct e1000_hw *hw = &adapter->hw; 10072 u32 reg; 10073 10074 switch (hw->mac.type) { 10075 case e1000_82575: 10076 case e1000_i210: 10077 case e1000_i211: 10078 case e1000_i354: 10079 default: 10080 /* replication is not supported for 82575 */ 10081 return; 10082 case e1000_82576: 10083 /* notify HW that the MAC is adding vlan tags */ 10084 reg = rd32(E1000_DTXCTL); 10085 reg |= E1000_DTXCTL_VLAN_ADDED; 10086 wr32(E1000_DTXCTL, reg); 10087 fallthrough; 10088 case e1000_82580: 10089 /* enable replication vlan tag stripping */ 10090 reg = rd32(E1000_RPLOLR); 10091 reg |= E1000_RPLOLR_STRVLAN; 10092 wr32(E1000_RPLOLR, reg); 10093 fallthrough; 10094 case e1000_i350: 10095 /* none of the above registers are supported by i350 */ 10096 break; 10097 } 10098 10099 if (adapter->vfs_allocated_count) { 10100 igb_vmdq_set_loopback_pf(hw, true); 10101 igb_vmdq_set_replication_pf(hw, true); 10102 igb_vmdq_set_anti_spoofing_pf(hw, true, 10103 adapter->vfs_allocated_count); 10104 } else { 10105 igb_vmdq_set_loopback_pf(hw, false); 10106 igb_vmdq_set_replication_pf(hw, false); 10107 } 10108 } 10109 10110 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 10111 { 10112 struct e1000_hw *hw = &adapter->hw; 10113 u32 dmac_thr; 10114 u16 hwm; 10115 u32 reg; 10116 10117 if (hw->mac.type > e1000_82580) { 10118 if (adapter->flags & IGB_FLAG_DMAC) { 10119 /* force threshold to 0. */ 10120 wr32(E1000_DMCTXTH, 0); 10121 10122 /* DMA Coalescing high water mark needs to be greater 10123 * than the Rx threshold. Set hwm to PBA - max frame 10124 * size in 16B units, capping it at PBA - 6KB. 10125 */ 10126 hwm = 64 * (pba - 6); 10127 reg = rd32(E1000_FCRTC); 10128 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 10129 reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm); 10130 wr32(E1000_FCRTC, reg); 10131 10132 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 10133 * frame size, capping it at PBA - 10KB. 10134 */ 10135 dmac_thr = pba - 10; 10136 reg = rd32(E1000_DMACR); 10137 reg &= ~E1000_DMACR_DMACTHR_MASK; 10138 reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr); 10139 10140 /* transition to L0x or L1 if available..*/ 10141 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 10142 10143 /* watchdog timer= +-1000 usec in 32usec intervals */ 10144 reg |= (1000 >> 5); 10145 10146 /* Disable BMC-to-OS Watchdog Enable */ 10147 if (hw->mac.type != e1000_i354) 10148 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 10149 wr32(E1000_DMACR, reg); 10150 10151 /* no lower threshold to disable 10152 * coalescing(smart fifb)-UTRESH=0 10153 */ 10154 wr32(E1000_DMCRTRH, 0); 10155 10156 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 10157 10158 wr32(E1000_DMCTLX, reg); 10159 10160 /* free space in tx packet buffer to wake from 10161 * DMA coal 10162 */ 10163 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 10164 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 10165 } 10166 10167 if (hw->mac.type >= e1000_i210 || 10168 (adapter->flags & IGB_FLAG_DMAC)) { 10169 reg = rd32(E1000_PCIEMISC); 10170 reg |= E1000_PCIEMISC_LX_DECISION; 10171 wr32(E1000_PCIEMISC, reg); 10172 } /* endif adapter->dmac is not disabled */ 10173 } else if (hw->mac.type == e1000_82580) { 10174 u32 reg = rd32(E1000_PCIEMISC); 10175 10176 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 10177 wr32(E1000_DMACR, 0); 10178 } 10179 } 10180 10181 /** 10182 * igb_read_i2c_byte - Reads 8 bit word over I2C 10183 * @hw: pointer to hardware structure 10184 * @byte_offset: byte offset to read 10185 * @dev_addr: device address 10186 * @data: value read 10187 * 10188 * Performs byte read operation over I2C interface at 10189 * a specified device address. 10190 **/ 10191 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10192 u8 dev_addr, u8 *data) 10193 { 10194 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10195 struct i2c_client *this_client = adapter->i2c_client; 10196 s32 status; 10197 u16 swfw_mask = 0; 10198 10199 if (!this_client) 10200 return E1000_ERR_I2C; 10201 10202 swfw_mask = E1000_SWFW_PHY0_SM; 10203 10204 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10205 return E1000_ERR_SWFW_SYNC; 10206 10207 status = i2c_smbus_read_byte_data(this_client, byte_offset); 10208 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10209 10210 if (status < 0) 10211 return E1000_ERR_I2C; 10212 else { 10213 *data = status; 10214 return 0; 10215 } 10216 } 10217 10218 /** 10219 * igb_write_i2c_byte - Writes 8 bit word over I2C 10220 * @hw: pointer to hardware structure 10221 * @byte_offset: byte offset to write 10222 * @dev_addr: device address 10223 * @data: value to write 10224 * 10225 * Performs byte write operation over I2C interface at 10226 * a specified device address. 10227 **/ 10228 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 10229 u8 dev_addr, u8 data) 10230 { 10231 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 10232 struct i2c_client *this_client = adapter->i2c_client; 10233 s32 status; 10234 u16 swfw_mask = E1000_SWFW_PHY0_SM; 10235 10236 if (!this_client) 10237 return E1000_ERR_I2C; 10238 10239 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 10240 return E1000_ERR_SWFW_SYNC; 10241 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 10242 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 10243 10244 if (status) 10245 return E1000_ERR_I2C; 10246 else 10247 return 0; 10248 10249 } 10250 10251 int igb_reinit_queues(struct igb_adapter *adapter) 10252 { 10253 struct net_device *netdev = adapter->netdev; 10254 struct pci_dev *pdev = adapter->pdev; 10255 int err = 0; 10256 10257 if (netif_running(netdev)) 10258 igb_close(netdev); 10259 10260 igb_reset_interrupt_capability(adapter); 10261 10262 if (igb_init_interrupt_scheme(adapter, true)) { 10263 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 10264 return -ENOMEM; 10265 } 10266 10267 if (netif_running(netdev)) 10268 err = igb_open(netdev); 10269 10270 return err; 10271 } 10272 10273 static void igb_nfc_filter_exit(struct igb_adapter *adapter) 10274 { 10275 struct igb_nfc_filter *rule; 10276 10277 spin_lock(&adapter->nfc_lock); 10278 10279 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10280 igb_erase_filter(adapter, rule); 10281 10282 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 10283 igb_erase_filter(adapter, rule); 10284 10285 spin_unlock(&adapter->nfc_lock); 10286 } 10287 10288 static void igb_nfc_filter_restore(struct igb_adapter *adapter) 10289 { 10290 struct igb_nfc_filter *rule; 10291 10292 spin_lock(&adapter->nfc_lock); 10293 10294 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 10295 igb_add_filter(adapter, rule); 10296 10297 spin_unlock(&adapter->nfc_lock); 10298 } 10299 10300 static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10301 igb_runtime_suspend, igb_runtime_resume, 10302 igb_runtime_idle); 10303 10304 static struct pci_driver igb_driver = { 10305 .name = igb_driver_name, 10306 .id_table = igb_pci_tbl, 10307 .probe = igb_probe, 10308 .remove = igb_remove, 10309 .driver.pm = pm_ptr(&igb_pm_ops), 10310 .shutdown = igb_shutdown, 10311 .sriov_configure = igb_pci_sriov_configure, 10312 .err_handler = &igb_err_handler 10313 }; 10314 10315 /* igb_main.c */ 10316