1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * link_encoder.h 25 * 26 * Created on: Oct 6, 2015 27 * Author: yonsun 28 */ 29 30 #ifndef LINK_ENCODER_H_ 31 #define LINK_ENCODER_H_ 32 33 #include "grph_object_defs.h" 34 #include "signal_types.h" 35 #include "dc_types.h" 36 37 struct dc_context; 38 struct encoder_set_dp_phy_pattern_param; 39 struct link_mst_stream_allocation_table; 40 struct dc_link_settings; 41 struct link_training_settings; 42 struct pipe_ctx; 43 44 struct encoder_init_data { 45 enum channel_id channel; 46 struct graphics_object_id connector; 47 struct gpio *hpd_gpio; 48 enum hpd_source_id hpd_source; 49 /* TODO: in DAL2, here was pointer to EventManagerInterface */ 50 struct graphics_object_id encoder; 51 struct graphics_object_id analog_encoder; 52 enum engine_id analog_engine; 53 struct dc_context *ctx; 54 enum transmitter transmitter; 55 }; 56 57 struct encoder_feature_support { 58 union { 59 struct { 60 uint32_t IS_HBR2_CAPABLE:1; 61 uint32_t IS_HBR3_CAPABLE:1; 62 uint32_t IS_TPS3_CAPABLE:1; 63 uint32_t IS_TPS4_CAPABLE:1; 64 uint32_t HDMI_6GB_EN:1; 65 uint32_t IS_DP2_CAPABLE:1; 66 uint32_t IS_UHBR10_CAPABLE:1; 67 uint32_t IS_UHBR13_5_CAPABLE:1; 68 uint32_t IS_UHBR20_CAPABLE:1; 69 uint32_t DP_IS_USB_C:1; 70 uint32_t IS_HDMI_FRL_CAPABLE:1; 71 uint32_t IS_FRL_8G_CAPABLE:1; 72 uint32_t IS_FRL_10G_CAPABLE:1; 73 uint32_t IS_FRL_12G_CAPABLE:1; 74 uint32_t IS_FRL_16G_CAPABLE:1; 75 uint32_t IS_FRL_20G_CAPABLE:1; 76 uint32_t IS_FRL_24G_CAPABLE:1; 77 } bits; 78 uint32_t raw; 79 } flags; 80 81 enum dc_color_depth max_hdmi_deep_color; 82 unsigned int max_hdmi_pixel_clock; 83 bool hdmi_ycbcr420_supported; 84 bool dp_ycbcr420_supported; 85 bool fec_supported; 86 }; 87 88 enum phy_source_select { 89 PHY_SOURCE_DIG, 90 PHY_SOURCE_HPO 91 }; 92 93 struct link_encoder { 94 const struct link_encoder_funcs *funcs; 95 int32_t aux_channel_offset; 96 struct dc_context *ctx; 97 struct graphics_object_id id; 98 struct graphics_object_id analog_id; 99 struct graphics_object_id connector; 100 uint32_t output_signals; 101 enum engine_id preferred_engine; 102 enum engine_id analog_engine; 103 struct encoder_feature_support features; 104 enum transmitter transmitter; 105 struct gpio *hpd_gpio; 106 enum hpd_source_id hpd_source; 107 bool usbc_combo_phy; 108 uint8_t txffe_state; 109 }; 110 111 struct link_enc_state { 112 113 uint32_t dphy_fec_en; 114 uint32_t dphy_fec_ready_shadow; 115 uint32_t dphy_fec_active_status; 116 uint32_t dp_link_training_complete; 117 118 }; 119 120 struct frl_txffe { 121 uint32_t amplitude[4]; 122 uint32_t pre_emphasis[4]; 123 uint32_t post_emphasis[4]; 124 }; 125 126 enum encoder_type_select { 127 ENCODER_TYPE_DIG = 0, 128 ENCODER_TYPE_HDMI_FRL = 1, 129 ENCODER_TYPE_DP_128B132B = 2 130 }; 131 132 struct link_encoder_funcs { 133 void (*read_state)( 134 struct link_encoder *enc, struct link_enc_state *s); 135 bool (*validate_output_with_stream)( 136 struct link_encoder *enc, const struct dc_stream_state *stream); 137 void (*hw_init)(struct link_encoder *enc); 138 void (*setup)(struct link_encoder *enc, 139 enum signal_type signal); 140 void (*enable_tmds_output)(struct link_encoder *enc, 141 enum clock_source_id clock_source, 142 enum dc_color_depth color_depth, 143 enum signal_type signal, 144 uint32_t pixel_clock); 145 void (*enable_dp_output)(struct link_encoder *enc, 146 const struct dc_link_settings *link_settings, 147 enum clock_source_id clock_source); 148 void (*enable_dp_mst_output)(struct link_encoder *enc, 149 const struct dc_link_settings *link_settings, 150 enum clock_source_id clock_source); 151 void (*enable_lvds_output)(struct link_encoder *enc, 152 enum clock_source_id clock_source, 153 uint32_t pixel_clock); 154 void (*enable_analog_output)(struct link_encoder *enc, 155 uint32_t pixel_clock); 156 void (*disable_output)(struct link_encoder *link_enc, 157 enum signal_type signal); 158 void (*dp_set_lane_settings)(struct link_encoder *enc, 159 const struct dc_link_settings *link_settings, 160 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 161 void (*dp_set_phy_pattern)(struct link_encoder *enc, 162 const struct encoder_set_dp_phy_pattern_param *para); 163 void (*update_mst_stream_allocation_table)( 164 struct link_encoder *enc, 165 const struct link_mst_stream_allocation_table *table); 166 void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc, 167 bool exit_link_training_required); 168 void (*psr_program_secondary_packet)(struct link_encoder *enc, 169 unsigned int sdp_transmit_line_num_deadline); 170 void (*connect_dig_be_to_fe)(struct link_encoder *enc, 171 enum engine_id engine, 172 bool connect); 173 void (*enable_hpd)(struct link_encoder *enc); 174 void (*disable_hpd)(struct link_encoder *enc); 175 bool (*is_dig_enabled)(struct link_encoder *enc); 176 unsigned int (*get_dig_frontend)(struct link_encoder *enc); 177 void (*destroy)(struct link_encoder **enc); 178 179 void (*fec_set_enable)(struct link_encoder *enc, 180 bool enable); 181 182 void (*fec_set_ready)(struct link_encoder *enc, 183 bool ready); 184 185 bool (*fec_is_active)(struct link_encoder *enc); 186 bool (*is_in_alt_mode) (struct link_encoder *enc); 187 188 void (*get_max_link_cap)(struct link_encoder *enc, 189 struct dc_link_settings *link_settings); 190 191 enum signal_type (*get_dig_mode)( 192 struct link_encoder *enc); 193 194 void (*dpcstx_set_order_invert_18_bit)( 195 struct link_encoder *enc, 196 bool invert); 197 198 void (*set_phy_source)( 199 struct link_encoder *enc, 200 enum phy_source_select src_sel, 201 uint32_t hpo_inst); 202 203 void (*dpcs_initialize_phy)( 204 struct link_encoder *enc, 205 uint32_t hpo_inst, 206 enum hdmi_frl_link_rate frl_link_rate); 207 208 void (*dpcs_configure_phypll)( 209 struct link_encoder *enc, 210 uint32_t hpo_inst, 211 enum hdmi_frl_link_rate frl_link_rate); 212 213 void (*dpcs_configure_dpcs)( 214 struct link_encoder *enc); 215 216 void (*dpcs_enable_dpcs)( 217 struct link_encoder *enc); 218 void (*prog_eq_setting)( 219 struct link_encoder *enc, 220 uint8_t FFE_Level, 221 bool de_emphasis_only, 222 bool pre_shoot_only, 223 bool no_ffe, 224 const struct dc_hdmi_frl_link_settings *link_settings); 225 void (*get_txffe)( 226 struct link_encoder *enc, 227 struct frl_txffe *lane_settings); 228 void (*set_txffe)( 229 struct link_encoder *enc, 230 struct frl_txffe *lane_settings); 231 void (*set_dio_phy_mux)( 232 struct link_encoder *enc, 233 enum encoder_type_select sel, 234 uint32_t hpo_inst); 235 void (*enable_dpia_output)(struct link_encoder *enc, 236 const struct dc_link_settings *link_settings, 237 uint8_t dpia_id, 238 uint8_t digmode, 239 uint8_t fec_rdy); 240 void (*disable_dpia_output)(struct link_encoder *link_enc, 241 uint8_t dpia_id, 242 uint8_t digmode); 243 bool (*get_hpd_state)(struct link_encoder *enc); 244 bool (*program_hpd_filter)(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); 245 }; 246 247 /* 248 * Used to track assignments of links (display endpoints) to link encoders. 249 * 250 * Entry in link_enc_assignments table in struct resource_context. 251 * Entries only marked valid once encoder assigned to a link and invalidated once unassigned. 252 * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint. 253 */ 254 struct link_enc_assignment { 255 bool valid; 256 struct display_endpoint_id ep_id; 257 enum engine_id eng_id; 258 struct dc_stream_state *stream; 259 }; 260 261 enum link_enc_cfg_mode { 262 LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */ 263 LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */ 264 }; 265 266 struct hpo_frl_link_encoder { 267 const struct hpo_frl_link_encoder_funcs *funcs; 268 struct dc_context *ctx; 269 int inst; 270 }; 271 272 /** 273 * @hpo_frl_link_enc_state - FRL data from the device 274 * 275 * This struct is used to store FRL information retrieved from the hardware. 276 * This is used as a parameter for the read_state function. 277 */ 278 struct hpo_frl_link_enc_state { 279 /** 280 * @link_enc_enabled: 0 means disable and 1 enabled. 281 */ 282 uint32_t link_enc_enabled; 283 284 /** 285 * @link_active: 286 * 287 * If link training is enable this field should be set to 1. 288 */ 289 uint32_t link_active; 290 291 /** 292 * @lane_count: FRL lane count. 293 */ 294 uint32_t lane_count; 295 }; 296 297 /*** 298 * @hpo_frl_link_encoder_funcs - FRL encoder functions 299 * 300 * DC handles FRL as an encoder; each ASIC may have some peculiarities in 301 * setting FRL. Thus, this struct, adds all the necessary callbacks that each 302 * DCN version must implement. 303 */ 304 struct hpo_frl_link_encoder_funcs { 305 /** 306 * @setup_link_encoder: 307 * 308 * This function is responsible for setup the ASIC to use FRL, i.e., it 309 * contains a register configuration. This function implementation 310 * expects the enablement of the link clock, lane count configuration, 311 * any reset/cleanup, and, finally, the enablement of the link. 312 */ 313 void (*setup_link_encoder)(struct hpo_frl_link_encoder *enc, 314 int lane_count); 315 316 /** 317 * @disable_link_encoder: 318 * 319 * Disable the FRL link. Note that this function must do the reverse of 320 * the setup_link_encoder. 321 */ 322 void (*disable_link_encoder)(struct hpo_frl_link_encoder *enc); 323 324 /** 325 * @set_hdmi_training_pattern: 326 * 327 * Register level configuration for each lane. 328 */ 329 void (*set_hdmi_training_pattern)(struct hpo_frl_link_encoder *enc, 330 uint32_t lane0_pattern, 331 uint32_t lane1_pattern, 332 uint32_t lane2_pattern, 333 uint32_t lane3_pattern); 334 335 /** 336 * @get_hdmi_training_pattern: 337 * 338 * Retrieve from the registers each of the lane pattern configurations. 339 */ 340 void (*get_hdmi_training_pattern)(struct hpo_frl_link_encoder *enc, 341 uint32_t *lane0_pattern, 342 uint32_t *lane1_pattern, 343 uint32_t *lane2_pattern, 344 uint32_t *lane3_pattern); 345 346 /** 347 * @enable_frl_phy_output: 348 * 349 * Based on the parameters, this function should fill out the 350 * bp_transmitter_control struct and use it to enable the FRL PHY link 351 * via VBIOS. 352 */ 353 void (*enable_frl_phy_output)(struct hpo_frl_link_encoder *hpo_enc, 354 struct link_encoder *enc, 355 enum clock_source_id clock_source, 356 enum hdmi_frl_link_rate frl_link_rate); 357 358 /** 359 * @enable_output: 360 * 361 * Enable FRL by sending the enable packet training. 362 */ 363 void (*enable_output)(struct hpo_frl_link_encoder *enc); 364 365 /** 366 * @read_state: 367 * 368 * Get the FRL information from registers and fill it out in the 369 * hpo_frl_link_enc_state struct. 370 */ 371 void (*read_state)(struct hpo_frl_link_encoder *enc, 372 struct hpo_frl_link_enc_state *state); 373 374 /** 375 * @destroy: 376 * 377 * Destroy encoder object. 378 */ 379 void (*destroy)(struct hpo_frl_link_encoder **enc); 380 381 void (*apply_vsdb_rcc_wa)( 382 struct hpo_frl_link_encoder *enc); 383 384 }; 385 386 enum dp2_link_mode { 387 DP2_LINK_TRAINING_TPS1, 388 DP2_LINK_TRAINING_TPS2, 389 DP2_LINK_ACTIVE, 390 DP2_TEST_PATTERN 391 }; 392 393 enum dp2_phy_tp_select { 394 DP_DPHY_TP_SELECT_TPS1, 395 DP_DPHY_TP_SELECT_TPS2, 396 DP_DPHY_TP_SELECT_PRBS, 397 DP_DPHY_TP_SELECT_CUSTOM, 398 DP_DPHY_TP_SELECT_SQUARE 399 }; 400 401 enum dp2_phy_tp_prbs { 402 DP_DPHY_TP_PRBS7, 403 DP_DPHY_TP_PRBS9, 404 DP_DPHY_TP_PRBS11, 405 DP_DPHY_TP_PRBS15, 406 DP_DPHY_TP_PRBS23, 407 DP_DPHY_TP_PRBS31 408 }; 409 410 struct hpo_dp_link_enc_state { 411 uint32_t link_enc_enabled; 412 uint32_t link_mode; 413 uint32_t lane_count; 414 uint32_t slot_count[4]; 415 uint32_t stream_src[4]; 416 uint32_t vc_rate_x[4]; 417 uint32_t vc_rate_y[4]; 418 }; 419 420 struct hpo_dp_link_encoder { 421 const struct hpo_dp_link_encoder_funcs *funcs; 422 struct dc_context *ctx; 423 int inst; 424 enum engine_id preferred_engine; 425 enum transmitter transmitter; 426 enum hpd_source_id hpd_source; 427 }; 428 429 struct hpo_dp_link_encoder_funcs { 430 431 void (*enable_link_phy)(struct hpo_dp_link_encoder *enc, 432 const struct dc_link_settings *link_settings, 433 enum transmitter transmitter, 434 enum hpd_source_id hpd_source); 435 436 void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc, 437 enum signal_type signal); 438 439 void (*link_enable)( 440 struct hpo_dp_link_encoder *enc, 441 enum dc_lane_count num_lanes); 442 443 void (*link_disable)( 444 struct hpo_dp_link_encoder *enc); 445 446 void (*set_link_test_pattern)( 447 struct hpo_dp_link_encoder *enc, 448 struct encoder_set_dp_phy_pattern_param *tp_params); 449 450 void (*update_stream_allocation_table)( 451 struct hpo_dp_link_encoder *enc, 452 const struct link_mst_stream_allocation_table *table); 453 454 void (*set_throttled_vcp_size)( 455 struct hpo_dp_link_encoder *enc, 456 uint32_t stream_encoder_inst, 457 struct fixed31_32 avg_time_slots_per_mtp); 458 459 bool (*is_in_alt_mode) ( 460 struct hpo_dp_link_encoder *enc); 461 462 void (*read_state)( 463 struct hpo_dp_link_encoder *enc, 464 struct hpo_dp_link_enc_state *state); 465 466 void (*set_ffe)( 467 struct hpo_dp_link_encoder *enc, 468 const struct dc_link_settings *link_settings, 469 uint8_t ffe_preset); 470 }; 471 472 #endif /* LINK_ENCODER_H_ */ 473