1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/console.h>
23 #include <linux/cpufreq.h>
24 #include <linux/ctype.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/ioport.h>
34 #include <linux/ktime.h>
35 #include <linux/major.h>
36 #include <linux/minmax.h>
37 #include <linux/mm.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/platform_device.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/reset.h>
43 #include <linux/scatterlist.h>
44 #include <linux/serial.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/platform_early.h>
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "rsci.h"
61 #include "serial_mctrl_gpio.h"
62 #include "sh-sci-common.h"
63
64 #define SCI_MAJOR 204
65 #define SCI_MINOR_START 8
66
67 /*
68 * SCI register subset common for all port types.
69 * Not all registers will exist on all parts.
70 */
71 enum {
72 SCSMR, /* Serial Mode Register */
73 SCBRR, /* Bit Rate Register */
74 SCSCR, /* Serial Control Register */
75 SCxSR, /* Serial Status Register */
76 SCFCR, /* FIFO Control Register */
77 SCFDR, /* FIFO Data Count Register */
78 SCxTDR, /* Transmit (FIFO) Data Register */
79 SCxRDR, /* Receive (FIFO) Data Register */
80 SCLSR, /* Line Status Register */
81 SCTFDR, /* Transmit FIFO Data Count Register */
82 SCRFDR, /* Receive FIFO Data Count Register */
83 SCSPTR, /* Serial Port Register */
84 HSSRR, /* Sampling Rate Register */
85 SCPCR, /* Serial Port Control Register */
86 SCPDR, /* Serial Port Data Register */
87 SCDL, /* BRG Frequency Division Register */
88 SCCKS, /* BRG Clock Select Register */
89 HSRTRGR, /* Rx FIFO Data Count Trigger Register */
90 HSTTRGR, /* Tx FIFO Data Count Trigger Register */
91 SEMR, /* Serial extended mode register */
92 };
93
94 /* SCSMR (Serial Mode Register) */
95 #define SCSMR_C_A BIT(7) /* Communication Mode */
96 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
97 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
98 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
99 #define SCSMR_PE BIT(5) /* Parity Enable */
100 #define SCSMR_ODD BIT(4) /* Odd Parity */
101 #define SCSMR_STOP BIT(3) /* Stop Bit Length */
102 #define SCSMR_CKS 0x0003 /* Clock Select */
103
104 /* Serial Mode Register, SCIFA/SCIFB only bits */
105 #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
106 #define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
107 #define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
108 #define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
109 #define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
110 #define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
111 #define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
112 #define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
113 #define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
114 #define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
115
116 /* Serial Control Register, SCI only bits */
117 #define SCSCR_TEIE BIT(2) /* Transmit End Interrupt Enable */
118
119 /* Serial Control Register, SCIFA/SCIFB only bits */
120 #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
121 #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
122
123 /* Serial Control Register, HSCIF-only bits */
124 #define HSSCR_TOT_SHIFT 14
125
126 /* SCxSR (Serial Status Register) on SCI */
127 #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
128 #define SCI_RDRF BIT(6) /* Receive Data Register Full */
129 #define SCI_ORER BIT(5) /* Overrun Error */
130 #define SCI_FER BIT(4) /* Framing Error */
131 #define SCI_PER BIT(3) /* Parity Error */
132 #define SCI_TEND BIT(2) /* Transmit End */
133 #define SCI_RESERVED 0x03 /* All reserved bits */
134
135 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
136
137 #define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF))
138 #define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
139 #define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
140 #define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
141
142 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
143 #define SCIF_ER BIT(7) /* Receive Error */
144 #define SCIF_TEND BIT(6) /* Transmission End */
145 #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
146 #define SCIF_BRK BIT(4) /* Break Detect */
147 #define SCIF_FER BIT(3) /* Framing Error */
148 #define SCIF_PER BIT(2) /* Parity Error */
149 #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
150 #define SCIF_DR BIT(0) /* Receive Data Ready */
151 /* SCIF only (optional) */
152 #define SCIF_PERC 0xf000 /* Number of Parity Errors */
153 #define SCIF_FERC 0x0f00 /* Number of Framing Errors */
154 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
155 #define SCIFA_ORER BIT(9) /* Overrun Error */
156
157 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
158
159 #define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF))
160 #define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
161 #define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE))
162 #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
163
164 /* SCFCR (FIFO Control Register) */
165 #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */
166 #define SCFCR_RTRG0 BIT(6)
167 #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */
168 #define SCFCR_TTRG0 BIT(4)
169 #define SCFCR_MCE BIT(3) /* Modem Control Enable */
170 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
171 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
172 #define SCFCR_LOOP BIT(0) /* Loopback Test */
173
174 /* SCLSR (Line Status Register) on (H)SCIF */
175 #define SCLSR_TO BIT(2) /* Timeout */
176 #define SCLSR_ORER BIT(0) /* Overrun Error */
177
178 /* SCSPTR (Serial Port Register), optional */
179 #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */
180 #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */
181 #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */
182 #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */
183 #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
184 #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
185 #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
186 #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
187
188 /* HSSRR HSCIF */
189 #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
190 #define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */
191
192 #define HSCIF_SRHP_SHIFT 8
193 #define HSCIF_SRHP_MASK 0x0f00
194
195 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
196 #define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */
197 #define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */
198 #define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */
199 #define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */
200 #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */
201
202 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
203 #define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */
204 #define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */
205 #define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */
206 #define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */
207 #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */
208
209 /*
210 * BRG Clock Select Register (Some SCIF and HSCIF)
211 * The Baud Rate Generator for external clock can provide a clock source for
212 * the sampling clock. It outputs either its frequency divided clock, or the
213 * (undivided) (H)SCK external clock.
214 */
215 #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
216 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
217
218 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
219 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
220 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
221 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
222 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
223 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
224
225 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
226
227 #define SCxSR_RDxF_CLEAR(port) \
228 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
229 #define SCxSR_ERROR_CLEAR(port) \
230 (to_sci_port(port)->params->error_clear)
231 #define SCxSR_TDxE_CLEAR(port) \
232 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
233 #define SCxSR_BREAK_CLEAR(port) \
234 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
235
236 #define SCIx_IRQ_IS_MUXED(port) \
237 ((port)->irqs[SCIx_ERI_IRQ] == \
238 (port)->irqs[SCIx_RXI_IRQ]) || \
239 ((port)->irqs[SCIx_ERI_IRQ] && \
240 ((port)->irqs[SCIx_RXI_IRQ] < 0))
241
242 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
243 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
244 SCI_SR(19) | SCI_SR(27)
245
246 /* Iterate over all supported sampling rates, from high to low */
247 #define for_each_sr(_sr, _port) \
248 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
249 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
250
251 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
252
253 #define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port))
254
255 static struct sci_port sci_ports[SCI_NPORTS];
256 static unsigned long sci_ports_in_use;
257 static struct uart_driver sci_uart_driver;
258 static bool sci_uart_earlycon;
259 static bool sci_uart_earlycon_dev_probing;
260
261 static const struct sci_port_params_bits sci_sci_port_params_bits = {
262 .rxtx_enable = SCSCR_RE | SCSCR_TE,
263 .te_clear = SCSCR_TE | SCSCR_TEIE,
264 .poll_sent_bits = SCI_TDRE | SCI_TEND
265 };
266
267 static const struct sci_port_params_bits sci_scif_port_params_bits = {
268 .rxtx_enable = SCSCR_RE | SCSCR_TE,
269 .te_clear = SCSCR_TE | SCSCR_TEIE,
270 .poll_sent_bits = SCIF_TDFE | SCIF_TEND
271 };
272
273 static const struct sci_common_regs sci_common_regs = {
274 .status = SCxSR,
275 .control = SCSCR,
276 };
277
278 struct sci_suspend_regs {
279 u16 scdl;
280 u16 sccks;
281 u16 scsmr;
282 u16 scscr;
283 u16 scfcr;
284 u16 scsptr;
285 u16 hssrr;
286 u16 scpcr;
287 u16 scpdr;
288 u8 scbrr;
289 u8 semr;
290 };
291
sci_suspend_regs_size(void)292 static size_t sci_suspend_regs_size(void)
293 {
294 return sizeof(struct sci_suspend_regs);
295 }
296
297 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
298 /*
299 * Common SCI definitions, dependent on the port's regshift
300 * value.
301 */
302 [SCIx_SCI_REGTYPE] = {
303 .regs = {
304 [SCSMR] = { 0x00, 8 },
305 [SCBRR] = { 0x01, 8 },
306 [SCSCR] = { 0x02, 8 },
307 [SCxTDR] = { 0x03, 8 },
308 [SCxSR] = { 0x04, 8 },
309 [SCxRDR] = { 0x05, 8 },
310 },
311 .fifosize = 1,
312 .overrun_reg = SCxSR,
313 .overrun_mask = SCI_ORER,
314 .sampling_rate_mask = SCI_SR(32),
315 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
316 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
317 .param_bits = &sci_sci_port_params_bits,
318 .common_regs = &sci_common_regs,
319 },
320
321 /*
322 * Common definitions for legacy IrDA ports.
323 */
324 [SCIx_IRDA_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 1,
336 .overrun_reg = SCxSR,
337 .overrun_mask = SCI_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
340 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
341 .param_bits = &sci_scif_port_params_bits,
342 .common_regs = &sci_common_regs,
343 },
344
345 /*
346 * Common SCIFA definitions.
347 */
348 [SCIx_SCIFA_REGTYPE] = {
349 .regs = {
350 [SCSMR] = { 0x00, 16 },
351 [SCBRR] = { 0x04, 8 },
352 [SCSCR] = { 0x08, 16 },
353 [SCxTDR] = { 0x20, 8 },
354 [SCxSR] = { 0x14, 16 },
355 [SCxRDR] = { 0x24, 8 },
356 [SCFCR] = { 0x18, 16 },
357 [SCFDR] = { 0x1c, 16 },
358 [SCPCR] = { 0x30, 16 },
359 [SCPDR] = { 0x34, 16 },
360 },
361 .fifosize = 64,
362 .overrun_reg = SCxSR,
363 .overrun_mask = SCIFA_ORER,
364 .sampling_rate_mask = SCI_SR_SCIFAB,
365 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
366 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
367 .param_bits = &sci_scif_port_params_bits,
368 .common_regs = &sci_common_regs,
369 },
370
371 /*
372 * Common SCIFB definitions.
373 */
374 [SCIx_SCIFB_REGTYPE] = {
375 .regs = {
376 [SCSMR] = { 0x00, 16 },
377 [SCBRR] = { 0x04, 8 },
378 [SCSCR] = { 0x08, 16 },
379 [SCxTDR] = { 0x40, 8 },
380 [SCxSR] = { 0x14, 16 },
381 [SCxRDR] = { 0x60, 8 },
382 [SCFCR] = { 0x18, 16 },
383 [SCTFDR] = { 0x38, 16 },
384 [SCRFDR] = { 0x3c, 16 },
385 [SCPCR] = { 0x30, 16 },
386 [SCPDR] = { 0x34, 16 },
387 },
388 .fifosize = 256,
389 .overrun_reg = SCxSR,
390 .overrun_mask = SCIFA_ORER,
391 .sampling_rate_mask = SCI_SR_SCIFAB,
392 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
393 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
394 .param_bits = &sci_scif_port_params_bits,
395 .common_regs = &sci_common_regs,
396 },
397
398 /*
399 * Common SH-2(A) SCIF definitions for ports with FIFO data
400 * count registers.
401 */
402 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
403 .regs = {
404 [SCSMR] = { 0x00, 16 },
405 [SCBRR] = { 0x04, 8 },
406 [SCSCR] = { 0x08, 16 },
407 [SCxTDR] = { 0x0c, 8 },
408 [SCxSR] = { 0x10, 16 },
409 [SCxRDR] = { 0x14, 8 },
410 [SCFCR] = { 0x18, 16 },
411 [SCFDR] = { 0x1c, 16 },
412 [SCSPTR] = { 0x20, 16 },
413 [SCLSR] = { 0x24, 16 },
414 },
415 .fifosize = 16,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR(32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 .param_bits = &sci_scif_port_params_bits,
422 .common_regs = &sci_common_regs,
423 },
424
425 /*
426 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
427 * It looks like a normal SCIF with FIFO data, but with a
428 * compressed address space. Also, the break out of interrupts
429 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
430 */
431 [SCIx_RZ_SCIFA_REGTYPE] = {
432 .regs = {
433 [SCSMR] = { 0x00, 16 },
434 [SCBRR] = { 0x02, 8 },
435 [SCSCR] = { 0x04, 16 },
436 [SCxTDR] = { 0x06, 8 },
437 [SCxSR] = { 0x08, 16 },
438 [SCxRDR] = { 0x0A, 8 },
439 [SCFCR] = { 0x0C, 16 },
440 [SCFDR] = { 0x0E, 16 },
441 [SCSPTR] = { 0x10, 16 },
442 [SCLSR] = { 0x12, 16 },
443 [SEMR] = { 0x14, 8 },
444 },
445 .fifosize = 16,
446 .overrun_reg = SCLSR,
447 .overrun_mask = SCLSR_ORER,
448 .sampling_rate_mask = SCI_SR(32),
449 .error_mask = SCIF_DEFAULT_ERROR_MASK,
450 .error_clear = SCIF_ERROR_CLEAR,
451 .param_bits = &sci_scif_port_params_bits,
452 .common_regs = &sci_common_regs,
453 },
454
455 /*
456 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
457 * with below differences,
458 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
459 * TEI-DRI, RXI-EDGE and TXI-EDGE.
460 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
461 * - SCFCR register does not have SCFCR_MCE bit.
462 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
463 */
464 [SCIx_RZV2H_SCIF_REGTYPE] = {
465 .regs = {
466 [SCSMR] = { 0x00, 16 },
467 [SCBRR] = { 0x02, 8 },
468 [SCSCR] = { 0x04, 16 },
469 [SCxTDR] = { 0x06, 8 },
470 [SCxSR] = { 0x08, 16 },
471 [SCxRDR] = { 0x0a, 8 },
472 [SCFCR] = { 0x0c, 16 },
473 [SCFDR] = { 0x0e, 16 },
474 [SCSPTR] = { 0x10, 16 },
475 [SCLSR] = { 0x12, 16 },
476 [SEMR] = { 0x14, 8 },
477 },
478 .fifosize = 16,
479 .overrun_reg = SCLSR,
480 .overrun_mask = SCLSR_ORER,
481 .sampling_rate_mask = SCI_SR(32),
482 .error_mask = SCIF_DEFAULT_ERROR_MASK,
483 .error_clear = SCIF_ERROR_CLEAR,
484 .param_bits = &sci_scif_port_params_bits,
485 .common_regs = &sci_common_regs,
486 },
487
488 /*
489 * Common SH-3 SCIF definitions.
490 */
491 [SCIx_SH3_SCIF_REGTYPE] = {
492 .regs = {
493 [SCSMR] = { 0x00, 8 },
494 [SCBRR] = { 0x02, 8 },
495 [SCSCR] = { 0x04, 8 },
496 [SCxTDR] = { 0x06, 8 },
497 [SCxSR] = { 0x08, 16 },
498 [SCxRDR] = { 0x0a, 8 },
499 [SCFCR] = { 0x0c, 8 },
500 [SCFDR] = { 0x0e, 16 },
501 },
502 .fifosize = 16,
503 .overrun_reg = SCLSR,
504 .overrun_mask = SCLSR_ORER,
505 .sampling_rate_mask = SCI_SR(32),
506 .error_mask = SCIF_DEFAULT_ERROR_MASK,
507 .error_clear = SCIF_ERROR_CLEAR,
508 .param_bits = &sci_scif_port_params_bits,
509 .common_regs = &sci_common_regs,
510 },
511
512 /*
513 * Common SH-4(A) SCIF(B) definitions.
514 */
515 [SCIx_SH4_SCIF_REGTYPE] = {
516 .regs = {
517 [SCSMR] = { 0x00, 16 },
518 [SCBRR] = { 0x04, 8 },
519 [SCSCR] = { 0x08, 16 },
520 [SCxTDR] = { 0x0c, 8 },
521 [SCxSR] = { 0x10, 16 },
522 [SCxRDR] = { 0x14, 8 },
523 [SCFCR] = { 0x18, 16 },
524 [SCFDR] = { 0x1c, 16 },
525 [SCSPTR] = { 0x20, 16 },
526 [SCLSR] = { 0x24, 16 },
527 },
528 .fifosize = 16,
529 .overrun_reg = SCLSR,
530 .overrun_mask = SCLSR_ORER,
531 .sampling_rate_mask = SCI_SR(32),
532 .error_mask = SCIF_DEFAULT_ERROR_MASK,
533 .error_clear = SCIF_ERROR_CLEAR,
534 .param_bits = &sci_scif_port_params_bits,
535 .common_regs = &sci_common_regs,
536 },
537
538 /*
539 * Common SCIF definitions for ports with a Baud Rate Generator for
540 * External Clock (BRG).
541 */
542 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
543 .regs = {
544 [SCSMR] = { 0x00, 16 },
545 [SCBRR] = { 0x04, 8 },
546 [SCSCR] = { 0x08, 16 },
547 [SCxTDR] = { 0x0c, 8 },
548 [SCxSR] = { 0x10, 16 },
549 [SCxRDR] = { 0x14, 8 },
550 [SCFCR] = { 0x18, 16 },
551 [SCFDR] = { 0x1c, 16 },
552 [SCSPTR] = { 0x20, 16 },
553 [SCLSR] = { 0x24, 16 },
554 [SCDL] = { 0x30, 16 },
555 [SCCKS] = { 0x34, 16 },
556 },
557 .fifosize = 16,
558 .overrun_reg = SCLSR,
559 .overrun_mask = SCLSR_ORER,
560 .sampling_rate_mask = SCI_SR(32),
561 .error_mask = SCIF_DEFAULT_ERROR_MASK,
562 .error_clear = SCIF_ERROR_CLEAR,
563 .param_bits = &sci_scif_port_params_bits,
564 .common_regs = &sci_common_regs,
565 },
566
567 /*
568 * Common HSCIF definitions.
569 */
570 [SCIx_HSCIF_REGTYPE] = {
571 .regs = {
572 [SCSMR] = { 0x00, 16 },
573 [SCBRR] = { 0x04, 8 },
574 [SCSCR] = { 0x08, 16 },
575 [SCxTDR] = { 0x0c, 8 },
576 [SCxSR] = { 0x10, 16 },
577 [SCxRDR] = { 0x14, 8 },
578 [SCFCR] = { 0x18, 16 },
579 [SCFDR] = { 0x1c, 16 },
580 [SCSPTR] = { 0x20, 16 },
581 [SCLSR] = { 0x24, 16 },
582 [HSSRR] = { 0x40, 16 },
583 [SCDL] = { 0x30, 16 },
584 [SCCKS] = { 0x34, 16 },
585 [HSRTRGR] = { 0x54, 16 },
586 [HSTTRGR] = { 0x58, 16 },
587 },
588 .fifosize = 128,
589 .overrun_reg = SCLSR,
590 .overrun_mask = SCLSR_ORER,
591 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
592 .error_mask = SCIF_DEFAULT_ERROR_MASK,
593 .error_clear = SCIF_ERROR_CLEAR,
594 .param_bits = &sci_scif_port_params_bits,
595 .common_regs = &sci_common_regs,
596 },
597
598 /*
599 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
600 * register.
601 */
602 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
603 .regs = {
604 [SCSMR] = { 0x00, 16 },
605 [SCBRR] = { 0x04, 8 },
606 [SCSCR] = { 0x08, 16 },
607 [SCxTDR] = { 0x0c, 8 },
608 [SCxSR] = { 0x10, 16 },
609 [SCxRDR] = { 0x14, 8 },
610 [SCFCR] = { 0x18, 16 },
611 [SCFDR] = { 0x1c, 16 },
612 [SCLSR] = { 0x24, 16 },
613 },
614 .fifosize = 16,
615 .overrun_reg = SCLSR,
616 .overrun_mask = SCLSR_ORER,
617 .sampling_rate_mask = SCI_SR(32),
618 .error_mask = SCIF_DEFAULT_ERROR_MASK,
619 .error_clear = SCIF_ERROR_CLEAR,
620 .param_bits = &sci_scif_port_params_bits,
621 .common_regs = &sci_common_regs,
622 },
623
624 /*
625 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
626 * count registers.
627 */
628 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
629 .regs = {
630 [SCSMR] = { 0x00, 16 },
631 [SCBRR] = { 0x04, 8 },
632 [SCSCR] = { 0x08, 16 },
633 [SCxTDR] = { 0x0c, 8 },
634 [SCxSR] = { 0x10, 16 },
635 [SCxRDR] = { 0x14, 8 },
636 [SCFCR] = { 0x18, 16 },
637 [SCFDR] = { 0x1c, 16 },
638 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
639 [SCRFDR] = { 0x20, 16 },
640 [SCSPTR] = { 0x24, 16 },
641 [SCLSR] = { 0x28, 16 },
642 },
643 .fifosize = 16,
644 .overrun_reg = SCLSR,
645 .overrun_mask = SCLSR_ORER,
646 .sampling_rate_mask = SCI_SR(32),
647 .error_mask = SCIF_DEFAULT_ERROR_MASK,
648 .error_clear = SCIF_ERROR_CLEAR,
649 .param_bits = &sci_scif_port_params_bits,
650 .common_regs = &sci_common_regs,
651 },
652
653 /*
654 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
655 * registers.
656 */
657 [SCIx_SH7705_SCIF_REGTYPE] = {
658 .regs = {
659 [SCSMR] = { 0x00, 16 },
660 [SCBRR] = { 0x04, 8 },
661 [SCSCR] = { 0x08, 16 },
662 [SCxTDR] = { 0x20, 8 },
663 [SCxSR] = { 0x14, 16 },
664 [SCxRDR] = { 0x24, 8 },
665 [SCFCR] = { 0x18, 16 },
666 [SCFDR] = { 0x1c, 16 },
667 },
668 .fifosize = 64,
669 .overrun_reg = SCxSR,
670 .overrun_mask = SCIFA_ORER,
671 .sampling_rate_mask = SCI_SR(16),
672 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
673 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
674 .param_bits = &sci_scif_port_params_bits,
675 .common_regs = &sci_common_regs,
676 },
677 };
678
679 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
680
681 /*
682 * The "offset" here is rather misleading, in that it refers to an enum
683 * value relative to the port mapping rather than the fixed offset
684 * itself, which needs to be manually retrieved from the platform's
685 * register map for the given port.
686 */
sci_serial_in(struct uart_port * p,int offset)687 static unsigned int sci_serial_in(struct uart_port *p, int offset)
688 {
689 const struct plat_sci_reg *reg = sci_getreg(p, offset);
690
691 if (reg->size == 8)
692 return ioread8(p->membase + (reg->offset << p->regshift));
693 else if (reg->size == 16)
694 return ioread16(p->membase + (reg->offset << p->regshift));
695 else
696 WARN(1, "Invalid register access\n");
697
698 return 0;
699 }
700
sci_serial_out(struct uart_port * p,int offset,int value)701 static void sci_serial_out(struct uart_port *p, int offset, int value)
702 {
703 const struct plat_sci_reg *reg = sci_getreg(p, offset);
704
705 if (reg->size == 8)
706 iowrite8(value, p->membase + (reg->offset << p->regshift));
707 else if (reg->size == 16)
708 iowrite16(value, p->membase + (reg->offset << p->regshift));
709 else
710 WARN(1, "Invalid register access\n");
711 }
712
sci_port_enable(struct sci_port * sci_port)713 void sci_port_enable(struct sci_port *sci_port)
714 {
715 unsigned int i;
716
717 if (!sci_port->port.dev)
718 return;
719
720 pm_runtime_get_sync(sci_port->port.dev);
721
722 for (i = 0; i < SCI_NUM_CLKS; i++) {
723 clk_prepare_enable(sci_port->clks[i]);
724 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
725 }
726 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
727 }
728 EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI");
729
sci_port_disable(struct sci_port * sci_port)730 void sci_port_disable(struct sci_port *sci_port)
731 {
732 unsigned int i;
733
734 if (!sci_port->port.dev)
735 return;
736
737 for (i = SCI_NUM_CLKS; i-- > 0; )
738 clk_disable_unprepare(sci_port->clks[i]);
739
740 pm_runtime_put_sync(sci_port->port.dev);
741 }
742 EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI");
743
port_rx_irq_mask(struct uart_port * port)744 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
745 {
746 /*
747 * Not all ports (such as SCIFA) will support REIE. Rather than
748 * special-casing the port type, we check the port initialization
749 * IRQ enable mask to see whether the IRQ is desired at all. If
750 * it's unset, it's logically inferred that there's no point in
751 * testing for it.
752 */
753 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
754 }
755
sci_start_tx(struct uart_port * port)756 static void sci_start_tx(struct uart_port *port)
757 {
758 struct sci_port *s = to_sci_port(port);
759 unsigned short ctrl;
760
761 #ifdef CONFIG_SERIAL_SH_SCI_DMA
762 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
763 u16 new, scr = sci_serial_in(port, SCSCR);
764 if (s->chan_tx)
765 new = scr | SCSCR_TDRQE;
766 else
767 new = scr & ~SCSCR_TDRQE;
768 if (new != scr)
769 sci_serial_out(port, SCSCR, new);
770 }
771
772 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
773 dma_submit_error(s->cookie_tx)) {
774 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
775 /* Switch irq from SCIF to DMA */
776 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
777
778 s->cookie_tx = 0;
779 schedule_work(&s->work_tx);
780 }
781 #endif
782
783 if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||
784 s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
785 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
786 ctrl = sci_serial_in(port, SCSCR);
787
788 /*
789 * For SCI, TE (transmit enable) must be set after setting TIE
790 * (transmit interrupt enable) or in the same instruction to start
791 * the transmit process.
792 */
793 if (s->type == PORT_SCI)
794 ctrl |= SCSCR_TE;
795
796 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
797 }
798 }
799
sci_stop_tx(struct uart_port * port)800 static void sci_stop_tx(struct uart_port *port)
801 {
802 struct sci_port *s = to_sci_port(port);
803 unsigned short ctrl;
804
805 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
806 ctrl = sci_serial_in(port, SCSCR);
807
808 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
809 ctrl &= ~SCSCR_TDRQE;
810
811 ctrl &= ~SCSCR_TIE;
812
813 sci_serial_out(port, SCSCR, ctrl);
814
815 #ifdef CONFIG_SERIAL_SH_SCI_DMA
816 if (s->chan_tx &&
817 !dma_submit_error(s->cookie_tx)) {
818 dmaengine_terminate_async(s->chan_tx);
819 s->cookie_tx = -EINVAL;
820 }
821 #endif
822 }
823
sci_start_rx(struct uart_port * port)824 static void sci_start_rx(struct uart_port *port)
825 {
826 struct sci_port *s = to_sci_port(port);
827 unsigned short ctrl;
828
829 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
830
831 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
832 ctrl &= ~SCSCR_RDRQE;
833
834 sci_serial_out(port, SCSCR, ctrl);
835 }
836
sci_stop_rx(struct uart_port * port)837 static void sci_stop_rx(struct uart_port *port)
838 {
839 struct sci_port *s = to_sci_port(port);
840 unsigned short ctrl;
841
842 ctrl = sci_serial_in(port, SCSCR);
843
844 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
845 ctrl &= ~SCSCR_RDRQE;
846
847 ctrl &= ~port_rx_irq_mask(port);
848
849 sci_serial_out(port, SCSCR, ctrl);
850 }
851
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)852 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
853 {
854 struct sci_port *s = to_sci_port(port);
855
856 if (s->type == PORT_SCI) {
857 /* Just store the mask */
858 sci_serial_out(port, SCxSR, mask);
859 } else if (s->params->overrun_mask == SCIFA_ORER) {
860 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
861 /* Only clear the status bits we want to clear */
862 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
863 } else {
864 /* Store the mask, clear parity/framing errors */
865 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
866 }
867 }
868
869 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
870 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
871
872 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)873 static int sci_poll_get_char(struct uart_port *port)
874 {
875 unsigned short status;
876 struct sci_port *s = to_sci_port(port);
877 int c;
878
879 do {
880 status = sci_serial_in(port, SCxSR);
881 if (status & SCxSR_ERRORS(port)) {
882 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
883 continue;
884 }
885 break;
886 } while (1);
887
888 if (!(status & SCxSR_RDxF(port)))
889 return NO_POLL_CHAR;
890
891 c = sci_serial_in(port, SCxRDR);
892
893 /* Dummy read */
894 sci_serial_in(port, SCxSR);
895 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
896
897 return c;
898 }
899 #endif
900
sci_poll_put_char(struct uart_port * port,unsigned char c)901 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
902 {
903 struct sci_port *s = to_sci_port(port);
904 const struct sci_common_regs *regs = s->params->common_regs;
905 unsigned int status;
906
907 do {
908 status = s->ops->read_reg(port, regs->status);
909 } while (!(status & SCxSR_TDxE(port)));
910
911 sci_serial_out(port, SCxTDR, c);
912 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
913 }
914 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
915 CONFIG_SERIAL_SH_SCI_EARLYCON */
916
sci_init_pins(struct uart_port * port,unsigned int cflag)917 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
918 {
919 struct sci_port *s = to_sci_port(port);
920
921 /*
922 * Use port-specific handler if provided.
923 */
924 if (s->cfg->ops && s->cfg->ops->init_pins) {
925 s->cfg->ops->init_pins(port, cflag);
926 return;
927 }
928
929 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
930 u16 data = sci_serial_in(port, SCPDR);
931 u16 ctrl = sci_serial_in(port, SCPCR);
932
933 /* Enable RXD and TXD pin functions */
934 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
935 if (s->has_rtscts) {
936 /* RTS# is output, active low, unless autorts */
937 if (!(port->mctrl & TIOCM_RTS)) {
938 ctrl |= SCPCR_RTSC;
939 data |= SCPDR_RTSD;
940 } else if (!s->autorts) {
941 ctrl |= SCPCR_RTSC;
942 data &= ~SCPDR_RTSD;
943 } else {
944 /* Enable RTS# pin function */
945 ctrl &= ~SCPCR_RTSC;
946 }
947 /* Enable CTS# pin function */
948 ctrl &= ~SCPCR_CTSC;
949 }
950 sci_serial_out(port, SCPDR, data);
951 sci_serial_out(port, SCPCR, ctrl);
952 } else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
953 u16 status = sci_serial_in(port, SCSPTR);
954
955 /* RTS# is always output; and active low, unless autorts */
956 status |= SCSPTR_RTSIO;
957 if (!(port->mctrl & TIOCM_RTS))
958 status |= SCSPTR_RTSDT;
959 else if (!s->autorts)
960 status &= ~SCSPTR_RTSDT;
961 /* CTS# and SCK are inputs */
962 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
963 sci_serial_out(port, SCSPTR, status);
964 }
965 }
966
sci_txfill(struct uart_port * port)967 static int sci_txfill(struct uart_port *port)
968 {
969 struct sci_port *s = to_sci_port(port);
970 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
971 const struct plat_sci_reg *reg;
972
973 reg = sci_getreg(port, SCTFDR);
974 if (reg->size)
975 return sci_serial_in(port, SCTFDR) & fifo_mask;
976
977 reg = sci_getreg(port, SCFDR);
978 if (reg->size)
979 return sci_serial_in(port, SCFDR) >> 8;
980
981 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
982 }
983
sci_txroom(struct uart_port * port)984 static int sci_txroom(struct uart_port *port)
985 {
986 return port->fifosize - sci_txfill(port);
987 }
988
sci_rxfill(struct uart_port * port)989 static int sci_rxfill(struct uart_port *port)
990 {
991 struct sci_port *s = to_sci_port(port);
992 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
993 const struct plat_sci_reg *reg;
994
995 reg = sci_getreg(port, SCRFDR);
996 if (reg->size)
997 return sci_serial_in(port, SCRFDR) & fifo_mask;
998
999 reg = sci_getreg(port, SCFDR);
1000 if (reg->size)
1001 return sci_serial_in(port, SCFDR) & fifo_mask;
1002
1003 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
1004 }
1005
1006 /* ********************************************************************** *
1007 * the interrupt related routines *
1008 * ********************************************************************** */
1009
sci_transmit_chars(struct uart_port * port)1010 static void sci_transmit_chars(struct uart_port *port)
1011 {
1012 struct tty_port *tport = &port->state->port;
1013 unsigned int stopped = uart_tx_stopped(port);
1014 struct sci_port *s = to_sci_port(port);
1015 unsigned short status;
1016 unsigned short ctrl;
1017 int count;
1018
1019 status = sci_serial_in(port, SCxSR);
1020 if (!(status & SCxSR_TDxE(port))) {
1021 ctrl = sci_serial_in(port, SCSCR);
1022 if (kfifo_is_empty(&tport->xmit_fifo))
1023 ctrl &= ~SCSCR_TIE;
1024 else
1025 ctrl |= SCSCR_TIE;
1026 sci_serial_out(port, SCSCR, ctrl);
1027 return;
1028 }
1029
1030 count = sci_txroom(port);
1031
1032 do {
1033 unsigned char c;
1034
1035 if (port->x_char) {
1036 c = port->x_char;
1037 port->x_char = 0;
1038 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
1039 if (s->type == PORT_SCI &&
1040 kfifo_is_empty(&tport->xmit_fifo)) {
1041 ctrl = sci_serial_in(port, SCSCR);
1042 ctrl &= ~SCSCR_TE;
1043 sci_serial_out(port, SCSCR, ctrl);
1044 return;
1045 }
1046 break;
1047 }
1048
1049 sci_serial_out(port, SCxTDR, c);
1050 s->tx_occurred = true;
1051
1052 port->icount.tx++;
1053 } while (--count > 0);
1054
1055 s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1056
1057 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1058 uart_write_wakeup(port);
1059 if (kfifo_is_empty(&tport->xmit_fifo)) {
1060 if (s->type == PORT_SCI) {
1061 ctrl = sci_serial_in(port, SCSCR);
1062 ctrl &= ~SCSCR_TIE;
1063 ctrl |= SCSCR_TEIE;
1064 sci_serial_out(port, SCSCR, ctrl);
1065 }
1066
1067 sci_stop_tx(port);
1068 }
1069 }
1070
sci_receive_chars(struct uart_port * port)1071 static void sci_receive_chars(struct uart_port *port)
1072 {
1073 struct tty_port *tport = &port->state->port;
1074 struct sci_port *s = to_sci_port(port);
1075 int i, count, copied = 0;
1076 unsigned short status;
1077 unsigned char flag;
1078
1079 status = sci_serial_in(port, SCxSR);
1080 if (!(status & SCxSR_RDxF(port)))
1081 return;
1082
1083 while (1) {
1084 /* Don't copy more bytes than there is room for in the buffer */
1085 count = tty_buffer_request_room(tport, sci_rxfill(port));
1086
1087 /* If for any reason we can't copy more data, we're done! */
1088 if (count == 0)
1089 break;
1090
1091 if (s->type == PORT_SCI) {
1092 char c = sci_serial_in(port, SCxRDR);
1093 if (uart_handle_sysrq_char(port, c))
1094 count = 0;
1095 else
1096 tty_insert_flip_char(tport, c, TTY_NORMAL);
1097 } else {
1098 for (i = 0; i < count; i++) {
1099 char c;
1100
1101 if (s->type == PORT_SCIF ||
1102 s->type == PORT_HSCIF) {
1103 status = sci_serial_in(port, SCxSR);
1104 c = sci_serial_in(port, SCxRDR);
1105 } else {
1106 c = sci_serial_in(port, SCxRDR);
1107 status = sci_serial_in(port, SCxSR);
1108 }
1109 if (uart_handle_sysrq_char(port, c)) {
1110 count--; i--;
1111 continue;
1112 }
1113
1114 /* Store data and status */
1115 if (status & SCxSR_FER(port)) {
1116 flag = TTY_FRAME;
1117 port->icount.frame++;
1118 } else if (status & SCxSR_PER(port)) {
1119 flag = TTY_PARITY;
1120 port->icount.parity++;
1121 } else
1122 flag = TTY_NORMAL;
1123
1124 tty_insert_flip_char(tport, c, flag);
1125 }
1126 }
1127
1128 sci_serial_in(port, SCxSR); /* dummy read */
1129 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1130
1131 copied += count;
1132 port->icount.rx += count;
1133 }
1134
1135 if (copied) {
1136 /* Tell the rest of the system the news. New characters! */
1137 tty_flip_buffer_push(tport);
1138 } else {
1139 /* TTY buffers full; read from RX reg to prevent lockup */
1140 sci_serial_in(port, SCxRDR);
1141 sci_serial_in(port, SCxSR); /* dummy read */
1142 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1143 }
1144 }
1145
sci_handle_errors(struct uart_port * port)1146 static int sci_handle_errors(struct uart_port *port)
1147 {
1148 int copied = 0;
1149 struct sci_port *s = to_sci_port(port);
1150 const struct sci_common_regs *regs = s->params->common_regs;
1151 unsigned int status = s->ops->read_reg(port, regs->status);
1152 struct tty_port *tport = &port->state->port;
1153
1154 /* Handle overruns */
1155 if (status & s->params->overrun_mask) {
1156 port->icount.overrun++;
1157
1158 /* overrun error */
1159 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
1160 copied++;
1161 }
1162
1163 if (status & SCxSR_FER(port)) {
1164 /* frame error */
1165 port->icount.frame++;
1166
1167 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1168 copied++;
1169 }
1170
1171 if (status & SCxSR_PER(port)) {
1172 /* parity error */
1173 port->icount.parity++;
1174
1175 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1176 copied++;
1177 }
1178
1179 if (copied)
1180 tty_flip_buffer_push(tport);
1181
1182 return copied;
1183 }
1184
sci_is_rsci_type(u8 type)1185 static bool sci_is_rsci_type(u8 type)
1186 {
1187 return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32);
1188 }
1189
sci_handle_fifo_overrun(struct uart_port * port)1190 static int sci_handle_fifo_overrun(struct uart_port *port)
1191 {
1192 struct tty_port *tport = &port->state->port;
1193 struct sci_port *s = to_sci_port(port);
1194 const struct plat_sci_reg *reg;
1195 int copied = 0;
1196 u32 status;
1197
1198 if (!sci_is_rsci_type(s->type)) {
1199 reg = sci_getreg(port, s->params->overrun_reg);
1200 if (!reg->size)
1201 return 0;
1202 }
1203
1204 status = s->ops->read_reg(port, s->params->overrun_reg);
1205 if (status & s->params->overrun_mask) {
1206 if (sci_is_rsci_type(s->type)) {
1207 /*
1208 * All of the CFCLR_*C clearing bits match the corresponding
1209 * CSR_*status bits. So, reuse the overrun mask for clearing.
1210 */
1211 s->ops->clear_SCxSR(port, s->params->overrun_mask);
1212 } else {
1213 status &= ~s->params->overrun_mask;
1214 s->ops->write_reg(port, s->params->overrun_reg, status);
1215 }
1216
1217 port->icount.overrun++;
1218
1219 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1220 tty_flip_buffer_push(tport);
1221 copied++;
1222 }
1223
1224 return copied;
1225 }
1226
sci_handle_breaks(struct uart_port * port)1227 static int sci_handle_breaks(struct uart_port *port)
1228 {
1229 int copied = 0;
1230 unsigned short status = sci_serial_in(port, SCxSR);
1231 struct tty_port *tport = &port->state->port;
1232
1233 if (uart_handle_break(port))
1234 return 0;
1235
1236 if (status & SCxSR_BRK(port)) {
1237 port->icount.brk++;
1238
1239 /* Notify of BREAK */
1240 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1241 copied++;
1242 }
1243
1244 if (copied)
1245 tty_flip_buffer_push(tport);
1246
1247 copied += sci_handle_fifo_overrun(port);
1248
1249 return copied;
1250 }
1251
scif_set_rtrg(struct uart_port * port,int rx_trig)1252 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1253 {
1254 struct sci_port *s = to_sci_port(port);
1255 unsigned int bits;
1256
1257 if (rx_trig >= port->fifosize)
1258 rx_trig = port->fifosize - 1;
1259 if (rx_trig < 1)
1260 rx_trig = 1;
1261
1262 /* HSCIF can be set to an arbitrary level. */
1263 if (sci_getreg(port, HSRTRGR)->size) {
1264 sci_serial_out(port, HSRTRGR, rx_trig);
1265 return rx_trig;
1266 }
1267
1268 switch (s->type) {
1269 case PORT_SCIF:
1270 if (rx_trig < 4) {
1271 bits = 0;
1272 rx_trig = 1;
1273 } else if (rx_trig < 8) {
1274 bits = SCFCR_RTRG0;
1275 rx_trig = 4;
1276 } else if (rx_trig < 14) {
1277 bits = SCFCR_RTRG1;
1278 rx_trig = 8;
1279 } else {
1280 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1281 rx_trig = 14;
1282 }
1283 break;
1284 case PORT_SCIFA:
1285 case PORT_SCIFB:
1286 if (rx_trig < 16) {
1287 bits = 0;
1288 rx_trig = 1;
1289 } else if (rx_trig < 32) {
1290 bits = SCFCR_RTRG0;
1291 rx_trig = 16;
1292 } else if (rx_trig < 48) {
1293 bits = SCFCR_RTRG1;
1294 rx_trig = 32;
1295 } else {
1296 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1297 rx_trig = 48;
1298 }
1299 break;
1300 default:
1301 WARN(1, "unknown FIFO configuration");
1302 return 1;
1303 }
1304
1305 sci_serial_out(port, SCFCR,
1306 (sci_serial_in(port, SCFCR) &
1307 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1308
1309 return rx_trig;
1310 }
1311
scif_rtrg_enabled(struct uart_port * port)1312 static int scif_rtrg_enabled(struct uart_port *port)
1313 {
1314 if (sci_getreg(port, HSRTRGR)->size)
1315 return sci_serial_in(port, HSRTRGR) != 0;
1316 else
1317 return (sci_serial_in(port, SCFCR) &
1318 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1319 }
1320
rx_fifo_timer_fn(struct timer_list * t)1321 static void rx_fifo_timer_fn(struct timer_list *t)
1322 {
1323 struct sci_port *s = timer_container_of(s, t, rx_fifo_timer);
1324 struct uart_port *port = &s->port;
1325
1326 dev_dbg(port->dev, "Rx timed out\n");
1327 s->ops->set_rtrg(port, 1);
1328 }
1329
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1330 static ssize_t rx_fifo_trigger_show(struct device *dev,
1331 struct device_attribute *attr, char *buf)
1332 {
1333 struct uart_port *port = dev_get_drvdata(dev);
1334 struct sci_port *sci = to_sci_port(port);
1335
1336 return sprintf(buf, "%d\n", sci->rx_trigger);
1337 }
1338
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1339 static ssize_t rx_fifo_trigger_store(struct device *dev,
1340 struct device_attribute *attr,
1341 const char *buf, size_t count)
1342 {
1343 struct uart_port *port = dev_get_drvdata(dev);
1344 struct sci_port *sci = to_sci_port(port);
1345 int ret;
1346 long r;
1347
1348 ret = kstrtol(buf, 0, &r);
1349 if (ret)
1350 return ret;
1351
1352 sci->rx_trigger = sci->ops->set_rtrg(port, r);
1353 if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB)
1354 sci->ops->set_rtrg(port, 1);
1355
1356 return count;
1357 }
1358
1359 static DEVICE_ATTR_RW(rx_fifo_trigger);
1360
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1361 static ssize_t rx_fifo_timeout_show(struct device *dev,
1362 struct device_attribute *attr,
1363 char *buf)
1364 {
1365 struct uart_port *port = dev_get_drvdata(dev);
1366 struct sci_port *sci = to_sci_port(port);
1367 int v;
1368
1369 if (sci->type == PORT_HSCIF)
1370 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1371 else
1372 v = sci->rx_fifo_timeout;
1373
1374 return sprintf(buf, "%d\n", v);
1375 }
1376
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1377 static ssize_t rx_fifo_timeout_store(struct device *dev,
1378 struct device_attribute *attr,
1379 const char *buf,
1380 size_t count)
1381 {
1382 struct uart_port *port = dev_get_drvdata(dev);
1383 struct sci_port *sci = to_sci_port(port);
1384 int ret;
1385 long r;
1386
1387 ret = kstrtol(buf, 0, &r);
1388 if (ret)
1389 return ret;
1390
1391 if (sci->type == PORT_HSCIF) {
1392 if (r < 0 || r > 3)
1393 return -EINVAL;
1394 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1395 } else {
1396 sci->rx_fifo_timeout = r;
1397 sci->ops->set_rtrg(port, 1);
1398 if (r > 0)
1399 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1400 }
1401
1402 return count;
1403 }
1404
1405 static DEVICE_ATTR_RW(rx_fifo_timeout);
1406
1407
1408 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1409 static void sci_dma_tx_complete(void *arg)
1410 {
1411 struct sci_port *s = arg;
1412 struct uart_port *port = &s->port;
1413 struct tty_port *tport = &port->state->port;
1414 unsigned long flags;
1415
1416 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1417
1418 uart_port_lock_irqsave(port, &flags);
1419
1420 uart_xmit_advance(port, s->tx_dma_len);
1421
1422 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1423 uart_write_wakeup(port);
1424
1425 s->tx_occurred = true;
1426
1427 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1428 s->cookie_tx = 0;
1429 schedule_work(&s->work_tx);
1430 } else {
1431 s->cookie_tx = -EINVAL;
1432 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1433 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1434 u16 ctrl = sci_serial_in(port, SCSCR);
1435 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1436 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1437 /* Switch irq from DMA to SCIF */
1438 dmaengine_pause(s->chan_tx_saved);
1439 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1440 }
1441 }
1442 }
1443
1444 uart_port_unlock_irqrestore(port, flags);
1445 }
1446
1447 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1448 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1449 {
1450 struct uart_port *port = &s->port;
1451 struct tty_port *tport = &port->state->port;
1452 int copied;
1453
1454 copied = tty_insert_flip_string(tport, buf, count);
1455 if (copied < count)
1456 port->icount.buf_overrun++;
1457
1458 port->icount.rx += copied;
1459
1460 return copied;
1461 }
1462
sci_dma_rx_find_active(struct sci_port * s)1463 static int sci_dma_rx_find_active(struct sci_port *s)
1464 {
1465 unsigned int i;
1466
1467 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1468 if (s->active_rx == s->cookie_rx[i])
1469 return i;
1470
1471 return -1;
1472 }
1473
1474 /* Must only be called with uart_port_lock taken */
sci_dma_rx_chan_invalidate(struct sci_port * s)1475 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1476 {
1477 unsigned int i;
1478
1479 s->chan_rx = NULL;
1480 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1481 s->cookie_rx[i] = -EINVAL;
1482 s->active_rx = 0;
1483 }
1484
sci_dma_rx_release(struct sci_port * s)1485 static void sci_dma_rx_release(struct sci_port *s)
1486 {
1487 struct dma_chan *chan = s->chan_rx_saved;
1488 struct uart_port *port = &s->port;
1489 unsigned long flags;
1490
1491 uart_port_lock_irqsave(port, &flags);
1492 s->chan_rx_saved = NULL;
1493 sci_dma_rx_chan_invalidate(s);
1494 uart_port_unlock_irqrestore(port, flags);
1495
1496 dmaengine_terminate_sync(chan);
1497 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1498 sg_dma_address(&s->sg_rx[0]));
1499 dma_release_channel(chan);
1500 }
1501
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1502 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1503 {
1504 long sec = usec / 1000000;
1505 long nsec = (usec % 1000000) * 1000;
1506 ktime_t t = ktime_set(sec, nsec);
1507
1508 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1509 }
1510
sci_dma_rx_reenable_irq(struct sci_port * s)1511 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1512 {
1513 struct uart_port *port = &s->port;
1514 u16 scr;
1515
1516 /* Direct new serial port interrupts back to CPU */
1517 scr = sci_serial_in(port, SCSCR);
1518 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1519 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1520 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1521 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1522 s->ops->set_rtrg(port, s->rx_trigger);
1523 else
1524 scr &= ~SCSCR_RDRQE;
1525 }
1526 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1527 }
1528
sci_dma_rx_complete(void * arg)1529 static void sci_dma_rx_complete(void *arg)
1530 {
1531 struct sci_port *s = arg;
1532 struct dma_chan *chan = s->chan_rx;
1533 struct uart_port *port = &s->port;
1534 struct dma_async_tx_descriptor *desc;
1535 unsigned long flags;
1536 int active, count = 0;
1537
1538 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1539 s->active_rx);
1540
1541 hrtimer_cancel(&s->rx_timer);
1542
1543 uart_port_lock_irqsave(port, &flags);
1544
1545 active = sci_dma_rx_find_active(s);
1546 if (active >= 0)
1547 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1548
1549 if (count)
1550 tty_flip_buffer_push(&port->state->port);
1551
1552 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1553 DMA_DEV_TO_MEM,
1554 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1555 if (!desc)
1556 goto fail;
1557
1558 desc->callback = sci_dma_rx_complete;
1559 desc->callback_param = s;
1560 s->cookie_rx[active] = dmaengine_submit(desc);
1561 if (dma_submit_error(s->cookie_rx[active]))
1562 goto fail;
1563
1564 s->active_rx = s->cookie_rx[!active];
1565
1566 dma_async_issue_pending(chan);
1567
1568 uart_port_unlock_irqrestore(port, flags);
1569 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1570 __func__, s->cookie_rx[active], active, s->active_rx);
1571
1572 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1573
1574 return;
1575
1576 fail:
1577 /* Switch to PIO */
1578 dmaengine_terminate_async(chan);
1579 sci_dma_rx_chan_invalidate(s);
1580 sci_dma_rx_reenable_irq(s);
1581 uart_port_unlock_irqrestore(port, flags);
1582 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1583 }
1584
sci_dma_tx_release(struct sci_port * s)1585 static void sci_dma_tx_release(struct sci_port *s)
1586 {
1587 struct dma_chan *chan = s->chan_tx_saved;
1588
1589 cancel_work_sync(&s->work_tx);
1590 s->chan_tx_saved = s->chan_tx = NULL;
1591 s->cookie_tx = -EINVAL;
1592 dmaengine_terminate_sync(chan);
1593 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1594 DMA_TO_DEVICE);
1595 dma_release_channel(chan);
1596 }
1597
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1598 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1599 {
1600 struct dma_chan *chan = s->chan_rx;
1601 struct uart_port *port = &s->port;
1602 unsigned long flags;
1603 int i;
1604
1605 for (i = 0; i < 2; i++) {
1606 struct scatterlist *sg = &s->sg_rx[i];
1607 struct dma_async_tx_descriptor *desc;
1608
1609 desc = dmaengine_prep_slave_sg(chan,
1610 sg, 1, DMA_DEV_TO_MEM,
1611 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1612 if (!desc)
1613 goto fail;
1614
1615 desc->callback = sci_dma_rx_complete;
1616 desc->callback_param = s;
1617 s->cookie_rx[i] = dmaengine_submit(desc);
1618 if (dma_submit_error(s->cookie_rx[i]))
1619 goto fail;
1620
1621 }
1622
1623 s->active_rx = s->cookie_rx[0];
1624
1625 dma_async_issue_pending(chan);
1626 return 0;
1627
1628 fail:
1629 /* Switch to PIO */
1630 if (!port_lock_held)
1631 uart_port_lock_irqsave(port, &flags);
1632 if (i)
1633 dmaengine_terminate_async(chan);
1634 sci_dma_rx_chan_invalidate(s);
1635 sci_start_rx(port);
1636 if (!port_lock_held)
1637 uart_port_unlock_irqrestore(port, flags);
1638 return -EAGAIN;
1639 }
1640
sci_dma_tx_work_fn(struct work_struct * work)1641 static void sci_dma_tx_work_fn(struct work_struct *work)
1642 {
1643 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1644 struct dma_async_tx_descriptor *desc;
1645 struct dma_chan *chan = s->chan_tx;
1646 struct uart_port *port = &s->port;
1647 struct tty_port *tport = &port->state->port;
1648 unsigned long flags;
1649 unsigned int tail;
1650 dma_addr_t buf;
1651
1652 /*
1653 * DMA is idle now.
1654 * Port xmit buffer is already mapped, and it is one page... Just adjust
1655 * offsets and lengths. Since it is a circular buffer, we have to
1656 * transmit till the end, and then the rest. Take the port lock to get a
1657 * consistent xmit buffer state.
1658 */
1659 uart_port_lock_irq(port);
1660 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1661 UART_XMIT_SIZE);
1662 buf = s->tx_dma_addr + tail;
1663 if (!s->tx_dma_len) {
1664 /* Transmit buffer has been flushed */
1665 uart_port_unlock_irq(port);
1666 return;
1667 }
1668
1669 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1670 DMA_MEM_TO_DEV,
1671 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1672 if (!desc) {
1673 uart_port_unlock_irq(port);
1674 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1675 goto switch_to_pio;
1676 }
1677
1678 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1679 DMA_TO_DEVICE);
1680
1681 desc->callback = sci_dma_tx_complete;
1682 desc->callback_param = s;
1683 s->cookie_tx = dmaengine_submit(desc);
1684 if (dma_submit_error(s->cookie_tx)) {
1685 uart_port_unlock_irq(port);
1686 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1687 goto switch_to_pio;
1688 }
1689
1690 uart_port_unlock_irq(port);
1691 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1692 __func__, tport->xmit_buf, tail, s->cookie_tx);
1693
1694 dma_async_issue_pending(chan);
1695 return;
1696
1697 switch_to_pio:
1698 uart_port_lock_irqsave(port, &flags);
1699 s->chan_tx = NULL;
1700 sci_start_tx(port);
1701 uart_port_unlock_irqrestore(port, flags);
1702 return;
1703 }
1704
sci_dma_rx_timer_fn(struct hrtimer * t)1705 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1706 {
1707 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1708 struct dma_chan *chan = s->chan_rx;
1709 struct uart_port *port = &s->port;
1710 struct dma_tx_state state;
1711 enum dma_status status;
1712 unsigned long flags;
1713 unsigned int read;
1714 int active, count;
1715
1716 dev_dbg(port->dev, "DMA Rx timed out\n");
1717
1718 uart_port_lock_irqsave(port, &flags);
1719
1720 active = sci_dma_rx_find_active(s);
1721 if (active < 0) {
1722 uart_port_unlock_irqrestore(port, flags);
1723 return HRTIMER_NORESTART;
1724 }
1725
1726 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1727 if (status == DMA_COMPLETE) {
1728 uart_port_unlock_irqrestore(port, flags);
1729 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1730 s->active_rx, active);
1731
1732 /* Let packet complete handler take care of the packet */
1733 return HRTIMER_NORESTART;
1734 }
1735
1736 dmaengine_pause(chan);
1737
1738 /*
1739 * sometimes DMA transfer doesn't stop even if it is stopped and
1740 * data keeps on coming until transaction is complete so check
1741 * for DMA_COMPLETE again
1742 * Let packet complete handler take care of the packet
1743 */
1744 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1745 if (status == DMA_COMPLETE) {
1746 uart_port_unlock_irqrestore(port, flags);
1747 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1748 return HRTIMER_NORESTART;
1749 }
1750
1751 /* Handle incomplete DMA receive */
1752 dmaengine_terminate_async(s->chan_rx);
1753 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1754
1755 if (read) {
1756 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1757 if (count)
1758 tty_flip_buffer_push(&port->state->port);
1759 }
1760
1761 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1762 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1763 sci_dma_rx_submit(s, true);
1764
1765 sci_dma_rx_reenable_irq(s);
1766
1767 uart_port_unlock_irqrestore(port, flags);
1768
1769 return HRTIMER_NORESTART;
1770 }
1771
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1772 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1773 enum dma_transfer_direction dir)
1774 {
1775 struct dma_chan *chan;
1776 struct dma_slave_config cfg;
1777 int ret;
1778
1779 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1780 if (IS_ERR(chan)) {
1781 dev_dbg(port->dev, "dma_request_chan failed\n");
1782 return NULL;
1783 }
1784
1785 memset(&cfg, 0, sizeof(cfg));
1786 cfg.direction = dir;
1787 cfg.dst_addr = port->mapbase +
1788 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1789 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1790 cfg.src_addr = port->mapbase +
1791 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1792 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1793
1794 ret = dmaengine_slave_config(chan, &cfg);
1795 if (ret) {
1796 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1797 dma_release_channel(chan);
1798 return NULL;
1799 }
1800
1801 return chan;
1802 }
1803
sci_request_dma(struct uart_port * port)1804 static void sci_request_dma(struct uart_port *port)
1805 {
1806 struct sci_port *s = to_sci_port(port);
1807 struct tty_port *tport = &port->state->port;
1808 struct dma_chan *chan;
1809
1810 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1811
1812 /*
1813 * DMA on console may interfere with Kernel log messages which use
1814 * plain putchar(). So, simply don't use it with a console.
1815 */
1816 if (uart_console(port))
1817 return;
1818
1819 if (!port->dev->of_node)
1820 return;
1821
1822 s->cookie_tx = -EINVAL;
1823
1824 /*
1825 * Don't request a dma channel if no channel was specified
1826 * in the device tree.
1827 */
1828 if (!of_property_present(port->dev->of_node, "dmas"))
1829 return;
1830
1831 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1832 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1833 if (chan) {
1834 /* UART circular tx buffer is an aligned page. */
1835 s->tx_dma_addr = dma_map_single(chan->device->dev,
1836 tport->xmit_buf,
1837 UART_XMIT_SIZE,
1838 DMA_TO_DEVICE);
1839 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1840 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1841 dma_release_channel(chan);
1842 } else {
1843 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1844 __func__, UART_XMIT_SIZE,
1845 tport->xmit_buf, &s->tx_dma_addr);
1846
1847 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1848 s->chan_tx_saved = s->chan_tx = chan;
1849 }
1850 }
1851
1852 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1853 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1854 if (chan) {
1855 unsigned int i;
1856 dma_addr_t dma;
1857 void *buf;
1858
1859 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1860 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1861 &dma, GFP_KERNEL);
1862 if (!buf) {
1863 dev_warn(port->dev,
1864 "Failed to allocate Rx dma buffer, using PIO\n");
1865 dma_release_channel(chan);
1866 return;
1867 }
1868
1869 for (i = 0; i < 2; i++) {
1870 struct scatterlist *sg = &s->sg_rx[i];
1871
1872 sg_init_table(sg, 1);
1873 s->rx_buf[i] = buf;
1874 sg_dma_address(sg) = dma;
1875 sg_dma_len(sg) = s->buf_len_rx;
1876
1877 buf += s->buf_len_rx;
1878 dma += s->buf_len_rx;
1879 }
1880
1881 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1882
1883 s->chan_rx_saved = s->chan_rx = chan;
1884
1885 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1886 s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1887 sci_dma_rx_submit(s, false);
1888 }
1889 }
1890
sci_free_dma(struct uart_port * port)1891 static void sci_free_dma(struct uart_port *port)
1892 {
1893 struct sci_port *s = to_sci_port(port);
1894
1895 if (s->chan_tx_saved)
1896 sci_dma_tx_release(s);
1897 if (s->chan_rx_saved)
1898 sci_dma_rx_release(s);
1899 }
1900
sci_flush_buffer(struct uart_port * port)1901 static void sci_flush_buffer(struct uart_port *port)
1902 {
1903 struct sci_port *s = to_sci_port(port);
1904
1905 /*
1906 * In uart_flush_buffer(), the xmit circular buffer has just been
1907 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1908 * pending transfers
1909 */
1910 s->tx_dma_len = 0;
1911 if (s->chan_tx) {
1912 dmaengine_terminate_async(s->chan_tx);
1913 s->cookie_tx = -EINVAL;
1914 }
1915 }
1916
sci_dma_check_tx_occurred(struct sci_port * s)1917 static void sci_dma_check_tx_occurred(struct sci_port *s)
1918 {
1919 struct dma_tx_state state;
1920 enum dma_status status;
1921
1922 if (!s->chan_tx || s->cookie_tx <= 0)
1923 return;
1924
1925 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1926 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1927 s->tx_occurred = true;
1928 }
1929 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1930 static inline void sci_request_dma(struct uart_port *port)
1931 {
1932 }
1933
sci_free_dma(struct uart_port * port)1934 static inline void sci_free_dma(struct uart_port *port)
1935 {
1936 }
1937
sci_dma_check_tx_occurred(struct sci_port * s)1938 static void sci_dma_check_tx_occurred(struct sci_port *s)
1939 {
1940 }
1941
1942 #define sci_flush_buffer NULL
1943 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1944
sci_rx_interrupt(int irq,void * ptr)1945 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1946 {
1947 struct uart_port *port = ptr;
1948 struct sci_port *s = to_sci_port(port);
1949
1950 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1951 if (s->chan_rx) {
1952 u16 scr = sci_serial_in(port, SCSCR);
1953 u16 ssr = sci_serial_in(port, SCxSR);
1954
1955 /* Disable future Rx interrupts */
1956 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1957 s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1958 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1959 if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1960 s->ops->set_rtrg(port, 1);
1961 scr |= SCSCR_RIE;
1962 } else {
1963 scr |= SCSCR_RDRQE;
1964 }
1965 } else {
1966 if (sci_dma_rx_submit(s, false) < 0)
1967 goto handle_pio;
1968
1969 scr &= ~SCSCR_RIE;
1970 }
1971 sci_serial_out(port, SCSCR, scr);
1972 /* Clear current interrupt */
1973 sci_serial_out(port, SCxSR,
1974 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1975 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1976 jiffies, s->rx_timeout);
1977 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1978
1979 return IRQ_HANDLED;
1980 }
1981
1982 handle_pio:
1983 #endif
1984
1985 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1986 if (!s->ops->rtrg_enabled(port))
1987 s->ops->set_rtrg(port, s->rx_trigger);
1988
1989 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1990 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1991 }
1992
1993 /* I think sci_receive_chars has to be called irrespective
1994 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1995 * to be disabled?
1996 */
1997 s->ops->receive_chars(port);
1998
1999 return IRQ_HANDLED;
2000 }
2001
sci_tx_interrupt(int irq,void * ptr)2002 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
2003 {
2004 struct uart_port *port = ptr;
2005 unsigned long flags;
2006 struct sci_port *s = to_sci_port(port);
2007
2008 uart_port_lock_irqsave(port, &flags);
2009 s->ops->transmit_chars(port);
2010 uart_port_unlock_irqrestore(port, flags);
2011
2012 return IRQ_HANDLED;
2013 }
2014
sci_tx_end_interrupt(int irq,void * ptr)2015 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
2016 {
2017 struct uart_port *port = ptr;
2018 struct sci_port *s = to_sci_port(port);
2019 const struct sci_common_regs *regs = s->params->common_regs;
2020 unsigned long flags;
2021 u32 ctrl;
2022
2023 if (s->type != PORT_SCI && !sci_is_rsci_type(s->type))
2024 return sci_tx_interrupt(irq, ptr);
2025
2026 uart_port_lock_irqsave(port, &flags);
2027 ctrl = s->ops->read_reg(port, regs->control) &
2028 ~(s->params->param_bits->te_clear);
2029 s->ops->write_reg(port, regs->control, ctrl);
2030 uart_port_unlock_irqrestore(port, flags);
2031
2032 return IRQ_HANDLED;
2033 }
2034
sci_br_interrupt(int irq,void * ptr)2035 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
2036 {
2037 struct uart_port *port = ptr;
2038 struct sci_port *s = to_sci_port(port);
2039
2040 /* Handle BREAKs */
2041 sci_handle_breaks(port);
2042
2043 /* drop invalid character received before break was detected */
2044 sci_serial_in(port, SCxRDR);
2045
2046 s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
2047
2048 return IRQ_HANDLED;
2049 }
2050
sci_er_interrupt(int irq,void * ptr)2051 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
2052 {
2053 struct uart_port *port = ptr;
2054 struct sci_port *s = to_sci_port(port);
2055
2056 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
2057 /* Break and Error interrupts are muxed */
2058 unsigned short ssr_status = sci_serial_in(port, SCxSR);
2059
2060 /* Break Interrupt */
2061 if (ssr_status & SCxSR_BRK(port))
2062 sci_br_interrupt(irq, ptr);
2063
2064 /* Break only? */
2065 if (!(ssr_status & SCxSR_ERRORS(port)))
2066 return IRQ_HANDLED;
2067 }
2068
2069 /* Handle errors */
2070 if (s->type == PORT_SCI) {
2071 if (sci_handle_errors(port)) {
2072 /* discard character in rx buffer */
2073 sci_serial_in(port, SCxSR);
2074 s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
2075 }
2076 } else {
2077 sci_handle_fifo_overrun(port);
2078 if (!s->chan_rx)
2079 s->ops->receive_chars(port);
2080 }
2081
2082 s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
2083
2084 /* Kick the transmission */
2085 if (!s->chan_tx)
2086 sci_tx_interrupt(irq, ptr);
2087
2088 return IRQ_HANDLED;
2089 }
2090
sci_mpxed_interrupt(int irq,void * ptr)2091 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
2092 {
2093 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
2094 struct uart_port *port = ptr;
2095 struct sci_port *s = to_sci_port(port);
2096 irqreturn_t ret = IRQ_NONE;
2097
2098 ssr_status = sci_serial_in(port, SCxSR);
2099 scr_status = sci_serial_in(port, SCSCR);
2100 if (s->params->overrun_reg == SCxSR)
2101 orer_status = ssr_status;
2102 else if (sci_getreg(port, s->params->overrun_reg)->size)
2103 orer_status = sci_serial_in(port, s->params->overrun_reg);
2104
2105 err_enabled = scr_status & port_rx_irq_mask(port);
2106
2107 /* Tx Interrupt */
2108 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
2109 !s->chan_tx)
2110 ret = sci_tx_interrupt(irq, ptr);
2111
2112 /*
2113 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
2114 * DR flags
2115 */
2116 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
2117 (scr_status & SCSCR_RIE))
2118 ret = sci_rx_interrupt(irq, ptr);
2119
2120 /* Error Interrupt */
2121 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
2122 ret = sci_er_interrupt(irq, ptr);
2123
2124 /* Break Interrupt */
2125 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
2126 (ssr_status & SCxSR_BRK(port)) && err_enabled)
2127 ret = sci_br_interrupt(irq, ptr);
2128
2129 /* Overrun Interrupt */
2130 if (orer_status & s->params->overrun_mask) {
2131 sci_handle_fifo_overrun(port);
2132 ret = IRQ_HANDLED;
2133 }
2134
2135 return ret;
2136 }
2137
2138 static const struct sci_irq_desc {
2139 const char *desc;
2140 irq_handler_t handler;
2141 } sci_irq_desc[] = {
2142 /*
2143 * Split out handlers, the default case.
2144 */
2145 [SCIx_ERI_IRQ] = {
2146 .desc = "rx err",
2147 .handler = sci_er_interrupt,
2148 },
2149
2150 [SCIx_RXI_IRQ] = {
2151 .desc = "rx full",
2152 .handler = sci_rx_interrupt,
2153 },
2154
2155 [SCIx_TXI_IRQ] = {
2156 .desc = "tx empty",
2157 .handler = sci_tx_interrupt,
2158 },
2159
2160 [SCIx_BRI_IRQ] = {
2161 .desc = "break",
2162 .handler = sci_br_interrupt,
2163 },
2164
2165 [SCIx_DRI_IRQ] = {
2166 .desc = "rx ready",
2167 .handler = sci_rx_interrupt,
2168 },
2169
2170 [SCIx_TEI_IRQ] = {
2171 .desc = "tx end",
2172 .handler = sci_tx_end_interrupt,
2173 },
2174
2175 /*
2176 * Special muxed handler.
2177 */
2178 [SCIx_MUX_IRQ] = {
2179 .desc = "mux",
2180 .handler = sci_mpxed_interrupt,
2181 },
2182 };
2183
sci_request_irq(struct sci_port * port)2184 static int sci_request_irq(struct sci_port *port)
2185 {
2186 struct uart_port *up = &port->port;
2187 int i, j, w, ret = 0;
2188
2189 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2190 const struct sci_irq_desc *desc;
2191 int irq;
2192
2193 /* Check if already registered (muxed) */
2194 for (w = 0; w < i; w++)
2195 if (port->irqs[w] == port->irqs[i])
2196 w = i + 1;
2197 if (w > i)
2198 continue;
2199
2200 if (SCIx_IRQ_IS_MUXED(port)) {
2201 i = SCIx_MUX_IRQ;
2202 irq = up->irq;
2203 } else {
2204 irq = port->irqs[i];
2205
2206 /*
2207 * Certain port types won't support all of the
2208 * available interrupt sources.
2209 */
2210 if (unlikely(irq < 0))
2211 continue;
2212 }
2213
2214 desc = sci_irq_desc + i;
2215 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2216 dev_name(up->dev), desc->desc);
2217 if (!port->irqstr[j]) {
2218 ret = -ENOMEM;
2219 goto out_nomem;
2220 }
2221
2222 ret = request_irq(irq, desc->handler, up->irqflags,
2223 port->irqstr[j], port);
2224 if (unlikely(ret)) {
2225 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2226 goto out_noirq;
2227 }
2228 }
2229
2230 return 0;
2231
2232 out_noirq:
2233 while (--i >= 0)
2234 free_irq(port->irqs[i], port);
2235
2236 out_nomem:
2237 while (--j >= 0)
2238 kfree(port->irqstr[j]);
2239
2240 return ret;
2241 }
2242
sci_free_irq(struct sci_port * port)2243 static void sci_free_irq(struct sci_port *port)
2244 {
2245 int i, j;
2246
2247 /*
2248 * Intentionally in reverse order so we iterate over the muxed
2249 * IRQ first.
2250 */
2251 for (i = 0; i < SCIx_NR_IRQS; i++) {
2252 int irq = port->irqs[i];
2253
2254 /*
2255 * Certain port types won't support all of the available
2256 * interrupt sources.
2257 */
2258 if (unlikely(irq < 0))
2259 continue;
2260
2261 /* Check if already freed (irq was muxed) */
2262 for (j = 0; j < i; j++)
2263 if (port->irqs[j] == irq)
2264 j = i + 1;
2265 if (j > i)
2266 continue;
2267
2268 free_irq(port->irqs[i], port);
2269 kfree(port->irqstr[i]);
2270
2271 if (SCIx_IRQ_IS_MUXED(port)) {
2272 /* If there's only one IRQ, we're done. */
2273 return;
2274 }
2275 }
2276 }
2277
sci_tx_empty(struct uart_port * port)2278 static unsigned int sci_tx_empty(struct uart_port *port)
2279 {
2280 unsigned short status = sci_serial_in(port, SCxSR);
2281 unsigned short in_tx_fifo = sci_txfill(port);
2282 struct sci_port *s = to_sci_port(port);
2283
2284 sci_dma_check_tx_occurred(s);
2285
2286 if (!s->tx_occurred)
2287 return TIOCSER_TEMT;
2288
2289 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2290 }
2291
sci_set_rts(struct uart_port * port,bool state)2292 static void sci_set_rts(struct uart_port *port, bool state)
2293 {
2294 struct sci_port *s = to_sci_port(port);
2295
2296 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2297 u16 data = sci_serial_in(port, SCPDR);
2298
2299 /* Active low */
2300 if (state)
2301 data &= ~SCPDR_RTSD;
2302 else
2303 data |= SCPDR_RTSD;
2304 sci_serial_out(port, SCPDR, data);
2305
2306 /* RTS# is output */
2307 sci_serial_out(port, SCPCR,
2308 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2309 } else if (sci_getreg(port, SCSPTR)->size) {
2310 u16 ctrl = sci_serial_in(port, SCSPTR);
2311
2312 /* Active low */
2313 if (state)
2314 ctrl &= ~SCSPTR_RTSDT;
2315 else
2316 ctrl |= SCSPTR_RTSDT;
2317 sci_serial_out(port, SCSPTR, ctrl);
2318 }
2319 }
2320
sci_get_cts(struct uart_port * port)2321 static bool sci_get_cts(struct uart_port *port)
2322 {
2323 struct sci_port *s = to_sci_port(port);
2324
2325 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2326 /* Active low */
2327 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2328 } else if (sci_getreg(port, SCSPTR)->size) {
2329 /* Active low */
2330 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2331 }
2332
2333 return true;
2334 }
2335
2336 /*
2337 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2338 * CTS/RTS is supported in hardware by at least one port and controlled
2339 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2340 * handled via the ->init_pins() op, which is a bit of a one-way street,
2341 * lacking any ability to defer pin control -- this will later be
2342 * converted over to the GPIO framework).
2343 *
2344 * Other modes (such as loopback) are supported generically on certain
2345 * port types, but not others. For these it's sufficient to test for the
2346 * existence of the support register and simply ignore the port type.
2347 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2348 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2349 {
2350 struct sci_port *s = to_sci_port(port);
2351
2352 if (mctrl & TIOCM_LOOP) {
2353 const struct plat_sci_reg *reg;
2354
2355 /*
2356 * Standard loopback mode for SCFCR ports.
2357 */
2358 reg = sci_getreg(port, SCFCR);
2359 if (reg->size)
2360 sci_serial_out(port, SCFCR,
2361 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2362 }
2363
2364 mctrl_gpio_set(s->gpios, mctrl);
2365
2366 if (!s->has_rtscts)
2367 return;
2368
2369 if (!(mctrl & TIOCM_RTS)) {
2370 /* Disable Auto RTS */
2371 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2372 sci_serial_out(port, SCFCR,
2373 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2374
2375 /* Clear RTS */
2376 sci_set_rts(port, 0);
2377 } else if (s->autorts) {
2378 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2379 /* Enable RTS# pin function */
2380 sci_serial_out(port, SCPCR,
2381 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2382 }
2383
2384 /* Enable Auto RTS */
2385 if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2386 sci_serial_out(port, SCFCR,
2387 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2388 } else {
2389 /* Set RTS */
2390 sci_set_rts(port, 1);
2391 }
2392 }
2393
sci_get_mctrl(struct uart_port * port)2394 static unsigned int sci_get_mctrl(struct uart_port *port)
2395 {
2396 struct sci_port *s = to_sci_port(port);
2397 struct mctrl_gpios *gpios = s->gpios;
2398 unsigned int mctrl = 0;
2399
2400 mctrl_gpio_get(gpios, &mctrl);
2401
2402 /*
2403 * CTS/RTS is handled in hardware when supported, while nothing
2404 * else is wired up.
2405 */
2406 if (s->autorts) {
2407 if (sci_get_cts(port))
2408 mctrl |= TIOCM_CTS;
2409 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2410 mctrl |= TIOCM_CTS;
2411 }
2412 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2413 mctrl |= TIOCM_DSR;
2414 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2415 mctrl |= TIOCM_CAR;
2416
2417 return mctrl;
2418 }
2419
sci_enable_ms(struct uart_port * port)2420 static void sci_enable_ms(struct uart_port *port)
2421 {
2422 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2423 }
2424
sci_break_ctl(struct uart_port * port,int break_state)2425 static void sci_break_ctl(struct uart_port *port, int break_state)
2426 {
2427 unsigned short scscr, scsptr;
2428 unsigned long flags;
2429
2430 /* check whether the port has SCSPTR */
2431 if (!sci_getreg(port, SCSPTR)->size) {
2432 /*
2433 * Not supported by hardware. Most parts couple break and rx
2434 * interrupts together, with break detection always enabled.
2435 */
2436 return;
2437 }
2438
2439 uart_port_lock_irqsave(port, &flags);
2440 scsptr = sci_serial_in(port, SCSPTR);
2441 scscr = sci_serial_in(port, SCSCR);
2442
2443 if (break_state == -1) {
2444 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2445 scscr &= ~SCSCR_TE;
2446 } else {
2447 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2448 scscr |= SCSCR_TE;
2449 }
2450
2451 sci_serial_out(port, SCSPTR, scsptr);
2452 sci_serial_out(port, SCSCR, scscr);
2453 uart_port_unlock_irqrestore(port, flags);
2454 }
2455
sci_shutdown_complete(struct uart_port * port)2456 static void sci_shutdown_complete(struct uart_port *port)
2457 {
2458 struct sci_port *s = to_sci_port(port);
2459 u16 scr;
2460
2461 scr = sci_serial_in(port, SCSCR);
2462 sci_serial_out(port, SCSCR,
2463 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2464 }
2465
sci_startup(struct uart_port * port)2466 int sci_startup(struct uart_port *port)
2467 {
2468 struct sci_port *s = to_sci_port(port);
2469 int ret;
2470
2471 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2472
2473 s->tx_occurred = false;
2474 sci_request_dma(port);
2475
2476 ret = sci_request_irq(s);
2477 if (unlikely(ret < 0)) {
2478 sci_free_dma(port);
2479 return ret;
2480 }
2481
2482 return 0;
2483 }
2484 EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI");
2485
sci_shutdown(struct uart_port * port)2486 void sci_shutdown(struct uart_port *port)
2487 {
2488 struct sci_port *s = to_sci_port(port);
2489 unsigned long flags;
2490
2491 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2492
2493 s->autorts = false;
2494 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2495
2496 uart_port_lock_irqsave(port, &flags);
2497 s->port.ops->stop_rx(port);
2498 s->port.ops->stop_tx(port);
2499 s->ops->shutdown_complete(port);
2500 uart_port_unlock_irqrestore(port, flags);
2501
2502 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2503 if (s->chan_rx_saved) {
2504 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2505 port->line);
2506 hrtimer_cancel(&s->rx_timer);
2507 }
2508 #endif
2509
2510 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2511 timer_delete_sync(&s->rx_fifo_timer);
2512 sci_free_irq(s);
2513 sci_free_dma(port);
2514 }
2515 EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI");
2516
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2517 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2518 unsigned int *srr)
2519 {
2520 unsigned long freq = s->clk_rates[SCI_SCK];
2521 int err, min_err = INT_MAX;
2522 unsigned int sr;
2523
2524 if (s->type != PORT_HSCIF)
2525 freq *= 2;
2526
2527 for_each_sr(sr, s) {
2528 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2529 if (abs(err) >= abs(min_err))
2530 continue;
2531
2532 min_err = err;
2533 *srr = sr - 1;
2534
2535 if (!err)
2536 break;
2537 }
2538
2539 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2540 *srr + 1);
2541 return min_err;
2542 }
2543
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2544 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2545 unsigned long freq, unsigned int *dlr,
2546 unsigned int *srr)
2547 {
2548 int err, min_err = INT_MAX;
2549 unsigned int sr, dl;
2550
2551 if (s->type != PORT_HSCIF)
2552 freq *= 2;
2553
2554 for_each_sr(sr, s) {
2555 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2556 dl = clamp(dl, 1U, 65535U);
2557
2558 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2559 if (abs(err) >= abs(min_err))
2560 continue;
2561
2562 min_err = err;
2563 *dlr = dl;
2564 *srr = sr - 1;
2565
2566 if (!err)
2567 break;
2568 }
2569
2570 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2571 min_err, *dlr, *srr + 1);
2572 return min_err;
2573 }
2574
2575 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2576 int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr,
2577 unsigned int *srr, unsigned int *cks)
2578 {
2579 unsigned long freq = s->clk_rates[SCI_FCK];
2580 unsigned int sr, br, prediv, scrate, c;
2581 int err, min_err = INT_MAX;
2582
2583 if (s->type != PORT_HSCIF)
2584 freq *= 2;
2585
2586 /*
2587 * Find the combination of sample rate and clock select with the
2588 * smallest deviation from the desired baud rate.
2589 * Prefer high sample rates to maximise the receive margin.
2590 *
2591 * M: Receive margin (%)
2592 * N: Ratio of bit rate to clock (N = sampling rate)
2593 * D: Clock duty (D = 0 to 1.0)
2594 * L: Frame length (L = 9 to 12)
2595 * F: Absolute value of clock frequency deviation
2596 *
2597 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2598 * (|D - 0.5| / N * (1 + F))|
2599 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2600 */
2601 for_each_sr(sr, s) {
2602 for (c = 0; c <= 3; c++) {
2603 /* integerized formulas from HSCIF documentation */
2604 prediv = sr << (2 * c + 1);
2605
2606 /*
2607 * We need to calculate:
2608 *
2609 * br = freq / (prediv * bps) clamped to [1..256]
2610 * err = freq / (br * prediv) - bps
2611 *
2612 * Watch out for overflow when calculating the desired
2613 * sampling clock rate!
2614 */
2615 if (bps > UINT_MAX / prediv)
2616 break;
2617
2618 scrate = prediv * bps;
2619 br = DIV_ROUND_CLOSEST(freq, scrate);
2620 br = clamp(br, 1U, 256U);
2621
2622 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2623 if (abs(err) >= abs(min_err))
2624 continue;
2625
2626 min_err = err;
2627 *brr = br - 1;
2628 *srr = sr - 1;
2629 *cks = c;
2630
2631 if (!err)
2632 goto found;
2633 }
2634 }
2635
2636 found:
2637 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2638 min_err, *brr, *srr + 1, *cks);
2639 return min_err;
2640 }
2641 EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI");
2642
sci_reset(struct uart_port * port)2643 static void sci_reset(struct uart_port *port)
2644 {
2645 const struct plat_sci_reg *reg;
2646 unsigned int status;
2647 struct sci_port *s = to_sci_port(port);
2648
2649 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2650
2651 reg = sci_getreg(port, SCFCR);
2652 if (reg->size)
2653 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2654
2655 s->ops->clear_SCxSR(port,
2656 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2657 SCxSR_BREAK_CLEAR(port));
2658 if (sci_getreg(port, SCLSR)->size) {
2659 status = sci_serial_in(port, SCLSR);
2660 status &= ~(SCLSR_TO | SCLSR_ORER);
2661 sci_serial_out(port, SCLSR, status);
2662 }
2663
2664 if (s->rx_trigger > 1) {
2665 if (s->rx_fifo_timeout) {
2666 s->ops->set_rtrg(port, 1);
2667 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2668 } else {
2669 if (s->type == PORT_SCIFA ||
2670 s->type == PORT_SCIFB)
2671 s->ops->set_rtrg(port, 1);
2672 else
2673 s->ops->set_rtrg(port, s->rx_trigger);
2674 }
2675 }
2676 }
2677
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2678 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2679 const struct ktermios *old)
2680 {
2681 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2682 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2683 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2684 struct sci_port *s = to_sci_port(port);
2685 const struct plat_sci_reg *reg;
2686 int min_err = INT_MAX, err;
2687 unsigned long max_freq = 0;
2688 int best_clk = -1;
2689 unsigned long flags;
2690
2691 if ((termios->c_cflag & CSIZE) == CS7) {
2692 smr_val |= SCSMR_CHR;
2693 } else {
2694 termios->c_cflag &= ~CSIZE;
2695 termios->c_cflag |= CS8;
2696 }
2697 if (termios->c_cflag & PARENB)
2698 smr_val |= SCSMR_PE;
2699 if (termios->c_cflag & PARODD)
2700 smr_val |= SCSMR_PE | SCSMR_ODD;
2701 if (termios->c_cflag & CSTOPB)
2702 smr_val |= SCSMR_STOP;
2703
2704 /*
2705 * earlyprintk comes here early on with port->uartclk set to zero.
2706 * the clock framework is not up and running at this point so here
2707 * we assume that 115200 is the maximum baud rate. please note that
2708 * the baud rate is not programmed during earlyprintk - it is assumed
2709 * that the previous boot loader has enabled required clocks and
2710 * setup the baud rate generator hardware for us already.
2711 */
2712 if (!port->uartclk) {
2713 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2714 goto done;
2715 }
2716
2717 for (i = 0; i < SCI_NUM_CLKS; i++)
2718 max_freq = max(max_freq, s->clk_rates[i]);
2719
2720 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2721 if (!baud)
2722 goto done;
2723
2724 /*
2725 * There can be multiple sources for the sampling clock. Find the one
2726 * that gives us the smallest deviation from the desired baud rate.
2727 */
2728
2729 /* Optional Undivided External Clock */
2730 if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA &&
2731 s->type != PORT_SCIFB) {
2732 err = sci_sck_calc(s, baud, &srr1);
2733 if (abs(err) < abs(min_err)) {
2734 best_clk = SCI_SCK;
2735 scr_val = SCSCR_CKE1;
2736 sccks = SCCKS_CKS;
2737 min_err = err;
2738 srr = srr1;
2739 if (!err)
2740 goto done;
2741 }
2742 }
2743
2744 /* Optional BRG Frequency Divided External Clock */
2745 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2746 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2747 &srr1);
2748 if (abs(err) < abs(min_err)) {
2749 best_clk = SCI_SCIF_CLK;
2750 scr_val = SCSCR_CKE1;
2751 sccks = 0;
2752 min_err = err;
2753 dl = dl1;
2754 srr = srr1;
2755 if (!err)
2756 goto done;
2757 }
2758 }
2759
2760 /* Optional BRG Frequency Divided Internal Clock */
2761 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2762 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2763 &srr1);
2764 if (abs(err) < abs(min_err)) {
2765 best_clk = SCI_BRG_INT;
2766 scr_val = SCSCR_CKE1;
2767 sccks = SCCKS_XIN;
2768 min_err = err;
2769 dl = dl1;
2770 srr = srr1;
2771 if (!min_err)
2772 goto done;
2773 }
2774 }
2775
2776 /* Divided Functional Clock using standard Bit Rate Register */
2777 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2778 if (abs(err) < abs(min_err)) {
2779 best_clk = SCI_FCK;
2780 scr_val = 0;
2781 min_err = err;
2782 brr = brr1;
2783 srr = srr1;
2784 cks = cks1;
2785 }
2786
2787 done:
2788 if (best_clk >= 0)
2789 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2790 s->clks[best_clk], baud, min_err);
2791
2792 sci_port_enable(s);
2793
2794 /*
2795 * Program the optional External Baud Rate Generator (BRG) first.
2796 * It controls the mux to select (H)SCK or frequency divided clock.
2797 */
2798 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2799 sci_serial_out(port, SCDL, dl);
2800 sci_serial_out(port, SCCKS, sccks);
2801 }
2802
2803 uart_port_lock_irqsave(port, &flags);
2804
2805 sci_reset(port);
2806
2807 uart_update_timeout(port, termios->c_cflag, baud);
2808
2809 /* byte size and parity */
2810 bits = tty_get_frame_size(termios->c_cflag);
2811
2812 if (sci_getreg(port, SEMR)->size)
2813 sci_serial_out(port, SEMR, 0);
2814
2815 if (best_clk >= 0) {
2816 if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
2817 switch (srr + 1) {
2818 case 5: smr_val |= SCSMR_SRC_5; break;
2819 case 7: smr_val |= SCSMR_SRC_7; break;
2820 case 11: smr_val |= SCSMR_SRC_11; break;
2821 case 13: smr_val |= SCSMR_SRC_13; break;
2822 case 16: smr_val |= SCSMR_SRC_16; break;
2823 case 17: smr_val |= SCSMR_SRC_17; break;
2824 case 19: smr_val |= SCSMR_SRC_19; break;
2825 case 27: smr_val |= SCSMR_SRC_27; break;
2826 }
2827 smr_val |= cks;
2828 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2829 sci_serial_out(port, SCSMR, smr_val);
2830 sci_serial_out(port, SCBRR, brr);
2831 if (sci_getreg(port, HSSRR)->size) {
2832 unsigned int hssrr = srr | HSCIF_SRE;
2833 /* Calculate deviation from intended rate at the
2834 * center of the last stop bit in sampling clocks.
2835 */
2836 int last_stop = bits * 2 - 1;
2837 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2838 (int)(srr + 1),
2839 2 * (int)baud);
2840
2841 if (abs(deviation) >= 2) {
2842 /* At least two sampling clocks off at the
2843 * last stop bit; we can increase the error
2844 * margin by shifting the sampling point.
2845 */
2846 int shift = clamp(deviation / 2, -8, 7);
2847
2848 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2849 HSCIF_SRHP_MASK;
2850 hssrr |= HSCIF_SRDE;
2851 }
2852 sci_serial_out(port, HSSRR, hssrr);
2853 }
2854
2855 /* Wait one bit interval */
2856 udelay((1000000 + (baud - 1)) / baud);
2857 } else {
2858 /* Don't touch the bit rate configuration */
2859 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2860 smr_val |= sci_serial_in(port, SCSMR) &
2861 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2862 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2863 sci_serial_out(port, SCSMR, smr_val);
2864 }
2865
2866 sci_init_pins(port, termios->c_cflag);
2867
2868 port->status &= ~UPSTAT_AUTOCTS;
2869 s->autorts = false;
2870 reg = sci_getreg(port, SCFCR);
2871 if (reg->size) {
2872 unsigned short ctrl = sci_serial_in(port, SCFCR);
2873
2874 if ((port->flags & UPF_HARD_FLOW) &&
2875 (termios->c_cflag & CRTSCTS)) {
2876 /* There is no CTS interrupt to restart the hardware */
2877 port->status |= UPSTAT_AUTOCTS;
2878 /* MCE is enabled when RTS is raised */
2879 s->autorts = true;
2880 }
2881
2882 /*
2883 * As we've done a sci_reset() above, ensure we don't
2884 * interfere with the FIFOs while toggling MCE. As the
2885 * reset values could still be set, simply mask them out.
2886 */
2887 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2888
2889 sci_serial_out(port, SCFCR, ctrl);
2890 }
2891 if (port->flags & UPF_HARD_FLOW) {
2892 /* Refresh (Auto) RTS */
2893 sci_set_mctrl(port, port->mctrl);
2894 }
2895
2896 /*
2897 * For SCI, TE (transmit enable) must be set after setting TIE
2898 * (transmit interrupt enable) or in the same instruction to
2899 * start the transmitting process. So skip setting TE here for SCI.
2900 */
2901 if (s->type != PORT_SCI)
2902 scr_val |= SCSCR_TE;
2903 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2904 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2905 if ((srr + 1 == 5) &&
2906 (s->type == PORT_SCIFA || s->type == PORT_SCIFB)) {
2907 /*
2908 * In asynchronous mode, when the sampling rate is 1/5, first
2909 * received data may become invalid on some SCIFA and SCIFB.
2910 * To avoid this problem wait more than 1 serial data time (1
2911 * bit time x serial data number) after setting SCSCR.RE = 1.
2912 */
2913 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2914 }
2915
2916 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2917 s->rx_frame = (10000 * bits) / (baud / 100);
2918 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2919 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2920 #endif
2921
2922 if ((termios->c_cflag & CREAD) != 0)
2923 sci_start_rx(port);
2924
2925 uart_port_unlock_irqrestore(port, flags);
2926
2927 sci_port_disable(s);
2928
2929 if (UART_ENABLE_MS(port, termios->c_cflag))
2930 sci_enable_ms(port);
2931 }
2932
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2933 void sci_pm(struct uart_port *port, unsigned int state,
2934 unsigned int oldstate)
2935 {
2936 struct sci_port *sci_port = to_sci_port(port);
2937
2938 switch (state) {
2939 case UART_PM_STATE_OFF:
2940 sci_port_disable(sci_port);
2941 break;
2942 default:
2943 sci_port_enable(sci_port);
2944 break;
2945 }
2946 }
2947 EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI");
2948
sci_type(struct uart_port * port)2949 static const char *sci_type(struct uart_port *port)
2950 {
2951 struct sci_port *s = to_sci_port(port);
2952
2953 switch (s->type) {
2954 case PORT_IRDA:
2955 return "irda";
2956 case PORT_SCI:
2957 return "sci";
2958 case PORT_SCIF:
2959 return "scif";
2960 case PORT_SCIFA:
2961 return "scifa";
2962 case PORT_SCIFB:
2963 return "scifb";
2964 case PORT_HSCIF:
2965 return "hscif";
2966 }
2967
2968 return NULL;
2969 }
2970
sci_remap_port(struct uart_port * port)2971 static int sci_remap_port(struct uart_port *port)
2972 {
2973 struct sci_port *sport = to_sci_port(port);
2974
2975 /*
2976 * Nothing to do if there's already an established membase.
2977 */
2978 if (port->membase)
2979 return 0;
2980
2981 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2982 port->membase = ioremap(port->mapbase, sport->reg_size);
2983 if (unlikely(!port->membase)) {
2984 dev_err(port->dev, "can't remap port#%d\n", port->line);
2985 return -ENXIO;
2986 }
2987 } else {
2988 /*
2989 * For the simple (and majority of) cases where we don't
2990 * need to do any remapping, just cast the cookie
2991 * directly.
2992 */
2993 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2994 }
2995
2996 return 0;
2997 }
2998
sci_release_port(struct uart_port * port)2999 void sci_release_port(struct uart_port *port)
3000 {
3001 struct sci_port *sport = to_sci_port(port);
3002
3003 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
3004 iounmap(port->membase);
3005 port->membase = NULL;
3006 }
3007
3008 release_mem_region(port->mapbase, sport->reg_size);
3009 }
3010 EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI");
3011
sci_request_port(struct uart_port * port)3012 int sci_request_port(struct uart_port *port)
3013 {
3014 struct resource *res;
3015 struct sci_port *sport = to_sci_port(port);
3016 int ret;
3017
3018 res = request_mem_region(port->mapbase, sport->reg_size,
3019 dev_name(port->dev));
3020 if (unlikely(res == NULL)) {
3021 dev_err(port->dev, "request_mem_region failed.");
3022 return -EBUSY;
3023 }
3024
3025 ret = sci_remap_port(port);
3026 if (unlikely(ret != 0)) {
3027 release_resource(res);
3028 return ret;
3029 }
3030
3031 return 0;
3032 }
3033 EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI");
3034
sci_config_port(struct uart_port * port,int flags)3035 void sci_config_port(struct uart_port *port, int flags)
3036 {
3037 if (flags & UART_CONFIG_TYPE) {
3038 struct sci_port *sport = to_sci_port(port);
3039 port->type = SCI_PUBLIC_PORT_ID(sport->type);
3040 sci_request_port(port);
3041 }
3042 }
3043 EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI");
3044
sci_verify_port(struct uart_port * port,struct serial_struct * ser)3045 int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
3046 {
3047 if (ser->baud_base < 2400)
3048 /* No paper tape reader for Mitch.. */
3049 return -EINVAL;
3050
3051 return 0;
3052 }
3053 EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI");
3054
sci_prepare_console_write(struct uart_port * port,u32 ctrl)3055 static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
3056 {
3057 struct sci_port *s = to_sci_port(port);
3058 u32 ctrl_temp =
3059 s->params->param_bits->rxtx_enable |
3060 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3061 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)) |
3062 s->hscif_tot;
3063 sci_serial_out(port, SCSCR, ctrl_temp);
3064 }
3065
sci_console_save(struct uart_port * port)3066 static void sci_console_save(struct uart_port *port)
3067 {
3068 struct sci_port *s = to_sci_port(port);
3069 struct sci_suspend_regs *regs = s->suspend_regs;
3070
3071 if (sci_getreg(port, SCDL)->size)
3072 regs->scdl = sci_serial_in(port, SCDL);
3073 if (sci_getreg(port, SCCKS)->size)
3074 regs->sccks = sci_serial_in(port, SCCKS);
3075 if (sci_getreg(port, SCSMR)->size)
3076 regs->scsmr = sci_serial_in(port, SCSMR);
3077 if (sci_getreg(port, SCSCR)->size)
3078 regs->scscr = sci_serial_in(port, SCSCR);
3079 if (sci_getreg(port, SCFCR)->size)
3080 regs->scfcr = sci_serial_in(port, SCFCR);
3081 if (sci_getreg(port, SCSPTR)->size)
3082 regs->scsptr = sci_serial_in(port, SCSPTR);
3083 if (sci_getreg(port, SCBRR)->size)
3084 regs->scbrr = sci_serial_in(port, SCBRR);
3085 if (sci_getreg(port, HSSRR)->size)
3086 regs->hssrr = sci_serial_in(port, HSSRR);
3087 if (sci_getreg(port, SCPCR)->size)
3088 regs->scpcr = sci_serial_in(port, SCPCR);
3089 if (sci_getreg(port, SCPDR)->size)
3090 regs->scpdr = sci_serial_in(port, SCPDR);
3091 if (sci_getreg(port, SEMR)->size)
3092 regs->semr = sci_serial_in(port, SEMR);
3093 }
3094
sci_console_restore(struct uart_port * port)3095 static void sci_console_restore(struct uart_port *port)
3096 {
3097 struct sci_port *s = to_sci_port(port);
3098 struct sci_suspend_regs *regs = s->suspend_regs;
3099
3100 if (sci_getreg(port, SCDL)->size)
3101 sci_serial_out(port, SCDL, regs->scdl);
3102 if (sci_getreg(port, SCCKS)->size)
3103 sci_serial_out(port, SCCKS, regs->sccks);
3104 if (sci_getreg(port, SCSMR)->size)
3105 sci_serial_out(port, SCSMR, regs->scsmr);
3106 if (sci_getreg(port, SCSCR)->size)
3107 sci_serial_out(port, SCSCR, regs->scscr);
3108 if (sci_getreg(port, SCFCR)->size)
3109 sci_serial_out(port, SCFCR, regs->scfcr);
3110 if (sci_getreg(port, SCSPTR)->size)
3111 sci_serial_out(port, SCSPTR, regs->scsptr);
3112 if (sci_getreg(port, SCBRR)->size)
3113 sci_serial_out(port, SCBRR, regs->scbrr);
3114 if (sci_getreg(port, HSSRR)->size)
3115 sci_serial_out(port, HSSRR, regs->hssrr);
3116 if (sci_getreg(port, SCPCR)->size)
3117 sci_serial_out(port, SCPCR, regs->scpcr);
3118 if (sci_getreg(port, SCPDR)->size)
3119 sci_serial_out(port, SCPDR, regs->scpdr);
3120 if (sci_getreg(port, SEMR)->size)
3121 sci_serial_out(port, SEMR, regs->semr);
3122 }
3123
3124 static const struct uart_ops sci_uart_ops = {
3125 .tx_empty = sci_tx_empty,
3126 .set_mctrl = sci_set_mctrl,
3127 .get_mctrl = sci_get_mctrl,
3128 .start_tx = sci_start_tx,
3129 .stop_tx = sci_stop_tx,
3130 .stop_rx = sci_stop_rx,
3131 .enable_ms = sci_enable_ms,
3132 .break_ctl = sci_break_ctl,
3133 .startup = sci_startup,
3134 .shutdown = sci_shutdown,
3135 .flush_buffer = sci_flush_buffer,
3136 .set_termios = sci_set_termios,
3137 .pm = sci_pm,
3138 .type = sci_type,
3139 .release_port = sci_release_port,
3140 .request_port = sci_request_port,
3141 .config_port = sci_config_port,
3142 .verify_port = sci_verify_port,
3143 #ifdef CONFIG_CONSOLE_POLL
3144 .poll_get_char = sci_poll_get_char,
3145 .poll_put_char = sci_poll_put_char,
3146 #endif
3147 };
3148
3149 static const struct sci_port_ops sci_port_ops = {
3150 .read_reg = sci_serial_in,
3151 .write_reg = sci_serial_out,
3152 .clear_SCxSR = sci_clear_SCxSR,
3153 .transmit_chars = sci_transmit_chars,
3154 .receive_chars = sci_receive_chars,
3155 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3156 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3157 .poll_put_char = sci_poll_put_char,
3158 #endif
3159 .set_rtrg = scif_set_rtrg,
3160 .rtrg_enabled = scif_rtrg_enabled,
3161 .shutdown_complete = sci_shutdown_complete,
3162 .prepare_console_write = sci_prepare_console_write,
3163 .console_save = sci_console_save,
3164 .console_restore = sci_console_restore,
3165 .suspend_regs_size = sci_suspend_regs_size,
3166 };
3167
sci_init_clocks(struct sci_port * sci_port,struct device * dev)3168 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
3169 {
3170 const char *clk_names[] = {
3171 [SCI_FCK] = "fck",
3172 [SCI_SCK] = "sck",
3173 [SCI_BRG_INT] = "brg_int",
3174 [SCI_SCIF_CLK] = "scif_clk",
3175 [SCI_FCK_DIV4] = "tclk_div4",
3176 [SCI_FCK_DIV16] = "tclk_div16",
3177 [SCI_FCK_DIV64] = "tclk_div64",
3178 };
3179 struct clk *clk;
3180 unsigned int i;
3181
3182 if (sci_port->type == PORT_HSCIF) {
3183 clk_names[SCI_SCK] = "hsck";
3184 } else if (sci_port->type == RSCI_PORT_SCIF16) {
3185 clk_names[SCI_FCK] = "operation";
3186 clk_names[SCI_BRG_INT] = "bus";
3187 } else if (sci_port->type == RSCI_PORT_SCIF32) {
3188 clk_names[SCI_FCK] = "tclk";
3189 clk_names[SCI_BRG_INT] = "pclk";
3190 }
3191
3192 for (i = 0; i < SCI_NUM_CLKS; i++) {
3193 const char *name = clk_names[i];
3194
3195 clk = devm_clk_get_optional(dev, name);
3196 if (IS_ERR(clk))
3197 return PTR_ERR(clk);
3198
3199 if (!clk && sci_port->type == RSCI_PORT_SCIF16 &&
3200 (i == SCI_FCK || i == SCI_BRG_INT))
3201 return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
3202
3203 if (!clk && sci_port->type == RSCI_PORT_SCIF32 &&
3204 (i != SCI_SCK && i != SCI_SCIF_CLK))
3205 return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
3206
3207 if (!clk && i == SCI_FCK) {
3208 /*
3209 * Not all SH platforms declare a clock lookup entry
3210 * for SCI devices, in which case we need to get the
3211 * global "peripheral_clk" clock.
3212 */
3213 clk = devm_clk_get(dev, "peripheral_clk");
3214 if (IS_ERR(clk))
3215 return dev_err_probe(dev, PTR_ERR(clk), "failed to get %s\n", name);
3216 }
3217
3218 if (!clk)
3219 dev_dbg(dev, "failed to get %s\n", name);
3220 else
3221 dev_dbg(dev, "clk %s is %pC rate %lu\n", name, clk, clk_get_rate(clk));
3222 sci_port->clks[i] = clk;
3223 }
3224 return 0;
3225 }
3226
3227 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg,struct sci_port * sci_port)3228 sci_probe_regmap(const struct plat_sci_port *cfg, struct sci_port *sci_port)
3229 {
3230 unsigned int regtype;
3231
3232 sci_port->ops = &sci_port_ops;
3233 sci_port->port.ops = &sci_uart_ops;
3234
3235 if (cfg->regtype != SCIx_PROBE_REGTYPE)
3236 return &sci_port_params[cfg->regtype];
3237
3238 switch (cfg->type) {
3239 case PORT_SCI:
3240 regtype = SCIx_SCI_REGTYPE;
3241 break;
3242 case PORT_IRDA:
3243 regtype = SCIx_IRDA_REGTYPE;
3244 break;
3245 case PORT_SCIFA:
3246 regtype = SCIx_SCIFA_REGTYPE;
3247 break;
3248 case PORT_SCIFB:
3249 regtype = SCIx_SCIFB_REGTYPE;
3250 break;
3251 case PORT_SCIF:
3252 /*
3253 * The SH-4 is a bit of a misnomer here, although that's
3254 * where this particular port layout originated. This
3255 * configuration (or some slight variation thereof)
3256 * remains the dominant model for all SCIFs.
3257 */
3258 regtype = SCIx_SH4_SCIF_REGTYPE;
3259 break;
3260 case PORT_HSCIF:
3261 regtype = SCIx_HSCIF_REGTYPE;
3262 break;
3263 default:
3264 pr_err("Can't probe register map for given port\n");
3265 return NULL;
3266 }
3267
3268 return &sci_port_params[regtype];
3269 }
3270
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)3271 static int sci_init_single(struct platform_device *dev,
3272 struct sci_port *sci_port, unsigned int index,
3273 const struct plat_sci_port *p, bool early)
3274 {
3275 struct uart_port *port = &sci_port->port;
3276 const struct resource *res;
3277 unsigned int i;
3278 int ret;
3279
3280 sci_port->cfg = p;
3281
3282 sci_port->type = p->type;
3283 sci_port->regtype = p->regtype;
3284
3285 port->iotype = UPIO_MEM;
3286 port->line = index;
3287 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
3288
3289 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3290 if (res == NULL)
3291 return -ENOMEM;
3292
3293 port->mapbase = res->start;
3294 sci_port->reg_size = resource_size(res);
3295
3296 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
3297 if (i)
3298 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
3299 else
3300 sci_port->irqs[i] = platform_get_irq(dev, i);
3301 }
3302
3303 /*
3304 * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
3305 * shuffle the interrupts.
3306 */
3307 if (p->type == PORT_SCI || sci_is_rsci_type(p->type))
3308 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3309
3310 /* The SCI generates several interrupts. They can be muxed together or
3311 * connected to different interrupt lines. In the muxed case only one
3312 * interrupt resource is specified as there is only one interrupt ID.
3313 * In the non-muxed case, up to 6 interrupt signals might be generated
3314 * from the SCI, however those signals might have their own individual
3315 * interrupt ID numbers, or muxed together with another interrupt.
3316 */
3317 if (sci_port->irqs[0] < 0)
3318 return -ENXIO;
3319
3320 if (sci_port->irqs[1] < 0)
3321 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3322 sci_port->irqs[i] = sci_port->irqs[0];
3323
3324 switch (p->type) {
3325 case PORT_SCIFB:
3326 sci_port->rx_trigger = 48;
3327 break;
3328 case PORT_HSCIF:
3329 sci_port->rx_trigger = 64;
3330 break;
3331 case PORT_SCIFA:
3332 case RSCI_PORT_SCIF32:
3333 sci_port->rx_trigger = 32;
3334 break;
3335 case PORT_SCIF:
3336 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3337 /* RX triggering not implemented for this IP */
3338 sci_port->rx_trigger = 1;
3339 else
3340 sci_port->rx_trigger = 8;
3341 break;
3342 case RSCI_PORT_SCIF16:
3343 sci_port->rx_trigger = 16;
3344 break;
3345 default:
3346 sci_port->rx_trigger = 1;
3347 break;
3348 }
3349
3350 sci_port->rx_fifo_timeout = 0;
3351 sci_port->hscif_tot = 0;
3352
3353 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3354 * match the SoC datasheet, this should be investigated. Let platform
3355 * data override the sampling rate for now.
3356 */
3357 sci_port->sampling_rate_mask = p->sampling_rate
3358 ? SCI_SR(p->sampling_rate)
3359 : sci_port->params->sampling_rate_mask;
3360
3361 if (!early) {
3362 ret = sci_init_clocks(sci_port, &dev->dev);
3363 if (ret < 0)
3364 return ret;
3365 }
3366
3367 port->type = SCI_PUBLIC_PORT_ID(p->type);
3368 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3369 port->fifosize = sci_port->params->fifosize;
3370
3371 if (p->type == PORT_SCI && !dev->dev.of_node) {
3372 if (sci_port->reg_size >= 0x20)
3373 port->regshift = 2;
3374 else
3375 port->regshift = 1;
3376 }
3377
3378 /*
3379 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3380 * for the multi-IRQ ports, which is where we are primarily
3381 * concerned with the shutdown path synchronization.
3382 *
3383 * For the muxed case there's nothing more to do.
3384 */
3385 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3386 port->irqflags = 0;
3387
3388 return 0;
3389 }
3390
3391 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3392 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)3393 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3394 {
3395 to_sci_port(port)->ops->poll_put_char(port, ch);
3396 }
3397
3398 /*
3399 * Print a string to the serial port trying not to disturb
3400 * any possible real use of the port...
3401 */
serial_console_write(struct console * co,const char * s,unsigned count)3402 static void serial_console_write(struct console *co, const char *s,
3403 unsigned count)
3404 {
3405 struct sci_port *sci_port = &sci_ports[co->index];
3406 struct uart_port *port = &sci_port->port;
3407 const struct sci_common_regs *regs = sci_port->params->common_regs;
3408 unsigned int bits;
3409 u32 ctrl;
3410 unsigned long flags;
3411 int locked = 1;
3412
3413 if (port->sysrq)
3414 locked = 0;
3415 else if (oops_in_progress)
3416 locked = uart_port_trylock_irqsave(port, &flags);
3417 else
3418 uart_port_lock_irqsave(port, &flags);
3419
3420 /* first save SCSCR then disable interrupts, keep clock source */
3421
3422 ctrl = sci_port->ops->read_reg(port, regs->control);
3423 sci_port->ops->prepare_console_write(port, ctrl);
3424
3425 uart_console_write(port, s, count, serial_console_putchar);
3426
3427 /* wait until fifo is empty and last bit has been transmitted */
3428
3429 bits = sci_port->params->param_bits->poll_sent_bits;
3430
3431 while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
3432 cpu_relax();
3433
3434 /* restore the SCSCR */
3435 if (sci_port->ops->finish_console_write)
3436 sci_port->ops->finish_console_write(port, ctrl);
3437 else
3438 sci_port->ops->write_reg(port, regs->control, ctrl);
3439
3440 if (locked)
3441 uart_port_unlock_irqrestore(port, flags);
3442 }
3443
serial_console_setup(struct console * co,char * options)3444 static int serial_console_setup(struct console *co, char *options)
3445 {
3446 struct sci_port *sci_port;
3447 struct uart_port *port;
3448 int baud = 115200;
3449 int bits = 8;
3450 int parity = 'n';
3451 int flow = 'n';
3452 int ret;
3453
3454 /*
3455 * Refuse to handle any bogus ports.
3456 */
3457 if (co->index < 0 || co->index >= SCI_NPORTS)
3458 return -ENODEV;
3459
3460 sci_port = &sci_ports[co->index];
3461 port = &sci_port->port;
3462
3463 /*
3464 * Refuse to handle uninitialized ports.
3465 */
3466 if (!port->ops)
3467 return -ENODEV;
3468
3469 ret = sci_remap_port(port);
3470 if (unlikely(ret != 0))
3471 return ret;
3472
3473 if (options)
3474 uart_parse_options(options, &baud, &parity, &bits, &flow);
3475
3476 return uart_set_options(port, co, baud, parity, bits, flow);
3477 }
3478
3479 static struct console serial_console = {
3480 .name = "ttySC",
3481 .device = uart_console_device,
3482 .write = serial_console_write,
3483 .setup = serial_console_setup,
3484 .flags = CON_PRINTBUFFER,
3485 .index = -1,
3486 .data = &sci_uart_driver,
3487 };
3488
3489 #ifdef CONFIG_SUPERH
3490 static char early_serial_buf[32];
3491
early_serial_console_setup(struct console * co,char * options)3492 static int early_serial_console_setup(struct console *co, char *options)
3493 {
3494 /*
3495 * This early console is always registered using the earlyprintk=
3496 * parameter, which does not call add_preferred_console(). Thus
3497 * @options is always NULL and the options for this early console
3498 * are passed using a custom buffer.
3499 */
3500 WARN_ON(options);
3501
3502 return serial_console_setup(co, early_serial_buf);
3503 }
3504
3505 static struct console early_serial_console = {
3506 .name = "early_ttySC",
3507 .write = serial_console_write,
3508 .setup = early_serial_console_setup,
3509 .flags = CON_PRINTBUFFER,
3510 .index = -1,
3511 };
3512
sci_probe_earlyprintk(struct platform_device * pdev)3513 static int sci_probe_earlyprintk(struct platform_device *pdev)
3514 {
3515 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3516 struct sci_port *sp = &sci_ports[pdev->id];
3517
3518 if (early_serial_console.data)
3519 return -EEXIST;
3520
3521 early_serial_console.index = pdev->id;
3522
3523 sp->params = sci_probe_regmap(cfg, sp);
3524 if (!sp->params)
3525 return -ENODEV;
3526
3527 sci_init_single(pdev, sp, pdev->id, cfg, true);
3528
3529 if (!strstr(early_serial_buf, "keep"))
3530 early_serial_console.flags |= CON_BOOT;
3531
3532 register_console(&early_serial_console);
3533 return 0;
3534 }
3535 #endif
3536
3537 #define SCI_CONSOLE (&serial_console)
3538
3539 #else
sci_probe_earlyprintk(struct platform_device * pdev)3540 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3541 {
3542 return -EINVAL;
3543 }
3544
3545 #define SCI_CONSOLE NULL
3546
3547 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3548
3549 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3550
3551 static DEFINE_MUTEX(sci_uart_registration_lock);
3552 static struct uart_driver sci_uart_driver = {
3553 .owner = THIS_MODULE,
3554 .driver_name = "sci",
3555 .dev_name = "ttySC",
3556 .major = SCI_MAJOR,
3557 .minor = SCI_MINOR_START,
3558 .nr = SCI_NPORTS,
3559 .cons = SCI_CONSOLE,
3560 };
3561
sci_remove(struct platform_device * dev)3562 static void sci_remove(struct platform_device *dev)
3563 {
3564 struct sci_port *s = platform_get_drvdata(dev);
3565
3566 sci_ports_in_use &= ~BIT(s->port.line);
3567 uart_remove_one_port(&sci_uart_driver, &s->port);
3568
3569 if (s->port.fifosize > 1) {
3570 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3571 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3572 }
3573 }
3574
3575 static const struct sci_of_data of_sci_scif_sh2 = {
3576 .type = PORT_SCIF,
3577 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
3578 .ops = &sci_port_ops,
3579 .uart_ops = &sci_uart_ops,
3580 .params = &sci_port_params[SCIx_SH2_SCIF_FIFODATA_REGTYPE],
3581 };
3582
3583 static const struct sci_of_data of_sci_scif_rz_scifa = {
3584 .type = PORT_SCIF,
3585 .regtype = SCIx_RZ_SCIFA_REGTYPE,
3586 .ops = &sci_port_ops,
3587 .uart_ops = &sci_uart_ops,
3588 .params = &sci_port_params[SCIx_RZ_SCIFA_REGTYPE],
3589 };
3590
3591 static const struct sci_of_data of_sci_scif_rzv2h = {
3592 .type = PORT_SCIF,
3593 .regtype = SCIx_RZV2H_SCIF_REGTYPE,
3594 .ops = &sci_port_ops,
3595 .uart_ops = &sci_uart_ops,
3596 .params = &sci_port_params[SCIx_RZV2H_SCIF_REGTYPE],
3597 };
3598
3599 static const struct sci_of_data of_sci_rcar_scif = {
3600 .type = PORT_SCIF,
3601 .regtype = SCIx_SH4_SCIF_BRG_REGTYPE,
3602 .ops = &sci_port_ops,
3603 .uart_ops = &sci_uart_ops,
3604 .params = &sci_port_params[SCIx_SH4_SCIF_BRG_REGTYPE],
3605 };
3606
3607 static const struct sci_of_data of_sci_scif_sh4 = {
3608 .type = PORT_SCIF,
3609 .regtype = SCIx_SH4_SCIF_REGTYPE,
3610 .ops = &sci_port_ops,
3611 .uart_ops = &sci_uart_ops,
3612 .params = &sci_port_params[SCIx_SH4_SCIF_REGTYPE],
3613 };
3614
3615 static const struct sci_of_data of_sci_scifa = {
3616 .type = PORT_SCIFA,
3617 .regtype = SCIx_SCIFA_REGTYPE,
3618 .ops = &sci_port_ops,
3619 .uart_ops = &sci_uart_ops,
3620 .params = &sci_port_params[SCIx_SCIFA_REGTYPE],
3621 };
3622
3623 static const struct sci_of_data of_sci_scifb = {
3624 .type = PORT_SCIFB,
3625 .regtype = SCIx_SCIFB_REGTYPE,
3626 .ops = &sci_port_ops,
3627 .uart_ops = &sci_uart_ops,
3628 .params = &sci_port_params[SCIx_SCIFB_REGTYPE],
3629 };
3630
3631 static const struct sci_of_data of_sci_hscif = {
3632 .type = PORT_HSCIF,
3633 .regtype = SCIx_HSCIF_REGTYPE,
3634 .ops = &sci_port_ops,
3635 .uart_ops = &sci_uart_ops,
3636 .params = &sci_port_params[SCIx_HSCIF_REGTYPE],
3637 };
3638
3639 static const struct sci_of_data of_sci_sci = {
3640 .type = PORT_SCI,
3641 .regtype = SCIx_SCI_REGTYPE,
3642 .ops = &sci_port_ops,
3643 .uart_ops = &sci_uart_ops,
3644 .params = &sci_port_params[SCIx_SCI_REGTYPE],
3645 };
3646
3647 static const struct of_device_id of_sci_match[] __maybe_unused = {
3648 /* SoC-specific types */
3649 {
3650 .compatible = "renesas,scif-r7s72100",
3651 .data = &of_sci_scif_sh2,
3652 },
3653 {
3654 .compatible = "renesas,scif-r7s9210",
3655 .data = &of_sci_scif_rz_scifa,
3656 },
3657 {
3658 .compatible = "renesas,scif-r9a07g044",
3659 .data = &of_sci_scif_rz_scifa,
3660 },
3661 {
3662 .compatible = "renesas,scif-r9a09g057",
3663 .data = &of_sci_scif_rzv2h,
3664 },
3665 #ifdef CONFIG_SERIAL_RSCI
3666 {
3667 .compatible = "renesas,r9a09g047-rsci",
3668 .data = &of_rsci_rzg3e_data,
3669 },
3670 {
3671 .compatible = "renesas,r9a09g077-rsci",
3672 .data = &of_rsci_rzt2h_data,
3673 },
3674 #endif /* CONFIG_SERIAL_RSCI */
3675 /* Family-specific types */
3676 {
3677 .compatible = "renesas,rcar-gen1-scif",
3678 .data = &of_sci_rcar_scif,
3679 }, {
3680 .compatible = "renesas,rcar-gen2-scif",
3681 .data = &of_sci_rcar_scif,
3682 }, {
3683 .compatible = "renesas,rcar-gen3-scif",
3684 .data = &of_sci_rcar_scif
3685 }, {
3686 .compatible = "renesas,rcar-gen4-scif",
3687 .data = &of_sci_rcar_scif
3688 }, {
3689 .compatible = "renesas,rcar-gen5-scif",
3690 .data = &of_sci_rcar_scif
3691 },
3692 /* Generic types */
3693 {
3694 .compatible = "renesas,scif",
3695 .data = &of_sci_scif_sh4,
3696 }, {
3697 .compatible = "renesas,scifa",
3698 .data = &of_sci_scifa,
3699 }, {
3700 .compatible = "renesas,scifb",
3701 .data = &of_sci_scifb,
3702 }, {
3703 .compatible = "renesas,hscif",
3704 .data = &of_sci_hscif,
3705 }, {
3706 .compatible = "renesas,sci",
3707 .data = &of_sci_sci,
3708 }, {
3709 /* Terminator */
3710 },
3711 };
3712 MODULE_DEVICE_TABLE(of, of_sci_match);
3713
sci_reset_control_assert(void * data)3714 static void sci_reset_control_assert(void *data)
3715 {
3716 reset_control_assert(data);
3717 }
3718
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3719 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3720 unsigned int *dev_id)
3721 {
3722 struct device_node *np = pdev->dev.of_node;
3723 struct reset_control *rstc;
3724 struct plat_sci_port *p;
3725 struct sci_port *sp;
3726 const struct sci_of_data *data;
3727 int id, ret;
3728
3729 if (!IS_ENABLED(CONFIG_OF) || !np)
3730 return ERR_PTR(-EINVAL);
3731
3732 data = of_device_get_match_data(&pdev->dev);
3733
3734 rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
3735 if (IS_ERR(rstc))
3736 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3737 "failed to get reset ctrl\n"));
3738
3739 ret = reset_control_deassert(rstc);
3740 if (ret) {
3741 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3742 return ERR_PTR(ret);
3743 }
3744
3745 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3746 if (ret) {
3747 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3748 ret);
3749 return ERR_PTR(ret);
3750 }
3751
3752 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3753 if (!p)
3754 return ERR_PTR(-ENOMEM);
3755
3756 /* Get the line number from the aliases node. */
3757 id = of_alias_get_id(np, "serial");
3758 if (id < 0 && ~sci_ports_in_use)
3759 id = ffz(sci_ports_in_use);
3760 if (id < 0) {
3761 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3762 return ERR_PTR(-EINVAL);
3763 }
3764 if (id >= ARRAY_SIZE(sci_ports)) {
3765 dev_err(&pdev->dev, "serial%d out of range\n", id);
3766 return ERR_PTR(-EINVAL);
3767 }
3768
3769 sp = &sci_ports[id];
3770 sp->rstc = rstc;
3771 *dev_id = id;
3772
3773 p->type = data->type;
3774 p->regtype = data->regtype;
3775
3776 sp->ops = data->ops;
3777 sp->port.ops = data->uart_ops;
3778 sp->params = data->params;
3779
3780 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3781
3782 return p;
3783 }
3784
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport,struct resource * sci_res)3785 static int sci_probe_single(struct platform_device *dev,
3786 unsigned int index,
3787 struct plat_sci_port *p,
3788 struct sci_port *sciport,
3789 struct resource *sci_res)
3790 {
3791 int ret;
3792
3793 /* Sanity check */
3794 if (unlikely(index >= SCI_NPORTS)) {
3795 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3796 index+1, SCI_NPORTS);
3797 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3798 return -EINVAL;
3799 }
3800 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3801 if (sci_ports_in_use & BIT(index))
3802 return -EBUSY;
3803
3804 mutex_lock(&sci_uart_registration_lock);
3805 if (!sci_uart_driver.state) {
3806 ret = uart_register_driver(&sci_uart_driver);
3807 if (ret) {
3808 mutex_unlock(&sci_uart_registration_lock);
3809 return ret;
3810 }
3811 }
3812 mutex_unlock(&sci_uart_registration_lock);
3813
3814 ret = sci_init_single(dev, sciport, index, p, false);
3815 if (ret)
3816 return ret;
3817
3818 sciport->port.dev = &dev->dev;
3819 ret = devm_pm_runtime_enable(&dev->dev);
3820 if (ret)
3821 return ret;
3822
3823 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3824 if (IS_ERR(sciport->gpios))
3825 return PTR_ERR(sciport->gpios);
3826
3827 if (sciport->has_rtscts) {
3828 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3829 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3830 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3831 return -EINVAL;
3832 }
3833 sciport->port.flags |= UPF_HARD_FLOW;
3834 }
3835
3836 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3837 /*
3838 * In case:
3839 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3840 * - it now maps to an alias other than zero and
3841 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3842 * available in bootargs)
3843 *
3844 * we need to avoid disabling clocks and PM domains through the runtime
3845 * PM APIs called in __device_attach(). For this, increment the runtime
3846 * PM reference counter (the clocks and PM domains were already enabled
3847 * by the bootloader). Otherwise the earlycon may access the HW when it
3848 * has no clocks enabled leading to failures (infinite loop in
3849 * sci_poll_put_char()).
3850 */
3851 pm_runtime_get_noresume(&dev->dev);
3852
3853 /*
3854 * Skip cleanup the sci_port[0] in early_console_exit(), this
3855 * port is the same as the earlycon one.
3856 */
3857 sci_uart_earlycon_dev_probing = true;
3858 }
3859
3860 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3861 }
3862
sci_probe(struct platform_device * dev)3863 static int sci_probe(struct platform_device *dev)
3864 {
3865 struct plat_sci_port *p;
3866 struct resource *res;
3867 struct sci_port *sp;
3868 unsigned int dev_id;
3869 int ret;
3870
3871 /*
3872 * If we've come here via earlyprintk initialization, head off to
3873 * the special early probe. We don't have sufficient device state
3874 * to make it beyond this yet.
3875 */
3876 #ifdef CONFIG_SUPERH
3877 if (is_sh_early_platform_device(dev))
3878 return sci_probe_earlyprintk(dev);
3879 #endif
3880
3881 if (dev->dev.of_node) {
3882 p = sci_parse_dt(dev, &dev_id);
3883 if (IS_ERR(p))
3884 return PTR_ERR(p);
3885 sp = &sci_ports[dev_id];
3886 } else {
3887 p = dev->dev.platform_data;
3888 if (p == NULL) {
3889 dev_err(&dev->dev, "no platform data supplied\n");
3890 return -EINVAL;
3891 }
3892
3893 dev_id = dev->id;
3894 sp = &sci_ports[dev_id];
3895 sp->params = sci_probe_regmap(p, sp);
3896 if (!sp->params)
3897 return -ENODEV;
3898 }
3899
3900 sp->suspend_regs = devm_kzalloc(&dev->dev,
3901 sp->ops->suspend_regs_size(),
3902 GFP_KERNEL);
3903 if (!sp->suspend_regs)
3904 return -ENOMEM;
3905
3906 /*
3907 * In case:
3908 * - the probed port alias is zero (as the one used by earlycon), and
3909 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3910 * bootargs)
3911 *
3912 * defer the probe of this serial. This is a debug scenario and the user
3913 * must be aware of it.
3914 *
3915 * Except when the probed port is the same as the earlycon port.
3916 */
3917
3918 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3919 if (!res)
3920 return -ENODEV;
3921
3922 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3923 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3924
3925 platform_set_drvdata(dev, sp);
3926
3927 ret = sci_probe_single(dev, dev_id, p, sp, res);
3928 if (ret)
3929 return ret;
3930
3931 if (sp->port.fifosize > 1) {
3932 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3933 if (ret)
3934 return ret;
3935
3936 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3937 if (ret) {
3938 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3939 return ret;
3940 }
3941 }
3942
3943 #ifdef CONFIG_SH_STANDARD_BIOS
3944 sh_bios_gdb_detach();
3945 #endif
3946
3947 sci_ports_in_use |= BIT(dev_id);
3948 return 0;
3949 }
3950
sci_suspend(struct device * dev)3951 static int sci_suspend(struct device *dev)
3952 {
3953 struct sci_port *sport = dev_get_drvdata(dev);
3954
3955 if (sport) {
3956 uart_suspend_port(&sci_uart_driver, &sport->port);
3957
3958 if (!console_suspend_enabled && uart_console(&sport->port)) {
3959 if (sport->ops->console_save)
3960 sport->ops->console_save(&sport->port);
3961 }
3962 else
3963 return reset_control_assert(sport->rstc);
3964 }
3965
3966 return 0;
3967 }
3968
sci_resume(struct device * dev)3969 static int sci_resume(struct device *dev)
3970 {
3971 struct sci_port *sport = dev_get_drvdata(dev);
3972
3973 if (sport) {
3974 if (!console_suspend_enabled && uart_console(&sport->port)) {
3975 if (sport->ops->console_restore)
3976 sport->ops->console_restore(&sport->port);
3977 } else {
3978 int ret = reset_control_deassert(sport->rstc);
3979
3980 if (ret)
3981 return ret;
3982 }
3983
3984 uart_resume_port(&sci_uart_driver, &sport->port);
3985 }
3986
3987 return 0;
3988 }
3989
3990 static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3991
3992 static struct platform_driver sci_driver = {
3993 .probe = sci_probe,
3994 .remove = sci_remove,
3995 .driver = {
3996 .name = "sh-sci",
3997 .pm = pm_sleep_ptr(&sci_dev_pm_ops),
3998 .of_match_table = of_match_ptr(of_sci_match),
3999 },
4000 };
4001
sci_init(void)4002 static int __init sci_init(void)
4003 {
4004 pr_info("%s\n", banner);
4005
4006 return platform_driver_register(&sci_driver);
4007 }
4008
sci_exit(void)4009 static void __exit sci_exit(void)
4010 {
4011 platform_driver_unregister(&sci_driver);
4012
4013 if (sci_uart_driver.state)
4014 uart_unregister_driver(&sci_uart_driver);
4015 }
4016
4017 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
4018 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
4019 early_serial_buf, ARRAY_SIZE(early_serial_buf));
4020 #endif
4021 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
4022 static struct plat_sci_port port_cfg;
4023
early_console_exit(struct console * co)4024 static int early_console_exit(struct console *co)
4025 {
4026 struct sci_port *sci_port = &sci_ports[0];
4027
4028 /*
4029 * Clean the slot used by earlycon. A new SCI device might
4030 * map to this slot.
4031 */
4032 if (!sci_uart_earlycon_dev_probing) {
4033 memset(sci_port, 0, sizeof(*sci_port));
4034 sci_uart_earlycon = false;
4035 }
4036
4037 return 0;
4038 }
4039
scix_early_console_setup(struct earlycon_device * device,const struct sci_of_data * data)4040 int __init scix_early_console_setup(struct earlycon_device *device,
4041 const struct sci_of_data *data)
4042 {
4043 const struct sci_common_regs *regs;
4044
4045 if (!device->port.membase)
4046 return -ENODEV;
4047
4048 device->port.type = SCI_PUBLIC_PORT_ID(data->type);
4049
4050 sci_ports[0].port = device->port;
4051 sci_ports[0].type = data->type;
4052 sci_ports[0].regtype = data->regtype;
4053
4054 port_cfg.type = data->type;
4055 port_cfg.regtype = data->regtype;
4056
4057 sci_ports[0].cfg = &port_cfg;
4058 sci_ports[0].params = data->params;
4059 sci_ports[0].ops = data->ops;
4060 sci_ports[0].port.ops = data->uart_ops;
4061 sci_uart_earlycon = true;
4062 regs = sci_ports[0].params->common_regs;
4063
4064 port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
4065 sci_ports[0].ops->write_reg(&sci_ports[0].port,
4066 regs->control,
4067 sci_ports[0].params->param_bits->rxtx_enable | port_cfg.scscr);
4068
4069 device->con->write = serial_console_write;
4070 device->con->exit = early_console_exit;
4071
4072 return 0;
4073 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)4074 static int __init sci_early_console_setup(struct earlycon_device *device,
4075 const char *opt)
4076 {
4077 return scix_early_console_setup(device, &of_sci_sci);
4078 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)4079 static int __init scif_early_console_setup(struct earlycon_device *device,
4080 const char *opt)
4081 {
4082 return scix_early_console_setup(device, &of_sci_scif_sh4);
4083 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)4084 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
4085 const char *opt)
4086 {
4087 return scix_early_console_setup(device, &of_sci_scif_rz_scifa);
4088 }
4089
rzv2hscif_early_console_setup(struct earlycon_device * device,const char * opt)4090 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
4091 const char *opt)
4092 {
4093 return scix_early_console_setup(device, &of_sci_scif_rzv2h);
4094 }
4095
scifa_early_console_setup(struct earlycon_device * device,const char * opt)4096 static int __init scifa_early_console_setup(struct earlycon_device *device,
4097 const char *opt)
4098 {
4099 return scix_early_console_setup(device, &of_sci_scifa);
4100 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)4101 static int __init scifb_early_console_setup(struct earlycon_device *device,
4102 const char *opt)
4103 {
4104 return scix_early_console_setup(device, &of_sci_scifb);
4105 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)4106 static int __init hscif_early_console_setup(struct earlycon_device *device,
4107 const char *opt)
4108 {
4109 return scix_early_console_setup(device, &of_sci_hscif);
4110 }
4111
4112 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
4113 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
4114 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
4115 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
4116 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
4117 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
4118 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
4119 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
4120 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
4121
4122 module_init(sci_init);
4123 module_exit(sci_exit);
4124
4125 MODULE_LICENSE("GPL");
4126 MODULE_ALIAS("platform:sh-sci");
4127 MODULE_AUTHOR("Paul Mundt");
4128 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
4129