1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * 8250_dma.c - DMA Engine API support for 8250.c
4 *
5 * Copyright (C) 2013 Intel Corporation
6 */
7 #include <linux/tty.h>
8 #include <linux/tty_flip.h>
9 #include <linux/serial_reg.h>
10 #include <linux/dma-mapping.h>
11
12 #include "8250.h"
13
__dma_tx_complete(void * param)14 static void __dma_tx_complete(void *param)
15 {
16 struct uart_8250_port *p = param;
17 struct uart_8250_dma *dma = p->dma;
18 struct tty_port *tport = &p->port.state->port;
19 unsigned long flags;
20 int ret;
21
22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
23 UART_XMIT_SIZE, DMA_TO_DEVICE);
24
25 uart_port_lock_irqsave(&p->port, &flags);
26
27 dma->tx_running = 0;
28
29 uart_xmit_advance(&p->port, dma->tx_size);
30
31 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
32 uart_write_wakeup(&p->port);
33
34 ret = serial8250_tx_dma(p);
35 if (ret || !dma->tx_running)
36 serial8250_set_THRI(p);
37
38 uart_port_unlock_irqrestore(&p->port, flags);
39 }
40
__dma_rx_complete(struct uart_8250_port * p)41 static void __dma_rx_complete(struct uart_8250_port *p)
42 {
43 struct uart_8250_dma *dma = p->dma;
44 struct tty_port *tty_port = &p->port.state->port;
45 struct dma_tx_state state;
46 enum dma_status dma_status;
47 int count;
48
49 /*
50 * New DMA Rx can be started during the completion handler before it
51 * could acquire port's lock and it might still be ongoing. Don't to
52 * anything in such case.
53 */
54 dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
55 if (dma_status == DMA_IN_PROGRESS)
56 return;
57
58 count = dma->rx_size - state.residue;
59
60 tty_insert_flip_string(tty_port, dma->rx_buf, count);
61 p->port.icount.rx += count;
62 dma->rx_running = 0;
63
64 tty_flip_buffer_push(tty_port);
65 }
66
dma_rx_complete(void * param)67 static void dma_rx_complete(void *param)
68 {
69 struct uart_8250_port *p = param;
70 struct uart_8250_dma *dma = p->dma;
71 unsigned long flags;
72
73 uart_port_lock_irqsave(&p->port, &flags);
74 if (dma->rx_running)
75 __dma_rx_complete(p);
76
77 /*
78 * Cannot be combined with the previous check because __dma_rx_complete()
79 * changes dma->rx_running.
80 */
81 if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR))
82 p->dma->rx_dma(p);
83 uart_port_unlock_irqrestore(&p->port, flags);
84 }
85
serial8250_tx_dma(struct uart_8250_port * p)86 int serial8250_tx_dma(struct uart_8250_port *p)
87 {
88 struct uart_8250_dma *dma = p->dma;
89 struct tty_port *tport = &p->port.state->port;
90 struct dma_async_tx_descriptor *desc;
91 struct uart_port *up = &p->port;
92 struct scatterlist *sg;
93 struct scatterlist sgl[2];
94 int i;
95 int ret;
96
97 if (dma->tx_running) {
98 if (up->x_char) {
99 dmaengine_pause(dma->txchan);
100 uart_xchar_out(up, UART_TX);
101 dmaengine_resume(dma->txchan);
102 }
103 return 0;
104 } else if (up->x_char) {
105 uart_xchar_out(up, UART_TX);
106 }
107
108 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) {
109 /* We have been called from __dma_tx_complete() */
110 return 0;
111 }
112
113 serial8250_do_prepare_tx_dma(p);
114
115 sg_init_table(sgl, ARRAY_SIZE(sgl));
116
117 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, sgl, ARRAY_SIZE(sgl),
118 UART_XMIT_SIZE, dma->tx_addr);
119
120 dma->tx_size = 0;
121
122 for_each_sg(sgl, sg, ret, i)
123 dma->tx_size += sg_dma_len(sg);
124
125 desc = dmaengine_prep_slave_sg(dma->txchan, sgl, ret,
126 DMA_MEM_TO_DEV,
127 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
128 if (!desc) {
129 ret = -EBUSY;
130 goto err;
131 }
132
133 dma->tx_running = 1;
134 desc->callback = __dma_tx_complete;
135 desc->callback_param = p;
136
137 dma->tx_cookie = dmaengine_submit(desc);
138
139 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
140 UART_XMIT_SIZE, DMA_TO_DEVICE);
141
142 dma_async_issue_pending(dma->txchan);
143 serial8250_clear_THRI(p);
144 dma->tx_err = 0;
145
146 return 0;
147 err:
148 dma->tx_err = 1;
149 return ret;
150 }
151
serial8250_tx_dma_flush(struct uart_8250_port * p)152 void serial8250_tx_dma_flush(struct uart_8250_port *p)
153 {
154 struct uart_8250_dma *dma = p->dma;
155
156 if (!dma->tx_running)
157 return;
158
159 /*
160 * kfifo_reset() has been called by the serial core, avoid
161 * advancing and underflowing in __dma_tx_complete().
162 */
163 dma->tx_size = 0;
164
165 /*
166 * We can't use `dmaengine_terminate_sync` because `uart_flush_buffer` is
167 * holding the uart port spinlock.
168 */
169 dmaengine_terminate_async(dma->txchan);
170
171 /*
172 * The callback might or might not run. If it doesn't run, we need to ensure
173 * that `tx_running` is cleared so that we can schedule new transactions.
174 * If it does run, then the zombie callback will clear `tx_running` again
175 * and perform a no-op since `tx_size` was cleared above.
176 *
177 * In either case, we ASSUME the DMA transaction will terminate before we
178 * issue a new `serial8250_tx_dma`.
179 */
180 dma->tx_running = 0;
181 }
182
serial8250_rx_dma(struct uart_8250_port * p)183 int serial8250_rx_dma(struct uart_8250_port *p)
184 {
185 struct uart_8250_dma *dma = p->dma;
186 struct dma_async_tx_descriptor *desc;
187
188 if (dma->rx_running)
189 return 0;
190
191 serial8250_do_prepare_rx_dma(p);
192
193 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
194 dma->rx_size, DMA_DEV_TO_MEM,
195 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
196 if (!desc)
197 return -EBUSY;
198
199 dma->rx_running = 1;
200 desc->callback = dma_rx_complete;
201 desc->callback_param = p;
202
203 dma->rx_cookie = dmaengine_submit(desc);
204
205 dma_async_issue_pending(dma->rxchan);
206
207 return 0;
208 }
209
serial8250_rx_dma_flush(struct uart_8250_port * p)210 void serial8250_rx_dma_flush(struct uart_8250_port *p)
211 {
212 struct uart_8250_dma *dma = p->dma;
213
214 if (!dma || !dma->rxchan || !dma->rx_running)
215 return;
216
217 dmaengine_pause(dma->rxchan);
218 __dma_rx_complete(p);
219 dmaengine_terminate_async(dma->rxchan);
220 }
221 EXPORT_SYMBOL_GPL(serial8250_rx_dma_flush);
222
serial8250_request_dma(struct uart_8250_port * p)223 int serial8250_request_dma(struct uart_8250_port *p)
224 {
225 struct uart_8250_dma *dma = p->dma;
226 phys_addr_t rx_dma_addr = dma->rx_dma_addr ?
227 dma->rx_dma_addr : p->port.mapbase;
228 phys_addr_t tx_dma_addr = dma->tx_dma_addr ?
229 dma->tx_dma_addr : p->port.mapbase;
230 dma_cap_mask_t mask;
231 struct dma_slave_caps caps;
232 int ret;
233
234 /* Default slave configuration parameters */
235 dma->rxconf.direction = DMA_DEV_TO_MEM;
236 dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
237 dma->rxconf.src_addr = rx_dma_addr + UART_RX;
238
239 dma->txconf.direction = DMA_MEM_TO_DEV;
240 dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
241 dma->txconf.dst_addr = tx_dma_addr + UART_TX;
242
243 dma_cap_zero(mask);
244 dma_cap_set(DMA_SLAVE, mask);
245
246 /* Get a channel for RX */
247 dma->rxchan = dma_request_slave_channel_compat(mask,
248 dma->fn, dma->rx_param,
249 p->port.dev, "rx");
250 if (!dma->rxchan)
251 return -ENODEV;
252
253 /* 8250 rx dma requires dmaengine driver to support pause/terminate */
254 ret = dma_get_slave_caps(dma->rxchan, &caps);
255 if (ret)
256 goto release_rx;
257 if (!caps.cmd_pause || !caps.cmd_terminate ||
258 caps.residue_granularity == DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
259 ret = -EINVAL;
260 goto release_rx;
261 }
262
263 dmaengine_slave_config(dma->rxchan, &dma->rxconf);
264
265 /* Get a channel for TX */
266 dma->txchan = dma_request_slave_channel_compat(mask,
267 dma->fn, dma->tx_param,
268 p->port.dev, "tx");
269 if (!dma->txchan) {
270 ret = -ENODEV;
271 goto release_rx;
272 }
273
274 /* 8250 tx dma requires dmaengine driver to support terminate */
275 ret = dma_get_slave_caps(dma->txchan, &caps);
276 if (ret)
277 goto err;
278 if (!caps.cmd_terminate) {
279 ret = -EINVAL;
280 goto err;
281 }
282
283 dmaengine_slave_config(dma->txchan, &dma->txconf);
284
285 /* RX buffer */
286 if (!dma->rx_size)
287 dma->rx_size = PAGE_SIZE;
288
289 dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
290 &dma->rx_addr, GFP_KERNEL);
291 if (!dma->rx_buf) {
292 ret = -ENOMEM;
293 goto err;
294 }
295
296 /* TX buffer */
297 dma->tx_addr = dma_map_single(dma->txchan->device->dev,
298 p->port.state->port.xmit_buf,
299 UART_XMIT_SIZE,
300 DMA_TO_DEVICE);
301 if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) {
302 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size,
303 dma->rx_buf, dma->rx_addr);
304 ret = -ENOMEM;
305 goto err;
306 }
307
308 dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
309
310 return 0;
311 err:
312 dma_release_channel(dma->txchan);
313 release_rx:
314 dma_release_channel(dma->rxchan);
315 return ret;
316 }
317 EXPORT_SYMBOL_GPL(serial8250_request_dma);
318
serial8250_release_dma(struct uart_8250_port * p)319 void serial8250_release_dma(struct uart_8250_port *p)
320 {
321 struct uart_8250_dma *dma = p->dma;
322
323 if (!dma)
324 return;
325
326 /* Release RX resources */
327 dmaengine_terminate_sync(dma->rxchan);
328 dma->rx_running = 0;
329 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
330 dma->rx_addr);
331 dma_release_channel(dma->rxchan);
332 dma->rxchan = NULL;
333
334 /* Release TX resources */
335 dmaengine_terminate_sync(dma->txchan);
336 dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
337 UART_XMIT_SIZE, DMA_TO_DEVICE);
338 dma_release_channel(dma->txchan);
339 dma->txchan = NULL;
340 dma->tx_running = 0;
341
342 dev_dbg_ratelimited(p->port.dev, "dma channels released\n");
343 }
344 EXPORT_SYMBOL_GPL(serial8250_release_dma);
345