1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DMA driver for Xilinx Video DMA Engine 4 * 5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. 6 * 7 * Based on the Freescale DMA driver. 8 * 9 * Description: 10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP 11 * core that provides high-bandwidth direct memory access between memory 12 * and AXI4-Stream type video target peripherals. The core provides efficient 13 * two dimensional DMA operations with independent asynchronous read (S2MM) 14 * and write (MM2S) channel operation. It can be configured to have either 15 * one channel or two channels. If configured as two channels, one is to 16 * transmit to the video device (MM2S) and another is to receive from the 17 * video device (S2MM). Initialization, status, interrupt and management 18 * registers are accessed through an AXI4-Lite slave interface. 19 * 20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that 21 * provides high-bandwidth one dimensional direct memory access between memory 22 * and AXI4-Stream target peripherals. It supports one receive and one 23 * transmit channel, both of them optional at synthesis time. 24 * 25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory 26 * Access (DMA) between a memory-mapped source address and a memory-mapped 27 * destination address. 28 * 29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft 30 * Xilinx IP that provides high-bandwidth direct memory access between 31 * memory and AXI4-Stream target peripherals. It provides scatter gather 32 * (SG) interface with multiple channels independent configuration support. 33 * 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/dmapool.h> 38 #include <linux/dma/xilinx_dma.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/iopoll.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 #include <linux/of_irq.h> 47 #include <linux/platform_device.h> 48 #include <linux/slab.h> 49 #include <linux/string_choices.h> 50 #include <linux/clk.h> 51 #include <linux/io-64-nonatomic-lo-hi.h> 52 53 #include "../dmaengine.h" 54 55 /* Register/Descriptor Offsets */ 56 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 57 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 58 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 59 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 60 61 /* Control Registers */ 62 #define XILINX_DMA_REG_DMACR 0x0000 63 #define XILINX_DMA_DMACR_DELAY_MAX 0xff 64 #define XILINX_DMA_DMACR_DELAY_SHIFT 24 65 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff 66 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 67 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) 68 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) 69 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) 70 #define XILINX_DMA_DMACR_MASTER_SHIFT 8 71 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 72 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) 73 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) 74 #define XILINX_DMA_DMACR_RESET BIT(2) 75 #define XILINX_DMA_DMACR_CIRC_EN BIT(1) 76 #define XILINX_DMA_DMACR_RUNSTOP BIT(0) 77 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) 78 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24) 79 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16) 80 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8) 81 82 #define XILINX_DMA_REG_DMASR 0x0004 83 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) 84 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) 85 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) 86 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) 87 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) 88 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) 89 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) 90 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) 91 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) 92 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) 93 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) 94 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) 95 #define XILINX_DMA_DMASR_SG_MASK BIT(3) 96 #define XILINX_DMA_DMASR_IDLE BIT(1) 97 #define XILINX_DMA_DMASR_HALTED BIT(0) 98 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) 99 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) 100 101 #define XILINX_DMA_REG_CURDESC 0x0008 102 #define XILINX_DMA_REG_TAILDESC 0x0010 103 #define XILINX_DMA_REG_REG_INDEX 0x0014 104 #define XILINX_DMA_REG_FRMSTORE 0x0018 105 #define XILINX_DMA_REG_THRESHOLD 0x001c 106 #define XILINX_DMA_REG_FRMPTR_STS 0x0024 107 #define XILINX_DMA_REG_PARK_PTR 0x0028 108 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 109 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8) 110 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 111 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) 112 #define XILINX_DMA_REG_VDMA_VERSION 0x002c 113 114 /* Register Direct Mode Registers */ 115 #define XILINX_DMA_REG_VSIZE 0x0000 116 #define XILINX_DMA_VSIZE_MASK GENMASK(12, 0) 117 #define XILINX_DMA_REG_HSIZE 0x0004 118 #define XILINX_DMA_HSIZE_MASK GENMASK(15, 0) 119 120 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 121 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 122 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 123 124 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) 125 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) 126 127 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec 128 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) 129 130 /* HW specific definitions */ 131 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20 132 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 133 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1 134 #define XILINX_DMA_DFAULT_ADDRWIDTH 0x20 135 136 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ 137 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ 138 XILINX_DMA_DMASR_DLY_CNT_IRQ | \ 139 XILINX_DMA_DMASR_ERR_IRQ) 140 141 #define XILINX_DMA_DMASR_ALL_ERR_MASK \ 142 (XILINX_DMA_DMASR_EOL_LATE_ERR | \ 143 XILINX_DMA_DMASR_SOF_LATE_ERR | \ 144 XILINX_DMA_DMASR_SG_DEC_ERR | \ 145 XILINX_DMA_DMASR_SG_SLV_ERR | \ 146 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 147 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 148 XILINX_DMA_DMASR_DMA_DEC_ERR | \ 149 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ 150 XILINX_DMA_DMASR_DMA_INT_ERR) 151 152 /* 153 * Recoverable errors are DMA Internal error, SOF Early, EOF Early 154 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC 155 * is enabled in the h/w system. 156 */ 157 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ 158 (XILINX_DMA_DMASR_SOF_LATE_ERR | \ 159 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 160 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 161 XILINX_DMA_DMASR_DMA_INT_ERR) 162 163 /* Axi VDMA Flush on Fsync bits */ 164 #define XILINX_DMA_FLUSH_S2MM 3 165 #define XILINX_DMA_FLUSH_MM2S 2 166 #define XILINX_DMA_FLUSH_BOTH 1 167 168 /* Delay loop counter to prevent hardware failure */ 169 #define XILINX_DMA_LOOP_COUNT 1000000 170 171 /* AXI DMA Specific Registers/Offsets */ 172 #define XILINX_DMA_REG_SRCDSTADDR 0x18 173 #define XILINX_DMA_REG_BTT 0x28 174 175 /* AXI DMA Specific Masks/Bit fields */ 176 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 177 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 178 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 179 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) 180 #define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) 181 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) 182 #define XILINX_DMA_CR_COALESCE_SHIFT 16 183 #define XILINX_DMA_CR_DELAY_SHIFT 24 184 #define XILINX_DMA_BD_SOP BIT(27) 185 #define XILINX_DMA_BD_EOP BIT(26) 186 #define XILINX_DMA_BD_COMP_MASK BIT(31) 187 #define XILINX_DMA_COALESCE_MAX 255 188 #define XILINX_DMA_NUM_DESCS 512 189 #define XILINX_DMA_NUM_APP_WORDS 5 190 191 /* AXI CDMA Specific Registers/Offsets */ 192 #define XILINX_CDMA_REG_SRCADDR 0x18 193 #define XILINX_CDMA_REG_DSTADDR 0x20 194 195 /* AXI CDMA Specific Masks */ 196 #define XILINX_CDMA_CR_SGMODE BIT(3) 197 198 #define xilinx_prep_dma_addr_t(addr) \ 199 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) 200 201 /* AXI MCDMA Specific Registers/Offsets */ 202 #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 203 #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 204 #define XILINX_MCDMA_CHEN_OFFSET 0x0008 205 #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 206 #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 207 #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 208 #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) 209 #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) 210 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) 211 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) 212 213 /* AXI MCDMA Specific Masks/Shifts */ 214 #define XILINX_MCDMA_COALESCE_SHIFT 16 215 #define XILINX_MCDMA_COALESCE_MAX 24 216 #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) 217 #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) 218 #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) 219 #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) 220 #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) 221 #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) 222 #define XILINX_MCDMA_BD_EOP BIT(30) 223 #define XILINX_MCDMA_BD_SOP BIT(31) 224 225 /** 226 * struct xilinx_vdma_desc_hw - Hardware Descriptor 227 * @next_desc: Next Descriptor Pointer @0x00 228 * @pad1: Reserved @0x04 229 * @buf_addr: Buffer address @0x08 230 * @buf_addr_msb: MSB of Buffer address @0x0C 231 * @vsize: Vertical Size @0x10 232 * @hsize: Horizontal Size @0x14 233 * @stride: Number of bytes between the first 234 * pixels of each horizontal line @0x18 235 */ 236 struct xilinx_vdma_desc_hw { 237 u32 next_desc; 238 u32 pad1; 239 u32 buf_addr; 240 u32 buf_addr_msb; 241 u32 vsize; 242 u32 hsize; 243 u32 stride; 244 } __aligned(64); 245 246 /** 247 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA 248 * @next_desc: Next Descriptor Pointer @0x00 249 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 250 * @buf_addr: Buffer address @0x08 251 * @buf_addr_msb: MSB of Buffer address @0x0C 252 * @reserved1: Reserved @0x10 253 * @reserved2: Reserved @0x14 254 * @control: Control field @0x18 255 * @status: Status field @0x1C 256 * @app: APP Fields @0x20 - 0x30 257 */ 258 struct xilinx_axidma_desc_hw { 259 u32 next_desc; 260 u32 next_desc_msb; 261 u32 buf_addr; 262 u32 buf_addr_msb; 263 u32 reserved1; 264 u32 reserved2; 265 u32 control; 266 u32 status; 267 u32 app[XILINX_DMA_NUM_APP_WORDS]; 268 } __aligned(64); 269 270 /** 271 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA 272 * @next_desc: Next Descriptor Pointer @0x00 273 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 274 * @buf_addr: Buffer address @0x08 275 * @buf_addr_msb: MSB of Buffer address @0x0C 276 * @rsvd: Reserved field @0x10 277 * @control: Control Information field @0x14 278 * @status: Status field @0x18 279 * @sideband_status: Status of sideband signals @0x1C 280 * @app: APP Fields @0x20 - 0x30 281 */ 282 struct xilinx_aximcdma_desc_hw { 283 u32 next_desc; 284 u32 next_desc_msb; 285 u32 buf_addr; 286 u32 buf_addr_msb; 287 u32 rsvd; 288 u32 control; 289 u32 status; 290 u32 sideband_status; 291 u32 app[XILINX_DMA_NUM_APP_WORDS]; 292 } __aligned(64); 293 294 /** 295 * struct xilinx_cdma_desc_hw - Hardware Descriptor 296 * @next_desc: Next Descriptor Pointer @0x00 297 * @next_desc_msb: Next Descriptor Pointer MSB @0x04 298 * @src_addr: Source address @0x08 299 * @src_addr_msb: Source address MSB @0x0C 300 * @dest_addr: Destination address @0x10 301 * @dest_addr_msb: Destination address MSB @0x14 302 * @control: Control field @0x18 303 * @status: Status field @0x1C 304 */ 305 struct xilinx_cdma_desc_hw { 306 u32 next_desc; 307 u32 next_desc_msb; 308 u32 src_addr; 309 u32 src_addr_msb; 310 u32 dest_addr; 311 u32 dest_addr_msb; 312 u32 control; 313 u32 status; 314 } __aligned(64); 315 316 /** 317 * struct xilinx_vdma_tx_segment - Descriptor segment 318 * @hw: Hardware descriptor 319 * @node: Node in the descriptor segments list 320 * @phys: Physical address of segment 321 */ 322 struct xilinx_vdma_tx_segment { 323 struct xilinx_vdma_desc_hw hw; 324 struct list_head node; 325 dma_addr_t phys; 326 } __aligned(64); 327 328 /** 329 * struct xilinx_axidma_tx_segment - Descriptor segment 330 * @hw: Hardware descriptor 331 * @node: Node in the descriptor segments list 332 * @phys: Physical address of segment 333 */ 334 struct xilinx_axidma_tx_segment { 335 struct xilinx_axidma_desc_hw hw; 336 struct list_head node; 337 dma_addr_t phys; 338 } __aligned(64); 339 340 /** 341 * struct xilinx_aximcdma_tx_segment - Descriptor segment 342 * @hw: Hardware descriptor 343 * @node: Node in the descriptor segments list 344 * @phys: Physical address of segment 345 */ 346 struct xilinx_aximcdma_tx_segment { 347 struct xilinx_aximcdma_desc_hw hw; 348 struct list_head node; 349 dma_addr_t phys; 350 } __aligned(64); 351 352 /** 353 * struct xilinx_cdma_tx_segment - Descriptor segment 354 * @hw: Hardware descriptor 355 * @node: Node in the descriptor segments list 356 * @phys: Physical address of segment 357 */ 358 struct xilinx_cdma_tx_segment { 359 struct xilinx_cdma_desc_hw hw; 360 struct list_head node; 361 dma_addr_t phys; 362 } __aligned(64); 363 364 /** 365 * struct xilinx_dma_tx_descriptor - Per Transaction structure 366 * @async_tx: Async transaction descriptor 367 * @segments: TX segments list 368 * @node: Node in the channel descriptors list 369 * @cyclic: Check for cyclic transfers. 370 * @err: Whether the descriptor has an error. 371 * @residue: Residue of the completed descriptor 372 */ 373 struct xilinx_dma_tx_descriptor { 374 struct dma_async_tx_descriptor async_tx; 375 struct list_head segments; 376 struct list_head node; 377 bool cyclic; 378 bool err; 379 u32 residue; 380 }; 381 382 /** 383 * struct xilinx_dma_chan - Driver specific DMA channel structure 384 * @xdev: Driver specific device structure 385 * @ctrl_offset: Control registers offset 386 * @desc_offset: TX descriptor registers offset 387 * @lock: Descriptor operation lock 388 * @pending_list: Descriptors waiting 389 * @active_list: Descriptors ready to submit 390 * @done_list: Complete descriptors 391 * @free_seg_list: Free descriptors 392 * @common: DMA common channel 393 * @desc_pool: Descriptors pool 394 * @dev: The dma device 395 * @irq: Channel IRQ 396 * @id: Channel ID 397 * @direction: Transfer direction 398 * @num_frms: Number of frames 399 * @has_sg: Support scatter transfers 400 * @cyclic: Check for cyclic transfers. 401 * @genlock: Support genlock mode 402 * @err: Channel has errors 403 * @idle: Check for channel idle 404 * @terminating: Check for channel being synchronized by user 405 * @tasklet: Cleanup work after irq 406 * @config: Device configuration info 407 * @flush_on_fsync: Flush on Frame sync 408 * @desc_pendingcount: Descriptor pending count 409 * @ext_addr: Indicates 64 bit addressing is supported by dma channel 410 * @desc_submitcount: Descriptor h/w submitted count 411 * @seg_v: Statically allocated segments base 412 * @seg_mv: Statically allocated segments base for MCDMA 413 * @seg_p: Physical allocated segments base 414 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers 415 * @cyclic_seg_p: Physical allocated segments base for cyclic dma 416 * @start_transfer: Differentiate b/w DMA IP's transfer 417 * @stop_transfer: Differentiate b/w DMA IP's quiesce 418 * @tdest: TDEST value for mcdma 419 * @has_vflip: S2MM vertical flip 420 * @irq_delay: Interrupt delay timeout 421 */ 422 struct xilinx_dma_chan { 423 struct xilinx_dma_device *xdev; 424 u32 ctrl_offset; 425 u32 desc_offset; 426 spinlock_t lock; 427 struct list_head pending_list; 428 struct list_head active_list; 429 struct list_head done_list; 430 struct list_head free_seg_list; 431 struct dma_chan common; 432 struct dma_pool *desc_pool; 433 struct device *dev; 434 int irq; 435 int id; 436 enum dma_transfer_direction direction; 437 int num_frms; 438 bool has_sg; 439 bool cyclic; 440 bool genlock; 441 bool err; 442 bool idle; 443 bool terminating; 444 struct tasklet_struct tasklet; 445 struct xilinx_vdma_config config; 446 bool flush_on_fsync; 447 u32 desc_pendingcount; 448 bool ext_addr; 449 u32 desc_submitcount; 450 struct xilinx_axidma_tx_segment *seg_v; 451 struct xilinx_aximcdma_tx_segment *seg_mv; 452 dma_addr_t seg_p; 453 struct xilinx_axidma_tx_segment *cyclic_seg_v; 454 dma_addr_t cyclic_seg_p; 455 void (*start_transfer)(struct xilinx_dma_chan *chan); 456 int (*stop_transfer)(struct xilinx_dma_chan *chan); 457 u16 tdest; 458 bool has_vflip; 459 u8 irq_delay; 460 }; 461 462 /** 463 * enum xdma_ip_type - DMA IP type. 464 * 465 * @XDMA_TYPE_AXIDMA: Axi dma ip. 466 * @XDMA_TYPE_CDMA: Axi cdma ip. 467 * @XDMA_TYPE_VDMA: Axi vdma ip. 468 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. 469 * 470 */ 471 enum xdma_ip_type { 472 XDMA_TYPE_AXIDMA = 0, 473 XDMA_TYPE_CDMA, 474 XDMA_TYPE_VDMA, 475 XDMA_TYPE_AXIMCDMA 476 }; 477 478 struct xilinx_dma_config { 479 enum xdma_ip_type dmatype; 480 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, 481 struct clk **tx_clk, struct clk **txs_clk, 482 struct clk **rx_clk, struct clk **rxs_clk); 483 irqreturn_t (*irq_handler)(int irq, void *data); 484 const int max_channels; 485 }; 486 487 /** 488 * struct xilinx_dma_device - DMA device structure 489 * @regs: I/O mapped base address 490 * @dev: Device Structure 491 * @common: DMA device structure 492 * @chan: Driver specific DMA channel 493 * @flush_on_fsync: Flush on frame sync 494 * @ext_addr: Indicates 64 bit addressing is supported by dma device 495 * @pdev: Platform device structure pointer 496 * @dma_config: DMA config structure 497 * @axi_clk: DMA Axi4-lite interace clock 498 * @tx_clk: DMA mm2s clock 499 * @txs_clk: DMA mm2s stream clock 500 * @rx_clk: DMA s2mm clock 501 * @rxs_clk: DMA s2mm stream clock 502 * @s2mm_chan_id: DMA s2mm channel identifier 503 * @mm2s_chan_id: DMA mm2s channel identifier 504 * @max_buffer_len: Max buffer length 505 * @has_axistream_connected: AXI DMA connected to AXI Stream IP 506 */ 507 struct xilinx_dma_device { 508 void __iomem *regs; 509 struct device *dev; 510 struct dma_device common; 511 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; 512 u32 flush_on_fsync; 513 bool ext_addr; 514 struct platform_device *pdev; 515 const struct xilinx_dma_config *dma_config; 516 struct clk *axi_clk; 517 struct clk *tx_clk; 518 struct clk *txs_clk; 519 struct clk *rx_clk; 520 struct clk *rxs_clk; 521 u32 s2mm_chan_id; 522 u32 mm2s_chan_id; 523 u32 max_buffer_len; 524 bool has_axistream_connected; 525 }; 526 527 /* Macros */ 528 #define to_xilinx_chan(chan) \ 529 container_of(chan, struct xilinx_dma_chan, common) 530 #define to_dma_tx_descriptor(tx) \ 531 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) 532 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ 533 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \ 534 val, cond, delay_us, timeout_us) 535 536 /* IO accessors */ 537 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) 538 { 539 return ioread32(chan->xdev->regs + reg); 540 } 541 542 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) 543 { 544 iowrite32(value, chan->xdev->regs + reg); 545 } 546 547 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, 548 u32 value) 549 { 550 dma_write(chan, chan->desc_offset + reg, value); 551 } 552 553 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) 554 { 555 return dma_read(chan, chan->ctrl_offset + reg); 556 } 557 558 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, 559 u32 value) 560 { 561 dma_write(chan, chan->ctrl_offset + reg, value); 562 } 563 564 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, 565 u32 clr) 566 { 567 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); 568 } 569 570 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, 571 u32 set) 572 { 573 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); 574 } 575 576 /** 577 * vdma_desc_write_64 - 64-bit descriptor write 578 * @chan: Driver specific VDMA channel 579 * @reg: Register to write 580 * @value_lsb: lower address of the descriptor. 581 * @value_msb: upper address of the descriptor. 582 * 583 * Since vdma driver is trying to write to a register offset which is not a 584 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits 585 * instead of a single 64 bit register write. 586 */ 587 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, 588 u32 value_lsb, u32 value_msb) 589 { 590 /* Write the lsb 32 bits*/ 591 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); 592 593 /* Write the msb 32 bits */ 594 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); 595 } 596 597 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) 598 { 599 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); 600 } 601 602 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, 603 dma_addr_t addr) 604 { 605 if (chan->ext_addr) 606 dma_writeq(chan, reg, addr); 607 else 608 dma_ctrl_write(chan, reg, addr); 609 } 610 611 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, 612 struct xilinx_axidma_desc_hw *hw, 613 dma_addr_t buf_addr, size_t sg_used, 614 size_t period_len) 615 { 616 if (chan->ext_addr) { 617 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); 618 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + 619 period_len); 620 } else { 621 hw->buf_addr = buf_addr + sg_used + period_len; 622 } 623 } 624 625 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, 626 struct xilinx_aximcdma_desc_hw *hw, 627 dma_addr_t buf_addr, size_t sg_used) 628 { 629 if (chan->ext_addr) { 630 hw->buf_addr = lower_32_bits(buf_addr + sg_used); 631 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); 632 } else { 633 hw->buf_addr = buf_addr + sg_used; 634 } 635 } 636 637 /** 638 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length 639 * @tx: async transaction descriptor 640 * @payload_len: metadata payload length 641 * @max_len: metadata max length 642 * Return: The app field pointer. 643 */ 644 static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, 645 size_t *payload_len, size_t *max_len) 646 { 647 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 648 struct xilinx_axidma_tx_segment *seg; 649 650 *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; 651 seg = list_first_entry(&desc->segments, 652 struct xilinx_axidma_tx_segment, node); 653 return seg->hw.app; 654 } 655 656 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { 657 .get_ptr = xilinx_dma_get_metadata_ptr, 658 }; 659 660 /* ----------------------------------------------------------------------------- 661 * Descriptors and segments alloc and free 662 */ 663 664 /** 665 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment 666 * @chan: Driver specific DMA channel 667 * 668 * Return: The allocated segment on success and NULL on failure. 669 */ 670 static struct xilinx_vdma_tx_segment * 671 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 672 { 673 struct xilinx_vdma_tx_segment *segment; 674 dma_addr_t phys; 675 676 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 677 if (!segment) 678 return NULL; 679 680 segment->phys = phys; 681 682 return segment; 683 } 684 685 /** 686 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment 687 * @chan: Driver specific DMA channel 688 * 689 * Return: The allocated segment on success and NULL on failure. 690 */ 691 static struct xilinx_cdma_tx_segment * 692 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 693 { 694 struct xilinx_cdma_tx_segment *segment; 695 dma_addr_t phys; 696 697 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 698 if (!segment) 699 return NULL; 700 701 segment->phys = phys; 702 703 return segment; 704 } 705 706 /** 707 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment 708 * @chan: Driver specific DMA channel 709 * 710 * Return: The allocated segment on success and NULL on failure. 711 */ 712 static struct xilinx_axidma_tx_segment * 713 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) 714 { 715 struct xilinx_axidma_tx_segment *segment = NULL; 716 unsigned long flags; 717 718 spin_lock_irqsave(&chan->lock, flags); 719 if (!list_empty(&chan->free_seg_list)) { 720 segment = list_first_entry(&chan->free_seg_list, 721 struct xilinx_axidma_tx_segment, 722 node); 723 list_del(&segment->node); 724 } 725 spin_unlock_irqrestore(&chan->lock, flags); 726 727 if (!segment) 728 dev_dbg(chan->dev, "Could not find free tx segment\n"); 729 730 return segment; 731 } 732 733 /** 734 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment 735 * @chan: Driver specific DMA channel 736 * 737 * Return: The allocated segment on success and NULL on failure. 738 */ 739 static struct xilinx_aximcdma_tx_segment * 740 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 741 { 742 struct xilinx_aximcdma_tx_segment *segment = NULL; 743 unsigned long flags; 744 745 spin_lock_irqsave(&chan->lock, flags); 746 if (!list_empty(&chan->free_seg_list)) { 747 segment = list_first_entry(&chan->free_seg_list, 748 struct xilinx_aximcdma_tx_segment, 749 node); 750 list_del(&segment->node); 751 } 752 spin_unlock_irqrestore(&chan->lock, flags); 753 754 return segment; 755 } 756 757 static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw) 758 { 759 u32 next_desc = hw->next_desc; 760 u32 next_desc_msb = hw->next_desc_msb; 761 762 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw)); 763 764 hw->next_desc = next_desc; 765 hw->next_desc_msb = next_desc_msb; 766 } 767 768 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) 769 { 770 u32 next_desc = hw->next_desc; 771 u32 next_desc_msb = hw->next_desc_msb; 772 773 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); 774 775 hw->next_desc = next_desc; 776 hw->next_desc_msb = next_desc_msb; 777 } 778 779 /** 780 * xilinx_dma_free_tx_segment - Free transaction segment 781 * @chan: Driver specific DMA channel 782 * @segment: DMA transaction segment 783 */ 784 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, 785 struct xilinx_axidma_tx_segment *segment) 786 { 787 xilinx_dma_clean_hw_desc(&segment->hw); 788 789 list_add_tail(&segment->node, &chan->free_seg_list); 790 } 791 792 /** 793 * xilinx_mcdma_free_tx_segment - Free transaction segment 794 * @chan: Driver specific DMA channel 795 * @segment: DMA transaction segment 796 */ 797 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, 798 struct xilinx_aximcdma_tx_segment * 799 segment) 800 { 801 xilinx_mcdma_clean_hw_desc(&segment->hw); 802 803 list_add_tail(&segment->node, &chan->free_seg_list); 804 } 805 806 /** 807 * xilinx_cdma_free_tx_segment - Free transaction segment 808 * @chan: Driver specific DMA channel 809 * @segment: DMA transaction segment 810 */ 811 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, 812 struct xilinx_cdma_tx_segment *segment) 813 { 814 dma_pool_free(chan->desc_pool, segment, segment->phys); 815 } 816 817 /** 818 * xilinx_vdma_free_tx_segment - Free transaction segment 819 * @chan: Driver specific DMA channel 820 * @segment: DMA transaction segment 821 */ 822 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, 823 struct xilinx_vdma_tx_segment *segment) 824 { 825 dma_pool_free(chan->desc_pool, segment, segment->phys); 826 } 827 828 /** 829 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor 830 * @chan: Driver specific DMA channel 831 * 832 * Return: The allocated descriptor on success and NULL on failure. 833 */ 834 static struct xilinx_dma_tx_descriptor * 835 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) 836 { 837 struct xilinx_dma_tx_descriptor *desc; 838 839 desc = kzalloc_obj(*desc, GFP_NOWAIT); 840 if (!desc) 841 return NULL; 842 843 INIT_LIST_HEAD(&desc->segments); 844 845 return desc; 846 } 847 848 /** 849 * xilinx_dma_free_tx_descriptor - Free transaction descriptor 850 * @chan: Driver specific DMA channel 851 * @desc: DMA transaction descriptor 852 */ 853 static void 854 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, 855 struct xilinx_dma_tx_descriptor *desc) 856 { 857 struct xilinx_vdma_tx_segment *segment, *next; 858 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; 859 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; 860 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; 861 862 if (!desc) 863 return; 864 865 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 866 list_for_each_entry_safe(segment, next, &desc->segments, node) { 867 list_del(&segment->node); 868 xilinx_vdma_free_tx_segment(chan, segment); 869 } 870 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 871 list_for_each_entry_safe(cdma_segment, cdma_next, 872 &desc->segments, node) { 873 list_del(&cdma_segment->node); 874 xilinx_cdma_free_tx_segment(chan, cdma_segment); 875 } 876 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 877 list_for_each_entry_safe(axidma_segment, axidma_next, 878 &desc->segments, node) { 879 list_del(&axidma_segment->node); 880 xilinx_dma_free_tx_segment(chan, axidma_segment); 881 } 882 } else { 883 list_for_each_entry_safe(aximcdma_segment, aximcdma_next, 884 &desc->segments, node) { 885 list_del(&aximcdma_segment->node); 886 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); 887 } 888 } 889 890 kfree(desc); 891 } 892 893 /* Required functions */ 894 895 /** 896 * xilinx_dma_free_desc_list - Free descriptors list 897 * @chan: Driver specific DMA channel 898 * @list: List to parse and delete the descriptor 899 */ 900 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, 901 struct list_head *list) 902 { 903 struct xilinx_dma_tx_descriptor *desc, *next; 904 905 list_for_each_entry_safe(desc, next, list, node) { 906 list_del(&desc->node); 907 xilinx_dma_free_tx_descriptor(chan, desc); 908 } 909 } 910 911 /** 912 * xilinx_dma_free_descriptors - Free channel descriptors 913 * @chan: Driver specific DMA channel 914 */ 915 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) 916 { 917 unsigned long flags; 918 919 spin_lock_irqsave(&chan->lock, flags); 920 921 xilinx_dma_free_desc_list(chan, &chan->pending_list); 922 xilinx_dma_free_desc_list(chan, &chan->done_list); 923 xilinx_dma_free_desc_list(chan, &chan->active_list); 924 925 spin_unlock_irqrestore(&chan->lock, flags); 926 } 927 928 /** 929 * xilinx_dma_free_chan_resources - Free channel resources 930 * @dchan: DMA channel 931 */ 932 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) 933 { 934 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 935 unsigned long flags; 936 937 dev_dbg(chan->dev, "Free all channel resources.\n"); 938 939 xilinx_dma_free_descriptors(chan); 940 941 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 942 spin_lock_irqsave(&chan->lock, flags); 943 INIT_LIST_HEAD(&chan->free_seg_list); 944 spin_unlock_irqrestore(&chan->lock, flags); 945 946 /* Free memory that is allocated for BD */ 947 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 948 XILINX_DMA_NUM_DESCS, chan->seg_v, 949 chan->seg_p); 950 951 /* Free Memory that is allocated for cyclic DMA Mode */ 952 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), 953 chan->cyclic_seg_v, chan->cyclic_seg_p); 954 } 955 956 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 957 spin_lock_irqsave(&chan->lock, flags); 958 INIT_LIST_HEAD(&chan->free_seg_list); 959 spin_unlock_irqrestore(&chan->lock, flags); 960 961 /* Free memory that is allocated for BD */ 962 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * 963 XILINX_DMA_NUM_DESCS, chan->seg_mv, 964 chan->seg_p); 965 } 966 967 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && 968 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { 969 dma_pool_destroy(chan->desc_pool); 970 chan->desc_pool = NULL; 971 } 972 973 } 974 975 /** 976 * xilinx_dma_get_residue - Compute residue for a given descriptor 977 * @chan: Driver specific dma channel 978 * @desc: dma transaction descriptor 979 * 980 * Return: The number of residue bytes for the descriptor. 981 */ 982 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, 983 struct xilinx_dma_tx_descriptor *desc) 984 { 985 struct xilinx_cdma_tx_segment *cdma_seg; 986 struct xilinx_axidma_tx_segment *axidma_seg; 987 struct xilinx_aximcdma_tx_segment *aximcdma_seg; 988 struct xilinx_cdma_desc_hw *cdma_hw; 989 struct xilinx_axidma_desc_hw *axidma_hw; 990 struct xilinx_aximcdma_desc_hw *aximcdma_hw; 991 struct list_head *entry; 992 u32 residue = 0; 993 994 list_for_each(entry, &desc->segments) { 995 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 996 cdma_seg = list_entry(entry, 997 struct xilinx_cdma_tx_segment, 998 node); 999 cdma_hw = &cdma_seg->hw; 1000 residue += (cdma_hw->control & chan->xdev->max_buffer_len) - 1001 (cdma_hw->status & chan->xdev->max_buffer_len); 1002 } else if (chan->xdev->dma_config->dmatype == 1003 XDMA_TYPE_AXIDMA) { 1004 axidma_seg = list_entry(entry, 1005 struct xilinx_axidma_tx_segment, 1006 node); 1007 axidma_hw = &axidma_seg->hw; 1008 residue += (axidma_hw->control & chan->xdev->max_buffer_len) - 1009 (axidma_hw->status & chan->xdev->max_buffer_len); 1010 } else { 1011 aximcdma_seg = 1012 list_entry(entry, 1013 struct xilinx_aximcdma_tx_segment, 1014 node); 1015 aximcdma_hw = &aximcdma_seg->hw; 1016 residue += 1017 (aximcdma_hw->control & chan->xdev->max_buffer_len) - 1018 (aximcdma_hw->status & chan->xdev->max_buffer_len); 1019 } 1020 } 1021 1022 return residue; 1023 } 1024 1025 static u32 1026 xilinx_dma_get_residue_axidma_direct_s2mm(struct xilinx_dma_chan *chan, 1027 struct xilinx_dma_tx_descriptor *desc) 1028 { 1029 struct xilinx_axidma_tx_segment *seg; 1030 struct xilinx_axidma_desc_hw *hw; 1031 u32 finished_len; 1032 1033 finished_len = dma_ctrl_read(chan, XILINX_DMA_REG_BTT); 1034 1035 seg = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, 1036 node); 1037 1038 hw = &seg->hw; 1039 1040 return hw->control - finished_len; 1041 } 1042 1043 /** 1044 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback 1045 * @chan: Driver specific dma channel 1046 * @desc: dma transaction descriptor 1047 * @flags: flags for spin lock 1048 */ 1049 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, 1050 struct xilinx_dma_tx_descriptor *desc, 1051 unsigned long *flags) 1052 { 1053 struct dmaengine_desc_callback cb; 1054 1055 dmaengine_desc_get_callback(&desc->async_tx, &cb); 1056 if (dmaengine_desc_callback_valid(&cb)) { 1057 spin_unlock_irqrestore(&chan->lock, *flags); 1058 dmaengine_desc_callback_invoke(&cb, NULL); 1059 spin_lock_irqsave(&chan->lock, *flags); 1060 } 1061 } 1062 1063 /** 1064 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors 1065 * @chan: Driver specific DMA channel 1066 */ 1067 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) 1068 { 1069 struct xilinx_dma_tx_descriptor *desc, *next; 1070 unsigned long flags; 1071 1072 spin_lock_irqsave(&chan->lock, flags); 1073 1074 list_for_each_entry_safe(desc, next, &chan->done_list, node) { 1075 struct dmaengine_result result; 1076 1077 if (desc->cyclic) { 1078 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); 1079 break; 1080 } 1081 1082 /* Remove from the list of running transactions */ 1083 list_del(&desc->node); 1084 1085 if (unlikely(desc->err)) { 1086 if (chan->direction == DMA_DEV_TO_MEM) 1087 result.result = DMA_TRANS_READ_FAILED; 1088 else 1089 result.result = DMA_TRANS_WRITE_FAILED; 1090 } else { 1091 result.result = DMA_TRANS_NOERROR; 1092 } 1093 1094 result.residue = desc->residue; 1095 1096 /* Run the link descriptor callback function */ 1097 spin_unlock_irqrestore(&chan->lock, flags); 1098 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); 1099 spin_lock_irqsave(&chan->lock, flags); 1100 1101 /* Run any dependencies, then free the descriptor */ 1102 dma_run_dependencies(&desc->async_tx); 1103 xilinx_dma_free_tx_descriptor(chan, desc); 1104 1105 /* 1106 * While we ran a callback the user called a terminate function, 1107 * which takes care of cleaning up any remaining descriptors 1108 */ 1109 if (chan->terminating) 1110 break; 1111 } 1112 1113 spin_unlock_irqrestore(&chan->lock, flags); 1114 } 1115 1116 /** 1117 * xilinx_dma_do_tasklet - Schedule completion tasklet 1118 * @t: Pointer to the Xilinx DMA channel structure 1119 */ 1120 static void xilinx_dma_do_tasklet(struct tasklet_struct *t) 1121 { 1122 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); 1123 1124 xilinx_dma_chan_desc_cleanup(chan); 1125 } 1126 1127 /** 1128 * xilinx_dma_alloc_chan_resources - Allocate channel resources 1129 * @dchan: DMA channel 1130 * 1131 * Return: '0' on success and failure value on error 1132 */ 1133 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) 1134 { 1135 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1136 int i; 1137 1138 /* Has this channel already been allocated? */ 1139 if (chan->desc_pool) 1140 return 0; 1141 1142 /* 1143 * We need the descriptor to be aligned to 64bytes 1144 * for meeting Xilinx VDMA specification requirement. 1145 */ 1146 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1147 /* Allocate the buffer descriptors. */ 1148 chan->seg_v = dma_alloc_coherent(chan->dev, 1149 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, 1150 &chan->seg_p, GFP_KERNEL); 1151 if (!chan->seg_v) { 1152 dev_err(chan->dev, 1153 "unable to allocate channel %d descriptors\n", 1154 chan->id); 1155 return -ENOMEM; 1156 } 1157 /* 1158 * For cyclic DMA mode we need to program the tail Descriptor 1159 * register with a value which is not a part of the BD chain 1160 * so allocating a desc segment during channel allocation for 1161 * programming tail descriptor. 1162 */ 1163 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, 1164 sizeof(*chan->cyclic_seg_v), 1165 &chan->cyclic_seg_p, 1166 GFP_KERNEL); 1167 if (!chan->cyclic_seg_v) { 1168 dev_err(chan->dev, 1169 "unable to allocate desc segment for cyclic DMA\n"); 1170 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 1171 XILINX_DMA_NUM_DESCS, chan->seg_v, 1172 chan->seg_p); 1173 return -ENOMEM; 1174 } 1175 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; 1176 1177 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1178 chan->seg_v[i].hw.next_desc = 1179 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1180 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1181 chan->seg_v[i].hw.next_desc_msb = 1182 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1183 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1184 chan->seg_v[i].phys = chan->seg_p + 1185 sizeof(*chan->seg_v) * i; 1186 list_add_tail(&chan->seg_v[i].node, 1187 &chan->free_seg_list); 1188 } 1189 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1190 /* Allocate the buffer descriptors. */ 1191 chan->seg_mv = dma_alloc_coherent(chan->dev, 1192 sizeof(*chan->seg_mv) * 1193 XILINX_DMA_NUM_DESCS, 1194 &chan->seg_p, GFP_KERNEL); 1195 if (!chan->seg_mv) { 1196 dev_err(chan->dev, 1197 "unable to allocate channel %d descriptors\n", 1198 chan->id); 1199 return -ENOMEM; 1200 } 1201 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1202 chan->seg_mv[i].hw.next_desc = 1203 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1204 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1205 chan->seg_mv[i].hw.next_desc_msb = 1206 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1207 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1208 chan->seg_mv[i].phys = chan->seg_p + 1209 sizeof(*chan->seg_mv) * i; 1210 list_add_tail(&chan->seg_mv[i].node, 1211 &chan->free_seg_list); 1212 } 1213 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1214 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", 1215 chan->dev, 1216 sizeof(struct xilinx_cdma_tx_segment), 1217 __alignof__(struct xilinx_cdma_tx_segment), 1218 0); 1219 } else { 1220 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", 1221 chan->dev, 1222 sizeof(struct xilinx_vdma_tx_segment), 1223 __alignof__(struct xilinx_vdma_tx_segment), 1224 0); 1225 } 1226 1227 if (!chan->desc_pool && 1228 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && 1229 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { 1230 dev_err(chan->dev, 1231 "unable to allocate channel %d descriptor pool\n", 1232 chan->id); 1233 return -ENOMEM; 1234 } 1235 1236 dma_cookie_init(dchan); 1237 1238 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 1239 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1240 XILINX_CDMA_CR_SGMODE); 1241 1242 return 0; 1243 } 1244 1245 /** 1246 * xilinx_dma_calc_copysize - Calculate the amount of data to copy 1247 * @chan: Driver specific DMA channel 1248 * @size: Total data that needs to be copied 1249 * @done: Amount of data that has been already copied 1250 * 1251 * Return: Amount of data that has to be copied 1252 */ 1253 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, 1254 int size, int done) 1255 { 1256 size_t copy; 1257 1258 copy = min_t(size_t, size - done, 1259 chan->xdev->max_buffer_len); 1260 1261 if ((copy + done < size) && 1262 chan->xdev->common.copy_align) { 1263 /* 1264 * If this is not the last descriptor, make sure 1265 * the next one will be properly aligned 1266 */ 1267 copy = rounddown(copy, 1268 (1 << chan->xdev->common.copy_align)); 1269 } 1270 return copy; 1271 } 1272 1273 /** 1274 * xilinx_dma_tx_status - Get DMA transaction status 1275 * @dchan: DMA channel 1276 * @cookie: Transaction identifier 1277 * @txstate: Transaction state 1278 * 1279 * Return: DMA transaction status 1280 */ 1281 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, 1282 dma_cookie_t cookie, 1283 struct dma_tx_state *txstate) 1284 { 1285 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1286 struct xilinx_dma_tx_descriptor *desc; 1287 enum dma_status ret; 1288 unsigned long flags; 1289 u32 residue = 0; 1290 1291 ret = dma_cookie_status(dchan, cookie, txstate); 1292 if (ret == DMA_COMPLETE || !txstate) 1293 return ret; 1294 1295 spin_lock_irqsave(&chan->lock, flags); 1296 if (!list_empty(&chan->active_list)) { 1297 desc = list_last_entry(&chan->active_list, 1298 struct xilinx_dma_tx_descriptor, node); 1299 /* 1300 * VDMA and simple mode do not support residue reporting, so the 1301 * residue field will always be 0. 1302 */ 1303 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) 1304 residue = xilinx_dma_get_residue(chan, desc); 1305 } 1306 spin_unlock_irqrestore(&chan->lock, flags); 1307 1308 dma_set_residue(txstate, residue); 1309 1310 return ret; 1311 } 1312 1313 /** 1314 * xilinx_dma_stop_transfer - Halt DMA channel 1315 * @chan: Driver specific DMA channel 1316 * 1317 * Return: '0' on success and failure value on error 1318 */ 1319 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) 1320 { 1321 u32 val; 1322 1323 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1324 1325 /* Wait for the hardware to halt */ 1326 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1327 val & XILINX_DMA_DMASR_HALTED, 0, 1328 XILINX_DMA_LOOP_COUNT); 1329 } 1330 1331 /** 1332 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete 1333 * @chan: Driver specific DMA channel 1334 * 1335 * Return: '0' on success and failure value on error 1336 */ 1337 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) 1338 { 1339 u32 val; 1340 1341 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1342 val & XILINX_DMA_DMASR_IDLE, 0, 1343 XILINX_DMA_LOOP_COUNT); 1344 } 1345 1346 /** 1347 * xilinx_dma_start - Start DMA channel 1348 * @chan: Driver specific DMA channel 1349 */ 1350 static void xilinx_dma_start(struct xilinx_dma_chan *chan) 1351 { 1352 int err; 1353 u32 val; 1354 1355 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1356 1357 /* Wait for the hardware to start */ 1358 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1359 !(val & XILINX_DMA_DMASR_HALTED), 0, 1360 XILINX_DMA_LOOP_COUNT); 1361 1362 if (err) { 1363 dev_err(chan->dev, "Cannot start channel %p: %x\n", 1364 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1365 1366 chan->err = true; 1367 } 1368 } 1369 1370 /** 1371 * xilinx_vdma_start_transfer - Starts VDMA transfer 1372 * @chan: Driver specific channel struct pointer 1373 */ 1374 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) 1375 { 1376 struct xilinx_vdma_config *config = &chan->config; 1377 struct xilinx_dma_tx_descriptor *desc; 1378 u32 reg, j; 1379 struct xilinx_vdma_tx_segment *segment, *last = NULL; 1380 int i = 0; 1381 1382 /* This function was invoked with lock held */ 1383 if (chan->err) 1384 return; 1385 1386 if (!chan->idle) 1387 return; 1388 1389 if (list_empty(&chan->pending_list)) 1390 return; 1391 1392 desc = list_first_entry(&chan->pending_list, 1393 struct xilinx_dma_tx_descriptor, node); 1394 1395 /* Configure the hardware using info in the config structure */ 1396 if (chan->has_vflip) { 1397 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); 1398 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; 1399 reg |= config->vflip_en; 1400 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, 1401 reg); 1402 } 1403 1404 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1405 1406 if (config->frm_cnt_en) 1407 reg |= XILINX_DMA_DMACR_FRAMECNT_EN; 1408 else 1409 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; 1410 1411 /* If not parking, enable circular mode */ 1412 if (config->park) 1413 reg &= ~XILINX_DMA_DMACR_CIRC_EN; 1414 else 1415 reg |= XILINX_DMA_DMACR_CIRC_EN; 1416 1417 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1418 1419 if (config->park) { 1420 j = chan->desc_submitcount; 1421 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); 1422 if (chan->direction == DMA_MEM_TO_DEV) { 1423 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; 1424 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; 1425 } else { 1426 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; 1427 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; 1428 } 1429 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); 1430 } 1431 1432 /* Start the hardware */ 1433 xilinx_dma_start(chan); 1434 1435 if (chan->err) 1436 return; 1437 1438 /* Start the transfer */ 1439 if (chan->desc_submitcount < chan->num_frms) 1440 i = chan->desc_submitcount; 1441 1442 list_for_each_entry(segment, &desc->segments, node) { 1443 if (chan->ext_addr) 1444 vdma_desc_write_64(chan, 1445 XILINX_VDMA_REG_START_ADDRESS_64(i++), 1446 segment->hw.buf_addr, 1447 segment->hw.buf_addr_msb); 1448 else 1449 vdma_desc_write(chan, 1450 XILINX_VDMA_REG_START_ADDRESS(i++), 1451 segment->hw.buf_addr); 1452 1453 last = segment; 1454 } 1455 1456 if (!last) 1457 return; 1458 1459 /* HW expects these parameters to be same for one transaction */ 1460 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); 1461 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, 1462 last->hw.stride); 1463 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); 1464 1465 chan->desc_submitcount++; 1466 chan->desc_pendingcount--; 1467 list_move_tail(&desc->node, &chan->active_list); 1468 if (chan->desc_submitcount == chan->num_frms) 1469 chan->desc_submitcount = 0; 1470 1471 chan->idle = false; 1472 } 1473 1474 /** 1475 * xilinx_cdma_start_transfer - Starts cdma transfer 1476 * @chan: Driver specific channel struct pointer 1477 */ 1478 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) 1479 { 1480 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1481 struct xilinx_cdma_tx_segment *tail_segment; 1482 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); 1483 1484 if (chan->err) 1485 return; 1486 1487 if (!chan->idle) 1488 return; 1489 1490 if (list_empty(&chan->pending_list)) 1491 return; 1492 1493 head_desc = list_first_entry(&chan->pending_list, 1494 struct xilinx_dma_tx_descriptor, node); 1495 tail_desc = list_last_entry(&chan->pending_list, 1496 struct xilinx_dma_tx_descriptor, node); 1497 tail_segment = list_last_entry(&tail_desc->segments, 1498 struct xilinx_cdma_tx_segment, node); 1499 1500 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1501 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1502 ctrl_reg |= chan->desc_pendingcount << 1503 XILINX_DMA_CR_COALESCE_SHIFT; 1504 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); 1505 } 1506 1507 if (chan->has_sg) { 1508 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 1509 XILINX_CDMA_CR_SGMODE); 1510 1511 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1512 XILINX_CDMA_CR_SGMODE); 1513 1514 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1515 head_desc->async_tx.phys); 1516 1517 /* Update tail ptr register which will start the transfer */ 1518 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1519 tail_segment->phys); 1520 } else { 1521 /* In simple mode */ 1522 struct xilinx_cdma_tx_segment *segment; 1523 struct xilinx_cdma_desc_hw *hw; 1524 1525 segment = list_first_entry(&head_desc->segments, 1526 struct xilinx_cdma_tx_segment, 1527 node); 1528 1529 hw = &segment->hw; 1530 1531 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, 1532 xilinx_prep_dma_addr_t(hw->src_addr)); 1533 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, 1534 xilinx_prep_dma_addr_t(hw->dest_addr)); 1535 1536 /* Start the transfer */ 1537 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1538 hw->control & chan->xdev->max_buffer_len); 1539 } 1540 1541 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1542 chan->desc_pendingcount = 0; 1543 chan->idle = false; 1544 } 1545 1546 /** 1547 * xilinx_dma_start_transfer - Starts DMA transfer 1548 * @chan: Driver specific channel struct pointer 1549 */ 1550 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) 1551 { 1552 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1553 struct xilinx_axidma_tx_segment *tail_segment; 1554 u32 reg; 1555 1556 if (chan->err) 1557 return; 1558 1559 if (list_empty(&chan->pending_list)) { 1560 if (chan->cyclic) { 1561 struct xilinx_dma_tx_descriptor *desc; 1562 struct list_head *entry; 1563 1564 desc = list_last_entry(&chan->done_list, 1565 struct xilinx_dma_tx_descriptor, node); 1566 list_for_each(entry, &desc->segments) { 1567 struct xilinx_axidma_tx_segment *axidma_seg; 1568 struct xilinx_axidma_desc_hw *axidma_hw; 1569 axidma_seg = list_entry(entry, 1570 struct xilinx_axidma_tx_segment, 1571 node); 1572 axidma_hw = &axidma_seg->hw; 1573 axidma_hw->status = 0; 1574 } 1575 1576 list_splice_tail_init(&chan->done_list, &chan->active_list); 1577 chan->desc_pendingcount = 0; 1578 chan->idle = false; 1579 } 1580 return; 1581 } 1582 1583 if (!chan->idle) 1584 return; 1585 1586 head_desc = list_first_entry(&chan->pending_list, 1587 struct xilinx_dma_tx_descriptor, node); 1588 tail_desc = list_last_entry(&chan->pending_list, 1589 struct xilinx_dma_tx_descriptor, node); 1590 tail_segment = list_last_entry(&tail_desc->segments, 1591 struct xilinx_axidma_tx_segment, node); 1592 1593 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1594 1595 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1596 reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1597 reg |= chan->desc_pendingcount << 1598 XILINX_DMA_CR_COALESCE_SHIFT; 1599 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1600 } 1601 1602 if (chan->has_sg) 1603 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1604 head_desc->async_tx.phys); 1605 reg &= ~XILINX_DMA_CR_DELAY_MAX; 1606 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; 1607 reg |= XILINX_DMA_DMAXR_ALL_IRQ_MASK; 1608 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1609 1610 xilinx_dma_start(chan); 1611 1612 if (chan->err) 1613 return; 1614 1615 /* Start the transfer */ 1616 if (chan->has_sg) { 1617 if (chan->cyclic) 1618 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1619 chan->cyclic_seg_v->phys); 1620 else 1621 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1622 tail_segment->phys); 1623 } else { 1624 struct xilinx_axidma_tx_segment *segment; 1625 struct xilinx_axidma_desc_hw *hw; 1626 1627 segment = list_first_entry(&head_desc->segments, 1628 struct xilinx_axidma_tx_segment, 1629 node); 1630 hw = &segment->hw; 1631 1632 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, 1633 xilinx_prep_dma_addr_t(hw->buf_addr)); 1634 1635 /* Start the transfer */ 1636 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1637 hw->control & chan->xdev->max_buffer_len); 1638 } 1639 1640 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1641 chan->desc_pendingcount = 0; 1642 chan->idle = false; 1643 } 1644 1645 /** 1646 * xilinx_mcdma_start_transfer - Starts MCDMA transfer 1647 * @chan: Driver specific channel struct pointer 1648 */ 1649 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) 1650 { 1651 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1652 struct xilinx_aximcdma_tx_segment *tail_segment; 1653 u32 reg; 1654 1655 /* 1656 * lock has been held by calling functions, so we don't need it 1657 * to take it here again. 1658 */ 1659 1660 if (chan->err) 1661 return; 1662 1663 if (!chan->idle) 1664 return; 1665 1666 if (list_empty(&chan->pending_list)) 1667 return; 1668 1669 head_desc = list_first_entry(&chan->pending_list, 1670 struct xilinx_dma_tx_descriptor, node); 1671 tail_desc = list_last_entry(&chan->pending_list, 1672 struct xilinx_dma_tx_descriptor, node); 1673 tail_segment = list_last_entry(&tail_desc->segments, 1674 struct xilinx_aximcdma_tx_segment, node); 1675 1676 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1677 1678 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { 1679 reg &= ~XILINX_MCDMA_COALESCE_MASK; 1680 reg |= chan->desc_pendingcount << 1681 XILINX_MCDMA_COALESCE_SHIFT; 1682 } 1683 1684 reg |= XILINX_MCDMA_IRQ_ALL_MASK; 1685 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1686 1687 /* Program current descriptor */ 1688 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), 1689 head_desc->async_tx.phys); 1690 1691 /* Program channel enable register */ 1692 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); 1693 reg |= BIT(chan->tdest); 1694 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); 1695 1696 /* Start the fetch of BDs for the channel */ 1697 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1698 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; 1699 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1700 1701 xilinx_dma_start(chan); 1702 1703 if (chan->err) 1704 return; 1705 1706 /* Start the transfer */ 1707 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), 1708 tail_segment->phys); 1709 1710 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1711 chan->desc_pendingcount = 0; 1712 chan->idle = false; 1713 } 1714 1715 /** 1716 * xilinx_dma_issue_pending - Issue pending transactions 1717 * @dchan: DMA channel 1718 */ 1719 static void xilinx_dma_issue_pending(struct dma_chan *dchan) 1720 { 1721 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1722 unsigned long flags; 1723 1724 spin_lock_irqsave(&chan->lock, flags); 1725 chan->start_transfer(chan); 1726 spin_unlock_irqrestore(&chan->lock, flags); 1727 } 1728 1729 /** 1730 * xilinx_dma_device_config - Configure the DMA channel 1731 * @dchan: DMA channel 1732 * @config: channel configuration 1733 * 1734 * Return: 0 always. 1735 */ 1736 static int xilinx_dma_device_config(struct dma_chan *dchan, 1737 struct dma_slave_config *config) 1738 { 1739 return 0; 1740 } 1741 1742 /** 1743 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete 1744 * @chan : xilinx DMA channel 1745 * 1746 * CONTEXT: hardirq 1747 */ 1748 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) 1749 { 1750 struct xilinx_dma_tx_descriptor *desc, *next; 1751 1752 /* This function was invoked with lock held */ 1753 if (list_empty(&chan->active_list)) 1754 return; 1755 1756 list_for_each_entry_safe(desc, next, &chan->active_list, node) { 1757 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1758 struct xilinx_axidma_tx_segment *seg; 1759 1760 seg = list_last_entry(&desc->segments, 1761 struct xilinx_axidma_tx_segment, node); 1762 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) 1763 break; 1764 } 1765 if (chan->has_sg && chan->xdev->dma_config->dmatype != 1766 XDMA_TYPE_VDMA) 1767 desc->residue = xilinx_dma_get_residue(chan, desc); 1768 else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA && 1769 chan->direction == DMA_DEV_TO_MEM && !chan->has_sg) 1770 desc->residue = xilinx_dma_get_residue_axidma_direct_s2mm(chan, desc); 1771 else 1772 desc->residue = 0; 1773 desc->err = chan->err; 1774 1775 list_del(&desc->node); 1776 if (!desc->cyclic) 1777 dma_cookie_complete(&desc->async_tx); 1778 list_add_tail(&desc->node, &chan->done_list); 1779 } 1780 } 1781 1782 /** 1783 * xilinx_dma_reset - Reset DMA channel 1784 * @chan: Driver specific DMA channel 1785 * 1786 * Return: '0' on success and failure value on error 1787 */ 1788 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) 1789 { 1790 int err; 1791 u32 tmp; 1792 1793 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); 1794 1795 /* Wait for the hardware to finish reset */ 1796 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, 1797 !(tmp & XILINX_DMA_DMACR_RESET), 0, 1798 XILINX_DMA_LOOP_COUNT); 1799 1800 if (err) { 1801 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", 1802 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), 1803 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1804 return -ETIMEDOUT; 1805 } 1806 1807 chan->err = false; 1808 chan->idle = true; 1809 chan->desc_pendingcount = 0; 1810 chan->desc_submitcount = 0; 1811 1812 return err; 1813 } 1814 1815 /** 1816 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts 1817 * @chan: Driver specific DMA channel 1818 * 1819 * Return: '0' on success and failure value on error 1820 */ 1821 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) 1822 { 1823 int err; 1824 1825 /* Reset VDMA */ 1826 err = xilinx_dma_reset(chan); 1827 if (err) 1828 return err; 1829 1830 /* Enable interrupts */ 1831 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1832 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1833 1834 return 0; 1835 } 1836 1837 /** 1838 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler 1839 * @irq: IRQ number 1840 * @data: Pointer to the Xilinx MCDMA channel structure 1841 * 1842 * Return: IRQ_HANDLED/IRQ_NONE 1843 */ 1844 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) 1845 { 1846 struct xilinx_dma_chan *chan = data; 1847 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; 1848 1849 if (chan->direction == DMA_DEV_TO_MEM) 1850 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; 1851 else 1852 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; 1853 1854 /* Read the channel id raising the interrupt*/ 1855 chan_sermask = dma_ctrl_read(chan, ser_offset); 1856 chan_id = ffs(chan_sermask); 1857 1858 if (!chan_id) 1859 return IRQ_NONE; 1860 1861 if (chan->direction == DMA_DEV_TO_MEM) 1862 chan_offset = chan->xdev->dma_config->max_channels / 2; 1863 1864 chan_offset = chan_offset + (chan_id - 1); 1865 chan = chan->xdev->chan[chan_offset]; 1866 /* Read the status and ack the interrupts. */ 1867 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); 1868 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) 1869 return IRQ_NONE; 1870 1871 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), 1872 status & XILINX_MCDMA_IRQ_ALL_MASK); 1873 1874 if (status & XILINX_MCDMA_IRQ_ERR_MASK) { 1875 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", 1876 chan, 1877 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), 1878 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET 1879 (chan->tdest)), 1880 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET 1881 (chan->tdest))); 1882 chan->err = true; 1883 } 1884 1885 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { 1886 /* 1887 * Device takes too long to do the transfer when user requires 1888 * responsiveness. 1889 */ 1890 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1891 } 1892 1893 if (status & XILINX_MCDMA_IRQ_IOC_MASK) { 1894 spin_lock(&chan->lock); 1895 xilinx_dma_complete_descriptor(chan); 1896 chan->idle = true; 1897 chan->start_transfer(chan); 1898 spin_unlock(&chan->lock); 1899 } 1900 1901 tasklet_hi_schedule(&chan->tasklet); 1902 return IRQ_HANDLED; 1903 } 1904 1905 /** 1906 * xilinx_dma_irq_handler - DMA Interrupt handler 1907 * @irq: IRQ number 1908 * @data: Pointer to the Xilinx DMA channel structure 1909 * 1910 * Return: IRQ_HANDLED/IRQ_NONE 1911 */ 1912 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) 1913 { 1914 struct xilinx_dma_chan *chan = data; 1915 u32 status; 1916 1917 /* Read the status and ack the interrupts. */ 1918 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); 1919 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) 1920 return IRQ_NONE; 1921 1922 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1923 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1924 1925 if (status & XILINX_DMA_DMASR_ERR_IRQ) { 1926 /* 1927 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the 1928 * error is recoverable, ignore it. Otherwise flag the error. 1929 * 1930 * Only recoverable errors can be cleared in the DMASR register, 1931 * make sure not to write to other error bits to 1. 1932 */ 1933 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; 1934 1935 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1936 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); 1937 1938 if (!chan->flush_on_fsync || 1939 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { 1940 dev_err(chan->dev, 1941 "Channel %p has errors %x, cdr %x tdr %x\n", 1942 chan, errors, 1943 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), 1944 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); 1945 chan->err = true; 1946 } 1947 } 1948 1949 if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | 1950 XILINX_DMA_DMASR_DLY_CNT_IRQ)) { 1951 spin_lock(&chan->lock); 1952 xilinx_dma_complete_descriptor(chan); 1953 chan->idle = true; 1954 chan->start_transfer(chan); 1955 spin_unlock(&chan->lock); 1956 } 1957 1958 tasklet_schedule(&chan->tasklet); 1959 return IRQ_HANDLED; 1960 } 1961 1962 /** 1963 * append_desc_queue - Queuing descriptor 1964 * @chan: Driver specific dma channel 1965 * @desc: dma transaction descriptor 1966 */ 1967 static void append_desc_queue(struct xilinx_dma_chan *chan, 1968 struct xilinx_dma_tx_descriptor *desc) 1969 { 1970 struct xilinx_vdma_tx_segment *tail_segment; 1971 struct xilinx_dma_tx_descriptor *tail_desc; 1972 struct xilinx_axidma_tx_segment *axidma_tail_segment; 1973 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment; 1974 struct xilinx_cdma_tx_segment *cdma_tail_segment; 1975 1976 if (list_empty(&chan->pending_list)) 1977 goto append; 1978 1979 /* 1980 * Add the hardware descriptor to the chain of hardware descriptors 1981 * that already exists in memory. 1982 */ 1983 tail_desc = list_last_entry(&chan->pending_list, 1984 struct xilinx_dma_tx_descriptor, node); 1985 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 1986 tail_segment = list_last_entry(&tail_desc->segments, 1987 struct xilinx_vdma_tx_segment, 1988 node); 1989 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1990 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1991 cdma_tail_segment = list_last_entry(&tail_desc->segments, 1992 struct xilinx_cdma_tx_segment, 1993 node); 1994 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 1995 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1996 axidma_tail_segment = list_last_entry(&tail_desc->segments, 1997 struct xilinx_axidma_tx_segment, 1998 node); 1999 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2000 } else { 2001 aximcdma_tail_segment = 2002 list_last_entry(&tail_desc->segments, 2003 struct xilinx_aximcdma_tx_segment, 2004 node); 2005 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2006 } 2007 2008 /* 2009 * Add the software descriptor and all children to the list 2010 * of pending transactions 2011 */ 2012 append: 2013 list_add_tail(&desc->node, &chan->pending_list); 2014 chan->desc_pendingcount++; 2015 2016 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) 2017 && unlikely(chan->desc_pendingcount > chan->num_frms)) { 2018 dev_dbg(chan->dev, "desc pendingcount is too high\n"); 2019 chan->desc_pendingcount = chan->num_frms; 2020 } 2021 } 2022 2023 /** 2024 * xilinx_dma_tx_submit - Submit DMA transaction 2025 * @tx: Async transaction descriptor 2026 * 2027 * Return: cookie value on success and failure value on error 2028 */ 2029 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) 2030 { 2031 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 2032 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); 2033 dma_cookie_t cookie; 2034 unsigned long flags; 2035 int err; 2036 2037 if (chan->cyclic) { 2038 xilinx_dma_free_tx_descriptor(chan, desc); 2039 return -EBUSY; 2040 } 2041 2042 if (chan->err) { 2043 /* 2044 * If reset fails, need to hard reset the system. 2045 * Channel is no longer functional 2046 */ 2047 err = xilinx_dma_chan_reset(chan); 2048 if (err < 0) 2049 return err; 2050 } 2051 2052 spin_lock_irqsave(&chan->lock, flags); 2053 2054 cookie = dma_cookie_assign(tx); 2055 2056 /* Put this transaction onto the tail of the pending queue */ 2057 append_desc_queue(chan, desc); 2058 2059 if (desc->cyclic) 2060 chan->cyclic = true; 2061 2062 chan->terminating = false; 2063 2064 spin_unlock_irqrestore(&chan->lock, flags); 2065 2066 return cookie; 2067 } 2068 2069 /** 2070 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a 2071 * DMA_SLAVE transaction 2072 * @dchan: DMA channel 2073 * @xt: Interleaved template pointer 2074 * @flags: transfer ack flags 2075 * 2076 * Return: Async transaction descriptor on success and NULL on failure 2077 */ 2078 static struct dma_async_tx_descriptor * 2079 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, 2080 struct dma_interleaved_template *xt, 2081 unsigned long flags) 2082 { 2083 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2084 struct xilinx_dma_tx_descriptor *desc; 2085 struct xilinx_vdma_tx_segment *segment; 2086 struct xilinx_vdma_desc_hw *hw; 2087 2088 if (!is_slave_direction(xt->dir)) 2089 return NULL; 2090 2091 if (!xt->numf || !xt->sgl[0].size) 2092 return NULL; 2093 2094 if (xt->numf & ~XILINX_DMA_VSIZE_MASK || 2095 xt->sgl[0].size & ~XILINX_DMA_HSIZE_MASK) 2096 return NULL; 2097 2098 if (xt->frame_size != 1) 2099 return NULL; 2100 2101 /* Allocate a transaction descriptor. */ 2102 desc = xilinx_dma_alloc_tx_descriptor(chan); 2103 if (!desc) 2104 return NULL; 2105 2106 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2107 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2108 async_tx_ack(&desc->async_tx); 2109 2110 /* Allocate the link descriptor from DMA pool */ 2111 segment = xilinx_vdma_alloc_tx_segment(chan); 2112 if (!segment) 2113 goto error; 2114 2115 /* Fill in the hardware descriptor */ 2116 hw = &segment->hw; 2117 hw->vsize = xt->numf; 2118 hw->hsize = xt->sgl[0].size; 2119 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << 2120 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; 2121 hw->stride |= chan->config.frm_dly << 2122 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; 2123 2124 if (xt->dir != DMA_MEM_TO_DEV) { 2125 if (chan->ext_addr) { 2126 hw->buf_addr = lower_32_bits(xt->dst_start); 2127 hw->buf_addr_msb = upper_32_bits(xt->dst_start); 2128 } else { 2129 hw->buf_addr = xt->dst_start; 2130 } 2131 } else { 2132 if (chan->ext_addr) { 2133 hw->buf_addr = lower_32_bits(xt->src_start); 2134 hw->buf_addr_msb = upper_32_bits(xt->src_start); 2135 } else { 2136 hw->buf_addr = xt->src_start; 2137 } 2138 } 2139 2140 /* Insert the segment into the descriptor segments list. */ 2141 list_add_tail(&segment->node, &desc->segments); 2142 2143 /* Link the last hardware descriptor with the first. */ 2144 segment = list_first_entry(&desc->segments, 2145 struct xilinx_vdma_tx_segment, node); 2146 desc->async_tx.phys = segment->phys; 2147 2148 return &desc->async_tx; 2149 2150 error: 2151 xilinx_dma_free_tx_descriptor(chan, desc); 2152 return NULL; 2153 } 2154 2155 /** 2156 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction 2157 * @dchan: DMA channel 2158 * @dma_dst: destination address 2159 * @dma_src: source address 2160 * @len: transfer length 2161 * @flags: transfer ack flags 2162 * 2163 * Return: Async transaction descriptor on success and NULL on failure 2164 */ 2165 static struct dma_async_tx_descriptor * 2166 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, 2167 dma_addr_t dma_src, size_t len, unsigned long flags) 2168 { 2169 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2170 struct xilinx_dma_tx_descriptor *desc; 2171 struct xilinx_cdma_tx_segment *segment; 2172 struct xilinx_cdma_desc_hw *hw; 2173 2174 if (!len || len > chan->xdev->max_buffer_len) 2175 return NULL; 2176 2177 desc = xilinx_dma_alloc_tx_descriptor(chan); 2178 if (!desc) 2179 return NULL; 2180 2181 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2182 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2183 2184 /* Allocate the link descriptor from DMA pool */ 2185 segment = xilinx_cdma_alloc_tx_segment(chan); 2186 if (!segment) 2187 goto error; 2188 2189 hw = &segment->hw; 2190 hw->control = len; 2191 hw->src_addr = dma_src; 2192 hw->dest_addr = dma_dst; 2193 if (chan->ext_addr) { 2194 hw->src_addr_msb = upper_32_bits(dma_src); 2195 hw->dest_addr_msb = upper_32_bits(dma_dst); 2196 } 2197 2198 /* Insert the segment into the descriptor segments list. */ 2199 list_add_tail(&segment->node, &desc->segments); 2200 2201 desc->async_tx.phys = segment->phys; 2202 hw->next_desc = segment->phys; 2203 2204 return &desc->async_tx; 2205 2206 error: 2207 xilinx_dma_free_tx_descriptor(chan, desc); 2208 return NULL; 2209 } 2210 2211 /** 2212 * xilinx_dma_prep_peripheral_dma_vec - prepare descriptors for a DMA_SLAVE 2213 * transaction from DMA vectors 2214 * @dchan: DMA channel 2215 * @vecs: Array of DMA vectors that should be transferred 2216 * @nb: number of entries in @vecs 2217 * @direction: DMA direction 2218 * @flags: transfer ack flags 2219 * 2220 * Return: Async transaction descriptor on success and NULL on failure 2221 */ 2222 static struct dma_async_tx_descriptor *xilinx_dma_prep_peripheral_dma_vec( 2223 struct dma_chan *dchan, const struct dma_vec *vecs, size_t nb, 2224 enum dma_transfer_direction direction, unsigned long flags) 2225 { 2226 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2227 struct xilinx_dma_tx_descriptor *desc; 2228 struct xilinx_axidma_tx_segment *segment, *head, *prev = NULL; 2229 size_t copy; 2230 size_t sg_used; 2231 unsigned int i; 2232 2233 if (!is_slave_direction(direction) || direction != chan->direction) 2234 return NULL; 2235 2236 desc = xilinx_dma_alloc_tx_descriptor(chan); 2237 if (!desc) 2238 return NULL; 2239 2240 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2241 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2242 2243 /* Build transactions using information from DMA vectors */ 2244 for (i = 0; i < nb; i++) { 2245 sg_used = 0; 2246 2247 /* Loop until the entire dma_vec entry is used */ 2248 while (sg_used < vecs[i].len) { 2249 struct xilinx_axidma_desc_hw *hw; 2250 2251 /* Get a free segment */ 2252 segment = xilinx_axidma_alloc_tx_segment(chan); 2253 if (!segment) 2254 goto error; 2255 2256 /* 2257 * Calculate the maximum number of bytes to transfer, 2258 * making sure it is less than the hw limit 2259 */ 2260 copy = xilinx_dma_calc_copysize(chan, vecs[i].len, 2261 sg_used); 2262 hw = &segment->hw; 2263 2264 /* Fill in the descriptor */ 2265 xilinx_axidma_buf(chan, hw, vecs[i].addr, sg_used, 0); 2266 hw->control = copy; 2267 2268 if (prev) 2269 prev->hw.next_desc = segment->phys; 2270 2271 prev = segment; 2272 sg_used += copy; 2273 2274 /* 2275 * Insert the segment into the descriptor segments 2276 * list. 2277 */ 2278 list_add_tail(&segment->node, &desc->segments); 2279 } 2280 } 2281 2282 head = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, node); 2283 desc->async_tx.phys = head->phys; 2284 2285 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2286 if (chan->direction == DMA_MEM_TO_DEV) { 2287 segment->hw.control |= XILINX_DMA_BD_SOP; 2288 segment = list_last_entry(&desc->segments, 2289 struct xilinx_axidma_tx_segment, 2290 node); 2291 segment->hw.control |= XILINX_DMA_BD_EOP; 2292 } 2293 2294 if (chan->xdev->has_axistream_connected) 2295 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2296 2297 return &desc->async_tx; 2298 2299 error: 2300 xilinx_dma_free_tx_descriptor(chan, desc); 2301 return NULL; 2302 } 2303 2304 /** 2305 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2306 * @dchan: DMA channel 2307 * @sgl: scatterlist to transfer to/from 2308 * @sg_len: number of entries in @scatterlist 2309 * @direction: DMA direction 2310 * @flags: transfer ack flags 2311 * @context: APP words of the descriptor 2312 * 2313 * Return: Async transaction descriptor on success and NULL on failure 2314 */ 2315 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( 2316 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 2317 enum dma_transfer_direction direction, unsigned long flags, 2318 void *context) 2319 { 2320 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2321 struct xilinx_dma_tx_descriptor *desc; 2322 struct xilinx_axidma_tx_segment *segment = NULL; 2323 u32 *app_w = (u32 *)context; 2324 struct scatterlist *sg; 2325 size_t copy; 2326 size_t sg_used; 2327 unsigned int i; 2328 2329 if (!is_slave_direction(direction)) 2330 return NULL; 2331 2332 /* Allocate a transaction descriptor. */ 2333 desc = xilinx_dma_alloc_tx_descriptor(chan); 2334 if (!desc) 2335 return NULL; 2336 2337 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2338 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2339 2340 /* Build transactions using information in the scatter gather list */ 2341 for_each_sg(sgl, sg, sg_len, i) { 2342 sg_used = 0; 2343 2344 /* Loop until the entire scatterlist entry is used */ 2345 while (sg_used < sg_dma_len(sg)) { 2346 struct xilinx_axidma_desc_hw *hw; 2347 2348 /* Get a free segment */ 2349 segment = xilinx_axidma_alloc_tx_segment(chan); 2350 if (!segment) 2351 goto error; 2352 2353 /* 2354 * Calculate the maximum number of bytes to transfer, 2355 * making sure it is less than the hw limit 2356 */ 2357 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), 2358 sg_used); 2359 hw = &segment->hw; 2360 2361 /* Fill in the descriptor */ 2362 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), 2363 sg_used, 0); 2364 2365 hw->control = copy; 2366 2367 if (chan->direction == DMA_MEM_TO_DEV) { 2368 if (app_w) 2369 memcpy(hw->app, app_w, sizeof(u32) * 2370 XILINX_DMA_NUM_APP_WORDS); 2371 } 2372 2373 sg_used += copy; 2374 2375 /* 2376 * Insert the segment into the descriptor segments 2377 * list. 2378 */ 2379 list_add_tail(&segment->node, &desc->segments); 2380 } 2381 } 2382 2383 segment = list_first_entry(&desc->segments, 2384 struct xilinx_axidma_tx_segment, node); 2385 desc->async_tx.phys = segment->phys; 2386 2387 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2388 if (chan->direction == DMA_MEM_TO_DEV) { 2389 segment->hw.control |= XILINX_DMA_BD_SOP; 2390 segment = list_last_entry(&desc->segments, 2391 struct xilinx_axidma_tx_segment, 2392 node); 2393 segment->hw.control |= XILINX_DMA_BD_EOP; 2394 } 2395 2396 if (chan->xdev->has_axistream_connected) 2397 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2398 2399 return &desc->async_tx; 2400 2401 error: 2402 xilinx_dma_free_tx_descriptor(chan, desc); 2403 return NULL; 2404 } 2405 2406 /** 2407 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction 2408 * @dchan: DMA channel 2409 * @buf_addr: Physical address of the buffer 2410 * @buf_len: Total length of the cyclic buffers 2411 * @period_len: length of individual cyclic buffer 2412 * @direction: DMA direction 2413 * @flags: transfer ack flags 2414 * 2415 * Return: Async transaction descriptor on success and NULL on failure 2416 */ 2417 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( 2418 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len, 2419 size_t period_len, enum dma_transfer_direction direction, 2420 unsigned long flags) 2421 { 2422 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2423 struct xilinx_dma_tx_descriptor *desc; 2424 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL; 2425 size_t copy, sg_used; 2426 unsigned int num_periods; 2427 int i; 2428 u32 reg; 2429 2430 if (!period_len) 2431 return NULL; 2432 2433 num_periods = buf_len / period_len; 2434 2435 if (!num_periods) 2436 return NULL; 2437 2438 if (!is_slave_direction(direction)) 2439 return NULL; 2440 2441 /* Allocate a transaction descriptor. */ 2442 desc = xilinx_dma_alloc_tx_descriptor(chan); 2443 if (!desc) 2444 return NULL; 2445 2446 chan->direction = direction; 2447 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2448 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2449 2450 for (i = 0; i < num_periods; ++i) { 2451 sg_used = 0; 2452 2453 while (sg_used < period_len) { 2454 struct xilinx_axidma_desc_hw *hw; 2455 2456 /* Get a free segment */ 2457 segment = xilinx_axidma_alloc_tx_segment(chan); 2458 if (!segment) 2459 goto error; 2460 2461 /* 2462 * Calculate the maximum number of bytes to transfer, 2463 * making sure it is less than the hw limit 2464 */ 2465 copy = xilinx_dma_calc_copysize(chan, period_len, 2466 sg_used); 2467 hw = &segment->hw; 2468 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, 2469 period_len * i); 2470 hw->control = copy; 2471 2472 if (prev) 2473 prev->hw.next_desc = segment->phys; 2474 2475 prev = segment; 2476 sg_used += copy; 2477 2478 /* 2479 * Insert the segment into the descriptor segments 2480 * list. 2481 */ 2482 list_add_tail(&segment->node, &desc->segments); 2483 } 2484 } 2485 2486 head_segment = list_first_entry(&desc->segments, 2487 struct xilinx_axidma_tx_segment, node); 2488 desc->async_tx.phys = head_segment->phys; 2489 2490 desc->cyclic = true; 2491 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2492 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2493 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2494 2495 segment = list_last_entry(&desc->segments, 2496 struct xilinx_axidma_tx_segment, 2497 node); 2498 segment->hw.next_desc = (u32) head_segment->phys; 2499 2500 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2501 if (direction == DMA_MEM_TO_DEV) { 2502 head_segment->hw.control |= XILINX_DMA_BD_SOP; 2503 segment->hw.control |= XILINX_DMA_BD_EOP; 2504 } 2505 2506 return &desc->async_tx; 2507 2508 error: 2509 xilinx_dma_free_tx_descriptor(chan, desc); 2510 return NULL; 2511 } 2512 2513 /** 2514 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2515 * @dchan: DMA channel 2516 * @sgl: scatterlist to transfer to/from 2517 * @sg_len: number of entries in @scatterlist 2518 * @direction: DMA direction 2519 * @flags: transfer ack flags 2520 * @context: APP words of the descriptor 2521 * 2522 * Return: Async transaction descriptor on success and NULL on failure 2523 */ 2524 static struct dma_async_tx_descriptor * 2525 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 2526 unsigned int sg_len, 2527 enum dma_transfer_direction direction, 2528 unsigned long flags, void *context) 2529 { 2530 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2531 struct xilinx_dma_tx_descriptor *desc; 2532 struct xilinx_aximcdma_tx_segment *segment = NULL; 2533 u32 *app_w = (u32 *)context; 2534 struct scatterlist *sg; 2535 size_t copy; 2536 size_t sg_used; 2537 unsigned int i; 2538 2539 if (!is_slave_direction(direction)) 2540 return NULL; 2541 2542 /* Allocate a transaction descriptor. */ 2543 desc = xilinx_dma_alloc_tx_descriptor(chan); 2544 if (!desc) 2545 return NULL; 2546 2547 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2548 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2549 2550 /* Build transactions using information in the scatter gather list */ 2551 for_each_sg(sgl, sg, sg_len, i) { 2552 sg_used = 0; 2553 2554 /* Loop until the entire scatterlist entry is used */ 2555 while (sg_used < sg_dma_len(sg)) { 2556 struct xilinx_aximcdma_desc_hw *hw; 2557 2558 /* Get a free segment */ 2559 segment = xilinx_aximcdma_alloc_tx_segment(chan); 2560 if (!segment) 2561 goto error; 2562 2563 /* 2564 * Calculate the maximum number of bytes to transfer, 2565 * making sure it is less than the hw limit 2566 */ 2567 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 2568 chan->xdev->max_buffer_len); 2569 hw = &segment->hw; 2570 2571 /* Fill in the descriptor */ 2572 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), 2573 sg_used); 2574 hw->control = copy; 2575 2576 if (chan->direction == DMA_MEM_TO_DEV && app_w) { 2577 memcpy(hw->app, app_w, sizeof(u32) * 2578 XILINX_DMA_NUM_APP_WORDS); 2579 } 2580 2581 sg_used += copy; 2582 /* 2583 * Insert the segment into the descriptor segments 2584 * list. 2585 */ 2586 list_add_tail(&segment->node, &desc->segments); 2587 } 2588 } 2589 2590 segment = list_first_entry(&desc->segments, 2591 struct xilinx_aximcdma_tx_segment, node); 2592 desc->async_tx.phys = segment->phys; 2593 2594 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2595 if (chan->direction == DMA_MEM_TO_DEV) { 2596 segment->hw.control |= XILINX_MCDMA_BD_SOP; 2597 segment = list_last_entry(&desc->segments, 2598 struct xilinx_aximcdma_tx_segment, 2599 node); 2600 segment->hw.control |= XILINX_MCDMA_BD_EOP; 2601 } 2602 2603 return &desc->async_tx; 2604 2605 error: 2606 xilinx_dma_free_tx_descriptor(chan, desc); 2607 2608 return NULL; 2609 } 2610 2611 /** 2612 * xilinx_dma_terminate_all - Halt the channel and free descriptors 2613 * @dchan: Driver specific DMA Channel pointer 2614 * 2615 * Return: '0' always. 2616 */ 2617 static int xilinx_dma_terminate_all(struct dma_chan *dchan) 2618 { 2619 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2620 u32 reg; 2621 int err; 2622 2623 if (!chan->cyclic) { 2624 err = chan->stop_transfer(chan); 2625 if (err) { 2626 dev_err(chan->dev, "Cannot stop channel %p: %x\n", 2627 chan, dma_ctrl_read(chan, 2628 XILINX_DMA_REG_DMASR)); 2629 chan->err = true; 2630 } 2631 } 2632 2633 xilinx_dma_chan_reset(chan); 2634 /* Remove and free all of the descriptors in the lists */ 2635 chan->terminating = true; 2636 xilinx_dma_free_descriptors(chan); 2637 chan->idle = true; 2638 2639 if (chan->cyclic) { 2640 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2641 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2642 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2643 chan->cyclic = false; 2644 } 2645 2646 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 2647 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2648 XILINX_CDMA_CR_SGMODE); 2649 2650 return 0; 2651 } 2652 2653 static void xilinx_dma_synchronize(struct dma_chan *dchan) 2654 { 2655 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2656 2657 tasklet_kill(&chan->tasklet); 2658 } 2659 2660 /** 2661 * xilinx_vdma_channel_set_config - Configure VDMA channel 2662 * Run-time configuration for Axi VDMA, supports: 2663 * . halt the channel 2664 * . configure interrupt coalescing and inter-packet delay threshold 2665 * . start/stop parking 2666 * . enable genlock 2667 * 2668 * @dchan: DMA channel 2669 * @cfg: VDMA device configuration pointer 2670 * 2671 * Return: '0' on success and failure value on error 2672 */ 2673 int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 2674 struct xilinx_vdma_config *cfg) 2675 { 2676 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2677 u32 dmacr; 2678 2679 if (cfg->reset) 2680 return xilinx_dma_chan_reset(chan); 2681 2682 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2683 2684 chan->config.frm_dly = cfg->frm_dly; 2685 chan->config.park = cfg->park; 2686 2687 /* genlock settings */ 2688 chan->config.gen_lock = cfg->gen_lock; 2689 chan->config.master = cfg->master; 2690 2691 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; 2692 if (cfg->gen_lock && chan->genlock) { 2693 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; 2694 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; 2695 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; 2696 } 2697 2698 chan->config.frm_cnt_en = cfg->frm_cnt_en; 2699 chan->config.vflip_en = cfg->vflip_en; 2700 2701 if (cfg->park) 2702 chan->config.park_frm = cfg->park_frm; 2703 else 2704 chan->config.park_frm = -1; 2705 2706 chan->config.coalesc = cfg->coalesc; 2707 chan->config.delay = cfg->delay; 2708 2709 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { 2710 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; 2711 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; 2712 chan->config.coalesc = cfg->coalesc; 2713 } 2714 2715 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { 2716 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; 2717 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; 2718 chan->config.delay = cfg->delay; 2719 } 2720 2721 /* FSync Source selection */ 2722 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; 2723 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; 2724 2725 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); 2726 2727 return 0; 2728 } 2729 EXPORT_SYMBOL(xilinx_vdma_channel_set_config); 2730 2731 /* ----------------------------------------------------------------------------- 2732 * Probe and remove 2733 */ 2734 2735 /** 2736 * xilinx_dma_chan_remove - Per Channel remove function 2737 * @chan: Driver specific DMA channel 2738 */ 2739 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) 2740 { 2741 /* Disable all interrupts */ 2742 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2743 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 2744 2745 if (chan->irq > 0) 2746 free_irq(chan->irq, chan); 2747 2748 tasklet_kill(&chan->tasklet); 2749 2750 list_del(&chan->common.device_node); 2751 } 2752 2753 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2754 struct clk **tx_clk, struct clk **rx_clk, 2755 struct clk **sg_clk, struct clk **tmp_clk) 2756 { 2757 int err; 2758 2759 *tmp_clk = NULL; 2760 2761 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2762 if (IS_ERR(*axi_clk)) 2763 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2764 2765 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2766 if (IS_ERR(*tx_clk)) 2767 *tx_clk = NULL; 2768 2769 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2770 if (IS_ERR(*rx_clk)) 2771 *rx_clk = NULL; 2772 2773 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); 2774 if (IS_ERR(*sg_clk)) 2775 *sg_clk = NULL; 2776 2777 err = clk_prepare_enable(*axi_clk); 2778 if (err) { 2779 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2780 return err; 2781 } 2782 2783 err = clk_prepare_enable(*tx_clk); 2784 if (err) { 2785 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2786 goto err_disable_axiclk; 2787 } 2788 2789 err = clk_prepare_enable(*rx_clk); 2790 if (err) { 2791 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2792 goto err_disable_txclk; 2793 } 2794 2795 err = clk_prepare_enable(*sg_clk); 2796 if (err) { 2797 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); 2798 goto err_disable_rxclk; 2799 } 2800 2801 return 0; 2802 2803 err_disable_rxclk: 2804 clk_disable_unprepare(*rx_clk); 2805 err_disable_txclk: 2806 clk_disable_unprepare(*tx_clk); 2807 err_disable_axiclk: 2808 clk_disable_unprepare(*axi_clk); 2809 2810 return err; 2811 } 2812 2813 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2814 struct clk **dev_clk, struct clk **tmp_clk, 2815 struct clk **tmp1_clk, struct clk **tmp2_clk) 2816 { 2817 int err; 2818 2819 *tmp_clk = NULL; 2820 *tmp1_clk = NULL; 2821 *tmp2_clk = NULL; 2822 2823 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2824 if (IS_ERR(*axi_clk)) 2825 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2826 2827 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); 2828 if (IS_ERR(*dev_clk)) 2829 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); 2830 2831 err = clk_prepare_enable(*axi_clk); 2832 if (err) { 2833 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2834 return err; 2835 } 2836 2837 err = clk_prepare_enable(*dev_clk); 2838 if (err) { 2839 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); 2840 goto err_disable_axiclk; 2841 } 2842 2843 return 0; 2844 2845 err_disable_axiclk: 2846 clk_disable_unprepare(*axi_clk); 2847 2848 return err; 2849 } 2850 2851 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2852 struct clk **tx_clk, struct clk **txs_clk, 2853 struct clk **rx_clk, struct clk **rxs_clk) 2854 { 2855 int err; 2856 2857 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2858 if (IS_ERR(*axi_clk)) 2859 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2860 2861 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2862 if (IS_ERR(*tx_clk)) 2863 *tx_clk = NULL; 2864 2865 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); 2866 if (IS_ERR(*txs_clk)) 2867 *txs_clk = NULL; 2868 2869 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2870 if (IS_ERR(*rx_clk)) 2871 *rx_clk = NULL; 2872 2873 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); 2874 if (IS_ERR(*rxs_clk)) 2875 *rxs_clk = NULL; 2876 2877 err = clk_prepare_enable(*axi_clk); 2878 if (err) { 2879 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", 2880 err); 2881 return err; 2882 } 2883 2884 err = clk_prepare_enable(*tx_clk); 2885 if (err) { 2886 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2887 goto err_disable_axiclk; 2888 } 2889 2890 err = clk_prepare_enable(*txs_clk); 2891 if (err) { 2892 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); 2893 goto err_disable_txclk; 2894 } 2895 2896 err = clk_prepare_enable(*rx_clk); 2897 if (err) { 2898 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2899 goto err_disable_txsclk; 2900 } 2901 2902 err = clk_prepare_enable(*rxs_clk); 2903 if (err) { 2904 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); 2905 goto err_disable_rxclk; 2906 } 2907 2908 return 0; 2909 2910 err_disable_rxclk: 2911 clk_disable_unprepare(*rx_clk); 2912 err_disable_txsclk: 2913 clk_disable_unprepare(*txs_clk); 2914 err_disable_txclk: 2915 clk_disable_unprepare(*tx_clk); 2916 err_disable_axiclk: 2917 clk_disable_unprepare(*axi_clk); 2918 2919 return err; 2920 } 2921 2922 static void xdma_disable_allclks(struct xilinx_dma_device *xdev) 2923 { 2924 clk_disable_unprepare(xdev->rxs_clk); 2925 clk_disable_unprepare(xdev->rx_clk); 2926 clk_disable_unprepare(xdev->txs_clk); 2927 clk_disable_unprepare(xdev->tx_clk); 2928 clk_disable_unprepare(xdev->axi_clk); 2929 } 2930 2931 /** 2932 * xilinx_dma_chan_probe - Per Channel Probing 2933 * It get channel features from the device tree entry and 2934 * initialize special channel handling routines 2935 * 2936 * @xdev: Driver specific device structure 2937 * @node: Device node 2938 * 2939 * Return: '0' on success and failure value on error 2940 */ 2941 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, 2942 struct device_node *node) 2943 { 2944 struct xilinx_dma_chan *chan; 2945 bool has_dre = false; 2946 u32 value, width; 2947 int err; 2948 2949 /* Allocate and initialize the channel structure */ 2950 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 2951 if (!chan) 2952 return -ENOMEM; 2953 2954 chan->dev = xdev->dev; 2955 chan->xdev = xdev; 2956 chan->desc_pendingcount = 0x0; 2957 chan->ext_addr = xdev->ext_addr; 2958 /* This variable ensures that descriptors are not 2959 * Submitted when dma engine is in progress. This variable is 2960 * Added to avoid polling for a bit in the status register to 2961 * Know dma state in the driver hot path. 2962 */ 2963 chan->idle = true; 2964 2965 spin_lock_init(&chan->lock); 2966 INIT_LIST_HEAD(&chan->pending_list); 2967 INIT_LIST_HEAD(&chan->done_list); 2968 INIT_LIST_HEAD(&chan->active_list); 2969 INIT_LIST_HEAD(&chan->free_seg_list); 2970 2971 /* Retrieve the channel properties from the device tree */ 2972 has_dre = of_property_read_bool(node, "xlnx,include-dre"); 2973 2974 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); 2975 2976 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); 2977 2978 err = of_property_read_u32(node, "xlnx,datawidth", &value); 2979 if (err) { 2980 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); 2981 return err; 2982 } 2983 width = value >> 3; /* Convert bits to bytes */ 2984 2985 /* If data width is greater than 8 bytes, DRE is not in hw */ 2986 if (width > 8) 2987 has_dre = false; 2988 2989 if (!has_dre) 2990 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); 2991 2992 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || 2993 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || 2994 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { 2995 chan->direction = DMA_MEM_TO_DEV; 2996 chan->id = xdev->mm2s_chan_id++; 2997 chan->tdest = chan->id; 2998 2999 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; 3000 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3001 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; 3002 chan->config.park = 1; 3003 3004 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 3005 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) 3006 chan->flush_on_fsync = true; 3007 } 3008 } else if (of_device_is_compatible(node, 3009 "xlnx,axi-vdma-s2mm-channel") || 3010 of_device_is_compatible(node, 3011 "xlnx,axi-dma-s2mm-channel")) { 3012 chan->direction = DMA_DEV_TO_MEM; 3013 chan->id = xdev->s2mm_chan_id++; 3014 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; 3015 chan->has_vflip = of_property_read_bool(node, 3016 "xlnx,enable-vert-flip"); 3017 if (chan->has_vflip) { 3018 chan->config.vflip_en = dma_read(chan, 3019 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) & 3020 XILINX_VDMA_ENABLE_VERTICAL_FLIP; 3021 } 3022 3023 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3024 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; 3025 else 3026 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; 3027 3028 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3029 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; 3030 chan->config.park = 1; 3031 3032 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 3033 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) 3034 chan->flush_on_fsync = true; 3035 } 3036 } else { 3037 dev_err(xdev->dev, "Invalid channel compatible node\n"); 3038 return -EINVAL; 3039 } 3040 3041 xdev->common.directions |= BIT(chan->direction); 3042 3043 /* Request the interrupt */ 3044 chan->irq = of_irq_get(node, chan->tdest); 3045 if (chan->irq < 0) 3046 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); 3047 err = request_irq(chan->irq, xdev->dma_config->irq_handler, 3048 IRQF_SHARED, "xilinx-dma-controller", chan); 3049 if (err) { 3050 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); 3051 return err; 3052 } 3053 3054 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3055 chan->start_transfer = xilinx_dma_start_transfer; 3056 chan->stop_transfer = xilinx_dma_stop_transfer; 3057 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3058 chan->start_transfer = xilinx_mcdma_start_transfer; 3059 chan->stop_transfer = xilinx_dma_stop_transfer; 3060 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3061 chan->start_transfer = xilinx_cdma_start_transfer; 3062 chan->stop_transfer = xilinx_cdma_stop_transfer; 3063 } else { 3064 chan->start_transfer = xilinx_vdma_start_transfer; 3065 chan->stop_transfer = xilinx_dma_stop_transfer; 3066 } 3067 3068 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */ 3069 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { 3070 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || 3071 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & 3072 XILINX_DMA_DMASR_SG_MASK) 3073 chan->has_sg = true; 3074 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, 3075 str_enabled_disabled(chan->has_sg)); 3076 } 3077 3078 /* Initialize the tasklet */ 3079 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); 3080 3081 /* 3082 * Initialize the DMA channel and add it to the DMA engine channels 3083 * list. 3084 */ 3085 chan->common.device = &xdev->common; 3086 3087 list_add_tail(&chan->common.device_node, &xdev->common.channels); 3088 xdev->chan[chan->id] = chan; 3089 3090 /* Reset the channel */ 3091 err = xilinx_dma_chan_reset(chan); 3092 if (err < 0) { 3093 dev_err(xdev->dev, "Reset channel failed\n"); 3094 return err; 3095 } 3096 3097 return 0; 3098 } 3099 3100 /** 3101 * xilinx_dma_child_probe - Per child node probe 3102 * It get number of dma-channels per child node from 3103 * device-tree and initializes all the channels. 3104 * 3105 * @xdev: Driver specific device structure 3106 * @node: Device node 3107 * 3108 * Return: '0' on success and failure value on error. 3109 */ 3110 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, 3111 struct device_node *node) 3112 { 3113 int ret, i; 3114 u32 nr_channels = 1; 3115 3116 ret = of_property_read_u32(node, "dma-channels", &nr_channels); 3117 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) 3118 dev_warn(xdev->dev, "missing dma-channels property\n"); 3119 3120 for (i = 0; i < nr_channels; i++) { 3121 ret = xilinx_dma_chan_probe(xdev, node); 3122 if (ret) 3123 return ret; 3124 } 3125 3126 return 0; 3127 } 3128 3129 /** 3130 * of_dma_xilinx_xlate - Translation function 3131 * @dma_spec: Pointer to DMA specifier as found in the device tree 3132 * @ofdma: Pointer to DMA controller data 3133 * 3134 * Return: DMA channel pointer on success and NULL on error 3135 */ 3136 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 3137 struct of_dma *ofdma) 3138 { 3139 struct xilinx_dma_device *xdev = ofdma->of_dma_data; 3140 int chan_id = dma_spec->args[0]; 3141 3142 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) 3143 return NULL; 3144 3145 return dma_get_slave_channel(&xdev->chan[chan_id]->common); 3146 } 3147 3148 static const struct xilinx_dma_config axidma_config = { 3149 .dmatype = XDMA_TYPE_AXIDMA, 3150 .clk_init = axidma_clk_init, 3151 .irq_handler = xilinx_dma_irq_handler, 3152 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3153 }; 3154 3155 static const struct xilinx_dma_config aximcdma_config = { 3156 .dmatype = XDMA_TYPE_AXIMCDMA, 3157 .clk_init = axidma_clk_init, 3158 .irq_handler = xilinx_mcdma_irq_handler, 3159 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE, 3160 }; 3161 static const struct xilinx_dma_config axicdma_config = { 3162 .dmatype = XDMA_TYPE_CDMA, 3163 .clk_init = axicdma_clk_init, 3164 .irq_handler = xilinx_dma_irq_handler, 3165 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE, 3166 }; 3167 3168 static const struct xilinx_dma_config axivdma_config = { 3169 .dmatype = XDMA_TYPE_VDMA, 3170 .clk_init = axivdma_clk_init, 3171 .irq_handler = xilinx_dma_irq_handler, 3172 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3173 }; 3174 3175 static const struct of_device_id xilinx_dma_of_ids[] = { 3176 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, 3177 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, 3178 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, 3179 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config }, 3180 {} 3181 }; 3182 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); 3183 3184 /** 3185 * xilinx_dma_probe - Driver probe function 3186 * @pdev: Pointer to the platform_device structure 3187 * 3188 * Return: '0' on success and failure value on error 3189 */ 3190 static int xilinx_dma_probe(struct platform_device *pdev) 3191 { 3192 int (*clk_init)(struct platform_device *, struct clk **, struct clk **, 3193 struct clk **, struct clk **, struct clk **) 3194 = axivdma_clk_init; 3195 struct device_node *node = pdev->dev.of_node; 3196 struct xilinx_dma_device *xdev; 3197 struct device_node *np = pdev->dev.of_node; 3198 u32 num_frames, addr_width = XILINX_DMA_DFAULT_ADDRWIDTH, len_width; 3199 int i, err; 3200 3201 /* Allocate and initialize the DMA engine structure */ 3202 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 3203 if (!xdev) 3204 return -ENOMEM; 3205 3206 xdev->dev = &pdev->dev; 3207 if (np) { 3208 const struct of_device_id *match; 3209 3210 match = of_match_node(xilinx_dma_of_ids, np); 3211 if (match && match->data) { 3212 xdev->dma_config = match->data; 3213 clk_init = xdev->dma_config->clk_init; 3214 } 3215 } 3216 3217 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, 3218 &xdev->rx_clk, &xdev->rxs_clk); 3219 if (err) 3220 return err; 3221 3222 /* Request and map I/O memory */ 3223 xdev->regs = devm_platform_ioremap_resource(pdev, 0); 3224 if (IS_ERR(xdev->regs)) { 3225 err = PTR_ERR(xdev->regs); 3226 goto disable_clks; 3227 } 3228 /* Retrieve the DMA engine properties from the device tree */ 3229 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); 3230 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; 3231 3232 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || 3233 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3234 if (!of_property_read_u32(node, "xlnx,sg-length-width", 3235 &len_width)) { 3236 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || 3237 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { 3238 dev_warn(xdev->dev, 3239 "invalid xlnx,sg-length-width property value. Using default width\n"); 3240 } else { 3241 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) 3242 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); 3243 xdev->max_buffer_len = 3244 GENMASK(len_width - 1, 0); 3245 } 3246 } 3247 } 3248 3249 dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len); 3250 3251 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3252 xdev->has_axistream_connected = 3253 of_property_read_bool(node, "xlnx,axistream-connected"); 3254 } 3255 3256 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3257 err = of_property_read_u32(node, "xlnx,num-fstores", 3258 &num_frames); 3259 if (err < 0) { 3260 dev_err(xdev->dev, 3261 "missing xlnx,num-fstores property\n"); 3262 goto disable_clks; 3263 } 3264 3265 err = of_property_read_u32(node, "xlnx,flush-fsync", 3266 &xdev->flush_on_fsync); 3267 if (err < 0) 3268 dev_warn(xdev->dev, 3269 "missing xlnx,flush-fsync property\n"); 3270 } 3271 3272 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); 3273 if (err < 0) 3274 dev_warn(xdev->dev, 3275 "missing xlnx,addrwidth property, using default value %d\n", 3276 XILINX_DMA_DFAULT_ADDRWIDTH); 3277 3278 if (addr_width > 32) 3279 xdev->ext_addr = true; 3280 else 3281 xdev->ext_addr = false; 3282 3283 /* Set metadata mode */ 3284 if (xdev->has_axistream_connected) 3285 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; 3286 3287 /* Set the dma mask bits */ 3288 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); 3289 if (err < 0) { 3290 dev_err(xdev->dev, "DMA mask error %d\n", err); 3291 goto disable_clks; 3292 } 3293 3294 /* Initialize the DMA engine */ 3295 xdev->common.dev = &pdev->dev; 3296 3297 INIT_LIST_HEAD(&xdev->common.channels); 3298 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { 3299 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); 3300 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); 3301 } 3302 3303 xdev->common.device_alloc_chan_resources = 3304 xilinx_dma_alloc_chan_resources; 3305 xdev->common.device_free_chan_resources = 3306 xilinx_dma_free_chan_resources; 3307 xdev->common.device_terminate_all = xilinx_dma_terminate_all; 3308 xdev->common.device_synchronize = xilinx_dma_synchronize; 3309 xdev->common.device_tx_status = xilinx_dma_tx_status; 3310 xdev->common.device_issue_pending = xilinx_dma_issue_pending; 3311 xdev->common.device_config = xilinx_dma_device_config; 3312 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3313 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); 3314 xdev->common.device_prep_peripheral_dma_vec = xilinx_dma_prep_peripheral_dma_vec; 3315 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; 3316 xdev->common.device_prep_dma_cyclic = 3317 xilinx_dma_prep_dma_cyclic; 3318 /* Residue calculation is supported by only AXI DMA and CDMA */ 3319 xdev->common.residue_granularity = 3320 DMA_RESIDUE_GRANULARITY_SEGMENT; 3321 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3322 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); 3323 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; 3324 /* Residue calculation is supported by only AXI DMA and CDMA */ 3325 xdev->common.residue_granularity = 3326 DMA_RESIDUE_GRANULARITY_SEGMENT; 3327 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3328 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; 3329 } else { 3330 xdev->common.device_prep_interleaved_dma = 3331 xilinx_vdma_dma_prep_interleaved; 3332 } 3333 3334 platform_set_drvdata(pdev, xdev); 3335 3336 /* Initialize the channels */ 3337 for_each_child_of_node_scoped(node, child) { 3338 err = xilinx_dma_child_probe(xdev, child); 3339 if (err < 0) 3340 goto error; 3341 } 3342 3343 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3344 for (i = 0; i < xdev->dma_config->max_channels; i++) 3345 if (xdev->chan[i]) 3346 xdev->chan[i]->num_frms = num_frames; 3347 } 3348 3349 /* Register the DMA engine with the core */ 3350 err = dma_async_device_register(&xdev->common); 3351 if (err) { 3352 dev_err(xdev->dev, "failed to register the dma device\n"); 3353 goto error; 3354 } 3355 3356 err = of_dma_controller_register(node, of_dma_xilinx_xlate, 3357 xdev); 3358 if (err < 0) { 3359 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); 3360 dma_async_device_unregister(&xdev->common); 3361 goto error; 3362 } 3363 3364 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) 3365 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); 3366 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) 3367 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); 3368 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3369 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); 3370 else 3371 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); 3372 3373 return 0; 3374 3375 error: 3376 for (i = 0; i < xdev->dma_config->max_channels; i++) 3377 if (xdev->chan[i]) 3378 xilinx_dma_chan_remove(xdev->chan[i]); 3379 disable_clks: 3380 xdma_disable_allclks(xdev); 3381 3382 return err; 3383 } 3384 3385 /** 3386 * xilinx_dma_remove - Driver remove function 3387 * @pdev: Pointer to the platform_device structure 3388 */ 3389 static void xilinx_dma_remove(struct platform_device *pdev) 3390 { 3391 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); 3392 int i; 3393 3394 of_dma_controller_free(pdev->dev.of_node); 3395 3396 dma_async_device_unregister(&xdev->common); 3397 3398 for (i = 0; i < xdev->dma_config->max_channels; i++) 3399 if (xdev->chan[i]) 3400 xilinx_dma_chan_remove(xdev->chan[i]); 3401 3402 xdma_disable_allclks(xdev); 3403 } 3404 3405 static struct platform_driver xilinx_vdma_driver = { 3406 .driver = { 3407 .name = "xilinx-vdma", 3408 .of_match_table = xilinx_dma_of_ids, 3409 }, 3410 .probe = xilinx_dma_probe, 3411 .remove = xilinx_dma_remove, 3412 }; 3413 3414 module_platform_driver(xilinx_vdma_driver); 3415 3416 MODULE_AUTHOR("Xilinx, Inc."); 3417 MODULE_DESCRIPTION("Xilinx VDMA driver"); 3418 MODULE_LICENSE("GPL v2"); 3419