1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
4 *
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <sound/core.h>
13 #include <linux/mutex.h>
14 #include <linux/iopoll.h>
15
16 #include "patch_cs8409.h"
17
18 /******************************************************************************
19 * CS8409 Specific Functions
20 ******************************************************************************/
21
cs8409_parse_auto_config(struct hda_codec * codec)22 static int cs8409_parse_auto_config(struct hda_codec *codec)
23 {
24 struct cs8409_spec *spec = codec->spec;
25 int err;
26 int i;
27
28 err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
29 if (err < 0)
30 return err;
31
32 err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
33 if (err < 0)
34 return err;
35
36 /* keep the ADCs powered up when it's dynamically switchable */
37 if (spec->gen.dyn_adc_switch) {
38 unsigned int done = 0;
39
40 for (i = 0; i < spec->gen.input_mux.num_items; i++) {
41 int idx = spec->gen.dyn_adc_idx[i];
42
43 if (done & (1 << idx))
44 continue;
45 snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
46 done |= 1 << idx;
47 }
48 }
49
50 return 0;
51 }
52
53 static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
54
cs8409_alloc_spec(struct hda_codec * codec)55 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
56 {
57 struct cs8409_spec *spec;
58
59 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
60 if (!spec)
61 return NULL;
62 codec->spec = spec;
63 spec->codec = codec;
64 codec->power_save_node = 1;
65 mutex_init(&spec->i2c_mux);
66 INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
67 snd_hda_gen_spec_init(&spec->gen);
68
69 return spec;
70 }
71
cs8409_vendor_coef_get(struct hda_codec * codec,unsigned int idx)72 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
73 {
74 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
75 return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
76 }
77
cs8409_vendor_coef_set(struct hda_codec * codec,unsigned int idx,unsigned int coef)78 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
79 unsigned int coef)
80 {
81 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
82 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
83 }
84
85 /*
86 * cs8409_enable_i2c_clock - Disable I2C clocks
87 * @codec: the codec instance
88 * Disable I2C clocks.
89 * This must be called when the i2c mutex is unlocked.
90 */
cs8409_disable_i2c_clock(struct hda_codec * codec)91 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
92 {
93 struct cs8409_spec *spec = codec->spec;
94
95 mutex_lock(&spec->i2c_mux);
96 if (spec->i2c_clck_enabled) {
97 cs8409_vendor_coef_set(spec->codec, 0x0,
98 cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
99 spec->i2c_clck_enabled = 0;
100 }
101 mutex_unlock(&spec->i2c_mux);
102 }
103
104 /*
105 * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
106 */
cs8409_disable_i2c_clock_worker(struct work_struct * work)107 static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
108 {
109 struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
110
111 cs8409_disable_i2c_clock(spec->codec);
112 }
113
114 /*
115 * cs8409_enable_i2c_clock - Enable I2C clocks
116 * @codec: the codec instance
117 * Enable I2C clocks.
118 * This must be called when the i2c mutex is locked.
119 */
cs8409_enable_i2c_clock(struct hda_codec * codec)120 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
121 {
122 struct cs8409_spec *spec = codec->spec;
123
124 /* Cancel the disable timer, but do not wait for any running disable functions to finish.
125 * If the disable timer runs out before cancel, the delayed work thread will be blocked,
126 * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
127 * any i2c transaction, so the disable function will run to completion immediately
128 * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
129 */
130 cancel_delayed_work(&spec->i2c_clk_work);
131
132 if (!spec->i2c_clck_enabled) {
133 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
134 spec->i2c_clck_enabled = 1;
135 }
136 queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
137 }
138
139 /**
140 * cs8409_i2c_wait_complete - Wait for I2C transaction
141 * @codec: the codec instance
142 *
143 * Wait for I2C transaction to complete.
144 * Return -ETIMEDOUT if transaction wait times out.
145 */
cs8409_i2c_wait_complete(struct hda_codec * codec)146 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
147 {
148 unsigned int retval;
149
150 return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
151 CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
152 }
153
154 /**
155 * cs8409_set_i2c_dev_addr - Set i2c address for transaction
156 * @codec: the codec instance
157 * @addr: I2C Address
158 */
cs8409_set_i2c_dev_addr(struct hda_codec * codec,unsigned int addr)159 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
160 {
161 struct cs8409_spec *spec = codec->spec;
162
163 if (spec->dev_addr != addr) {
164 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
165 spec->dev_addr = addr;
166 }
167 }
168
169 /**
170 * cs8409_i2c_set_page - CS8409 I2C set page register.
171 * @scodec: the codec instance
172 * @i2c_reg: Page register
173 *
174 * Returns negative on error.
175 */
cs8409_i2c_set_page(struct sub_codec * scodec,unsigned int i2c_reg)176 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
177 {
178 struct hda_codec *codec = scodec->codec;
179
180 if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
181 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
182 if (cs8409_i2c_wait_complete(codec) < 0)
183 return -EIO;
184 scodec->last_page = i2c_reg >> 8;
185 }
186
187 return 0;
188 }
189
190 /**
191 * cs8409_i2c_read - CS8409 I2C Read.
192 * @scodec: the codec instance
193 * @addr: Register to read
194 *
195 * Returns negative on error, otherwise returns read value in bits 0-7.
196 */
cs8409_i2c_read(struct sub_codec * scodec,unsigned int addr)197 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
198 {
199 struct hda_codec *codec = scodec->codec;
200 struct cs8409_spec *spec = codec->spec;
201 unsigned int i2c_reg_data;
202 unsigned int read_data;
203
204 if (scodec->suspended)
205 return -EPERM;
206
207 mutex_lock(&spec->i2c_mux);
208 cs8409_enable_i2c_clock(codec);
209 cs8409_set_i2c_dev_addr(codec, scodec->addr);
210
211 if (cs8409_i2c_set_page(scodec, addr))
212 goto error;
213
214 i2c_reg_data = (addr << 8) & 0x0ffff;
215 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
216 if (cs8409_i2c_wait_complete(codec) < 0)
217 goto error;
218
219 /* Register in bits 15-8 and the data in 7-0 */
220 read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
221
222 mutex_unlock(&spec->i2c_mux);
223
224 return read_data & 0x0ff;
225
226 error:
227 mutex_unlock(&spec->i2c_mux);
228 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
229 return -EIO;
230 }
231
232 /**
233 * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
234 * @scodec: the codec instance
235 * @seq: Register Sequence to read
236 * @count: Number of registeres to read
237 *
238 * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
239 */
cs8409_i2c_bulk_read(struct sub_codec * scodec,struct cs8409_i2c_param * seq,int count)240 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
241 {
242 struct hda_codec *codec = scodec->codec;
243 struct cs8409_spec *spec = codec->spec;
244 unsigned int i2c_reg_data;
245 int i;
246
247 if (scodec->suspended)
248 return -EPERM;
249
250 mutex_lock(&spec->i2c_mux);
251 cs8409_set_i2c_dev_addr(codec, scodec->addr);
252
253 for (i = 0; i < count; i++) {
254 cs8409_enable_i2c_clock(codec);
255 if (cs8409_i2c_set_page(scodec, seq[i].addr))
256 goto error;
257
258 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
259 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
260
261 if (cs8409_i2c_wait_complete(codec) < 0)
262 goto error;
263
264 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
265 }
266
267 mutex_unlock(&spec->i2c_mux);
268
269 return 0;
270
271 error:
272 mutex_unlock(&spec->i2c_mux);
273 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
274 return -EIO;
275 }
276
277 /**
278 * cs8409_i2c_write - CS8409 I2C Write.
279 * @scodec: the codec instance
280 * @addr: Register to write to
281 * @value: Data to write
282 *
283 * Returns negative on error, otherwise returns 0.
284 */
cs8409_i2c_write(struct sub_codec * scodec,unsigned int addr,unsigned int value)285 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
286 {
287 struct hda_codec *codec = scodec->codec;
288 struct cs8409_spec *spec = codec->spec;
289 unsigned int i2c_reg_data;
290
291 if (scodec->suspended)
292 return -EPERM;
293
294 mutex_lock(&spec->i2c_mux);
295
296 cs8409_enable_i2c_clock(codec);
297 cs8409_set_i2c_dev_addr(codec, scodec->addr);
298
299 if (cs8409_i2c_set_page(scodec, addr))
300 goto error;
301
302 i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
303 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
304
305 if (cs8409_i2c_wait_complete(codec) < 0)
306 goto error;
307
308 mutex_unlock(&spec->i2c_mux);
309 return 0;
310
311 error:
312 mutex_unlock(&spec->i2c_mux);
313 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
314 return -EIO;
315 }
316
317 /**
318 * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
319 * @scodec: the codec instance
320 * @seq: Register Sequence to write
321 * @count: Number of registeres to write
322 *
323 * Returns negative on error.
324 */
cs8409_i2c_bulk_write(struct sub_codec * scodec,const struct cs8409_i2c_param * seq,int count)325 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
326 int count)
327 {
328 struct hda_codec *codec = scodec->codec;
329 struct cs8409_spec *spec = codec->spec;
330 unsigned int i2c_reg_data;
331 int i;
332
333 if (scodec->suspended)
334 return -EPERM;
335
336 mutex_lock(&spec->i2c_mux);
337 cs8409_set_i2c_dev_addr(codec, scodec->addr);
338
339 for (i = 0; i < count; i++) {
340 cs8409_enable_i2c_clock(codec);
341 if (cs8409_i2c_set_page(scodec, seq[i].addr))
342 goto error;
343
344 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
345 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
346
347 if (cs8409_i2c_wait_complete(codec) < 0)
348 goto error;
349 /* Certain use cases may require a delay
350 * after a write operation before proceeding.
351 */
352 if (seq[i].delay)
353 fsleep(seq[i].delay);
354 }
355
356 mutex_unlock(&spec->i2c_mux);
357
358 return 0;
359
360 error:
361 mutex_unlock(&spec->i2c_mux);
362 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
363 return -EIO;
364 }
365
cs8409_init(struct hda_codec * codec)366 static int cs8409_init(struct hda_codec *codec)
367 {
368 int ret = snd_hda_gen_init(codec);
369
370 if (!ret)
371 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
372
373 return ret;
374 }
375
cs8409_build_controls(struct hda_codec * codec)376 static int cs8409_build_controls(struct hda_codec *codec)
377 {
378 int err;
379
380 err = snd_hda_gen_build_controls(codec);
381 if (err < 0)
382 return err;
383 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
384
385 return 0;
386 }
387
388 /* Enable/Disable Unsolicited Response */
cs8409_enable_ur(struct hda_codec * codec,int flag)389 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
390 {
391 struct cs8409_spec *spec = codec->spec;
392 unsigned int ur_gpios = 0;
393 int i;
394
395 for (i = 0; i < spec->num_scodecs; i++)
396 ur_gpios |= spec->scodecs[i]->irq_mask;
397
398 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
399 flag ? ur_gpios : 0);
400
401 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
402 flag ? AC_UNSOL_ENABLED : 0);
403 }
404
cs8409_fix_caps(struct hda_codec * codec,unsigned int nid)405 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
406 {
407 int caps;
408
409 /* CS8409 is simple HDA bridge and intended to be used with a remote
410 * companion codec. Most of input/output PIN(s) have only basic
411 * capabilities. Receive and Transmit NID(s) have only OUTC and INC
412 * capabilities and no presence detect capable (PDC) and call to
413 * snd_hda_gen_build_controls() will mark them as non detectable
414 * phantom jacks. However, a companion codec may be
415 * connected to these pins which supports jack detect
416 * capabilities. We have to override pin capabilities,
417 * otherwise they will not be created as input devices.
418 */
419 caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
420 if (caps >= 0)
421 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
422 (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
423
424 snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
425 }
426
cs8409_spk_sw_gpio_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)427 static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429 {
430 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct cs8409_spec *spec = codec->spec;
432
433 ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio);
434 return 0;
435 }
436
cs8409_spk_sw_gpio_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)437 static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol,
438 struct snd_ctl_elem_value *ucontrol)
439 {
440 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
441 struct cs8409_spec *spec = codec->spec;
442 unsigned int gpio_data;
443
444 gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) |
445 (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0);
446 if (gpio_data == spec->gpio_data)
447 return 0;
448 spec->gpio_data = gpio_data;
449 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
450 return 1;
451 }
452
453 static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = {
454 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
455 .info = snd_ctl_boolean_mono_info,
456 .get = cs8409_spk_sw_gpio_get,
457 .put = cs8409_spk_sw_gpio_put,
458 };
459
460 /******************************************************************************
461 * CS42L42 Specific Functions
462 ******************************************************************************/
463
cs42l42_volume_info(struct snd_kcontrol * kctrl,struct snd_ctl_elem_info * uinfo)464 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
465 {
466 unsigned int ofs = get_amp_offset(kctrl);
467 u8 chs = get_amp_channels(kctrl);
468
469 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
470 uinfo->value.integer.step = 1;
471 uinfo->count = chs == 3 ? 2 : 1;
472
473 switch (ofs) {
474 case CS42L42_VOL_DAC:
475 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
476 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
477 break;
478 case CS42L42_VOL_ADC:
479 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
480 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
481 break;
482 default:
483 break;
484 }
485
486 return 0;
487 }
488
cs42l42_volume_get(struct snd_kcontrol * kctrl,struct snd_ctl_elem_value * uctrl)489 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
490 {
491 struct hda_codec *codec = snd_kcontrol_chip(kctrl);
492 struct cs8409_spec *spec = codec->spec;
493 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
494 int chs = get_amp_channels(kctrl);
495 unsigned int ofs = get_amp_offset(kctrl);
496 long *valp = uctrl->value.integer.value;
497
498 switch (ofs) {
499 case CS42L42_VOL_DAC:
500 if (chs & BIT(0))
501 *valp++ = cs42l42->vol[ofs];
502 if (chs & BIT(1))
503 *valp = cs42l42->vol[ofs+1];
504 break;
505 case CS42L42_VOL_ADC:
506 if (chs & BIT(0))
507 *valp = cs42l42->vol[ofs];
508 break;
509 default:
510 break;
511 }
512
513 return 0;
514 }
515
cs42l42_mute(struct sub_codec * cs42l42,int vol_type,unsigned int chs,bool mute)516 static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
517 unsigned int chs, bool mute)
518 {
519 if (mute) {
520 if (vol_type == CS42L42_VOL_DAC) {
521 if (chs & BIT(0))
522 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f);
523 if (chs & BIT(1))
524 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f);
525 } else if (vol_type == CS42L42_VOL_ADC) {
526 if (chs & BIT(0))
527 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f);
528 }
529 } else {
530 if (vol_type == CS42L42_VOL_DAC) {
531 if (chs & BIT(0))
532 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL,
533 -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
534 & CS42L42_MIXER_CH_VOL_MASK);
535 if (chs & BIT(1))
536 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL,
537 -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
538 & CS42L42_MIXER_CH_VOL_MASK);
539 } else if (vol_type == CS42L42_VOL_ADC) {
540 if (chs & BIT(0))
541 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME,
542 cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
543 & CS42L42_REG_AMIC_VOL_MASK);
544 }
545 }
546 }
547
cs42l42_volume_put(struct snd_kcontrol * kctrl,struct snd_ctl_elem_value * uctrl)548 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
549 {
550 struct hda_codec *codec = snd_kcontrol_chip(kctrl);
551 struct cs8409_spec *spec = codec->spec;
552 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
553 int chs = get_amp_channels(kctrl);
554 unsigned int ofs = get_amp_offset(kctrl);
555 long *valp = uctrl->value.integer.value;
556
557 switch (ofs) {
558 case CS42L42_VOL_DAC:
559 if (chs & BIT(0))
560 cs42l42->vol[ofs] = *valp;
561 if (chs & BIT(1)) {
562 valp++;
563 cs42l42->vol[ofs + 1] = *valp;
564 }
565 if (spec->playback_started)
566 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false);
567 break;
568 case CS42L42_VOL_ADC:
569 if (chs & BIT(0))
570 cs42l42->vol[ofs] = *valp;
571 if (spec->capture_started)
572 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false);
573 break;
574 default:
575 break;
576 }
577
578 return 0;
579 }
580
cs42l42_playback_pcm_hook(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream,int action)581 static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo,
582 struct hda_codec *codec,
583 struct snd_pcm_substream *substream,
584 int action)
585 {
586 struct cs8409_spec *spec = codec->spec;
587 struct sub_codec *cs42l42;
588 int i;
589 bool mute;
590
591 switch (action) {
592 case HDA_GEN_PCM_ACT_PREPARE:
593 mute = false;
594 spec->playback_started = 1;
595 break;
596 case HDA_GEN_PCM_ACT_CLEANUP:
597 mute = true;
598 spec->playback_started = 0;
599 break;
600 default:
601 return;
602 }
603
604 for (i = 0; i < spec->num_scodecs; i++) {
605 cs42l42 = spec->scodecs[i];
606 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
607 }
608 }
609
cs42l42_capture_pcm_hook(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream,int action)610 static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo,
611 struct hda_codec *codec,
612 struct snd_pcm_substream *substream,
613 int action)
614 {
615 struct cs8409_spec *spec = codec->spec;
616 struct sub_codec *cs42l42;
617 int i;
618 bool mute;
619
620 switch (action) {
621 case HDA_GEN_PCM_ACT_PREPARE:
622 mute = false;
623 spec->capture_started = 1;
624 break;
625 case HDA_GEN_PCM_ACT_CLEANUP:
626 mute = true;
627 spec->capture_started = 0;
628 break;
629 default:
630 return;
631 }
632
633 for (i = 0; i < spec->num_scodecs; i++) {
634 cs42l42 = spec->scodecs[i];
635 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
636 }
637 }
638
639 /* Configure CS42L42 slave codec for jack autodetect */
cs42l42_enable_jack_detect(struct sub_codec * cs42l42)640 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
641 {
642 cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz);
643 /* Clear WAKE# */
644 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1);
645 /* Wait ~2.5ms */
646 usleep_range(2500, 3000);
647 /* Set mode WAKE# output follows the combination logic directly */
648 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0);
649 /* Clear interrupts status */
650 cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
651 /* Enable interrupt */
652 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
653 }
654
655 /* Enable and run CS42L42 slave codec jack auto detect */
cs42l42_run_jack_detect(struct sub_codec * cs42l42)656 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
657 {
658 /* Clear interrupts */
659 cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
660 cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1);
661 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF);
662 cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
663
664 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
665 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86);
666 cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07);
667 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD);
668 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
669 /* Wait ~20ms*/
670 usleep_range(20000, 25000);
671 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77);
672 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0);
673 }
674
cs42l42_manual_hs_det(struct sub_codec * cs42l42)675 static int cs42l42_manual_hs_det(struct sub_codec *cs42l42)
676 {
677 unsigned int hs_det_status;
678 unsigned int hs_det_comp1;
679 unsigned int hs_det_comp2;
680 unsigned int hs_det_sw;
681 unsigned int hs_type;
682
683 /* Set hs detect to manual, active mode */
684 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
685 (1 << CS42L42_HSDET_CTRL_SHIFT) |
686 (0 << CS42L42_HSDET_SET_SHIFT) |
687 (0 << CS42L42_HSBIAS_REF_SHIFT) |
688 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
689
690 /* Configure HS DET comparator reference levels. */
691 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
692 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
693 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
694
695 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
696 cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
697
698 msleep(100);
699
700 hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
701
702 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
703 CS42L42_HSDET_COMP1_OUT_SHIFT;
704 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
705 CS42L42_HSDET_COMP2_OUT_SHIFT;
706
707 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
708 cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
709
710 msleep(100);
711
712 hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
713
714 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
715 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
716 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
717 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
718
719 /* Use Comparator 1 with 1.25V Threshold. */
720 switch (hs_det_comp1) {
721 case CS42L42_HSDET_COMP_TYPE1:
722 hs_type = CS42L42_PLUG_CTIA;
723 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
724 break;
725 case CS42L42_HSDET_COMP_TYPE2:
726 hs_type = CS42L42_PLUG_OMTP;
727 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
728 break;
729 default:
730 /* Fallback to Comparator 2 with 1.75V Threshold. */
731 switch (hs_det_comp2) {
732 case CS42L42_HSDET_COMP_TYPE1:
733 hs_type = CS42L42_PLUG_CTIA;
734 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
735 break;
736 case CS42L42_HSDET_COMP_TYPE2:
737 hs_type = CS42L42_PLUG_OMTP;
738 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
739 break;
740 case CS42L42_HSDET_COMP_TYPE3:
741 hs_type = CS42L42_PLUG_HEADPHONE;
742 hs_det_sw = CS42L42_HSDET_SW_TYPE3;
743 break;
744 default:
745 hs_type = CS42L42_PLUG_INVALID;
746 hs_det_sw = CS42L42_HSDET_SW_TYPE4;
747 break;
748 }
749 }
750
751 /* Set Switches */
752 cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw);
753
754 /* Set HSDET mode to Manual—Disabled */
755 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
756 (0 << CS42L42_HSDET_CTRL_SHIFT) |
757 (0 << CS42L42_HSDET_SET_SHIFT) |
758 (0 << CS42L42_HSBIAS_REF_SHIFT) |
759 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
760
761 /* Configure HS DET comparator reference levels. */
762 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
763 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
764 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
765
766 return hs_type;
767 }
768
cs42l42_handle_tip_sense(struct sub_codec * cs42l42,unsigned int reg_ts_status)769 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
770 {
771 int status_changed = 0;
772
773 /* TIP_SENSE INSERT/REMOVE */
774 switch (reg_ts_status) {
775 case CS42L42_TS_PLUG:
776 if (cs42l42->no_type_dect) {
777 status_changed = 1;
778 cs42l42->hp_jack_in = 1;
779 cs42l42->mic_jack_in = 0;
780 } else {
781 cs42l42_run_jack_detect(cs42l42);
782 }
783 break;
784
785 case CS42L42_TS_UNPLUG:
786 status_changed = 1;
787 cs42l42->hp_jack_in = 0;
788 cs42l42->mic_jack_in = 0;
789 break;
790 default:
791 /* jack in transition */
792 break;
793 }
794
795 codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status);
796
797 return status_changed;
798 }
799
cs42l42_jack_unsol_event(struct sub_codec * cs42l42)800 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
801 {
802 int current_plug_status;
803 int status_changed = 0;
804 int reg_cdc_status;
805 int reg_hs_status;
806 int reg_ts_status;
807 int type;
808
809 /* Read jack detect status registers */
810 reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
811 reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
812 reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
813
814 /* If status values are < 0, read error has occurred. */
815 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
816 return -EIO;
817
818 current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK))
819 >> CS42L42_TS_PLUG_SHIFT;
820
821 /* HSDET_AUTO_DONE */
822 if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) {
823
824 /* Disable HSDET_AUTO_DONE */
825 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);
826
827 type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT;
828
829 /* Configure the HSDET mode. */
830 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
831
832 if (cs42l42->no_type_dect) {
833 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
834 } else {
835 if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) {
836 codec_dbg(cs42l42->codec,
837 "Auto detect value not valid (%d), running manual det\n",
838 type);
839 type = cs42l42_manual_hs_det(cs42l42);
840 }
841
842 switch (type) {
843 case CS42L42_PLUG_CTIA:
844 case CS42L42_PLUG_OMTP:
845 status_changed = 1;
846 cs42l42->hp_jack_in = 1;
847 cs42l42->mic_jack_in = 1;
848 break;
849 case CS42L42_PLUG_HEADPHONE:
850 status_changed = 1;
851 cs42l42->hp_jack_in = 1;
852 cs42l42->mic_jack_in = 0;
853 break;
854 default:
855 status_changed = 1;
856 cs42l42->hp_jack_in = 0;
857 cs42l42->mic_jack_in = 0;
858 break;
859 }
860 codec_dbg(cs42l42->codec, "Detection done (%d)\n", type);
861 }
862
863 /* Enable the HPOUT ground clamp and configure the HP pull-down */
864 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);
865 /* Re-Enable Tip Sense Interrupt */
866 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
867 } else {
868 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
869 }
870
871 return status_changed;
872 }
873
cs42l42_resume(struct sub_codec * cs42l42)874 static void cs42l42_resume(struct sub_codec *cs42l42)
875 {
876 struct hda_codec *codec = cs42l42->codec;
877 struct cs8409_spec *spec = codec->spec;
878 struct cs8409_i2c_param irq_regs[] = {
879 { CS42L42_CODEC_STATUS, 0x00 },
880 { CS42L42_DET_INT_STATUS1, 0x00 },
881 { CS42L42_DET_INT_STATUS2, 0x00 },
882 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
883 };
884 unsigned int fsv;
885
886 /* Bring CS42L42 out of Reset */
887 spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
888 spec->gpio_data |= cs42l42->reset_gpio;
889 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
890 usleep_range(10000, 15000);
891
892 cs42l42->suspended = 0;
893
894 /* Initialize CS42L42 companion codec */
895 cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
896
897 /* Clear interrupts, by reading interrupt status registers */
898 cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
899
900 fsv = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL);
901 if (cs42l42->full_scale_vol) {
902 // Set the full scale volume bit
903 fsv |= CS42L42_FULL_SCALE_VOL_MASK;
904 cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv);
905 }
906 // Unmute analog channels A and B
907 fsv = (fsv & ~CS42L42_ANA_MUTE_AB);
908 cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv);
909
910 /* we have to explicitly allow unsol event handling even during the
911 * resume phase so that the jack event is processed properly
912 */
913 snd_hda_codec_allow_unsol_events(cs42l42->codec);
914
915 cs42l42_enable_jack_detect(cs42l42);
916 }
917
cs42l42_suspend(struct sub_codec * cs42l42)918 static void cs42l42_suspend(struct sub_codec *cs42l42)
919 {
920 struct hda_codec *codec = cs42l42->codec;
921 struct cs8409_spec *spec = codec->spec;
922 int reg_cdc_status = 0;
923 const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
924 { CS42L42_DAC_CTL2, 0x02 },
925 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
926 { CS42L42_MIXER_CHA_VOL, 0x3F },
927 { CS42L42_MIXER_ADC_VOL, 0x3F },
928 { CS42L42_MIXER_CHB_VOL, 0x3F },
929 { CS42L42_HP_CTL, 0x0D },
930 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
931 { CS42L42_ASP_CLK_CFG, 0x00 },
932 { CS42L42_PWR_CTL1, 0xFE },
933 { CS42L42_PWR_CTL2, 0x8C },
934 { CS42L42_PWR_CTL1, 0xFF },
935 };
936
937 cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
938
939 if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
940 (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
941 true, cs42l42, CS42L42_CODEC_STATUS) < 0)
942 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
943
944 /* Power down CS42L42 ASP/EQ/MIX/HP */
945 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
946 cs42l42->suspended = 1;
947 cs42l42->last_page = 0;
948 cs42l42->hp_jack_in = 0;
949 cs42l42->mic_jack_in = 0;
950
951 /* Put CS42L42 into Reset */
952 spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
953 spec->gpio_data &= ~cs42l42->reset_gpio;
954 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
955 }
956
cs8409_free(struct hda_codec * codec)957 static void cs8409_free(struct hda_codec *codec)
958 {
959 struct cs8409_spec *spec = codec->spec;
960
961 /* Cancel i2c clock disable timer, and disable clock if left enabled */
962 cancel_delayed_work_sync(&spec->i2c_clk_work);
963 cs8409_disable_i2c_clock(codec);
964
965 snd_hda_gen_free(codec);
966 }
967
968 /******************************************************************************
969 * BULLSEYE / WARLOCK / CYBORG Specific Functions
970 * CS8409/CS42L42
971 ******************************************************************************/
972
973 /*
974 * In the case of CS8409 we do not have unsolicited events from NID's 0x24
975 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
976 * generate interrupt via gpio 4 to notify jack events. We have to overwrite
977 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
978 * and then notify status via generic snd_hda_jack_unsol_event() call.
979 */
cs8409_cs42l42_jack_unsol_event(struct hda_codec * codec,unsigned int res)980 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
981 {
982 struct cs8409_spec *spec = codec->spec;
983 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
984 struct hda_jack_tbl *jk;
985
986 /* jack_unsol_event() will be called every time gpio line changing state.
987 * In this case gpio4 line goes up as a result of reading interrupt status
988 * registers in previous cs8409_jack_unsol_event() call.
989 * We don't need to handle this event, ignoring...
990 */
991 if (res & cs42l42->irq_mask)
992 return;
993
994 if (cs42l42_jack_unsol_event(cs42l42)) {
995 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
996 cs42l42->hp_jack_in ? 0 : PIN_OUT);
997 /* Report jack*/
998 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
999 if (jk)
1000 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1001 AC_UNSOL_RES_TAG);
1002 /* Report jack*/
1003 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
1004 if (jk)
1005 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1006 AC_UNSOL_RES_TAG);
1007 }
1008 }
1009
1010 /* Manage PDREF, when transition to D3hot */
cs8409_cs42l42_suspend(struct hda_codec * codec)1011 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
1012 {
1013 struct cs8409_spec *spec = codec->spec;
1014 int i;
1015
1016 spec->init_done = 0;
1017
1018 cs8409_enable_ur(codec, 0);
1019
1020 for (i = 0; i < spec->num_scodecs; i++)
1021 cs42l42_suspend(spec->scodecs[i]);
1022
1023 /* Cancel i2c clock disable timer, and disable clock if left enabled */
1024 cancel_delayed_work_sync(&spec->i2c_clk_work);
1025 cs8409_disable_i2c_clock(codec);
1026
1027 snd_hda_shutup_pins(codec);
1028
1029 return 0;
1030 }
1031
1032 /* Vendor specific HW configuration
1033 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1034 */
cs8409_cs42l42_hw_init(struct hda_codec * codec)1035 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
1036 {
1037 const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
1038 const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
1039 struct cs8409_spec *spec = codec->spec;
1040 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1041
1042 if (spec->gpio_mask) {
1043 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1044 spec->gpio_mask);
1045 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1046 spec->gpio_dir);
1047 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1048 spec->gpio_data);
1049 }
1050
1051 for (; seq->nid; seq++)
1052 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1053
1054 if (codec->fixup_id == CS8409_BULLSEYE) {
1055 for (; seq_bullseye->nid; seq_bullseye++)
1056 cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
1057 }
1058
1059 switch (codec->fixup_id) {
1060 case CS8409_CYBORG:
1061 case CS8409_WARLOCK_MLK_DUAL_MIC:
1062 /* DMIC1_MO=00b, DMIC1/2_SR=1 */
1063 cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003);
1064 break;
1065 case CS8409_ODIN:
1066 /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */
1067 cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00);
1068 break;
1069 default:
1070 break;
1071 }
1072
1073 cs42l42_resume(cs42l42);
1074
1075 /* Enable Unsolicited Response */
1076 cs8409_enable_ur(codec, 1);
1077 }
1078
1079 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = {
1080 .build_controls = cs8409_build_controls,
1081 .build_pcms = snd_hda_gen_build_pcms,
1082 .init = cs8409_init,
1083 .free = cs8409_free,
1084 .unsol_event = cs8409_cs42l42_jack_unsol_event,
1085 .suspend = cs8409_cs42l42_suspend,
1086 };
1087
cs8409_cs42l42_exec_verb(struct hdac_device * dev,unsigned int cmd,unsigned int flags,unsigned int * res)1088 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1089 unsigned int *res)
1090 {
1091 struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1092 struct cs8409_spec *spec = codec->spec;
1093 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1094
1095 unsigned int nid = ((cmd >> 20) & 0x07f);
1096 unsigned int verb = ((cmd >> 8) & 0x0fff);
1097
1098 /* CS8409 pins have no AC_PINSENSE_PRESENCE
1099 * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
1100 * and return correct pin sense values for read_pin_sense() call from
1101 * hda_jack based on CS42L42 jack detect status.
1102 */
1103 switch (nid) {
1104 case CS8409_CS42L42_HP_PIN_NID:
1105 if (verb == AC_VERB_GET_PIN_SENSE) {
1106 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1107 return 0;
1108 }
1109 break;
1110 case CS8409_CS42L42_AMIC_PIN_NID:
1111 if (verb == AC_VERB_GET_PIN_SENSE) {
1112 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1113 return 0;
1114 }
1115 break;
1116 default:
1117 break;
1118 }
1119
1120 return spec->exec_verb(dev, cmd, flags, res);
1121 }
1122
cs8409_cs42l42_fixups(struct hda_codec * codec,const struct hda_fixup * fix,int action)1123 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1124 {
1125 struct cs8409_spec *spec = codec->spec;
1126
1127 switch (action) {
1128 case HDA_FIXUP_ACT_PRE_PROBE:
1129 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
1130 /* verb exec op override */
1131 spec->exec_verb = codec->core.exec_verb;
1132 codec->core.exec_verb = cs8409_cs42l42_exec_verb;
1133
1134 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
1135 spec->num_scodecs = 1;
1136 spec->scodecs[CS8409_CODEC0]->codec = codec;
1137 codec->patch_ops = cs8409_cs42l42_patch_ops;
1138
1139 spec->gen.suppress_auto_mute = 1;
1140 spec->gen.no_primary_hp = 1;
1141 spec->gen.suppress_vmaster = 1;
1142
1143 spec->speaker_pdn_gpio = 0;
1144
1145 /* GPIO 5 out, 3,4 in */
1146 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
1147 spec->gpio_data = 0;
1148 spec->gpio_mask = 0x03f;
1149
1150 /* Basic initial sequence for specific hw configuration */
1151 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
1152
1153 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
1154 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
1155
1156 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1157
1158 switch (codec->fixup_id) {
1159 case CS8409_CYBORG:
1160 spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1161 CS42L42_FULL_SCALE_VOL_MINUS6DB;
1162 spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1163 break;
1164 case CS8409_ODIN:
1165 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1166 spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1167 break;
1168 case CS8409_WARLOCK_MLK:
1169 case CS8409_WARLOCK_MLK_DUAL_MIC:
1170 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1171 spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1172 break;
1173 default:
1174 spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1175 CS42L42_FULL_SCALE_VOL_MINUS6DB;
1176 spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1177 break;
1178 }
1179
1180 if (spec->speaker_pdn_gpio > 0) {
1181 spec->gpio_dir |= spec->speaker_pdn_gpio;
1182 spec->gpio_data |= spec->speaker_pdn_gpio;
1183 }
1184
1185 break;
1186 case HDA_FIXUP_ACT_PROBE:
1187 /* Fix Sample Rate to 48kHz */
1188 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1189 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1190 /* add hooks */
1191 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1192 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1193 if (codec->fixup_id != CS8409_ODIN)
1194 /* Set initial DMIC volume to -26 dB */
1195 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1196 HDA_INPUT, 0, 0xff, 0x19);
1197 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1198 &cs42l42_dac_volume_mixer);
1199 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1200 &cs42l42_adc_volume_mixer);
1201 if (spec->speaker_pdn_gpio > 0)
1202 snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch",
1203 &cs8409_spk_sw_ctrl);
1204 /* Disable Unsolicited Response during boot */
1205 cs8409_enable_ur(codec, 0);
1206 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1207 break;
1208 case HDA_FIXUP_ACT_INIT:
1209 cs8409_cs42l42_hw_init(codec);
1210 spec->init_done = 1;
1211 if (spec->init_done && spec->build_ctrl_done
1212 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1213 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1214 break;
1215 case HDA_FIXUP_ACT_BUILD:
1216 spec->build_ctrl_done = 1;
1217 /* Run jack auto detect first time on boot
1218 * after controls have been added, to check if jack has
1219 * been already plugged in.
1220 * Run immediately after init.
1221 */
1222 if (spec->init_done && spec->build_ctrl_done
1223 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1224 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1225 break;
1226 default:
1227 break;
1228 }
1229 }
1230
1231 /******************************************************************************
1232 * Dolphin Specific Functions
1233 * CS8409/ 2 X CS42L42
1234 ******************************************************************************/
1235
1236 /*
1237 * In the case of CS8409 we do not have unsolicited events when
1238 * hs mic and hp are connected. Companion codec CS42L42 will
1239 * generate interrupt via irq_mask to notify jack events. We have to overwrite
1240 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
1241 * and then notify status via generic snd_hda_jack_unsol_event() call.
1242 */
dolphin_jack_unsol_event(struct hda_codec * codec,unsigned int res)1243 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1244 {
1245 struct cs8409_spec *spec = codec->spec;
1246 struct sub_codec *cs42l42;
1247 struct hda_jack_tbl *jk;
1248
1249 cs42l42 = spec->scodecs[CS8409_CODEC0];
1250 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1251 cs42l42_jack_unsol_event(cs42l42)) {
1252 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1253 if (jk)
1254 snd_hda_jack_unsol_event(codec,
1255 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1256 AC_UNSOL_RES_TAG);
1257
1258 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1259 if (jk)
1260 snd_hda_jack_unsol_event(codec,
1261 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1262 AC_UNSOL_RES_TAG);
1263 }
1264
1265 cs42l42 = spec->scodecs[CS8409_CODEC1];
1266 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1267 cs42l42_jack_unsol_event(cs42l42)) {
1268 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1269 if (jk)
1270 snd_hda_jack_unsol_event(codec,
1271 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1272 AC_UNSOL_RES_TAG);
1273 }
1274 }
1275
1276 /* Vendor specific HW configuration
1277 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1278 */
dolphin_hw_init(struct hda_codec * codec)1279 static void dolphin_hw_init(struct hda_codec *codec)
1280 {
1281 const struct cs8409_cir_param *seq = dolphin_hw_cfg;
1282 struct cs8409_spec *spec = codec->spec;
1283 struct sub_codec *cs42l42;
1284 int i;
1285
1286 if (spec->gpio_mask) {
1287 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1288 spec->gpio_mask);
1289 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1290 spec->gpio_dir);
1291 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1292 spec->gpio_data);
1293 }
1294
1295 for (; seq->nid; seq++)
1296 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1297
1298 for (i = 0; i < spec->num_scodecs; i++) {
1299 cs42l42 = spec->scodecs[i];
1300 cs42l42_resume(cs42l42);
1301 }
1302
1303 /* Enable Unsolicited Response */
1304 cs8409_enable_ur(codec, 1);
1305 }
1306
1307 static const struct hda_codec_ops cs8409_dolphin_patch_ops = {
1308 .build_controls = cs8409_build_controls,
1309 .build_pcms = snd_hda_gen_build_pcms,
1310 .init = cs8409_init,
1311 .free = cs8409_free,
1312 .unsol_event = dolphin_jack_unsol_event,
1313 .suspend = cs8409_cs42l42_suspend,
1314 };
1315
dolphin_exec_verb(struct hdac_device * dev,unsigned int cmd,unsigned int flags,unsigned int * res)1316 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1317 unsigned int *res)
1318 {
1319 struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1320 struct cs8409_spec *spec = codec->spec;
1321 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1322
1323 unsigned int nid = ((cmd >> 20) & 0x07f);
1324 unsigned int verb = ((cmd >> 8) & 0x0fff);
1325
1326 /* CS8409 pins have no AC_PINSENSE_PRESENCE
1327 * capabilities. We have to intercept calls for CS42L42 pins
1328 * and return correct pin sense values for read_pin_sense() call from
1329 * hda_jack based on CS42L42 jack detect status.
1330 */
1331 switch (nid) {
1332 case DOLPHIN_HP_PIN_NID:
1333 case DOLPHIN_LO_PIN_NID:
1334 if (nid == DOLPHIN_LO_PIN_NID)
1335 cs42l42 = spec->scodecs[CS8409_CODEC1];
1336 if (verb == AC_VERB_GET_PIN_SENSE) {
1337 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1338 return 0;
1339 }
1340 break;
1341 case DOLPHIN_AMIC_PIN_NID:
1342 if (verb == AC_VERB_GET_PIN_SENSE) {
1343 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1344 return 0;
1345 }
1346 break;
1347 default:
1348 break;
1349 }
1350
1351 return spec->exec_verb(dev, cmd, flags, res);
1352 }
1353
dolphin_fixups(struct hda_codec * codec,const struct hda_fixup * fix,int action)1354 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1355 {
1356 struct cs8409_spec *spec = codec->spec;
1357 struct snd_kcontrol_new *kctrl;
1358 int i;
1359
1360 switch (action) {
1361 case HDA_FIXUP_ACT_PRE_PROBE:
1362 snd_hda_add_verbs(codec, dolphin_init_verbs);
1363 /* verb exec op override */
1364 spec->exec_verb = codec->core.exec_verb;
1365 codec->core.exec_verb = dolphin_exec_verb;
1366
1367 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1368 spec->scodecs[CS8409_CODEC0]->codec = codec;
1369 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1370 spec->scodecs[CS8409_CODEC1]->codec = codec;
1371 spec->num_scodecs = 2;
1372 spec->gen.suppress_vmaster = 1;
1373
1374 codec->patch_ops = cs8409_dolphin_patch_ops;
1375
1376 /* GPIO 1,5 out, 0,4 in */
1377 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1378 spec->scodecs[CS8409_CODEC1]->reset_gpio;
1379 spec->gpio_data = 0;
1380 spec->gpio_mask = 0x03f;
1381
1382 /* Basic initial sequence for specific hw configuration */
1383 snd_hda_sequence_write(codec, dolphin_init_verbs);
1384
1385 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1386 SND_JACK_HEADPHONE, NULL);
1387
1388 snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1389 SND_JACK_MICROPHONE, NULL);
1390
1391 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1392 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1393 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1394
1395 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1396 spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1397
1398 break;
1399 case HDA_FIXUP_ACT_PROBE:
1400 /* Fix Sample Rate to 48kHz */
1401 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1402 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1403 /* add hooks */
1404 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1405 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1406 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1407 &cs42l42_dac_volume_mixer);
1408 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1409 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1410 &cs42l42_dac_volume_mixer);
1411 /* Update Line Out kcontrol template */
1412 if (kctrl)
1413 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1414 HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1415 cs8409_enable_ur(codec, 0);
1416 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1417 break;
1418 case HDA_FIXUP_ACT_INIT:
1419 dolphin_hw_init(codec);
1420 spec->init_done = 1;
1421 if (spec->init_done && spec->build_ctrl_done) {
1422 for (i = 0; i < spec->num_scodecs; i++) {
1423 if (!spec->scodecs[i]->hp_jack_in)
1424 cs42l42_run_jack_detect(spec->scodecs[i]);
1425 }
1426 }
1427 break;
1428 case HDA_FIXUP_ACT_BUILD:
1429 spec->build_ctrl_done = 1;
1430 /* Run jack auto detect first time on boot
1431 * after controls have been added, to check if jack has
1432 * been already plugged in.
1433 * Run immediately after init.
1434 */
1435 if (spec->init_done && spec->build_ctrl_done) {
1436 for (i = 0; i < spec->num_scodecs; i++) {
1437 if (!spec->scodecs[i]->hp_jack_in)
1438 cs42l42_run_jack_detect(spec->scodecs[i]);
1439 }
1440 }
1441 break;
1442 default:
1443 break;
1444 }
1445 }
1446
patch_cs8409(struct hda_codec * codec)1447 static int patch_cs8409(struct hda_codec *codec)
1448 {
1449 int err;
1450
1451 if (!cs8409_alloc_spec(codec))
1452 return -ENOMEM;
1453
1454 snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1455
1456 codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1457 codec->bus->pci->subsystem_vendor,
1458 codec->bus->pci->subsystem_device);
1459
1460 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1461
1462 err = cs8409_parse_auto_config(codec);
1463 if (err < 0) {
1464 cs8409_free(codec);
1465 return err;
1466 }
1467
1468 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1469 return 0;
1470 }
1471
1472 static const struct hda_device_id snd_hda_id_cs8409[] = {
1473 HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409),
1474 {} /* terminator */
1475 };
1476 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1477
1478 static struct hda_codec_driver cs8409_driver = {
1479 .id = snd_hda_id_cs8409,
1480 };
1481 module_hda_codec_driver(cs8409_driver);
1482
1483 MODULE_LICENSE("GPL");
1484 MODULE_DESCRIPTION("Cirrus Logic HDA bridge");
1485