1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 #include <asm/perf_event.h> 10 #include <asm/posted_intr.h> 11 12 #include "capabilities.h" 13 #include "../regs.h" 14 #include "pmu_intel.h" 15 #include "vmcs.h" 16 #include "vmx_ops.h" 17 #include "../cpuid.h" 18 #include "../mmu.h" 19 #include "common.h" 20 21 #ifdef CONFIG_X86_64 22 #define MAX_NR_USER_RETURN_MSRS 7 23 #else 24 #define MAX_NR_USER_RETURN_MSRS 4 25 #endif 26 27 #define MAX_NR_LOADSTORE_MSRS 8 28 29 struct vmx_msrs { 30 unsigned int nr; 31 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 32 }; 33 34 struct vmx_uret_msr { 35 bool load_into_hardware; 36 u64 data; 37 u64 mask; 38 }; 39 40 enum segment_cache_field { 41 SEG_FIELD_SEL = 0, 42 SEG_FIELD_BASE = 1, 43 SEG_FIELD_LIMIT = 2, 44 SEG_FIELD_AR = 3, 45 46 SEG_FIELD_NR = 4 47 }; 48 49 #define RTIT_ADDR_RANGE 4 50 51 struct pt_ctx { 52 u64 ctl; 53 u64 status; 54 u64 output_base; 55 u64 output_mask; 56 u64 cr3_match; 57 u64 addr_a[RTIT_ADDR_RANGE]; 58 u64 addr_b[RTIT_ADDR_RANGE]; 59 }; 60 61 struct pt_desc { 62 u64 ctl_bitmask; 63 u32 num_address_ranges; 64 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 65 struct pt_ctx host; 66 struct pt_ctx guest; 67 }; 68 69 /* 70 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 71 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 72 */ 73 struct nested_vmx { 74 /* Has the level1 guest done vmxon? */ 75 bool vmxon; 76 gpa_t vmxon_ptr; 77 bool pml_full; 78 79 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 80 gpa_t current_vmptr; 81 /* 82 * Cache of the guest's VMCS, existing outside of guest memory. 83 * Loaded from guest memory during VMPTRLD. Flushed to guest 84 * memory during VMCLEAR and VMPTRLD. 85 */ 86 struct vmcs12 *cached_vmcs12; 87 /* 88 * Cache of the guest's shadow VMCS, existing outside of guest 89 * memory. Loaded from guest memory during VM entry. Flushed 90 * to guest memory during VM exit. 91 */ 92 struct vmcs12 *cached_shadow_vmcs12; 93 94 /* 95 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer 96 */ 97 struct gfn_to_hva_cache shadow_vmcs12_cache; 98 99 /* 100 * GPA to HVA cache for VMCS12 101 */ 102 struct gfn_to_hva_cache vmcs12_cache; 103 104 /* 105 * Indicates if the shadow vmcs or enlightened vmcs must be updated 106 * with the data held by struct vmcs12. 107 */ 108 bool need_vmcs12_to_shadow_sync; 109 bool dirty_vmcs12; 110 111 /* 112 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 113 * changes in MSR bitmap for L1 or switching to a different L2. Note, 114 * this flag can only be used reliably in conjunction with a paravirt L1 115 * which informs L0 whether any changes to MSR bitmap for L2 were done 116 * on its side. 117 */ 118 bool force_msr_bitmap_recalc; 119 120 /* 121 * Indicates lazily loaded guest state has not yet been decached from 122 * vmcs02. 123 */ 124 bool need_sync_vmcs02_to_vmcs12_rare; 125 126 /* 127 * vmcs02 has been initialized, i.e. state that is constant for 128 * vmcs02 has been written to the backing VMCS. Initialization 129 * is delayed until L1 actually attempts to run a nested VM. 130 */ 131 bool vmcs02_initialized; 132 133 /* 134 * Enlightened VMCS has been enabled. It does not mean that L1 has to 135 * use it. However, VMX features available to L1 will be limited based 136 * on what the enlightened VMCS supports. 137 */ 138 bool enlightened_vmcs_enabled; 139 140 /* Pending MTF VM-exit into L1. */ 141 bool mtf_pending; 142 143 struct loaded_vmcs vmcs02; 144 145 /* 146 * Guest pages referred to in the vmcs02 with host-physical 147 * pointers, so we must keep them pinned while L2 runs. 148 */ 149 struct kvm_host_map apic_access_page_map; 150 struct kvm_host_map virtual_apic_map; 151 struct kvm_host_map pi_desc_map; 152 153 struct pi_desc *pi_desc; 154 bool pi_pending; 155 u16 posted_intr_nv; 156 157 struct hrtimer preemption_timer; 158 u64 preemption_timer_deadline; 159 bool has_preemption_timer_deadline; 160 bool preemption_timer_expired; 161 162 /* 163 * Used to restore L1's CR3 if hardware detects a VM-Fail Consistency 164 * Check that KVM does not, in which case KVM needs to unwind CR3 back 165 * to its pre-VM-Enter state, NOT to vmcs01.HOST_CR3. 166 */ 167 unsigned long pre_vmenter_cr3; 168 169 /* 170 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in 171 * order to propagate the guest's pre-VM-Enter value into vmcs02. For 172 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value. 173 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_ 174 * userspace restores MSRs before nested state. If userspace restores 175 * MSRs after nested state, the snapshot holds garbage, but KVM can't 176 * detect that, and the garbage value in vmcs02 will be overwritten by 177 * MSR restoration in any case. 178 */ 179 u64 pre_vmenter_debugctl; 180 u64 pre_vmenter_bndcfgs; 181 u64 pre_vmenter_s_cet; 182 u64 pre_vmenter_ssp; 183 u64 pre_vmenter_ssp_tbl; 184 185 u16 vpid02; 186 u16 last_vpid; 187 188 int tsc_autostore_slot; 189 struct nested_vmx_msrs msrs; 190 191 /* SMM related state */ 192 struct { 193 /* in VMX operation on SMM entry? */ 194 bool vmxon; 195 /* in guest mode on SMM entry? */ 196 bool guest_mode; 197 } smm; 198 199 #ifdef CONFIG_KVM_HYPERV 200 gpa_t hv_evmcs_vmptr; 201 struct kvm_host_map hv_evmcs_map; 202 struct hv_enlightened_vmcs *hv_evmcs; 203 #endif 204 }; 205 206 struct vcpu_vmx { 207 struct kvm_vcpu vcpu; 208 struct vcpu_vt vt; 209 u8 fail; 210 u8 x2apic_msr_bitmap_mode; 211 212 u32 idt_vectoring_info; 213 ulong rflags; 214 215 /* 216 * User return MSRs are always emulated when enabled in the guest, but 217 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 218 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 219 * be loaded into hardware if those conditions aren't met. 220 */ 221 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 222 bool guest_uret_msrs_loaded; 223 #ifdef CONFIG_X86_64 224 u64 msr_guest_kernel_gs_base; 225 #endif 226 227 u64 spec_ctrl; 228 u32 msr_ia32_umwait_control; 229 230 /* 231 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 232 * non-nested (L1) guest, it always points to vmcs01. For a nested 233 * guest (L2), it points to a different VMCS. 234 */ 235 struct loaded_vmcs vmcs01; 236 struct loaded_vmcs *loaded_vmcs; 237 238 struct msr_autoload { 239 struct vmx_msrs guest; 240 struct vmx_msrs host; 241 } msr_autoload; 242 243 struct vmx_msrs msr_autostore; 244 245 struct { 246 int vm86_active; 247 ulong save_rflags; 248 struct kvm_segment segs[8]; 249 } rmode; 250 struct { 251 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 252 struct kvm_save_segment { 253 u16 selector; 254 unsigned long base; 255 u32 limit; 256 u32 ar; 257 } seg[8]; 258 } segment_cache; 259 int vpid; 260 261 /* Support for a guest hypervisor (nested VMX) */ 262 struct nested_vmx nested; 263 264 /* Dynamic PLE window. */ 265 unsigned int ple_window; 266 bool ple_window_dirty; 267 268 /* apic deadline value in host tsc */ 269 u64 hv_deadline_tsc; 270 271 /* 272 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 273 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 274 * in msr_ia32_feature_control_valid_bits. 275 */ 276 u64 msr_ia32_feature_control; 277 u64 msr_ia32_feature_control_valid_bits; 278 /* SGX Launch Control public key hash */ 279 u64 msr_ia32_sgxlepubkeyhash[4]; 280 u64 msr_ia32_mcu_opt_ctrl; 281 bool disable_fb_clear; 282 283 struct pt_desc pt_desc; 284 struct lbr_desc lbr_desc; 285 286 /* ve_info must be page aligned. */ 287 struct vmx_ve_information *ve_info; 288 }; 289 290 struct kvm_vmx { 291 struct kvm kvm; 292 293 unsigned int tss_addr; 294 bool ept_identity_pagetable_done; 295 gpa_t ept_identity_map_addr; 296 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */ 297 u64 *pid_table; 298 }; 299 300 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu); 301 int allocate_vpid(void); 302 void free_vpid(int vpid); 303 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 304 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 305 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 306 unsigned long fs_base, unsigned long gs_base); 307 int vmx_get_cpl(struct kvm_vcpu *vcpu); 308 int vmx_get_cpl_no_cache(struct kvm_vcpu *vcpu); 309 bool vmx_emulation_required(struct kvm_vcpu *vcpu); 310 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 311 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 312 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 313 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 314 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 315 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 316 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 317 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 318 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 319 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 320 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 321 322 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu); 323 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 324 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 325 bool __vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 326 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 327 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 328 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 329 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 330 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 331 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 332 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 333 unsigned int __vmx_vcpu_enter_flags(struct vcpu_vmx *vmx); 334 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned int flags); 335 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 336 337 void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set); 338 339 static inline void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, 340 u32 msr, int type) 341 { 342 vmx_set_intercept_for_msr(vcpu, msr, type, false); 343 } 344 345 static inline void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, 346 u32 msr, int type) 347 { 348 vmx_set_intercept_for_msr(vcpu, msr, type, true); 349 } 350 351 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu); 352 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu); 353 354 gva_t vmx_get_untagged_addr(struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags); 355 356 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu, bool enable); 357 358 u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated); 359 bool vmx_is_valid_debugctl(struct kvm_vcpu *vcpu, u64 data, bool host_initiated); 360 361 #define VMX_HOST_OWNED_DEBUGCTL_BITS (DEBUGCTLMSR_FREEZE_IN_SMM) 362 363 static inline void vmx_guest_debugctl_write(struct kvm_vcpu *vcpu, u64 val) 364 { 365 WARN_ON_ONCE(val & VMX_HOST_OWNED_DEBUGCTL_BITS); 366 367 val |= vcpu->arch.host_debugctl & VMX_HOST_OWNED_DEBUGCTL_BITS; 368 vmcs_write64(GUEST_IA32_DEBUGCTL, val); 369 } 370 371 static inline u64 vmx_guest_debugctl_read(void) 372 { 373 return vmcs_read64(GUEST_IA32_DEBUGCTL) & ~VMX_HOST_OWNED_DEBUGCTL_BITS; 374 } 375 376 static inline void vmx_reload_guest_debugctl(struct kvm_vcpu *vcpu) 377 { 378 u64 val = vmcs_read64(GUEST_IA32_DEBUGCTL); 379 380 if (!((val ^ vcpu->arch.host_debugctl) & VMX_HOST_OWNED_DEBUGCTL_BITS)) 381 return; 382 383 vmx_guest_debugctl_write(vcpu, val & ~VMX_HOST_OWNED_DEBUGCTL_BITS); 384 } 385 386 /* 387 * Note, early Intel manuals have the write-low and read-high bitmap offsets 388 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and 389 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and 390 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and 391 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always 392 * VM-Exit. 393 */ 394 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \ 395 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 396 u32 msr) \ 397 { \ 398 int f = sizeof(unsigned long); \ 399 \ 400 if (msr <= 0x1fff) \ 401 return bitop##_bit(msr, bitmap + base / f); \ 402 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \ 403 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \ 404 return (rtype)true; \ 405 } 406 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 407 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \ 408 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800) 409 410 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test) 411 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear) 412 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set) 413 414 static inline u8 vmx_get_rvi(void) 415 { 416 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 417 } 418 419 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 420 (VM_ENTRY_LOAD_DEBUG_CONTROLS) 421 #ifdef CONFIG_X86_64 422 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 423 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \ 424 VM_ENTRY_IA32E_MODE) 425 #else 426 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \ 427 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS 428 #endif 429 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \ 430 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \ 431 VM_ENTRY_LOAD_IA32_PAT | \ 432 VM_ENTRY_LOAD_IA32_EFER | \ 433 VM_ENTRY_LOAD_BNDCFGS | \ 434 VM_ENTRY_PT_CONCEAL_PIP | \ 435 VM_ENTRY_LOAD_IA32_RTIT_CTL | \ 436 VM_ENTRY_LOAD_CET_STATE) 437 438 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 439 (VM_EXIT_SAVE_DEBUG_CONTROLS | \ 440 VM_EXIT_ACK_INTR_ON_EXIT) 441 #ifdef CONFIG_X86_64 442 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 443 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \ 444 VM_EXIT_HOST_ADDR_SPACE_SIZE) 445 #else 446 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \ 447 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS 448 #endif 449 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \ 450 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \ 451 VM_EXIT_SAVE_IA32_PAT | \ 452 VM_EXIT_LOAD_IA32_PAT | \ 453 VM_EXIT_SAVE_IA32_EFER | \ 454 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \ 455 VM_EXIT_LOAD_IA32_EFER | \ 456 VM_EXIT_CLEAR_BNDCFGS | \ 457 VM_EXIT_PT_CONCEAL_PIP | \ 458 VM_EXIT_CLEAR_IA32_RTIT_CTL | \ 459 VM_EXIT_LOAD_CET_STATE | \ 460 VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL) 461 462 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \ 463 (PIN_BASED_EXT_INTR_MASK | \ 464 PIN_BASED_NMI_EXITING) 465 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \ 466 (PIN_BASED_VIRTUAL_NMIS | \ 467 PIN_BASED_POSTED_INTR | \ 468 PIN_BASED_VMX_PREEMPTION_TIMER) 469 470 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 471 (CPU_BASED_HLT_EXITING | \ 472 CPU_BASED_CR3_LOAD_EXITING | \ 473 CPU_BASED_CR3_STORE_EXITING | \ 474 CPU_BASED_UNCOND_IO_EXITING | \ 475 CPU_BASED_MOV_DR_EXITING | \ 476 CPU_BASED_USE_TSC_OFFSETTING | \ 477 CPU_BASED_MWAIT_EXITING | \ 478 CPU_BASED_MONITOR_EXITING | \ 479 CPU_BASED_INVLPG_EXITING | \ 480 CPU_BASED_RDPMC_EXITING | \ 481 CPU_BASED_INTR_WINDOW_EXITING) 482 483 #ifdef CONFIG_X86_64 484 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 485 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \ 486 CPU_BASED_CR8_LOAD_EXITING | \ 487 CPU_BASED_CR8_STORE_EXITING) 488 #else 489 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \ 490 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL 491 #endif 492 493 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \ 494 (CPU_BASED_RDTSC_EXITING | \ 495 CPU_BASED_TPR_SHADOW | \ 496 CPU_BASED_USE_IO_BITMAPS | \ 497 CPU_BASED_MONITOR_TRAP_FLAG | \ 498 CPU_BASED_USE_MSR_BITMAPS | \ 499 CPU_BASED_NMI_WINDOW_EXITING | \ 500 CPU_BASED_PAUSE_EXITING | \ 501 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \ 502 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS) 503 504 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0 505 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \ 506 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \ 507 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \ 508 SECONDARY_EXEC_WBINVD_EXITING | \ 509 SECONDARY_EXEC_ENABLE_VPID | \ 510 SECONDARY_EXEC_ENABLE_EPT | \ 511 SECONDARY_EXEC_UNRESTRICTED_GUEST | \ 512 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \ 513 SECONDARY_EXEC_DESC | \ 514 SECONDARY_EXEC_ENABLE_RDTSCP | \ 515 SECONDARY_EXEC_ENABLE_INVPCID | \ 516 SECONDARY_EXEC_APIC_REGISTER_VIRT | \ 517 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \ 518 SECONDARY_EXEC_SHADOW_VMCS | \ 519 SECONDARY_EXEC_ENABLE_XSAVES | \ 520 SECONDARY_EXEC_RDSEED_EXITING | \ 521 SECONDARY_EXEC_RDRAND_EXITING | \ 522 SECONDARY_EXEC_ENABLE_PML | \ 523 SECONDARY_EXEC_TSC_SCALING | \ 524 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \ 525 SECONDARY_EXEC_PT_USE_GPA | \ 526 SECONDARY_EXEC_PT_CONCEAL_VMX | \ 527 SECONDARY_EXEC_ENABLE_VMFUNC | \ 528 SECONDARY_EXEC_BUS_LOCK_DETECTION | \ 529 SECONDARY_EXEC_NOTIFY_VM_EXITING | \ 530 SECONDARY_EXEC_MODE_BASED_EPT_EXEC | \ 531 SECONDARY_EXEC_ENCLS_EXITING | \ 532 SECONDARY_EXEC_EPT_VIOLATION_VE) 533 534 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0 535 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \ 536 (TERTIARY_EXEC_IPI_VIRT) 537 538 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ 539 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ 540 { \ 541 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 542 vmcs_write##bits(uname, val); \ 543 vmx->loaded_vmcs->controls_shadow.lname = val; \ 544 } \ 545 } \ 546 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ 547 { \ 548 return vmcs->controls_shadow.lname; \ 549 } \ 550 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ 551 { \ 552 return __##lname##_controls_get(vmx->loaded_vmcs); \ 553 } \ 554 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ 555 { \ 556 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 557 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 558 } \ 559 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ 560 { \ 561 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \ 562 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 563 } \ 564 static __always_inline void lname##_controls_changebit(struct vcpu_vmx *vmx, u##bits val, \ 565 bool set) \ 566 { \ 567 if (set) \ 568 lname##_controls_setbit(vmx, val); \ 569 else \ 570 lname##_controls_clearbit(vmx, val); \ 571 } 572 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) 573 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) 574 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) 575 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) 576 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) 577 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64) 578 579 /* 580 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the 581 * cache on demand. Other registers not listed here are synced to 582 * the cache immediately after VM-Exit. 583 */ 584 #define VMX_REGS_LAZY_LOAD_SET (BIT(VCPU_REGS_RSP) | \ 585 BIT(VCPU_REG_RIP) | \ 586 BIT(VCPU_REG_RFLAGS) | \ 587 BIT(VCPU_REG_PDPTR) | \ 588 BIT(VCPU_REG_SEGMENTS) | \ 589 BIT(VCPU_REG_CR0) | \ 590 BIT(VCPU_REG_CR3) | \ 591 BIT(VCPU_REG_CR4) | \ 592 BIT(VCPU_REG_EXIT_INFO_1) | \ 593 BIT(VCPU_REG_EXIT_INFO_2)) 594 595 static inline unsigned long vmx_l1_guest_owned_cr0_bits(void) 596 { 597 unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS; 598 599 /* 600 * CR0.WP needs to be intercepted when KVM is shadowing legacy paging 601 * in order to construct shadow PTEs with the correct protections. 602 * Note! CR0.WP technically can be passed through to the guest if 603 * paging is disabled, but checking CR0.PG would generate a cyclical 604 * dependency of sorts due to forcing the caller to ensure CR0 holds 605 * the correct value prior to determining which CR0 bits can be owned 606 * by L1. Keep it simple and limit the optimization to EPT. 607 */ 608 if (!enable_ept) 609 bits &= ~X86_CR0_WP; 610 return bits; 611 } 612 613 static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 614 { 615 return container_of(kvm, struct kvm_vmx, kvm); 616 } 617 618 static __always_inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 619 { 620 return container_of(vcpu, struct vcpu_vmx, vcpu); 621 } 622 623 u64 __intel_pmu_compute_pebs_enable(struct kvm_pmu *pmu); 624 625 static inline u64 intel_pmu_compute_pebs_enable(struct kvm_pmu *pmu) 626 { 627 /* 628 * Avoid the function call overhead in the common case that the guest 629 * isn't using PEBS. 630 */ 631 if (!(pmu->pebs_enable & pmu->global_ctrl)) 632 return 0; 633 634 return __intel_pmu_compute_pebs_enable(pmu); 635 } 636 637 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 638 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 639 640 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 641 void free_vmcs(struct vmcs *vmcs); 642 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 643 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 644 645 static inline struct vmcs *alloc_vmcs(bool shadow) 646 { 647 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 648 GFP_KERNEL_ACCOUNT); 649 } 650 651 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 652 { 653 return secondary_exec_controls_get(vmx) & 654 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 655 } 656 657 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 658 { 659 if (!enable_ept) 660 return true; 661 662 return allow_smaller_maxphyaddr && 663 cpuid_maxphyaddr(vcpu) < kvm_host.maxphyaddr; 664 } 665 666 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 667 { 668 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 669 (secondary_exec_controls_get(to_vmx(vcpu)) & 670 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 671 } 672 673 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 674 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 675 { 676 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 677 } 678 679 void dump_vmcs(struct kvm_vcpu *vcpu); 680 681 static inline int vmx_get_instr_info_reg(u32 vmx_instr_info) 682 { 683 return (vmx_instr_info >> 3) & 0xf; 684 } 685 686 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info) 687 { 688 return (vmx_instr_info >> 28) & 0xf; 689 } 690 691 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu) 692 { 693 return lapic_in_kernel(vcpu) && enable_ipiv; 694 } 695 696 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx) 697 { 698 vmx->segment_cache.bitmask = 0; 699 } 700 701 int vmx_init(void); 702 void vmx_exit(void); 703 704 #endif /* __KVM_X86_VMX_H */ 705