1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include <linux/ptp_classify.h> 5 #include <linux/posix-clock.h> 6 #include "i40e.h" 7 #include "i40e_devids.h" 8 9 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 10 * the fundamental clock design. However, the clock operations are much simpler 11 * in the XL710 because the device supports a full 64 bits of nanoseconds. 12 * Because the field is so wide, we can forgo the cycle counter and just 13 * operate with the nanosecond field directly without fear of overflow. 14 * 15 * Much like the 82599, the update period is dependent upon the link speed: 16 * At 40Gb, 25Gb, or no link, the period is 1.6ns. 17 * At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns) 18 * At 1Gb link, the period is multiplied by 20. (32ns) 19 * 1588 functionality is not supported at 100Mbps. 20 */ 21 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 22 #define I40E_PTP_10GB_INCVAL_MULT 2 23 #define I40E_PTP_5GB_INCVAL_MULT 2 24 #define I40E_PTP_1GB_INCVAL_MULT 20 25 #define I40E_ISGN 0x80000000 26 27 #define I40E_SUBDEV_ID_25G_PTP_PIN 0xB 28 29 enum i40e_ptp_pin { 30 SDP3_2 = 0, 31 SDP3_3, 32 GPIO_4 33 }; 34 35 enum i40e_can_set_pins { 36 CANT_DO_PINS = -1, 37 CAN_SET_PINS, 38 CAN_DO_PINS 39 }; 40 41 static struct ptp_pin_desc sdp_desc[] = { 42 /* name idx func chan */ 43 {"SDP3_2", SDP3_2, PTP_PF_NONE, 0}, 44 {"SDP3_3", SDP3_3, PTP_PF_NONE, 1}, 45 {"GPIO_4", GPIO_4, PTP_PF_NONE, 1}, 46 }; 47 48 enum i40e_ptp_gpio_pin_state { 49 end = -2, 50 invalid, 51 off, 52 in_A, 53 in_B, 54 out_A, 55 out_B, 56 }; 57 58 static const char * const i40e_ptp_gpio_pin_state2str[] = { 59 "off", "in_A", "in_B", "out_A", "out_B" 60 }; 61 62 enum i40e_ptp_led_pin_state { 63 led_end = -2, 64 low = 0, 65 high, 66 }; 67 68 struct i40e_ptp_pins_settings { 69 enum i40e_ptp_gpio_pin_state sdp3_2; 70 enum i40e_ptp_gpio_pin_state sdp3_3; 71 enum i40e_ptp_gpio_pin_state gpio_4; 72 enum i40e_ptp_led_pin_state led2_0; 73 enum i40e_ptp_led_pin_state led2_1; 74 enum i40e_ptp_led_pin_state led3_0; 75 enum i40e_ptp_led_pin_state led3_1; 76 }; 77 78 static const struct i40e_ptp_pins_settings 79 i40e_ptp_pin_led_allowed_states[] = { 80 {off, off, off, high, high, high, high}, 81 {off, in_A, off, high, high, high, low}, 82 {off, out_A, off, high, low, high, high}, 83 {off, in_B, off, high, high, high, low}, 84 {off, out_B, off, high, low, high, high}, 85 {in_A, off, off, high, high, high, low}, 86 {in_A, in_B, off, high, high, high, low}, 87 {in_A, out_B, off, high, low, high, high}, 88 {out_A, off, off, high, low, high, high}, 89 {out_A, in_B, off, high, low, high, high}, 90 {in_B, off, off, high, high, high, low}, 91 {in_B, in_A, off, high, high, high, low}, 92 {in_B, out_A, off, high, low, high, high}, 93 {out_B, off, off, high, low, high, high}, 94 {out_B, in_A, off, high, low, high, high}, 95 {off, off, in_A, high, high, low, high}, 96 {off, out_A, in_A, high, low, low, high}, 97 {off, in_B, in_A, high, high, low, low}, 98 {off, out_B, in_A, high, low, low, high}, 99 {out_A, off, in_A, high, low, low, high}, 100 {out_A, in_B, in_A, high, low, low, high}, 101 {in_B, off, in_A, high, high, low, low}, 102 {in_B, out_A, in_A, high, low, low, high}, 103 {out_B, off, in_A, high, low, low, high}, 104 {off, off, out_A, low, high, high, high}, 105 {off, in_A, out_A, low, high, high, low}, 106 {off, in_B, out_A, low, high, high, low}, 107 {off, out_B, out_A, low, low, high, high}, 108 {in_A, off, out_A, low, high, high, low}, 109 {in_A, in_B, out_A, low, high, high, low}, 110 {in_A, out_B, out_A, low, low, high, high}, 111 {in_B, off, out_A, low, high, high, low}, 112 {in_B, in_A, out_A, low, high, high, low}, 113 {out_B, off, out_A, low, low, high, high}, 114 {out_B, in_A, out_A, low, low, high, high}, 115 {off, off, in_B, high, high, low, high}, 116 {off, in_A, in_B, high, high, low, low}, 117 {off, out_A, in_B, high, low, low, high}, 118 {off, out_B, in_B, high, low, low, high}, 119 {in_A, off, in_B, high, high, low, low}, 120 {in_A, out_B, in_B, high, low, low, high}, 121 {out_A, off, in_B, high, low, low, high}, 122 {out_B, off, in_B, high, low, low, high}, 123 {out_B, in_A, in_B, high, low, low, high}, 124 {off, off, out_B, low, high, high, high}, 125 {off, in_A, out_B, low, high, high, low}, 126 {off, out_A, out_B, low, low, high, high}, 127 {off, in_B, out_B, low, high, high, low}, 128 {in_A, off, out_B, low, high, high, low}, 129 {in_A, in_B, out_B, low, high, high, low}, 130 {out_A, off, out_B, low, low, high, high}, 131 {out_A, in_B, out_B, low, low, high, high}, 132 {in_B, off, out_B, low, high, high, low}, 133 {in_B, in_A, out_B, low, high, high, low}, 134 {in_B, out_A, out_B, low, low, high, high}, 135 {end, end, end, led_end, led_end, led_end, led_end} 136 }; 137 138 static int i40e_ptp_set_pins(struct i40e_pf *pf, 139 struct i40e_ptp_pins_settings *pins); 140 141 /** 142 * i40e_ptp_extts0_work - workqueue task function 143 * @work: workqueue task structure 144 * 145 * Service for PTP external clock event 146 **/ 147 static void i40e_ptp_extts0_work(struct work_struct *work) 148 { 149 struct i40e_pf *pf = container_of(work, struct i40e_pf, 150 ptp_extts0_work); 151 struct i40e_hw *hw = &pf->hw; 152 struct ptp_clock_event event; 153 u32 hi, lo; 154 155 /* Event time is captured by one of the two matched registers 156 * PRTTSYN_EVNT_L: 32 LSB of sampled time event 157 * PRTTSYN_EVNT_H: 32 MSB of sampled time event 158 * Event is defined in PRTTSYN_EVNT_0 register 159 */ 160 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0)); 161 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0)); 162 163 event.timestamp = (((u64)hi) << 32) | lo; 164 165 event.type = PTP_CLOCK_EXTTS; 166 event.index = hw->pf_id; 167 168 /* fire event */ 169 ptp_clock_event(pf->ptp_clock, &event); 170 } 171 172 /** 173 * i40e_is_ptp_pin_dev - check if device supports PTP pins 174 * @hw: pointer to the hardware structure 175 * 176 * Return true if device supports PTP pins, false otherwise. 177 **/ 178 static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw) 179 { 180 return hw->device_id == I40E_DEV_ID_25G_SFP28 && 181 hw->subsystem_device_id == I40E_SUBDEV_ID_25G_PTP_PIN; 182 } 183 184 /** 185 * i40e_can_set_pins - check possibility of manipulating the pins 186 * @pf: board private structure 187 * 188 * Check if all conditions are satisfied to manipulate PTP pins. 189 * Return CAN_SET_PINS if pins can be set on a specific PF or 190 * return CAN_DO_PINS if pins can be manipulated within a NIC or 191 * return CANT_DO_PINS otherwise. 192 **/ 193 static enum i40e_can_set_pins i40e_can_set_pins(struct i40e_pf *pf) 194 { 195 if (!i40e_is_ptp_pin_dev(&pf->hw)) { 196 dev_warn(&pf->pdev->dev, 197 "PTP external clock not supported.\n"); 198 return CANT_DO_PINS; 199 } 200 201 if (!pf->ptp_pins) { 202 dev_warn(&pf->pdev->dev, 203 "PTP PIN manipulation not allowed.\n"); 204 return CANT_DO_PINS; 205 } 206 207 if (pf->hw.pf_id) { 208 dev_warn(&pf->pdev->dev, 209 "PTP PINs should be accessed via PF0.\n"); 210 return CAN_DO_PINS; 211 } 212 213 return CAN_SET_PINS; 214 } 215 216 /** 217 * i40_ptp_reset_timing_events - Reset PTP timing events 218 * @pf: Board private structure 219 * 220 * This function resets timing events for pf. 221 **/ 222 static void i40_ptp_reset_timing_events(struct i40e_pf *pf) 223 { 224 u32 i; 225 226 spin_lock_bh(&pf->ptp_rx_lock); 227 for (i = 0; i <= I40E_PRTTSYN_RXTIME_L_MAX_INDEX; i++) { 228 /* reading and automatically clearing timing events registers */ 229 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i)); 230 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i)); 231 pf->latch_events[i] = 0; 232 } 233 /* reading and automatically clearing timing events registers */ 234 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L); 235 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H); 236 237 pf->tx_hwtstamp_timeouts = 0; 238 pf->tx_hwtstamp_skipped = 0; 239 pf->rx_hwtstamp_cleared = 0; 240 pf->latch_event_flags = 0; 241 spin_unlock_bh(&pf->ptp_rx_lock); 242 } 243 244 /** 245 * i40e_ptp_verify - check pins 246 * @ptp: ptp clock 247 * @pin: pin index 248 * @func: assigned function 249 * @chan: channel 250 * 251 * Check pins consistency. 252 * Return 0 on success or error on failure. 253 **/ 254 static int i40e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, 255 enum ptp_pin_function func, unsigned int chan) 256 { 257 switch (func) { 258 case PTP_PF_NONE: 259 case PTP_PF_EXTTS: 260 case PTP_PF_PEROUT: 261 break; 262 case PTP_PF_PHYSYNC: 263 return -EOPNOTSUPP; 264 } 265 return 0; 266 } 267 268 /** 269 * i40e_ptp_read - Read the PHC time from the device 270 * @pf: Board private structure 271 * @ts: timespec structure to hold the current time value 272 * @sts: structure to hold the system time before and after reading the PHC 273 * 274 * This function reads the PRTTSYN_TIME registers and stores them in a 275 * timespec. However, since the registers are 64 bits of nanoseconds, we must 276 * convert the result to a timespec before we can return. 277 **/ 278 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts, 279 struct ptp_system_timestamp *sts) 280 { 281 struct i40e_hw *hw = &pf->hw; 282 u32 hi, lo; 283 u64 ns; 284 285 /* The timer latches on the lowest register read. */ 286 ptp_read_system_prets(sts); 287 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 288 ptp_read_system_postts(sts); 289 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 290 291 ns = (((u64)hi) << 32) | lo; 292 293 *ts = ns_to_timespec64(ns); 294 } 295 296 /** 297 * i40e_ptp_write - Write the PHC time to the device 298 * @pf: Board private structure 299 * @ts: timespec structure that holds the new time value 300 * 301 * This function writes the PRTTSYN_TIME registers with the user value. Since 302 * we receive a timespec from the stack, we must convert that timespec into 303 * nanoseconds before programming the registers. 304 **/ 305 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 306 { 307 struct i40e_hw *hw = &pf->hw; 308 u64 ns = timespec64_to_ns(ts); 309 310 /* The timer will not update until the high register is written, so 311 * write the low register first. 312 */ 313 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 314 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 315 } 316 317 /** 318 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 319 * @hwtstamps: Timestamp structure to update 320 * @timestamp: Timestamp from the hardware 321 * 322 * We need to convert the NIC clock value into a hwtstamp which can be used by 323 * the upper level timestamping functions. Since the timestamp is simply a 64- 324 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 325 **/ 326 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 327 u64 timestamp) 328 { 329 memset(hwtstamps, 0, sizeof(*hwtstamps)); 330 331 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 332 } 333 334 /** 335 * i40e_ptp_adjfine - Adjust the PHC frequency 336 * @ptp: The PTP clock structure 337 * @scaled_ppm: Scaled parts per million adjustment from base 338 * 339 * Adjust the frequency of the PHC by the indicated delta from the base 340 * frequency. 341 * 342 * Scaled parts per million is ppm with a 16 bit binary fractional field. 343 **/ 344 static int i40e_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 345 { 346 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 347 struct i40e_hw *hw = &pf->hw; 348 u64 adj, base_adj; 349 350 smp_mb(); /* Force any pending update before accessing. */ 351 base_adj = I40E_PTP_40GB_INCVAL * READ_ONCE(pf->ptp_adj_mult); 352 353 adj = adjust_by_scaled_ppm(base_adj, scaled_ppm); 354 355 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 356 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 357 358 return 0; 359 } 360 361 /** 362 * i40e_ptp_set_1pps_signal_hw - configure 1PPS PTP signal for pins 363 * @pf: the PF private data structure 364 * 365 * Configure 1PPS signal used for PTP pins 366 **/ 367 static void i40e_ptp_set_1pps_signal_hw(struct i40e_pf *pf) 368 { 369 struct i40e_hw *hw = &pf->hw; 370 struct timespec64 now; 371 u64 ns; 372 373 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0); 374 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); 375 wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE); 376 377 i40e_ptp_read(pf, &now, NULL); 378 now.tv_sec += I40E_PTP_2_SEC_DELAY; 379 now.tv_nsec = 0; 380 ns = timespec64_to_ns(&now); 381 382 /* I40E_PRTTSYN_TGT_L(1) */ 383 wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF); 384 /* I40E_PRTTSYN_TGT_H(1) */ 385 wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32); 386 wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND); 387 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); 388 wr32(hw, I40E_PRTTSYN_AUX_0(1), 389 I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD); 390 } 391 392 /** 393 * i40e_ptp_adjtime - Adjust the PHC time 394 * @ptp: The PTP clock structure 395 * @delta: Offset in nanoseconds to adjust the PHC time by 396 * 397 * Adjust the current clock time by a delta specified in nanoseconds. 398 **/ 399 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 400 { 401 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 402 struct i40e_hw *hw = &pf->hw; 403 404 mutex_lock(&pf->tmreg_lock); 405 406 if (delta > -999999900LL && delta < 999999900LL) { 407 int neg_adj = 0; 408 u32 timadj; 409 u64 tohw; 410 411 if (delta < 0) { 412 neg_adj = 1; 413 tohw = -delta; 414 } else { 415 tohw = delta; 416 } 417 418 timadj = tohw & 0x3FFFFFFF; 419 if (neg_adj) 420 timadj |= I40E_ISGN; 421 wr32(hw, I40E_PRTTSYN_ADJ, timadj); 422 } else { 423 struct timespec64 then, now; 424 425 then = ns_to_timespec64(delta); 426 i40e_ptp_read(pf, &now, NULL); 427 now = timespec64_add(now, then); 428 i40e_ptp_write(pf, (const struct timespec64 *)&now); 429 i40e_ptp_set_1pps_signal_hw(pf); 430 } 431 432 mutex_unlock(&pf->tmreg_lock); 433 434 return 0; 435 } 436 437 /** 438 * i40e_ptp_gettimex - Get the time of the PHC 439 * @ptp: The PTP clock structure 440 * @ts: timespec structure to hold the current time value 441 * @sts: structure to hold the system time before and after reading the PHC 442 * 443 * Read the device clock and return the correct value on ns, after converting it 444 * into a timespec struct. 445 **/ 446 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 447 struct ptp_system_timestamp *sts) 448 { 449 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 450 451 mutex_lock(&pf->tmreg_lock); 452 i40e_ptp_read(pf, ts, sts); 453 mutex_unlock(&pf->tmreg_lock); 454 455 return 0; 456 } 457 458 /** 459 * i40e_ptp_settime - Set the time of the PHC 460 * @ptp: The PTP clock structure 461 * @ts: timespec64 structure that holds the new time value 462 * 463 * Set the device clock to the user input value. The conversion from timespec 464 * to ns happens in the write function. 465 **/ 466 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 467 const struct timespec64 *ts) 468 { 469 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 470 471 mutex_lock(&pf->tmreg_lock); 472 i40e_ptp_write(pf, ts); 473 mutex_unlock(&pf->tmreg_lock); 474 475 return 0; 476 } 477 478 /** 479 * i40e_pps_configure - configure PPS events 480 * @ptp: ptp clock 481 * @rq: clock request 482 * @on: status 483 * 484 * Configure PPS events for external clock source. 485 * Return 0 on success or error on failure. 486 **/ 487 static int i40e_pps_configure(struct ptp_clock_info *ptp, 488 struct ptp_clock_request *rq, 489 int on) 490 { 491 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 492 493 if (!!on) 494 i40e_ptp_set_1pps_signal_hw(pf); 495 496 return 0; 497 } 498 499 /** 500 * i40e_pin_state - determine PIN state 501 * @index: PIN index 502 * @func: function assigned to PIN 503 * 504 * Determine PIN state based on PIN index and function assigned. 505 * Return PIN state. 506 **/ 507 static enum i40e_ptp_gpio_pin_state i40e_pin_state(int index, int func) 508 { 509 enum i40e_ptp_gpio_pin_state state = off; 510 511 if (index == 0 && func == PTP_PF_EXTTS) 512 state = in_A; 513 if (index == 1 && func == PTP_PF_EXTTS) 514 state = in_B; 515 if (index == 0 && func == PTP_PF_PEROUT) 516 state = out_A; 517 if (index == 1 && func == PTP_PF_PEROUT) 518 state = out_B; 519 520 return state; 521 } 522 523 /** 524 * i40e_ptp_enable_pin - enable PINs. 525 * @pf: private board structure 526 * @chan: channel 527 * @func: PIN function 528 * @on: state 529 * 530 * Enable PTP pins for external clock source. 531 * Return 0 on success or error code on failure. 532 **/ 533 static int i40e_ptp_enable_pin(struct i40e_pf *pf, unsigned int chan, 534 enum ptp_pin_function func, int on) 535 { 536 enum i40e_ptp_gpio_pin_state *pin = NULL; 537 struct i40e_ptp_pins_settings pins; 538 int pin_index; 539 540 /* Use PF0 to set pins. Return success for user space tools */ 541 if (pf->hw.pf_id) 542 return 0; 543 544 /* Preserve previous state of pins that we don't touch */ 545 pins.sdp3_2 = pf->ptp_pins->sdp3_2; 546 pins.sdp3_3 = pf->ptp_pins->sdp3_3; 547 pins.gpio_4 = pf->ptp_pins->gpio_4; 548 549 /* To turn on the pin - find the corresponding one based on 550 * the given index. To turn the function off - find 551 * which pin had it assigned. Don't use ptp_find_pin here 552 * because it tries to lock the pincfg_mux which is locked by 553 * ptp_pin_store() that calls here. 554 */ 555 if (on) { 556 pin_index = ptp_find_pin(pf->ptp_clock, func, chan); 557 if (pin_index < 0) 558 return -EBUSY; 559 560 switch (pin_index) { 561 case SDP3_2: 562 pin = &pins.sdp3_2; 563 break; 564 case SDP3_3: 565 pin = &pins.sdp3_3; 566 break; 567 case GPIO_4: 568 pin = &pins.gpio_4; 569 break; 570 default: 571 return -EINVAL; 572 } 573 574 *pin = i40e_pin_state(chan, func); 575 } else { 576 pins.sdp3_2 = off; 577 pins.sdp3_3 = off; 578 pins.gpio_4 = off; 579 } 580 581 return i40e_ptp_set_pins(pf, &pins) ? -EINVAL : 0; 582 } 583 584 /** 585 * i40e_ptp_feature_enable - Enable external clock pins 586 * @ptp: The PTP clock structure 587 * @rq: The PTP clock request structure 588 * @on: To turn feature on/off 589 * 590 * Setting on/off PTP PPS feature for pin. 591 **/ 592 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 593 struct ptp_clock_request *rq, 594 int on) 595 { 596 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 597 598 enum ptp_pin_function func; 599 unsigned int chan; 600 601 /* TODO: Implement flags handling for EXTTS and PEROUT */ 602 switch (rq->type) { 603 case PTP_CLK_REQ_EXTTS: 604 func = PTP_PF_EXTTS; 605 chan = rq->extts.index; 606 break; 607 case PTP_CLK_REQ_PEROUT: 608 func = PTP_PF_PEROUT; 609 chan = rq->perout.index; 610 break; 611 case PTP_CLK_REQ_PPS: 612 return i40e_pps_configure(ptp, rq, on); 613 default: 614 return -EOPNOTSUPP; 615 } 616 617 return i40e_ptp_enable_pin(pf, chan, func, on); 618 } 619 620 /** 621 * i40e_ptp_get_rx_events - Read I40E_PRTTSYN_STAT_1 and latch events 622 * @pf: the PF data structure 623 * 624 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 625 * for noticed latch events. This allows the driver to keep track of the first 626 * time a latch event was noticed which will be used to help clear out Rx 627 * timestamps for packets that got dropped or lost. 628 * 629 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 630 * expected to be called only while under the ptp_rx_lock. 631 **/ 632 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 633 { 634 struct i40e_hw *hw = &pf->hw; 635 u32 prttsyn_stat, new_latch_events; 636 int i; 637 638 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 639 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 640 641 /* Update the jiffies time for any newly latched timestamp. This 642 * ensures that we store the time that we first discovered a timestamp 643 * was latched by the hardware. The service task will later determine 644 * if we should free the latch and drop that timestamp should too much 645 * time pass. This flow ensures that we only update jiffies for new 646 * events latched since the last time we checked, and not all events 647 * currently latched, so that the service task accounting remains 648 * accurate. 649 */ 650 for (i = 0; i < 4; i++) { 651 if (new_latch_events & BIT(i)) 652 pf->latch_events[i] = jiffies; 653 } 654 655 /* Finally, we store the current status of the Rx timestamp latches */ 656 pf->latch_event_flags = prttsyn_stat; 657 658 return prttsyn_stat; 659 } 660 661 /** 662 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 663 * @pf: The PF private data structure 664 * 665 * This watchdog task is scheduled to detect error case where hardware has 666 * dropped an Rx packet that was timestamped when the ring is full. The 667 * particular error is rare but leaves the device in a state unable to timestamp 668 * any future packets. 669 **/ 670 void i40e_ptp_rx_hang(struct i40e_pf *pf) 671 { 672 struct i40e_hw *hw = &pf->hw; 673 unsigned int i, cleared = 0; 674 675 /* Since we cannot turn off the Rx timestamp logic if the device is 676 * configured for Tx timestamping, we check if Rx timestamping is 677 * configured. We don't want to spuriously warn about Rx timestamp 678 * hangs if we don't care about the timestamps. 679 */ 680 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags) || !pf->ptp_rx) 681 return; 682 683 spin_lock_bh(&pf->ptp_rx_lock); 684 685 /* Update current latch times for Rx events */ 686 i40e_ptp_get_rx_events(pf); 687 688 /* Check all the currently latched Rx events and see whether they have 689 * been latched for over a second. It is assumed that any timestamp 690 * should have been cleared within this time, or else it was captured 691 * for a dropped frame that the driver never received. Thus, we will 692 * clear any timestamp that has been latched for over 1 second. 693 */ 694 for (i = 0; i < 4; i++) { 695 if ((pf->latch_event_flags & BIT(i)) && 696 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 697 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 698 pf->latch_event_flags &= ~BIT(i); 699 cleared++; 700 } 701 } 702 703 spin_unlock_bh(&pf->ptp_rx_lock); 704 705 /* Log a warning if more than 2 timestamps got dropped in the same 706 * check. We don't want to warn about all drops because it can occur 707 * in normal scenarios such as PTP frames on multicast addresses we 708 * aren't listening to. However, administrator should know if this is 709 * the reason packets aren't receiving timestamps. 710 */ 711 if (cleared > 2) 712 dev_dbg(&pf->pdev->dev, 713 "Dropped %d missed RXTIME timestamp events\n", 714 cleared); 715 716 /* Finally, update the rx_hwtstamp_cleared counter */ 717 pf->rx_hwtstamp_cleared += cleared; 718 } 719 720 /** 721 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 722 * @pf: The PF private data structure 723 * 724 * This watchdog task is run periodically to make sure that we clear the Tx 725 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 726 * time. It is unexpected in the normal case but if it occurs it results in 727 * permanently preventing timestamps of future packets. 728 **/ 729 void i40e_ptp_tx_hang(struct i40e_pf *pf) 730 { 731 struct sk_buff *skb; 732 733 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags) || !pf->ptp_tx) 734 return; 735 736 /* Nothing to do if we're not already waiting for a timestamp */ 737 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 738 return; 739 740 /* We already have a handler routine which is run when we are notified 741 * of a Tx timestamp in the hardware. If we don't get an interrupt 742 * within a second it is reasonable to assume that we never will. 743 */ 744 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 745 skb = pf->ptp_tx_skb; 746 pf->ptp_tx_skb = NULL; 747 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 748 749 /* Free the skb after we clear the bitlock */ 750 dev_kfree_skb_any(skb); 751 pf->tx_hwtstamp_timeouts++; 752 } 753 } 754 755 /** 756 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 757 * @pf: Board private structure 758 * 759 * Read the value of the Tx timestamp from the registers, convert it into a 760 * value consumable by the stack, and store that result into the shhwtstamps 761 * struct before returning it up the stack. 762 **/ 763 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 764 { 765 struct skb_shared_hwtstamps shhwtstamps; 766 struct sk_buff *skb = pf->ptp_tx_skb; 767 struct i40e_hw *hw = &pf->hw; 768 u32 hi, lo; 769 u64 ns; 770 771 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags) || !pf->ptp_tx) 772 return; 773 774 /* don't attempt to timestamp if we don't have an skb */ 775 if (!pf->ptp_tx_skb) 776 return; 777 778 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 779 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 780 781 ns = (((u64)hi) << 32) | lo; 782 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 783 784 /* Clear the bit lock as soon as possible after reading the register, 785 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 786 * applications might wake up and attempt to request another transmit 787 * timestamp prior to the bit lock being cleared. 788 */ 789 pf->ptp_tx_skb = NULL; 790 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 791 792 /* Notify the stack and free the skb after we've unlocked */ 793 skb_tstamp_tx(skb, &shhwtstamps); 794 dev_kfree_skb_any(skb); 795 } 796 797 /** 798 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 799 * @pf: Board private structure 800 * @skb: Particular skb to send timestamp with 801 * @index: Index into the receive timestamp registers for the timestamp 802 * 803 * The XL710 receives a notification in the receive descriptor with an offset 804 * into the set of RXTIME registers where the timestamp is for that skb. This 805 * function goes and fetches the receive timestamp from that offset, if a valid 806 * one exists. The RXTIME registers are in ns, so we must convert the result 807 * first. 808 **/ 809 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 810 { 811 u32 prttsyn_stat, hi, lo; 812 struct i40e_hw *hw; 813 u64 ns; 814 815 /* Since we cannot turn off the Rx timestamp logic if the device is 816 * doing Tx timestamping, check if Rx timestamping is configured. 817 */ 818 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags) || !pf->ptp_rx) 819 return; 820 821 hw = &pf->hw; 822 823 spin_lock_bh(&pf->ptp_rx_lock); 824 825 /* Get current Rx events and update latch times */ 826 prttsyn_stat = i40e_ptp_get_rx_events(pf); 827 828 /* TODO: Should we warn about missing Rx timestamp event? */ 829 if (!(prttsyn_stat & BIT(index))) { 830 spin_unlock_bh(&pf->ptp_rx_lock); 831 return; 832 } 833 834 /* Clear the latched event since we're about to read its register */ 835 pf->latch_event_flags &= ~BIT(index); 836 837 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 838 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 839 840 spin_unlock_bh(&pf->ptp_rx_lock); 841 842 ns = (((u64)hi) << 32) | lo; 843 844 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 845 } 846 847 /** 848 * i40e_ptp_set_increment - Utility function to update clock increment rate 849 * @pf: Board private structure 850 * 851 * During a link change, the DMA frequency that drives the 1588 logic will 852 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 853 * we must update the increment value per clock tick. 854 **/ 855 void i40e_ptp_set_increment(struct i40e_pf *pf) 856 { 857 struct i40e_link_status *hw_link_info; 858 struct i40e_hw *hw = &pf->hw; 859 u64 incval; 860 u32 mult; 861 862 hw_link_info = &hw->phy.link_info; 863 864 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 865 866 switch (hw_link_info->link_speed) { 867 case I40E_LINK_SPEED_10GB: 868 mult = I40E_PTP_10GB_INCVAL_MULT; 869 break; 870 case I40E_LINK_SPEED_5GB: 871 mult = I40E_PTP_5GB_INCVAL_MULT; 872 break; 873 case I40E_LINK_SPEED_1GB: 874 mult = I40E_PTP_1GB_INCVAL_MULT; 875 break; 876 case I40E_LINK_SPEED_100MB: 877 { 878 static int warn_once; 879 880 if (!warn_once) { 881 dev_warn(&pf->pdev->dev, 882 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 883 warn_once++; 884 } 885 mult = 0; 886 break; 887 } 888 case I40E_LINK_SPEED_40GB: 889 default: 890 mult = 1; 891 break; 892 } 893 894 /* The increment value is calculated by taking the base 40GbE incvalue 895 * and multiplying it by a factor based on the link speed. 896 */ 897 incval = I40E_PTP_40GB_INCVAL * mult; 898 899 /* Write the new increment value into the increment register. The 900 * hardware will not update the clock until both registers have been 901 * written. 902 */ 903 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 904 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 905 906 /* Update the base adjustement value. */ 907 WRITE_ONCE(pf->ptp_adj_mult, mult); 908 smp_mb(); /* Force the above update. */ 909 } 910 911 /** 912 * i40e_ptp_hwtstamp_get - interface to read the HW timestamping 913 * @netdev: Network device structure 914 * @config: Timestamping configuration structure 915 * 916 * Obtain the current hardware timestamping settigs as requested. To do this, 917 * keep a shadow copy of the timestamp settings rather than attempting to 918 * deconstruct it from the registers. 919 **/ 920 int i40e_ptp_hwtstamp_get(struct net_device *netdev, 921 struct kernel_hwtstamp_config *config) 922 { 923 struct i40e_netdev_priv *np = netdev_priv(netdev); 924 struct i40e_pf *pf = np->vsi->back; 925 926 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags)) 927 return -EOPNOTSUPP; 928 929 *config = pf->tstamp_config; 930 931 return 0; 932 } 933 934 /** 935 * i40e_ptp_free_pins - free memory used by PTP pins 936 * @pf: Board private structure 937 * 938 * Release memory allocated for PTP pins. 939 **/ 940 void i40e_ptp_free_pins(struct i40e_pf *pf) 941 { 942 if (i40e_is_ptp_pin_dev(&pf->hw)) { 943 kfree(pf->ptp_pins); 944 kfree(pf->ptp_caps.pin_config); 945 pf->ptp_pins = NULL; 946 pf->ptp_caps.pin_config = NULL; 947 } 948 } 949 950 /** 951 * i40e_ptp_set_pin_hw - Set HW GPIO pin 952 * @hw: pointer to the hardware structure 953 * @pin: pin index 954 * @state: pin state 955 * 956 * Set status of GPIO pin for external clock handling. 957 **/ 958 static void i40e_ptp_set_pin_hw(struct i40e_hw *hw, 959 unsigned int pin, 960 enum i40e_ptp_gpio_pin_state state) 961 { 962 switch (state) { 963 case off: 964 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 0); 965 break; 966 case in_A: 967 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 968 I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0); 969 break; 970 case in_B: 971 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 972 I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0); 973 break; 974 case out_A: 975 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 976 I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1); 977 break; 978 case out_B: 979 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 980 I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1); 981 break; 982 default: 983 break; 984 } 985 } 986 987 /** 988 * i40e_ptp_set_led_hw - Set HW GPIO led 989 * @hw: pointer to the hardware structure 990 * @led: led index 991 * @state: led state 992 * 993 * Set status of GPIO led for external clock handling. 994 **/ 995 static void i40e_ptp_set_led_hw(struct i40e_hw *hw, 996 unsigned int led, 997 enum i40e_ptp_led_pin_state state) 998 { 999 switch (state) { 1000 case low: 1001 wr32(hw, I40E_GLGEN_GPIO_SET, 1002 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | led); 1003 break; 1004 case high: 1005 wr32(hw, I40E_GLGEN_GPIO_SET, 1006 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | 1007 I40E_GLGEN_GPIO_SET_SDP_DATA_HI | led); 1008 break; 1009 default: 1010 break; 1011 } 1012 } 1013 1014 /** 1015 * i40e_ptp_init_leds_hw - init LEDs 1016 * @hw: pointer to a hardware structure 1017 * 1018 * Set initial state of LEDs 1019 **/ 1020 static void i40e_ptp_init_leds_hw(struct i40e_hw *hw) 1021 { 1022 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_0), 1023 I40E_GLGEN_GPIO_CTL_LED_INIT); 1024 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_1), 1025 I40E_GLGEN_GPIO_CTL_LED_INIT); 1026 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_0), 1027 I40E_GLGEN_GPIO_CTL_LED_INIT); 1028 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_1), 1029 I40E_GLGEN_GPIO_CTL_LED_INIT); 1030 } 1031 1032 /** 1033 * i40e_ptp_set_pins_hw - Set HW GPIO pins 1034 * @pf: Board private structure 1035 * 1036 * This function sets GPIO pins for PTP 1037 **/ 1038 static void i40e_ptp_set_pins_hw(struct i40e_pf *pf) 1039 { 1040 const struct i40e_ptp_pins_settings *pins = pf->ptp_pins; 1041 struct i40e_hw *hw = &pf->hw; 1042 1043 /* pin must be disabled before it may be used */ 1044 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off); 1045 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off); 1046 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off); 1047 1048 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, pins->sdp3_2); 1049 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, pins->sdp3_3); 1050 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, pins->gpio_4); 1051 1052 i40e_ptp_set_led_hw(hw, I40E_LED2_0, pins->led2_0); 1053 i40e_ptp_set_led_hw(hw, I40E_LED2_1, pins->led2_1); 1054 i40e_ptp_set_led_hw(hw, I40E_LED3_0, pins->led3_0); 1055 i40e_ptp_set_led_hw(hw, I40E_LED3_1, pins->led3_1); 1056 1057 dev_info(&pf->pdev->dev, 1058 "PTP configuration set to: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n", 1059 i40e_ptp_gpio_pin_state2str[pins->sdp3_2], 1060 i40e_ptp_gpio_pin_state2str[pins->sdp3_3], 1061 i40e_ptp_gpio_pin_state2str[pins->gpio_4]); 1062 } 1063 1064 /** 1065 * i40e_ptp_set_pins - set PTP pins in HW 1066 * @pf: Board private structure 1067 * @pins: PTP pins to be applied 1068 * 1069 * Validate and set PTP pins in HW for specific PF. 1070 * Return 0 on success or negative value on error. 1071 **/ 1072 static int i40e_ptp_set_pins(struct i40e_pf *pf, 1073 struct i40e_ptp_pins_settings *pins) 1074 { 1075 enum i40e_can_set_pins pin_caps = i40e_can_set_pins(pf); 1076 int i = 0; 1077 1078 if (pin_caps == CANT_DO_PINS) 1079 return -EOPNOTSUPP; 1080 else if (pin_caps == CAN_DO_PINS) 1081 return 0; 1082 1083 if (pins->sdp3_2 == invalid) 1084 pins->sdp3_2 = pf->ptp_pins->sdp3_2; 1085 if (pins->sdp3_3 == invalid) 1086 pins->sdp3_3 = pf->ptp_pins->sdp3_3; 1087 if (pins->gpio_4 == invalid) 1088 pins->gpio_4 = pf->ptp_pins->gpio_4; 1089 while (i40e_ptp_pin_led_allowed_states[i].sdp3_2 != end) { 1090 if (pins->sdp3_2 == i40e_ptp_pin_led_allowed_states[i].sdp3_2 && 1091 pins->sdp3_3 == i40e_ptp_pin_led_allowed_states[i].sdp3_3 && 1092 pins->gpio_4 == i40e_ptp_pin_led_allowed_states[i].gpio_4) { 1093 pins->led2_0 = 1094 i40e_ptp_pin_led_allowed_states[i].led2_0; 1095 pins->led2_1 = 1096 i40e_ptp_pin_led_allowed_states[i].led2_1; 1097 pins->led3_0 = 1098 i40e_ptp_pin_led_allowed_states[i].led3_0; 1099 pins->led3_1 = 1100 i40e_ptp_pin_led_allowed_states[i].led3_1; 1101 break; 1102 } 1103 i++; 1104 } 1105 if (i40e_ptp_pin_led_allowed_states[i].sdp3_2 == end) { 1106 dev_warn(&pf->pdev->dev, 1107 "Unsupported PTP pin configuration: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n", 1108 i40e_ptp_gpio_pin_state2str[pins->sdp3_2], 1109 i40e_ptp_gpio_pin_state2str[pins->sdp3_3], 1110 i40e_ptp_gpio_pin_state2str[pins->gpio_4]); 1111 1112 return -EPERM; 1113 } 1114 memcpy(pf->ptp_pins, pins, sizeof(*pins)); 1115 i40e_ptp_set_pins_hw(pf); 1116 i40_ptp_reset_timing_events(pf); 1117 1118 return 0; 1119 } 1120 1121 /** 1122 * i40e_ptp_alloc_pins - allocate PTP pins structure 1123 * @pf: Board private structure 1124 * 1125 * allocate PTP pins structure 1126 **/ 1127 int i40e_ptp_alloc_pins(struct i40e_pf *pf) 1128 { 1129 if (!i40e_is_ptp_pin_dev(&pf->hw)) 1130 return 0; 1131 1132 pf->ptp_pins = 1133 kzalloc_obj(struct i40e_ptp_pins_settings); 1134 1135 if (!pf->ptp_pins) { 1136 dev_warn(&pf->pdev->dev, "Cannot allocate memory for PTP pins structure.\n"); 1137 return -ENOMEM; 1138 } 1139 1140 pf->ptp_pins->sdp3_2 = off; 1141 pf->ptp_pins->sdp3_3 = off; 1142 pf->ptp_pins->gpio_4 = off; 1143 pf->ptp_pins->led2_0 = high; 1144 pf->ptp_pins->led2_1 = high; 1145 pf->ptp_pins->led3_0 = high; 1146 pf->ptp_pins->led3_1 = high; 1147 1148 /* Use PF0 to set pins in HW. Return success for user space tools */ 1149 if (pf->hw.pf_id) 1150 return 0; 1151 1152 i40e_ptp_init_leds_hw(&pf->hw); 1153 i40e_ptp_set_pins_hw(pf); 1154 1155 return 0; 1156 } 1157 1158 /** 1159 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 1160 * @pf: Board private structure 1161 * @config: hwtstamp settings requested or saved 1162 * 1163 * Control hardware registers to enter the specific mode requested by the 1164 * user. Also used during reset path to ensure that timestamp settings are 1165 * maintained. 1166 * 1167 * Note: modifies config in place, and may update the requested mode to be 1168 * more broad if the specific filter is not directly supported. 1169 **/ 1170 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 1171 struct kernel_hwtstamp_config *config) 1172 { 1173 struct i40e_hw *hw = &pf->hw; 1174 u32 tsyntype, regval; 1175 1176 /* Selects external trigger to cause event */ 1177 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0)); 1178 /* Bit 17:16 is EVNTLVL, 01B rising edge */ 1179 regval &= 0; 1180 regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT); 1181 /* regval: 0001 0000 0000 0000 0000 */ 1182 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval); 1183 1184 /* Enabel interrupts */ 1185 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1186 regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT; 1187 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1188 1189 INIT_WORK(&pf->ptp_extts0_work, i40e_ptp_extts0_work); 1190 1191 switch (config->tx_type) { 1192 case HWTSTAMP_TX_OFF: 1193 pf->ptp_tx = false; 1194 break; 1195 case HWTSTAMP_TX_ON: 1196 pf->ptp_tx = true; 1197 break; 1198 default: 1199 return -ERANGE; 1200 } 1201 1202 switch (config->rx_filter) { 1203 case HWTSTAMP_FILTER_NONE: 1204 pf->ptp_rx = false; 1205 /* We set the type to V1, but do not enable UDP packet 1206 * recognition. In this way, we should be as close to 1207 * disabling PTP Rx timestamps as possible since V1 packets 1208 * are always UDP, since L2 packets are a V2 feature. 1209 */ 1210 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 1211 break; 1212 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1213 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1214 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1215 if (!test_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps)) 1216 return -ERANGE; 1217 pf->ptp_rx = true; 1218 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 1219 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 1220 I40E_PRTTSYN_CTL1_UDP_ENA_319; 1221 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1222 break; 1223 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1224 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1225 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1226 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1227 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1228 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1229 if (!test_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps)) 1230 return -ERANGE; 1231 fallthrough; 1232 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1233 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1234 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1235 pf->ptp_rx = true; 1236 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 1237 I40E_PRTTSYN_CTL1_TSYNTYPE_V2_EVENT; 1238 if (test_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps)) { 1239 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_319; 1240 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1241 } else { 1242 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1243 } 1244 break; 1245 case HWTSTAMP_FILTER_NTP_ALL: 1246 case HWTSTAMP_FILTER_ALL: 1247 default: 1248 return -ERANGE; 1249 } 1250 1251 /* Clear out all 1588-related registers to clear and unlatch them. */ 1252 spin_lock_bh(&pf->ptp_rx_lock); 1253 rd32(hw, I40E_PRTTSYN_STAT_0); 1254 rd32(hw, I40E_PRTTSYN_TXTIME_H); 1255 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 1256 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 1257 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 1258 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 1259 pf->latch_event_flags = 0; 1260 spin_unlock_bh(&pf->ptp_rx_lock); 1261 1262 /* Enable/disable the Tx timestamp interrupt based on user input. */ 1263 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1264 if (pf->ptp_tx) 1265 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 1266 else 1267 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 1268 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1269 1270 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 1271 if (pf->ptp_tx) 1272 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 1273 else 1274 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 1275 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 1276 1277 /* Although there is no simple on/off switch for Rx, we "disable" Rx 1278 * timestamps by setting to V1 only mode and clear the UDP 1279 * recognition. This ought to disable all PTP Rx timestamps as V1 1280 * packets are always over UDP. Note that software is configured to 1281 * ignore Rx timestamps via the pf->ptp_rx flag. 1282 */ 1283 regval = rd32(hw, I40E_PRTTSYN_CTL1); 1284 /* clear everything but the enable bit */ 1285 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 1286 /* now enable bits for desired Rx timestamps */ 1287 regval |= tsyntype; 1288 wr32(hw, I40E_PRTTSYN_CTL1, regval); 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * i40e_ptp_hwtstamp_set - interface to control the HW timestamping 1295 * @netdev: Network device structure 1296 * @config: Timestamping configuration structure 1297 * @extack: Netlink extended ack structure for error reporting 1298 * 1299 * Respond to the user filter requests and make the appropriate hardware 1300 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 1301 * logic, so keep track in software of whether to indicate these timestamps 1302 * or not. 1303 * 1304 * It is permissible to "upgrade" the user request to a broader filter, as long 1305 * as the user receives the timestamps they care about and the user is notified 1306 * the filter has been broadened. 1307 **/ 1308 int i40e_ptp_hwtstamp_set(struct net_device *netdev, 1309 struct kernel_hwtstamp_config *config, 1310 struct netlink_ext_ack *extack) 1311 { 1312 struct i40e_netdev_priv *np = netdev_priv(netdev); 1313 struct i40e_pf *pf = np->vsi->back; 1314 int err; 1315 1316 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags)) 1317 return -EOPNOTSUPP; 1318 1319 err = i40e_ptp_set_timestamp_mode(pf, config); 1320 if (err) 1321 return err; 1322 1323 /* save these settings for future reference */ 1324 pf->tstamp_config = *config; 1325 1326 return 0; 1327 } 1328 1329 /** 1330 * i40e_init_pin_config - initialize pins. 1331 * @pf: private board structure 1332 * 1333 * Initialize pins for external clock source. 1334 * Return 0 on success or error code on failure. 1335 **/ 1336 static int i40e_init_pin_config(struct i40e_pf *pf) 1337 { 1338 int i; 1339 1340 pf->ptp_caps.n_pins = 3; 1341 pf->ptp_caps.n_ext_ts = 2; 1342 pf->ptp_caps.pps = 1; 1343 pf->ptp_caps.n_per_out = 2; 1344 1345 pf->ptp_caps.pin_config = kzalloc_objs(*pf->ptp_caps.pin_config, 1346 pf->ptp_caps.n_pins); 1347 if (!pf->ptp_caps.pin_config) 1348 return -ENOMEM; 1349 1350 for (i = 0; i < pf->ptp_caps.n_pins; i++) { 1351 snprintf(pf->ptp_caps.pin_config[i].name, 1352 sizeof(pf->ptp_caps.pin_config[i].name), 1353 "%s", sdp_desc[i].name); 1354 pf->ptp_caps.pin_config[i].index = sdp_desc[i].index; 1355 pf->ptp_caps.pin_config[i].func = PTP_PF_NONE; 1356 pf->ptp_caps.pin_config[i].chan = sdp_desc[i].chan; 1357 } 1358 1359 pf->ptp_caps.verify = i40e_ptp_verify; 1360 pf->ptp_caps.enable = i40e_ptp_feature_enable; 1361 1362 pf->ptp_caps.pps = 1; 1363 1364 return 0; 1365 } 1366 1367 /** 1368 * i40e_ptp_create_clock - Create PTP clock device for userspace 1369 * @pf: Board private structure 1370 * 1371 * This function creates a new PTP clock device. It only creates one if we 1372 * don't already have one, so it is safe to call. Will return error if it 1373 * can't create one, but success if we already have a device. Should be used 1374 * by i40e_ptp_init to create clock initially, and prevent global resets from 1375 * creating new clock devices. 1376 **/ 1377 static long i40e_ptp_create_clock(struct i40e_pf *pf) 1378 { 1379 /* no need to create a clock device if we already have one */ 1380 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 1381 return 0; 1382 1383 strscpy(pf->ptp_caps.name, i40e_driver_name, 1384 sizeof(pf->ptp_caps.name) - 1); 1385 pf->ptp_caps.owner = THIS_MODULE; 1386 pf->ptp_caps.max_adj = 999999999; 1387 pf->ptp_caps.adjfine = i40e_ptp_adjfine; 1388 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 1389 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex; 1390 pf->ptp_caps.settime64 = i40e_ptp_settime; 1391 if (i40e_is_ptp_pin_dev(&pf->hw)) { 1392 int err = i40e_init_pin_config(pf); 1393 1394 if (err) 1395 return err; 1396 } 1397 1398 /* Attempt to register the clock before enabling the hardware. */ 1399 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 1400 if (IS_ERR(pf->ptp_clock)) 1401 return PTR_ERR(pf->ptp_clock); 1402 1403 /* clear the hwtstamp settings here during clock create, instead of 1404 * during regular init, so that we can maintain settings across a 1405 * reset or suspend. 1406 */ 1407 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1408 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1409 1410 /* Set the previous "reset" time to the current Kernel clock time */ 1411 ktime_get_real_ts64(&pf->ptp_prev_hw_time); 1412 pf->ptp_reset_start = ktime_get(); 1413 1414 return 0; 1415 } 1416 1417 /** 1418 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time 1419 * @pf: Board private structure 1420 * 1421 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should 1422 * be called at the end of preparing to reset, just before hardware reset 1423 * occurs, in order to preserve the PTP time as close as possible across 1424 * resets. 1425 */ 1426 void i40e_ptp_save_hw_time(struct i40e_pf *pf) 1427 { 1428 /* don't try to access the PTP clock if it's not enabled */ 1429 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags)) 1430 return; 1431 1432 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL); 1433 /* Get a monotonic starting time for this reset */ 1434 pf->ptp_reset_start = ktime_get(); 1435 } 1436 1437 /** 1438 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs 1439 * @pf: Board private structure 1440 * 1441 * Restore the PTP hardware clock registers. We previously cached the PTP 1442 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible, 1443 * update this value based on the time delta since the time was saved, using 1444 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference. 1445 * 1446 * This ensures that the hardware clock is restored to nearly what it should 1447 * have been if a reset had not occurred. 1448 */ 1449 void i40e_ptp_restore_hw_time(struct i40e_pf *pf) 1450 { 1451 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start); 1452 1453 /* Update the previous HW time with the ktime delta */ 1454 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta)); 1455 1456 /* Restore the hardware clock registers */ 1457 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time); 1458 } 1459 1460 /** 1461 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 1462 * @pf: Board private structure 1463 * 1464 * This function sets device up for 1588 support. The first time it is run, it 1465 * will create a PHC clock device. It does not create a clock device if one 1466 * already exists. It also reconfigures the device after a reset. 1467 * 1468 * The first time a clock is created, i40e_ptp_create_clock will set 1469 * pf->ptp_prev_hw_time to the current system time. During resets, it is 1470 * expected that this timespec will be set to the last known PTP clock time, 1471 * in order to preserve the clock time as close as possible across a reset. 1472 **/ 1473 void i40e_ptp_init(struct i40e_pf *pf) 1474 { 1475 struct i40e_vsi *vsi = i40e_pf_get_main_vsi(pf); 1476 struct net_device *netdev = vsi->netdev; 1477 struct i40e_hw *hw = &pf->hw; 1478 u32 pf_id; 1479 long err; 1480 1481 /* Only one PF is assigned to control 1588 logic per port. Do not 1482 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 1483 */ 1484 pf_id = FIELD_GET(I40E_PRTTSYN_CTL0_PF_ID_MASK, 1485 rd32(hw, I40E_PRTTSYN_CTL0)); 1486 if (hw->pf_id != pf_id) { 1487 clear_bit(I40E_FLAG_PTP_ENA, pf->flags); 1488 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 1489 __func__, 1490 netdev->name); 1491 return; 1492 } 1493 1494 mutex_init(&pf->tmreg_lock); 1495 spin_lock_init(&pf->ptp_rx_lock); 1496 1497 /* ensure we have a clock device */ 1498 err = i40e_ptp_create_clock(pf); 1499 if (err) { 1500 pf->ptp_clock = NULL; 1501 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 1502 __func__); 1503 } else if (pf->ptp_clock) { 1504 u32 regval; 1505 1506 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 1507 dev_info(&pf->pdev->dev, "PHC enabled\n"); 1508 set_bit(I40E_FLAG_PTP_ENA, pf->flags); 1509 1510 /* Ensure the clocks are running. */ 1511 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1512 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 1513 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1514 regval = rd32(hw, I40E_PRTTSYN_CTL1); 1515 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 1516 wr32(hw, I40E_PRTTSYN_CTL1, regval); 1517 1518 /* Set the increment value per clock tick. */ 1519 i40e_ptp_set_increment(pf); 1520 1521 /* reset timestamping mode */ 1522 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 1523 1524 /* Restore the clock time based on last known value */ 1525 i40e_ptp_restore_hw_time(pf); 1526 } 1527 1528 i40e_ptp_set_1pps_signal_hw(pf); 1529 } 1530 1531 /** 1532 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 1533 * @pf: Board private structure 1534 * 1535 * This function handles the cleanup work required from the initialization by 1536 * clearing out the important information and unregistering the PHC. 1537 **/ 1538 void i40e_ptp_stop(struct i40e_pf *pf) 1539 { 1540 struct i40e_vsi *main_vsi = i40e_pf_get_main_vsi(pf); 1541 struct i40e_hw *hw = &pf->hw; 1542 u32 regval; 1543 1544 clear_bit(I40E_FLAG_PTP_ENA, pf->flags); 1545 pf->ptp_tx = false; 1546 pf->ptp_rx = false; 1547 1548 if (pf->ptp_tx_skb) { 1549 struct sk_buff *skb = pf->ptp_tx_skb; 1550 1551 pf->ptp_tx_skb = NULL; 1552 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 1553 dev_kfree_skb_any(skb); 1554 } 1555 1556 if (pf->ptp_clock) { 1557 ptp_clock_unregister(pf->ptp_clock); 1558 pf->ptp_clock = NULL; 1559 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 1560 main_vsi->netdev->name); 1561 } 1562 1563 if (i40e_is_ptp_pin_dev(&pf->hw)) { 1564 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off); 1565 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off); 1566 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off); 1567 } 1568 1569 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0)); 1570 regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK; 1571 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval); 1572 1573 /* Disable interrupts */ 1574 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1575 regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK; 1576 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1577 1578 i40e_ptp_free_pins(pf); 1579 } 1580