1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_sdma.h" 32 #include "amdgpu_trace.h" 33 34 #include "gc/gc_11_0_0_offset.h" 35 #include "gc/gc_11_0_0_sh_mask.h" 36 #include "gc/gc_11_0_0_default.h" 37 #include "hdp/hdp_6_0_0_offset.h" 38 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "sdma_v6_0_0_pkt_open.h" 43 #include "nbio_v4_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v6_0.h" 46 #include "v11_structs.h" 47 #include "mes_userqueue.h" 48 #include "amdgpu_userq_fence.h" 49 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 52 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 53 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); 56 MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin"); 57 MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin"); 58 MODULE_FIRMWARE("amdgpu/sdma_6_1_4.bin"); 59 MODULE_FIRMWARE("amdgpu/sdma_6_4_0.bin"); 60 61 #define SDMA1_REG_OFFSET 0x600 62 #define SDMA0_HYP_DEC_REG_START 0x5880 63 #define SDMA0_HYP_DEC_REG_END 0x589a 64 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 65 66 static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = { 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 116 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 117 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 118 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 119 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 120 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 121 }; 122 123 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 124 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 125 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 126 static int sdma_v6_0_start(struct amdgpu_device *adev); 127 128 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 129 { 130 u32 base; 131 132 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 133 internal_offset <= SDMA0_HYP_DEC_REG_END) { 134 base = adev->reg_offset[GC_HWIP][0][1]; 135 if (instance != 0) 136 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 137 } else { 138 base = adev->reg_offset[GC_HWIP][0][0]; 139 if (instance == 1) 140 internal_offset += SDMA1_REG_OFFSET; 141 } 142 143 return base + internal_offset; 144 } 145 146 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring, 147 uint64_t addr) 148 { 149 unsigned ret; 150 151 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 152 amdgpu_ring_write(ring, lower_32_bits(addr)); 153 amdgpu_ring_write(ring, upper_32_bits(addr)); 154 amdgpu_ring_write(ring, 1); 155 /* this is the offset we need patch later */ 156 ret = ring->wptr & ring->buf_mask; 157 /* insert dummy here and patch it later */ 158 amdgpu_ring_write(ring, 0); 159 160 return ret; 161 } 162 163 /** 164 * sdma_v6_0_ring_get_rptr - get the current read pointer 165 * 166 * @ring: amdgpu ring pointer 167 * 168 * Get the current rptr from the hardware. 169 */ 170 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 171 { 172 u64 *rptr; 173 174 /* XXX check if swapping is necessary on BE */ 175 rptr = (u64 *)ring->rptr_cpu_addr; 176 177 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 178 return ((*rptr) >> 2); 179 } 180 181 /** 182 * sdma_v6_0_ring_get_wptr - get the current write pointer 183 * 184 * @ring: amdgpu ring pointer 185 * 186 * Get the current wptr from the hardware. 187 */ 188 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 189 { 190 u64 wptr = 0; 191 192 if (ring->use_doorbell) { 193 /* XXX check if swapping is necessary on BE */ 194 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 195 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 196 } 197 198 return wptr >> 2; 199 } 200 201 /** 202 * sdma_v6_0_ring_set_wptr - commit the write pointer 203 * 204 * @ring: amdgpu ring pointer 205 * 206 * Write the wptr back to the hardware. 207 */ 208 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 209 { 210 struct amdgpu_device *adev = ring->adev; 211 212 if (ring->use_doorbell) { 213 DRM_DEBUG("Using doorbell -- " 214 "wptr_offs == 0x%08x " 215 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 216 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 217 ring->wptr_offs, 218 lower_32_bits(ring->wptr << 2), 219 upper_32_bits(ring->wptr << 2)); 220 /* XXX check if swapping is necessary on BE */ 221 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 222 ring->wptr << 2); 223 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 224 ring->doorbell_index, ring->wptr << 2); 225 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 226 } else { 227 DRM_DEBUG("Not using doorbell -- " 228 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 229 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 230 ring->me, 231 lower_32_bits(ring->wptr << 2), 232 ring->me, 233 upper_32_bits(ring->wptr << 2)); 234 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 235 ring->me, regSDMA0_QUEUE0_RB_WPTR), 236 lower_32_bits(ring->wptr << 2)); 237 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 238 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 239 upper_32_bits(ring->wptr << 2)); 240 } 241 } 242 243 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 244 { 245 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 246 const u32 nop = ring->funcs->nop; 247 248 if (count && sdma->burst_nop) { 249 --count; 250 amdgpu_ring_write(ring, nop | SDMA_PKT_NOP_HEADER_COUNT(count)); 251 } 252 253 amdgpu_ring_fill(ring, nop, count); 254 } 255 256 /* 257 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 258 * 259 * @ring: amdgpu ring pointer 260 * @ib: IB object to schedule 261 * @flags: unused 262 * @job: job to retrieve vmid from 263 * 264 * Schedule an IB in the DMA ring. 265 */ 266 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 267 struct amdgpu_job *job, 268 struct amdgpu_ib *ib, 269 uint32_t flags) 270 { 271 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 272 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 273 274 /* An IB packet must end on a 8 DW boundary--the next dword 275 * must be on a 8-dword boundary. Our IB packet below is 6 276 * dwords long, thus add x number of NOPs, such that, in 277 * modular arithmetic, 278 * wptr + 6 + x = 8k, k >= 0, which in C is, 279 * (wptr + 6 + x) % 8 = 0. 280 * The expression below, is a solution of x. 281 */ 282 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 283 284 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 285 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 286 /* base must be 32 byte aligned */ 287 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 288 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 289 amdgpu_ring_write(ring, ib->length_dw); 290 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 291 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 292 } 293 294 /** 295 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 296 * 297 * @ring: amdgpu ring pointer 298 * 299 * flush the IB by graphics cache rinse. 300 */ 301 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 302 { 303 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 304 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 305 SDMA_GCR_GLI_INV(1); 306 307 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 308 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 309 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 310 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 311 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 312 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 313 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 314 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 315 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 316 } 317 318 319 /** 320 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 321 * 322 * @ring: amdgpu ring pointer 323 * 324 * Emit an hdp flush packet on the requested DMA ring. 325 */ 326 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 327 { 328 struct amdgpu_device *adev = ring->adev; 329 u32 ref_and_mask = 0; 330 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 331 332 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 333 334 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 335 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 336 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 337 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 338 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 339 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 340 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 341 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 342 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 343 } 344 345 /** 346 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 347 * 348 * @ring: amdgpu ring pointer 349 * @addr: address 350 * @seq: fence seq number 351 * @flags: fence flags 352 * 353 * Add a DMA fence packet to the ring to write 354 * the fence seq number and DMA trap packet to generate 355 * an interrupt if needed. 356 */ 357 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 358 unsigned flags) 359 { 360 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 361 /* write the fence */ 362 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 363 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 364 /* zero in first two bits */ 365 WARN_ON(addr & 0x3); 366 amdgpu_ring_write(ring, lower_32_bits(addr)); 367 amdgpu_ring_write(ring, upper_32_bits(addr)); 368 amdgpu_ring_write(ring, lower_32_bits(seq)); 369 370 /* optionally write high bits as well */ 371 if (write64bit) { 372 addr += 4; 373 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 374 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 375 /* zero in first two bits */ 376 WARN_ON(addr & 0x3); 377 amdgpu_ring_write(ring, lower_32_bits(addr)); 378 amdgpu_ring_write(ring, upper_32_bits(addr)); 379 amdgpu_ring_write(ring, upper_32_bits(seq)); 380 } 381 382 if (flags & AMDGPU_FENCE_FLAG_INT) { 383 /* generate an interrupt */ 384 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 385 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 386 } 387 } 388 389 /** 390 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 391 * 392 * @adev: amdgpu_device pointer 393 * 394 * Stop the gfx async dma ring buffers. 395 */ 396 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 397 { 398 u32 rb_cntl, ib_cntl; 399 int i; 400 401 for (i = 0; i < adev->sdma.num_instances; i++) { 402 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 403 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 404 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 405 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 406 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 407 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 408 } 409 } 410 411 /** 412 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 413 * 414 * @adev: amdgpu_device pointer 415 * @enable: enable/disable context switching due to queue empty conditions 416 * 417 * Enable or disable the async dma engines queue empty context switch. 418 */ 419 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 420 { 421 u32 f32_cntl; 422 int i; 423 424 if (!amdgpu_sriov_vf(adev)) { 425 for (i = 0; i < adev->sdma.num_instances; i++) { 426 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 427 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 428 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 429 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 430 } 431 } 432 } 433 434 /** 435 * sdma_v6_0_enable - stop the async dma engines 436 * 437 * @adev: amdgpu_device pointer 438 * @enable: enable/disable the DMA MEs. 439 * 440 * Halt or unhalt the async dma engines. 441 */ 442 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 443 { 444 u32 f32_cntl; 445 int i; 446 447 if (!enable) { 448 sdma_v6_0_gfx_stop(adev); 449 } 450 451 if (amdgpu_sriov_vf(adev)) 452 return; 453 454 for (i = 0; i < adev->sdma.num_instances; i++) { 455 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 456 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 457 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 458 } 459 } 460 461 /** 462 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine 463 * 464 * @adev: amdgpu_device pointer 465 * @i: instance 466 * @restore: used to restore wptr when restart 467 * 468 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 469 * Return 0 for success. 470 */ 471 static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 472 { 473 struct amdgpu_ring *ring; 474 u32 rb_cntl, ib_cntl; 475 u32 rb_bufsz; 476 u32 doorbell; 477 u32 doorbell_offset; 478 u32 temp; 479 u64 wptr_gpu_addr; 480 481 ring = &adev->sdma.instance[i].ring; 482 if (!amdgpu_sriov_vf(adev)) 483 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 484 485 /* Set ring buffer size in dwords */ 486 rb_bufsz = order_base_2(ring->ring_size / 4); 487 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 488 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 489 #ifdef __BIG_ENDIAN 490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 491 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 492 RPTR_WRITEBACK_SWAP_ENABLE, 1); 493 #endif 494 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 495 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 496 497 /* Initialize the ring buffer's read and write pointers */ 498 if (restore) { 499 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 500 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 501 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 502 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 503 } else { 504 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 505 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 506 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 507 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 508 } 509 /* setup the wptr shadow polling */ 510 wptr_gpu_addr = ring->wptr_gpu_addr; 511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 512 lower_32_bits(wptr_gpu_addr)); 513 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 514 upper_32_bits(wptr_gpu_addr)); 515 516 /* set the wb address whether it's enabled or not */ 517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 518 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 520 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 521 522 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 523 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 524 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 525 526 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 527 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 528 529 if (!restore) 530 ring->wptr = 0; 531 532 /* before programing wptr to a less value, need set minor_ptr_update first */ 533 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 534 535 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 536 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 538 } 539 540 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 541 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 542 543 if (ring->use_doorbell) { 544 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 545 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 546 OFFSET, ring->doorbell_index); 547 } else { 548 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 549 } 550 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 551 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 552 553 if (i == 0) 554 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 555 ring->doorbell_index, 556 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 557 558 if (amdgpu_sriov_vf(adev)) 559 sdma_v6_0_ring_set_wptr(ring); 560 561 /* set minor_ptr_update to 0 after wptr programed */ 562 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 563 564 /* Set up sdma hang watchdog */ 565 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 566 /* 100ms per unit */ 567 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 568 max(adev->usec_timeout/100000, 1)); 569 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 570 571 /* Set up RESP_MODE to non-copy addresses */ 572 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 573 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 574 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 575 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 576 577 /* program default cache read and write policy */ 578 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 579 /* clean read policy and write policy bits */ 580 temp &= 0xFF0FFF; 581 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 582 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 583 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 584 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 585 586 if (!amdgpu_sriov_vf(adev)) { 587 /* unhalt engine */ 588 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 589 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 590 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 591 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 592 } 593 594 /* enable DMA RB */ 595 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 596 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 597 598 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 599 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 600 #ifdef __BIG_ENDIAN 601 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 602 #endif 603 /* enable DMA IBs */ 604 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 605 606 if (amdgpu_sriov_vf(adev)) 607 sdma_v6_0_enable(adev, true); 608 609 return amdgpu_ring_test_helper(ring); 610 } 611 612 /** 613 * sdma_v6_0_gfx_resume - setup and start the async dma engines 614 * 615 * @adev: amdgpu_device pointer 616 * 617 * Set up the gfx DMA ring buffers and enable them. 618 * Returns 0 for success, error for failure. 619 */ 620 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 621 { 622 int i, r; 623 624 for (i = 0; i < adev->sdma.num_instances; i++) { 625 r = sdma_v6_0_gfx_resume_instance(adev, i, false); 626 if (r) 627 return r; 628 } 629 630 return 0; 631 } 632 633 /** 634 * sdma_v6_0_load_microcode - load the sDMA ME ucode 635 * 636 * @adev: amdgpu_device pointer 637 * 638 * Loads the sDMA0/1 ucode. 639 * Returns 0 for success, -EINVAL if the ucode is not available. 640 */ 641 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 642 { 643 const struct sdma_firmware_header_v2_0 *hdr; 644 const __le32 *fw_data; 645 u32 fw_size; 646 int i, j; 647 bool use_broadcast; 648 649 /* halt the MEs */ 650 sdma_v6_0_enable(adev, false); 651 652 if (!adev->sdma.instance[0].fw) 653 return -EINVAL; 654 655 /* use broadcast mode to load SDMA microcode by default */ 656 use_broadcast = true; 657 658 if (use_broadcast) { 659 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 660 /* load Control Thread microcode */ 661 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 662 amdgpu_ucode_print_sdma_hdr(&hdr->header); 663 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 664 665 fw_data = (const __le32 *) 666 (adev->sdma.instance[0].fw->data + 667 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 668 669 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 670 671 for (j = 0; j < fw_size; j++) { 672 if (amdgpu_emu_mode == 1 && j % 500 == 0) 673 msleep(1); 674 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 675 } 676 677 /* load Context Switch microcode */ 678 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 679 680 fw_data = (const __le32 *) 681 (adev->sdma.instance[0].fw->data + 682 le32_to_cpu(hdr->ctl_ucode_offset)); 683 684 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 685 686 for (j = 0; j < fw_size; j++) { 687 if (amdgpu_emu_mode == 1 && j % 500 == 0) 688 msleep(1); 689 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 690 } 691 } else { 692 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 693 for (i = 0; i < adev->sdma.num_instances; i++) { 694 /* load Control Thread microcode */ 695 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 696 amdgpu_ucode_print_sdma_hdr(&hdr->header); 697 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 698 699 fw_data = (const __le32 *) 700 (adev->sdma.instance[0].fw->data + 701 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 702 703 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 704 705 for (j = 0; j < fw_size; j++) { 706 if (amdgpu_emu_mode == 1 && j % 500 == 0) 707 msleep(1); 708 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 709 } 710 711 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 712 713 /* load Context Switch microcode */ 714 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 715 716 fw_data = (const __le32 *) 717 (adev->sdma.instance[0].fw->data + 718 le32_to_cpu(hdr->ctl_ucode_offset)); 719 720 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 721 722 for (j = 0; j < fw_size; j++) { 723 if (amdgpu_emu_mode == 1 && j % 500 == 0) 724 msleep(1); 725 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 726 } 727 728 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 729 } 730 } 731 732 return 0; 733 } 734 735 static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 736 { 737 struct amdgpu_device *adev = ip_block->adev; 738 u32 tmp; 739 int i; 740 741 sdma_v6_0_gfx_stop(adev); 742 743 for (i = 0; i < adev->sdma.num_instances; i++) { 744 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 745 tmp |= SDMA0_FREEZE__FREEZE_MASK; 746 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 747 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 748 tmp |= SDMA0_F32_CNTL__HALT_MASK; 749 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 750 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 751 752 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 753 754 udelay(100); 755 756 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 757 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 758 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 759 760 udelay(100); 761 762 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 763 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 764 765 udelay(100); 766 } 767 768 return sdma_v6_0_start(adev); 769 } 770 771 /** 772 * sdma_v6_0_start - setup and start the async dma engines 773 * 774 * @adev: amdgpu_device pointer 775 * 776 * Set up the DMA engines and enable them. 777 * Returns 0 for success, error for failure. 778 */ 779 static int sdma_v6_0_start(struct amdgpu_device *adev) 780 { 781 int r = 0; 782 783 if (amdgpu_sriov_vf(adev)) { 784 sdma_v6_0_enable(adev, false); 785 786 /* set RB registers */ 787 r = sdma_v6_0_gfx_resume(adev); 788 return r; 789 } 790 791 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 792 r = sdma_v6_0_load_microcode(adev); 793 if (r) 794 return r; 795 796 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 797 if (amdgpu_emu_mode == 1) 798 msleep(1000); 799 } 800 801 /* unhalt the MEs */ 802 sdma_v6_0_enable(adev, true); 803 /* enable sdma ring preemption */ 804 sdma_v6_0_ctxempty_int_enable(adev, true); 805 806 /* start the gfx rings and rlc compute queues */ 807 r = sdma_v6_0_gfx_resume(adev); 808 if (r) 809 return r; 810 811 return r; 812 } 813 814 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 815 struct amdgpu_mqd_prop *prop) 816 { 817 struct v11_sdma_mqd *m = mqd; 818 uint64_t wb_gpu_addr; 819 820 m->sdmax_rlcx_rb_cntl = 821 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 822 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 823 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 824 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 825 826 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 827 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 828 829 wb_gpu_addr = prop->wptr_gpu_addr; 830 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 831 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 832 833 wb_gpu_addr = prop->rptr_gpu_addr; 834 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 835 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 836 837 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 838 regSDMA0_QUEUE0_IB_CNTL)); 839 840 m->sdmax_rlcx_doorbell_offset = 841 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 842 843 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 844 845 m->sdmax_rlcx_skip_cntl = 0; 846 m->sdmax_rlcx_context_status = 0; 847 m->sdmax_rlcx_doorbell_log = 0; 848 849 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 850 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 851 852 m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); 853 m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); 854 855 m->sdmax_rlcx_f32_dbg0 = lower_32_bits(prop->fence_address); 856 m->sdmax_rlcx_f32_dbg1 = upper_32_bits(prop->fence_address); 857 858 return 0; 859 } 860 861 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 862 { 863 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 864 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 865 } 866 867 /** 868 * sdma_v6_0_ring_test_ring - simple async dma engine test 869 * 870 * @ring: amdgpu_ring structure holding ring information 871 * 872 * Test the DMA engine by writing using it to write an 873 * value to memory. 874 * Returns 0 for success, error for failure. 875 */ 876 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 877 { 878 struct amdgpu_device *adev = ring->adev; 879 unsigned i; 880 unsigned index; 881 int r; 882 u32 tmp; 883 u64 gpu_addr; 884 885 tmp = 0xCAFEDEAD; 886 887 r = amdgpu_wb_get(adev, &index); 888 if (r) { 889 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 890 return r; 891 } 892 893 gpu_addr = adev->wb.gpu_addr + (index * 4); 894 adev->wb.wb[index] = cpu_to_le32(tmp); 895 896 r = amdgpu_ring_alloc(ring, 5); 897 if (r) { 898 drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); 899 amdgpu_wb_free(adev, index); 900 return r; 901 } 902 903 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 904 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 905 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 906 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 907 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 908 amdgpu_ring_write(ring, 0xDEADBEEF); 909 amdgpu_ring_commit(ring); 910 911 for (i = 0; i < adev->usec_timeout; i++) { 912 tmp = le32_to_cpu(adev->wb.wb[index]); 913 if (tmp == 0xDEADBEEF) 914 break; 915 if (amdgpu_emu_mode == 1) 916 msleep(1); 917 else 918 udelay(1); 919 } 920 921 if (i >= adev->usec_timeout) 922 r = -ETIMEDOUT; 923 924 amdgpu_wb_free(adev, index); 925 926 return r; 927 } 928 929 /* 930 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 931 * 932 * @ring: amdgpu_ring structure holding ring information 933 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 934 * 935 * Test a simple IB in the DMA ring. 936 * Returns 0 on success, error on failure. 937 */ 938 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 939 { 940 struct amdgpu_device *adev = ring->adev; 941 struct amdgpu_job *job; 942 struct amdgpu_ib *ib; 943 struct dma_fence *f = NULL; 944 unsigned index; 945 long r; 946 u32 tmp = 0; 947 u64 gpu_addr; 948 949 tmp = 0xCAFEDEAD; 950 951 r = amdgpu_wb_get(adev, &index); 952 if (r) { 953 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 954 return r; 955 } 956 957 gpu_addr = adev->wb.gpu_addr + (index * 4); 958 adev->wb.wb[index] = cpu_to_le32(tmp); 959 960 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256, 961 AMDGPU_IB_POOL_DIRECT, 962 AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST, 963 &job); 964 if (r) { 965 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 966 goto err0; 967 } 968 969 ib = &job->ibs[0]; 970 ib->ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 971 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 972 ib->ptr[1] = lower_32_bits(gpu_addr); 973 ib->ptr[2] = upper_32_bits(gpu_addr); 974 ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 975 ib->ptr[4] = 0xDEADBEEF; 976 ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 977 ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 978 ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 979 ib->length_dw = 8; 980 981 r = amdgpu_job_submit_direct(job, ring, &f); 982 if (r) { 983 amdgpu_job_free(job); 984 goto err1; 985 } 986 987 r = dma_fence_wait_timeout(f, false, timeout); 988 if (r == 0) { 989 drm_err(adev_to_drm(adev), "IB test timed out\n"); 990 r = -ETIMEDOUT; 991 goto err1; 992 } else if (r < 0) { 993 drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r); 994 goto err1; 995 } 996 997 tmp = le32_to_cpu(adev->wb.wb[index]); 998 999 if (tmp == 0xDEADBEEF) 1000 r = 0; 1001 else 1002 r = -EINVAL; 1003 1004 err1: 1005 dma_fence_put(f); 1006 err0: 1007 amdgpu_wb_free(adev, index); 1008 return r; 1009 } 1010 1011 1012 /** 1013 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1014 * 1015 * @ib: indirect buffer to fill with commands 1016 * @pe: addr of the page entry 1017 * @src: src addr to copy from 1018 * @count: number of page entries to update 1019 * 1020 * Update PTEs by copying them from the GART using sDMA. 1021 */ 1022 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1023 uint64_t pe, uint64_t src, 1024 unsigned count) 1025 { 1026 unsigned bytes = count * 8; 1027 1028 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1029 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1030 ib->ptr[ib->length_dw++] = bytes - 1; 1031 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1032 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1033 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1034 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1035 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1036 1037 } 1038 1039 /** 1040 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1041 * 1042 * @ib: indirect buffer to fill with commands 1043 * @pe: addr of the page entry 1044 * @value: dst addr to write into pe 1045 * @count: number of page entries to update 1046 * @incr: increase next addr by incr bytes 1047 * 1048 * Update PTEs by writing them manually using sDMA. 1049 */ 1050 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1051 uint64_t value, unsigned count, 1052 uint32_t incr) 1053 { 1054 unsigned ndw = count * 2; 1055 1056 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1057 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1058 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1059 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1060 ib->ptr[ib->length_dw++] = ndw - 1; 1061 for (; ndw > 0; ndw -= 2) { 1062 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1063 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1064 value += incr; 1065 } 1066 } 1067 1068 /** 1069 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1070 * 1071 * @ib: indirect buffer to fill with commands 1072 * @pe: addr of the page entry 1073 * @addr: dst addr to write into pe 1074 * @count: number of page entries to update 1075 * @incr: increase next addr by incr bytes 1076 * @flags: access flags 1077 * 1078 * Update the page tables using sDMA. 1079 */ 1080 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1081 uint64_t pe, 1082 uint64_t addr, unsigned count, 1083 uint32_t incr, uint64_t flags) 1084 { 1085 /* for physically contiguous pages (vram) */ 1086 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1087 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1088 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1089 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1090 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1091 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1092 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1093 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1094 ib->ptr[ib->length_dw++] = 0; 1095 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1096 } 1097 1098 /* 1099 * sdma_v6_0_ring_pad_ib - pad the IB 1100 * @ib: indirect buffer to fill with padding 1101 * @ring: amdgpu ring pointer 1102 * 1103 * Pad the IB with NOPs to a boundary multiple of 8. 1104 */ 1105 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1106 { 1107 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1108 const bool burst_nop = sdma->burst_nop; 1109 u32 pad_count; 1110 int i; 1111 1112 pad_count = (-ib->length_dw) & 0x7; 1113 for (i = 0; i < pad_count; i++) 1114 if (i == 0 && burst_nop) 1115 ib->ptr[ib->length_dw++] = 1116 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1117 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1118 else 1119 ib->ptr[ib->length_dw++] = 1120 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1121 } 1122 1123 /** 1124 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1125 * 1126 * @ring: amdgpu_ring pointer 1127 * 1128 * Make sure all previous operations are completed (CIK). 1129 */ 1130 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1131 { 1132 uint32_t seq = ring->fence_drv.sync_seq; 1133 uint64_t addr = ring->fence_drv.gpu_addr; 1134 1135 /* wait for idle */ 1136 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1137 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1138 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1139 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1140 amdgpu_ring_write(ring, addr & 0xfffffffc); 1141 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1142 amdgpu_ring_write(ring, seq); /* reference */ 1143 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1144 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1145 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1146 } 1147 1148 /* 1149 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1150 * 1151 * @ring: amdgpu_ring pointer 1152 * @vmid: vmid number to use 1153 * @pd_addr: address 1154 * 1155 * Update the page table base and flush the VM TLB 1156 * using sDMA. 1157 */ 1158 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1159 unsigned vmid, uint64_t pd_addr) 1160 { 1161 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1162 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1163 1164 /* Update the PD address for this VMID. */ 1165 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1166 (hub->ctx_addr_distance * vmid), 1167 lower_32_bits(pd_addr)); 1168 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1169 (hub->ctx_addr_distance * vmid), 1170 upper_32_bits(pd_addr)); 1171 1172 /* Trigger invalidation. */ 1173 amdgpu_ring_write(ring, 1174 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1175 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1176 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1177 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1178 amdgpu_ring_write(ring, req); 1179 amdgpu_ring_write(ring, 0xFFFFFFFF); 1180 amdgpu_ring_write(ring, 1181 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1182 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1183 } 1184 1185 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1186 uint32_t reg, uint32_t val) 1187 { 1188 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1189 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1190 amdgpu_ring_write(ring, reg); 1191 amdgpu_ring_write(ring, val); 1192 } 1193 1194 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1195 uint32_t val, uint32_t mask) 1196 { 1197 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1198 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1199 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1200 amdgpu_ring_write(ring, reg << 2); 1201 amdgpu_ring_write(ring, 0); 1202 amdgpu_ring_write(ring, val); /* reference */ 1203 amdgpu_ring_write(ring, mask); /* mask */ 1204 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1205 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1206 } 1207 1208 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1209 uint32_t reg0, uint32_t reg1, 1210 uint32_t ref, uint32_t mask) 1211 { 1212 amdgpu_ring_emit_wreg(ring, reg0, ref); 1213 /* wait for a cycle to reset vm_inv_eng*_ack */ 1214 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1215 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1216 } 1217 1218 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1219 .ras_block = { 1220 .ras_late_init = amdgpu_ras_block_late_init, 1221 }, 1222 }; 1223 1224 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1225 { 1226 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1227 case IP_VERSION(6, 0, 3): 1228 adev->sdma.ras = &sdma_v6_0_3_ras; 1229 break; 1230 default: 1231 break; 1232 } 1233 } 1234 1235 /* all sizes are in bytes */ 1236 #define SDMA6_CSA_SIZE 32 1237 #define SDMA6_CSA_ALIGNMENT 4 1238 1239 static void sdma_v6_0_get_csa_info(struct amdgpu_device *adev, 1240 struct amdgpu_sdma_csa_info *csa_info) 1241 { 1242 csa_info->size = SDMA6_CSA_SIZE; 1243 csa_info->alignment = SDMA6_CSA_ALIGNMENT; 1244 } 1245 1246 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1247 .copy_pte_num_dw = 7, 1248 .copy_pte = sdma_v6_0_vm_copy_pte, 1249 .write_pte = sdma_v6_0_vm_write_pte, 1250 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1251 }; 1252 1253 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) 1254 { 1255 struct amdgpu_device *adev = ip_block->adev; 1256 int r; 1257 1258 switch (amdgpu_user_queue) { 1259 case -1: 1260 case 0: 1261 default: 1262 adev->sdma.no_user_submission = false; 1263 adev->sdma.disable_uq = true; 1264 break; 1265 case 1: 1266 adev->sdma.no_user_submission = false; 1267 adev->sdma.disable_uq = false; 1268 break; 1269 case 2: 1270 adev->sdma.no_user_submission = true; 1271 adev->sdma.disable_uq = false; 1272 break; 1273 } 1274 1275 r = amdgpu_sdma_init_microcode(adev, 0, true); 1276 if (r) 1277 return r; 1278 1279 sdma_v6_0_set_ring_funcs(adev); 1280 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); 1281 sdma_v6_0_set_irq_funcs(adev); 1282 sdma_v6_0_set_mqd_funcs(adev); 1283 sdma_v6_0_set_ras_funcs(adev); 1284 adev->sdma.get_csa_info = &sdma_v6_0_get_csa_info; 1285 1286 return 0; 1287 } 1288 1289 static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 1290 { 1291 struct amdgpu_ring *ring; 1292 int r, i; 1293 struct amdgpu_device *adev = ip_block->adev; 1294 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1295 uint32_t *ptr; 1296 1297 /* SDMA trap event */ 1298 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1299 GFX_11_0_0__SRCID__SDMA_TRAP, 1300 &adev->sdma.trap_irq); 1301 if (r) 1302 return r; 1303 1304 /* SDMA user fence event */ 1305 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1306 GFX_11_0_0__SRCID__SDMA_FENCE, 1307 &adev->sdma.fence_irq); 1308 if (r) 1309 return r; 1310 1311 for (i = 0; i < adev->sdma.num_instances; i++) { 1312 ring = &adev->sdma.instance[i].ring; 1313 ring->use_doorbell = true; 1314 ring->me = i; 1315 ring->no_user_submission = adev->sdma.no_user_submission; 1316 1317 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1318 ring->use_doorbell?"true":"false"); 1319 1320 ring->doorbell_index = 1321 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1322 1323 ring->vm_hub = AMDGPU_GFXHUB(0); 1324 1325 r = amdgpu_sdma_ring_init(adev, ring, i, "sdma%d", i); 1326 if (r) 1327 return r; 1328 } 1329 1330 adev->sdma.supported_reset = 1331 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1332 if (!amdgpu_sriov_vf(adev) && 1333 !adev->debug_disable_gpu_ring_reset) 1334 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1335 1336 if (amdgpu_sdma_ras_sw_init(adev)) { 1337 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1338 return -EINVAL; 1339 } 1340 1341 /* Allocate memory for SDMA IP Dump buffer */ 1342 ptr = kzalloc_objs(*ptr, adev->sdma.num_instances * reg_count); 1343 if (ptr) 1344 adev->sdma.ip_dump = ptr; 1345 else 1346 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1347 1348 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1349 case IP_VERSION(6, 0, 0): 1350 if ((adev->sdma.instance[0].fw_version >= 27) && !adev->sdma.disable_uq) 1351 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1352 break; 1353 case IP_VERSION(6, 0, 1): 1354 if ((adev->sdma.instance[0].fw_version >= 18) && !adev->sdma.disable_uq) 1355 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1356 break; 1357 case IP_VERSION(6, 0, 2): 1358 if ((adev->sdma.instance[0].fw_version >= 23) && !adev->sdma.disable_uq) 1359 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1360 break; 1361 case IP_VERSION(6, 0, 3): 1362 if (adev->sdma.instance[0].fw_version >= 29 && !adev->sdma.disable_uq) 1363 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1364 break; 1365 case IP_VERSION(6, 1, 0): 1366 if ((adev->sdma.instance[0].fw_version >= 14) && !adev->sdma.disable_uq) 1367 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1368 break; 1369 case IP_VERSION(6, 1, 1): 1370 if ((adev->sdma.instance[0].fw_version >= 17) && !adev->sdma.disable_uq) 1371 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1372 break; 1373 case IP_VERSION(6, 1, 2): 1374 if ((adev->sdma.instance[0].fw_version >= 15) && !adev->sdma.disable_uq) 1375 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1376 break; 1377 case IP_VERSION(6, 1, 3): 1378 if ((adev->sdma.instance[0].fw_version >= 10) && !adev->sdma.disable_uq) 1379 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1380 break; 1381 default: 1382 break; 1383 } 1384 1385 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1386 if (r) 1387 return r; 1388 1389 return r; 1390 } 1391 1392 static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 1393 { 1394 struct amdgpu_device *adev = ip_block->adev; 1395 int i; 1396 1397 for (i = 0; i < adev->sdma.num_instances; i++) 1398 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1399 1400 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1401 amdgpu_sdma_destroy_inst_ctx(adev, true); 1402 1403 kfree(adev->sdma.ip_dump); 1404 1405 return 0; 1406 } 1407 1408 static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev, 1409 bool enable) 1410 { 1411 unsigned int irq_type; 1412 int i, r; 1413 1414 if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) { 1415 for (i = 0; i < adev->sdma.num_instances; i++) { 1416 irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i; 1417 if (enable) 1418 r = amdgpu_irq_get(adev, &adev->sdma.trap_irq, 1419 irq_type); 1420 else 1421 r = amdgpu_irq_put(adev, &adev->sdma.trap_irq, 1422 irq_type); 1423 if (r) 1424 return r; 1425 } 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 1432 { 1433 struct amdgpu_device *adev = ip_block->adev; 1434 int r; 1435 1436 r = sdma_v6_0_start(adev); 1437 if (r) 1438 return r; 1439 sdma_v6_0_set_buffer_funcs(adev); 1440 1441 return sdma_v6_0_set_userq_trap_interrupts(adev, true); 1442 } 1443 1444 static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 1445 { 1446 struct amdgpu_device *adev = ip_block->adev; 1447 1448 if (amdgpu_sriov_vf(adev)) 1449 return 0; 1450 1451 sdma_v6_0_ctxempty_int_enable(adev, false); 1452 sdma_v6_0_enable(adev, false); 1453 sdma_v6_0_set_userq_trap_interrupts(adev, false); 1454 1455 return 0; 1456 } 1457 1458 static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) 1459 { 1460 return sdma_v6_0_hw_fini(ip_block); 1461 } 1462 1463 static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) 1464 { 1465 return sdma_v6_0_hw_init(ip_block); 1466 } 1467 1468 static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1469 { 1470 unsigned i; 1471 u32 sdma0, sdma1; 1472 struct amdgpu_device *adev = ip_block->adev; 1473 1474 for (i = 0; i < adev->usec_timeout; i++) { 1475 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1476 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1477 1478 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1479 return 0; 1480 udelay(1); 1481 } 1482 return -ETIMEDOUT; 1483 } 1484 1485 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1486 { 1487 int i, r = 0; 1488 struct amdgpu_device *adev = ring->adev; 1489 u64 sdma_gfx_preempt; 1490 1491 sdma_gfx_preempt = sdma_v6_0_get_reg_offset(adev, ring->me, 1492 regSDMA0_QUEUE0_PREEMPT); 1493 1494 /* assert preemption condition */ 1495 amdgpu_ring_set_preempt_cond_exec(ring, false); 1496 1497 /* emit the trailing fence */ 1498 ring->trail_seq += 1; 1499 amdgpu_ring_alloc(ring, 10); 1500 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1501 ring->trail_seq, 0); 1502 amdgpu_ring_commit(ring); 1503 1504 /* assert IB preemption */ 1505 WREG32(sdma_gfx_preempt, 1); 1506 1507 /* poll the trailing fence */ 1508 for (i = 0; i < adev->usec_timeout; i++) { 1509 if (ring->trail_seq == 1510 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1511 break; 1512 udelay(1); 1513 } 1514 1515 if (i >= adev->usec_timeout) { 1516 r = -EINVAL; 1517 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1518 } 1519 1520 /* deassert IB preemption */ 1521 WREG32(sdma_gfx_preempt, 0); 1522 1523 /* deassert the preemption condition */ 1524 amdgpu_ring_set_preempt_cond_exec(ring, true); 1525 return r; 1526 } 1527 1528 /* dword stride between adjacent per-queue register banks */ 1529 #define SDMA_V6_0_QUEUE_REG_STRIDE \ 1530 (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL) 1531 1532 /* find the HW slot (instance, queue_id) whose doorbell matches doorbell_index */ 1533 static bool sdma_v6_0_detect_hung_queue(struct amdgpu_device *adev, 1534 u32 doorbell_index, 1535 u32 *instance_id, u32 *queue_id) 1536 { 1537 u32 i, q, reg, dboff; 1538 1539 for (i = 0; i < adev->sdma.num_instances; i++) { 1540 for (q = 0; q < 8; q++) { 1541 reg = sdma_v6_0_get_reg_offset(adev, i, 1542 regSDMA0_QUEUE0_DOORBELL_OFFSET + 1543 q * SDMA_V6_0_QUEUE_REG_STRIDE); 1544 dboff = (RREG32(reg) & 1545 SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK) >> 2; 1546 if (dboff == doorbell_index) { 1547 *instance_id = i; 1548 *queue_id = q; 1549 return true; 1550 } 1551 } 1552 } 1553 return false; 1554 } 1555 1556 static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, 1557 unsigned int vmid, 1558 struct amdgpu_fence *timedout_fence) 1559 { 1560 struct amdgpu_device *adev = ring->adev; 1561 int r; 1562 1563 if (ring->me >= adev->sdma.num_instances) { 1564 dev_err(adev->dev, "sdma instance not found\n"); 1565 return -EINVAL; 1566 } 1567 1568 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1569 1570 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); 1571 if (r) 1572 return r; 1573 1574 r = sdma_v6_0_gfx_resume_instance(adev, ring->me, true); 1575 if (r) 1576 return r; 1577 1578 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1579 } 1580 1581 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1582 struct amdgpu_irq_src *source, 1583 unsigned type, 1584 enum amdgpu_interrupt_state state) 1585 { 1586 u32 sdma_cntl; 1587 1588 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1589 1590 if (!amdgpu_sriov_vf(adev)) { 1591 sdma_cntl = RREG32(reg_offset); 1592 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1593 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1594 WREG32(reg_offset, sdma_cntl); 1595 } 1596 1597 return 0; 1598 } 1599 1600 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1601 struct amdgpu_irq_src *source, 1602 struct amdgpu_iv_entry *entry) 1603 { 1604 int instances, queue; 1605 1606 DRM_DEBUG("IH: SDMA trap\n"); 1607 1608 queue = entry->ring_id & 0xf; 1609 instances = (entry->ring_id & 0xf0) >> 4; 1610 if (instances > 1) { 1611 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1612 return -EINVAL; 1613 } 1614 1615 switch (entry->client_id) { 1616 case SOC21_IH_CLIENTID_GFX: 1617 switch (queue) { 1618 case 0: 1619 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1620 break; 1621 default: 1622 break; 1623 } 1624 break; 1625 } 1626 return 0; 1627 } 1628 1629 static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, 1630 struct amdgpu_irq_src *source, 1631 struct amdgpu_iv_entry *entry) 1632 { 1633 u32 doorbell_offset = entry->src_data[0]; 1634 1635 if (adev->enable_mes && doorbell_offset) { 1636 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1637 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 1638 } 1639 1640 return 0; 1641 } 1642 1643 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1644 struct amdgpu_irq_src *source, 1645 struct amdgpu_iv_entry *entry) 1646 { 1647 return 0; 1648 } 1649 1650 static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1651 enum amd_clockgating_state state) 1652 { 1653 return 0; 1654 } 1655 1656 static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1657 enum amd_powergating_state state) 1658 { 1659 return 0; 1660 } 1661 1662 static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1663 { 1664 } 1665 1666 static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1667 { 1668 struct amdgpu_device *adev = ip_block->adev; 1669 int i, j; 1670 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1671 uint32_t instance_offset; 1672 1673 if (!adev->sdma.ip_dump) 1674 return; 1675 1676 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1677 for (i = 0; i < adev->sdma.num_instances; i++) { 1678 instance_offset = i * reg_count; 1679 drm_printf(p, "\nInstance:%d\n", i); 1680 1681 for (j = 0; j < reg_count; j++) 1682 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name, 1683 adev->sdma.ip_dump[instance_offset + j]); 1684 } 1685 } 1686 1687 static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1688 { 1689 struct amdgpu_device *adev = ip_block->adev; 1690 int i, j; 1691 uint32_t instance_offset; 1692 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1693 1694 if (!adev->sdma.ip_dump) 1695 return; 1696 1697 amdgpu_gfx_off_ctrl(adev, false); 1698 for (i = 0; i < adev->sdma.num_instances; i++) { 1699 instance_offset = i * reg_count; 1700 for (j = 0; j < reg_count; j++) 1701 adev->sdma.ip_dump[instance_offset + j] = 1702 RREG32(sdma_v6_0_get_reg_offset(adev, i, 1703 sdma_reg_list_6_0[j].reg_offset)); 1704 } 1705 amdgpu_gfx_off_ctrl(adev, true); 1706 } 1707 1708 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1709 .name = "sdma_v6_0", 1710 .early_init = sdma_v6_0_early_init, 1711 .sw_init = sdma_v6_0_sw_init, 1712 .sw_fini = sdma_v6_0_sw_fini, 1713 .hw_init = sdma_v6_0_hw_init, 1714 .hw_fini = sdma_v6_0_hw_fini, 1715 .suspend = sdma_v6_0_suspend, 1716 .resume = sdma_v6_0_resume, 1717 .wait_for_idle = sdma_v6_0_wait_for_idle, 1718 .soft_reset = sdma_v6_0_soft_reset, 1719 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1720 .set_powergating_state = sdma_v6_0_set_powergating_state, 1721 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1722 .dump_ip_state = sdma_v6_0_dump_ip_state, 1723 .print_ip_state = sdma_v6_0_print_ip_state, 1724 }; 1725 1726 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1727 .type = AMDGPU_RING_TYPE_SDMA, 1728 .align_mask = 0xf, 1729 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1730 .support_64bit_ptrs = true, 1731 .secure_submission_supported = true, 1732 .get_rptr = sdma_v6_0_ring_get_rptr, 1733 .get_wptr = sdma_v6_0_ring_get_wptr, 1734 .set_wptr = sdma_v6_0_ring_set_wptr, 1735 .emit_frame_size = 1736 5 + /* sdma_v6_0_ring_init_cond_exec */ 1737 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1738 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1739 /* sdma_v6_0_ring_emit_vm_flush */ 1740 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1741 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1742 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1743 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1744 .emit_ib = sdma_v6_0_ring_emit_ib, 1745 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1746 .emit_fence = sdma_v6_0_ring_emit_fence, 1747 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1748 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1749 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1750 .test_ring = sdma_v6_0_ring_test_ring, 1751 .test_ib = sdma_v6_0_ring_test_ib, 1752 .insert_nop = sdma_v6_0_ring_insert_nop, 1753 .pad_ib = sdma_v6_0_ring_pad_ib, 1754 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1755 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1756 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1757 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1758 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1759 .reset = sdma_v6_0_reset_queue, 1760 }; 1761 1762 static const struct amdgpu_sdma_funcs sdma_v6_0_sdma_funcs = { 1763 .detect_hung_queue = sdma_v6_0_detect_hung_queue, 1764 }; 1765 1766 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1767 { 1768 int i; 1769 1770 for (i = 0; i < adev->sdma.num_instances; i++) { 1771 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1772 adev->sdma.instance[i].ring.me = i; 1773 adev->sdma.instance[i].funcs = &sdma_v6_0_sdma_funcs; 1774 } 1775 } 1776 1777 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1778 .set = sdma_v6_0_set_trap_irq_state, 1779 .process = sdma_v6_0_process_trap_irq, 1780 }; 1781 1782 static const struct amdgpu_irq_src_funcs sdma_v6_0_fence_irq_funcs = { 1783 .process = sdma_v6_0_process_fence_irq, 1784 }; 1785 1786 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1787 .process = sdma_v6_0_process_illegal_inst_irq, 1788 }; 1789 1790 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1791 { 1792 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1793 adev->sdma.num_instances; 1794 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1795 adev->sdma.fence_irq.funcs = &sdma_v6_0_fence_irq_funcs; 1796 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1797 } 1798 1799 /** 1800 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1801 * 1802 * @ib: indirect buffer to fill with commands 1803 * @src_offset: src GPU address 1804 * @dst_offset: dst GPU address 1805 * @byte_count: number of bytes to xfer 1806 * @copy_flags: copy flags for the buffers 1807 * 1808 * Copy GPU buffers using the DMA engine. 1809 * Used by the amdgpu ttm implementation to move pages if 1810 * registered as the asic copy callback. 1811 */ 1812 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1813 uint64_t src_offset, 1814 uint64_t dst_offset, 1815 uint32_t byte_count, 1816 uint32_t copy_flags) 1817 { 1818 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1819 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1820 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1821 ib->ptr[ib->length_dw++] = byte_count - 1; 1822 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1823 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1824 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1825 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1826 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1827 } 1828 1829 /** 1830 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1831 * 1832 * @ib: indirect buffer to fill 1833 * @src_data: value to write to buffer 1834 * @dst_offset: dst GPU address 1835 * @byte_count: number of bytes to xfer 1836 * 1837 * Fill GPU buffers using the DMA engine. 1838 */ 1839 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1840 uint32_t src_data, 1841 uint64_t dst_offset, 1842 uint32_t byte_count) 1843 { 1844 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL); 1845 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1846 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1847 ib->ptr[ib->length_dw++] = src_data; 1848 ib->ptr[ib->length_dw++] = byte_count - 1; 1849 } 1850 1851 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1852 .copy_max_bytes = 1 << 30, 1853 .copy_num_dw = 7, 1854 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1855 1856 .fill_max_bytes = 1 << 30, 1857 .fill_num_dw = 5, 1858 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1859 }; 1860 1861 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1862 { 1863 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v6_0_buffer_funcs); 1864 } 1865 1866 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1867 .type = AMD_IP_BLOCK_TYPE_SDMA, 1868 .major = 6, 1869 .minor = 0, 1870 .rev = 0, 1871 .funcs = &sdma_v6_0_ip_funcs, 1872 }; 1873