1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 #include "amdgpu_reset.h" 34 #include "gc/gc_9_0_sh_mask.h" 35 36 #include "sdma/sdma_4_4_2_offset.h" 37 #include "sdma/sdma_4_4_2_sh_mask.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "vega10_sdma_pkt_open.h" 42 43 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 44 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 45 46 #include "amdgpu_ras.h" 47 48 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 50 51 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 96 }; 97 98 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 99 100 #define WREG32_SDMA(instance, offset, value) \ 101 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 102 #define RREG32_SDMA(instance, offset) \ 103 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 104 105 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 108 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 109 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 110 static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev); 111 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 112 113 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 114 u32 instance, u32 offset) 115 { 116 u32 dev_inst = GET_INST(SDMA0, instance); 117 118 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 119 } 120 121 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 122 { 123 switch (seq_num) { 124 case 0: 125 return SOC15_IH_CLIENTID_SDMA0; 126 case 1: 127 return SOC15_IH_CLIENTID_SDMA1; 128 case 2: 129 return SOC15_IH_CLIENTID_SDMA2; 130 case 3: 131 return SOC15_IH_CLIENTID_SDMA3; 132 default: 133 return -EINVAL; 134 } 135 } 136 137 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 138 { 139 switch (client_id) { 140 case SOC15_IH_CLIENTID_SDMA0: 141 return 0; 142 case SOC15_IH_CLIENTID_SDMA1: 143 return 1; 144 case SOC15_IH_CLIENTID_SDMA2: 145 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 146 return 0; 147 else 148 return 2; 149 case SOC15_IH_CLIENTID_SDMA3: 150 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 151 return 1; 152 else 153 return 3; 154 default: 155 return -EINVAL; 156 } 157 } 158 159 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 160 uint32_t inst_mask) 161 { 162 u32 val; 163 int i; 164 165 for (i = 0; i < adev->sdma.num_instances; i++) { 166 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 167 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 168 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 169 PIPE_INTERLEAVE_SIZE, 0); 170 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 171 172 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 173 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 174 4); 175 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 176 PIPE_INTERLEAVE_SIZE, 0); 177 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 178 } 179 } 180 181 /** 182 * sdma_v4_4_2_init_microcode - load ucode images from disk 183 * 184 * @adev: amdgpu_device pointer 185 * 186 * Use the firmware interface to load the ucode images into 187 * the driver (not loaded into hw). 188 * Returns 0 on success, error on failure. 189 */ 190 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 191 { 192 int ret, i; 193 194 for (i = 0; i < adev->sdma.num_instances; i++) { 195 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 196 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 197 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 198 ret = amdgpu_sdma_init_microcode(adev, 0, true); 199 break; 200 } else { 201 ret = amdgpu_sdma_init_microcode(adev, i, false); 202 if (ret) 203 return ret; 204 } 205 } 206 207 return ret; 208 } 209 210 /** 211 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 212 * 213 * @ring: amdgpu ring pointer 214 * 215 * Get the current rptr from the hardware. 216 */ 217 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 218 { 219 u64 rptr; 220 221 /* XXX check if swapping is necessary on BE */ 222 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 223 224 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 225 return rptr >> 2; 226 } 227 228 /** 229 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 230 * 231 * @ring: amdgpu ring pointer 232 * 233 * Get the current wptr from the hardware. 234 */ 235 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 236 { 237 struct amdgpu_device *adev = ring->adev; 238 u64 wptr; 239 240 if (ring->use_doorbell) { 241 /* XXX check if swapping is necessary on BE */ 242 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 243 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 244 } else { 245 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 246 wptr = wptr << 32; 247 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 248 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 249 ring->me, wptr); 250 } 251 252 return wptr >> 2; 253 } 254 255 /** 256 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 257 * 258 * @ring: amdgpu ring pointer 259 * 260 * Write the wptr back to the hardware. 261 */ 262 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 263 { 264 struct amdgpu_device *adev = ring->adev; 265 266 DRM_DEBUG("Setting write pointer\n"); 267 if (ring->use_doorbell) { 268 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 269 270 DRM_DEBUG("Using doorbell -- " 271 "wptr_offs == 0x%08x " 272 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 273 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 274 ring->wptr_offs, 275 lower_32_bits(ring->wptr << 2), 276 upper_32_bits(ring->wptr << 2)); 277 /* XXX check if swapping is necessary on BE */ 278 WRITE_ONCE(*wb, (ring->wptr << 2)); 279 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 280 ring->doorbell_index, ring->wptr << 2); 281 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 282 } else { 283 DRM_DEBUG("Not using doorbell -- " 284 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 285 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 286 ring->me, 287 lower_32_bits(ring->wptr << 2), 288 ring->me, 289 upper_32_bits(ring->wptr << 2)); 290 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 291 lower_32_bits(ring->wptr << 2)); 292 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 293 upper_32_bits(ring->wptr << 2)); 294 } 295 } 296 297 /** 298 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 299 * 300 * @ring: amdgpu ring pointer 301 * 302 * Get the current wptr from the hardware. 303 */ 304 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 305 { 306 struct amdgpu_device *adev = ring->adev; 307 u64 wptr; 308 309 if (ring->use_doorbell) { 310 /* XXX check if swapping is necessary on BE */ 311 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 312 } else { 313 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 314 wptr = wptr << 32; 315 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 316 } 317 318 return wptr >> 2; 319 } 320 321 /** 322 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 323 * 324 * @ring: amdgpu ring pointer 325 * 326 * Write the wptr back to the hardware. 327 */ 328 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 329 { 330 struct amdgpu_device *adev = ring->adev; 331 332 if (ring->use_doorbell) { 333 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 334 335 /* XXX check if swapping is necessary on BE */ 336 WRITE_ONCE(*wb, (ring->wptr << 2)); 337 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 338 } else { 339 uint64_t wptr = ring->wptr << 2; 340 341 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 342 lower_32_bits(wptr)); 343 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 344 upper_32_bits(wptr)); 345 } 346 } 347 348 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 349 { 350 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 351 int i; 352 353 for (i = 0; i < count; i++) 354 if (sdma && sdma->burst_nop && (i == 0)) 355 amdgpu_ring_write(ring, ring->funcs->nop | 356 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 357 else 358 amdgpu_ring_write(ring, ring->funcs->nop); 359 } 360 361 /** 362 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 363 * 364 * @ring: amdgpu ring pointer 365 * @job: job to retrieve vmid from 366 * @ib: IB object to schedule 367 * @flags: unused 368 * 369 * Schedule an IB in the DMA ring. 370 */ 371 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 372 struct amdgpu_job *job, 373 struct amdgpu_ib *ib, 374 uint32_t flags) 375 { 376 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 377 378 /* IB packet must end on a 8 DW boundary */ 379 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 380 381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 382 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 383 /* base must be 32 byte aligned */ 384 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 385 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 386 amdgpu_ring_write(ring, ib->length_dw); 387 amdgpu_ring_write(ring, 0); 388 amdgpu_ring_write(ring, 0); 389 390 } 391 392 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 393 int mem_space, int hdp, 394 uint32_t addr0, uint32_t addr1, 395 uint32_t ref, uint32_t mask, 396 uint32_t inv) 397 { 398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 399 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 400 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 401 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 402 if (mem_space) { 403 /* memory */ 404 amdgpu_ring_write(ring, addr0); 405 amdgpu_ring_write(ring, addr1); 406 } else { 407 /* registers */ 408 amdgpu_ring_write(ring, addr0 << 2); 409 amdgpu_ring_write(ring, addr1 << 2); 410 } 411 amdgpu_ring_write(ring, ref); /* reference */ 412 amdgpu_ring_write(ring, mask); /* mask */ 413 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 414 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 415 } 416 417 /** 418 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 419 * 420 * @ring: amdgpu ring pointer 421 * 422 * Emit an hdp flush packet on the requested DMA ring. 423 */ 424 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 425 { 426 struct amdgpu_device *adev = ring->adev; 427 u32 ref_and_mask = 0; 428 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 429 430 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 431 << (ring->me % adev->sdma.num_inst_per_aid); 432 433 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 434 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 435 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 436 ref_and_mask, ref_and_mask, 10); 437 } 438 439 /** 440 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 441 * 442 * @ring: amdgpu ring pointer 443 * @addr: address 444 * @seq: sequence number 445 * @flags: fence related flags 446 * 447 * Add a DMA fence packet to the ring to write 448 * the fence seq number and DMA trap packet to generate 449 * an interrupt if needed. 450 */ 451 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 452 unsigned flags) 453 { 454 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 455 /* write the fence */ 456 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 457 /* zero in first two bits */ 458 BUG_ON(addr & 0x3); 459 amdgpu_ring_write(ring, lower_32_bits(addr)); 460 amdgpu_ring_write(ring, upper_32_bits(addr)); 461 amdgpu_ring_write(ring, lower_32_bits(seq)); 462 463 /* optionally write high bits as well */ 464 if (write64bit) { 465 addr += 4; 466 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 467 /* zero in first two bits */ 468 BUG_ON(addr & 0x3); 469 amdgpu_ring_write(ring, lower_32_bits(addr)); 470 amdgpu_ring_write(ring, upper_32_bits(addr)); 471 amdgpu_ring_write(ring, upper_32_bits(seq)); 472 } 473 474 /* generate an interrupt */ 475 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 476 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 477 } 478 479 480 /** 481 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 482 * 483 * @adev: amdgpu_device pointer 484 * @inst_mask: mask of dma engine instances to be disabled 485 * 486 * Stop the gfx async dma ring buffers. 487 */ 488 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 489 uint32_t inst_mask) 490 { 491 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 492 u32 doorbell_offset, doorbell; 493 u32 rb_cntl, ib_cntl; 494 int i; 495 496 for_each_inst(i, inst_mask) { 497 sdma[i] = &adev->sdma.instance[i].ring; 498 499 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 501 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 502 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 503 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 504 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 505 506 if (sdma[i]->use_doorbell) { 507 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 508 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 509 510 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 511 doorbell_offset = REG_SET_FIELD(doorbell_offset, 512 SDMA_GFX_DOORBELL_OFFSET, 513 OFFSET, 0); 514 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 515 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 516 } 517 } 518 } 519 520 /** 521 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 522 * 523 * @adev: amdgpu_device pointer 524 * @inst_mask: mask of dma engine instances to be disabled 525 * 526 * Stop the compute async dma queues. 527 */ 528 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 529 uint32_t inst_mask) 530 { 531 /* XXX todo */ 532 } 533 534 /** 535 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 536 * 537 * @adev: amdgpu_device pointer 538 * @inst_mask: mask of dma engine instances to be disabled 539 * 540 * Stop the page async dma ring buffers. 541 */ 542 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 543 uint32_t inst_mask) 544 { 545 u32 rb_cntl, ib_cntl; 546 int i; 547 548 for_each_inst(i, inst_mask) { 549 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 550 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 551 RB_ENABLE, 0); 552 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 553 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 554 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 555 IB_ENABLE, 0); 556 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 557 } 558 } 559 560 /** 561 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 562 * 563 * @adev: amdgpu_device pointer 564 * @enable: enable/disable the DMA MEs context switch. 565 * @inst_mask: mask of dma engine instances to be enabled 566 * 567 * Halt or unhalt the async dma engines context switch. 568 */ 569 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 570 bool enable, uint32_t inst_mask) 571 { 572 u32 f32_cntl, phase_quantum = 0; 573 int i; 574 575 if (amdgpu_sdma_phase_quantum) { 576 unsigned value = amdgpu_sdma_phase_quantum; 577 unsigned unit = 0; 578 579 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 580 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 581 value = (value + 1) >> 1; 582 unit++; 583 } 584 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 585 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 586 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 587 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 588 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 589 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 590 WARN_ONCE(1, 591 "clamping sdma_phase_quantum to %uK clock cycles\n", 592 value << unit); 593 } 594 phase_quantum = 595 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 596 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 597 } 598 599 for_each_inst(i, inst_mask) { 600 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 601 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 602 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 603 if (enable && amdgpu_sdma_phase_quantum) { 604 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 605 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 606 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 607 } 608 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 609 610 /* Extend page fault timeout to avoid interrupt storm */ 611 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 612 } 613 } 614 615 /** 616 * sdma_v4_4_2_inst_enable - stop the async dma engines 617 * 618 * @adev: amdgpu_device pointer 619 * @enable: enable/disable the DMA MEs. 620 * @inst_mask: mask of dma engine instances to be enabled 621 * 622 * Halt or unhalt the async dma engines. 623 */ 624 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 625 uint32_t inst_mask) 626 { 627 u32 f32_cntl; 628 int i; 629 630 if (!enable) { 631 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 632 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 633 if (adev->sdma.has_page_queue) 634 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 635 636 /* SDMA FW needs to respond to FREEZE requests during reset. 637 * Keep it running during reset */ 638 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 639 return; 640 } 641 642 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 643 return; 644 645 for_each_inst(i, inst_mask) { 646 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 647 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 648 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 649 } 650 } 651 652 /* 653 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 654 */ 655 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 656 { 657 /* Set ring buffer size in dwords */ 658 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 659 660 barrier(); /* work around https://llvm.org/pr42576 */ 661 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 662 #ifdef __BIG_ENDIAN 663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 665 RPTR_WRITEBACK_SWAP_ENABLE, 1); 666 #endif 667 return rb_cntl; 668 } 669 670 /** 671 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 672 * 673 * @adev: amdgpu_device pointer 674 * @i: instance to resume 675 * @restore: used to restore wptr when restart 676 * 677 * Set up the gfx DMA ring buffers and enable them. 678 * Returns 0 for success, error for failure. 679 */ 680 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 681 { 682 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 683 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 684 u32 wb_offset; 685 u32 doorbell; 686 u32 doorbell_offset; 687 u64 wptr_gpu_addr; 688 u64 rwptr; 689 690 wb_offset = (ring->rptr_offs * 4); 691 692 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 693 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 694 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 695 696 /* set the wb address whether it's enabled or not */ 697 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 698 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 699 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 700 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 701 702 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 703 RPTR_WRITEBACK_ENABLE, 1); 704 705 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 706 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 707 708 if (!restore) 709 ring->wptr = 0; 710 711 /* before programing wptr to a less value, need set minor_ptr_update first */ 712 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 713 714 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 715 * It is not a guilty queue, restore cache_rptr and continue execution. 716 */ 717 if (adev->sdma.instance[i].gfx_guilty) 718 rwptr = ring->wptr; 719 else 720 rwptr = ring->cached_rptr; 721 722 /* Initialize the ring buffer's read and write pointers */ 723 if (restore) { 724 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2)); 725 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 726 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2)); 727 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 728 } else { 729 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 730 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 731 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 732 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 733 } 734 735 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 736 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 737 738 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 739 ring->use_doorbell); 740 doorbell_offset = REG_SET_FIELD(doorbell_offset, 741 SDMA_GFX_DOORBELL_OFFSET, 742 OFFSET, ring->doorbell_index); 743 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 744 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 745 746 sdma_v4_4_2_ring_set_wptr(ring); 747 748 /* set minor_ptr_update to 0 after wptr programed */ 749 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 750 751 /* setup the wptr shadow polling */ 752 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 753 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 754 lower_32_bits(wptr_gpu_addr)); 755 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 756 upper_32_bits(wptr_gpu_addr)); 757 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 758 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 759 SDMA_GFX_RB_WPTR_POLL_CNTL, 760 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 761 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 762 763 /* enable DMA RB */ 764 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 765 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 766 767 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 768 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 769 #ifdef __BIG_ENDIAN 770 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 771 #endif 772 /* enable DMA IBs */ 773 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 774 } 775 776 /** 777 * sdma_v4_4_2_page_resume - setup and start the async dma engines 778 * 779 * @adev: amdgpu_device pointer 780 * @i: instance to resume 781 * @restore: boolean to say restore needed or not 782 * 783 * Set up the page DMA ring buffers and enable them. 784 * Returns 0 for success, error for failure. 785 */ 786 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 787 { 788 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 789 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 790 u32 wb_offset; 791 u32 doorbell; 792 u32 doorbell_offset; 793 u64 wptr_gpu_addr; 794 u64 rwptr; 795 796 wb_offset = (ring->rptr_offs * 4); 797 798 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 799 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 800 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 801 802 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 803 * It is not a guilty queue, restore cache_rptr and continue execution. 804 */ 805 if (adev->sdma.instance[i].page_guilty) 806 rwptr = ring->wptr; 807 else 808 rwptr = ring->cached_rptr; 809 810 /* Initialize the ring buffer's read and write pointers */ 811 if (restore) { 812 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2)); 813 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 814 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2)); 815 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 816 } else { 817 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 818 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 819 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 820 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 821 } 822 823 /* set the wb address whether it's enabled or not */ 824 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 825 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 826 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 827 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 828 829 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 830 RPTR_WRITEBACK_ENABLE, 1); 831 832 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 833 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 834 835 if (!restore) 836 ring->wptr = 0; 837 838 /* before programing wptr to a less value, need set minor_ptr_update first */ 839 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 840 841 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 842 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 843 844 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 845 ring->use_doorbell); 846 doorbell_offset = REG_SET_FIELD(doorbell_offset, 847 SDMA_PAGE_DOORBELL_OFFSET, 848 OFFSET, ring->doorbell_index); 849 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 850 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 851 852 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 853 sdma_v4_4_2_page_ring_set_wptr(ring); 854 855 /* set minor_ptr_update to 0 after wptr programed */ 856 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 857 858 /* setup the wptr shadow polling */ 859 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 860 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 861 lower_32_bits(wptr_gpu_addr)); 862 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 863 upper_32_bits(wptr_gpu_addr)); 864 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 865 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 866 SDMA_PAGE_RB_WPTR_POLL_CNTL, 867 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 868 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 869 870 /* enable DMA RB */ 871 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 872 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 873 874 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 875 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 876 #ifdef __BIG_ENDIAN 877 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 878 #endif 879 /* enable DMA IBs */ 880 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 881 } 882 883 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 884 { 885 886 } 887 888 /** 889 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 890 * 891 * @adev: amdgpu_device pointer 892 * @inst_mask: mask of dma engine instances to be enabled 893 * 894 * Set up the compute DMA queues and enable them. 895 * Returns 0 for success, error for failure. 896 */ 897 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 898 uint32_t inst_mask) 899 { 900 sdma_v4_4_2_init_pg(adev); 901 902 return 0; 903 } 904 905 /** 906 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 907 * 908 * @adev: amdgpu_device pointer 909 * @inst_mask: mask of dma engine instances to be enabled 910 * 911 * Loads the sDMA0/1 ucode. 912 * Returns 0 for success, -EINVAL if the ucode is not available. 913 */ 914 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 915 uint32_t inst_mask) 916 { 917 const struct sdma_firmware_header_v1_0 *hdr; 918 const __le32 *fw_data; 919 u32 fw_size; 920 int i, j; 921 922 /* halt the MEs */ 923 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 924 925 for_each_inst(i, inst_mask) { 926 if (!adev->sdma.instance[i].fw) 927 return -EINVAL; 928 929 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 930 amdgpu_ucode_print_sdma_hdr(&hdr->header); 931 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 932 933 fw_data = (const __le32 *) 934 (adev->sdma.instance[i].fw->data + 935 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 936 937 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 938 939 for (j = 0; j < fw_size; j++) 940 WREG32_SDMA(i, regSDMA_UCODE_DATA, 941 le32_to_cpup(fw_data++)); 942 943 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 944 adev->sdma.instance[i].fw_version); 945 } 946 947 return 0; 948 } 949 950 /** 951 * sdma_v4_4_2_inst_start - setup and start the async dma engines 952 * 953 * @adev: amdgpu_device pointer 954 * @inst_mask: mask of dma engine instances to be enabled 955 * @restore: boolean to say restore needed or not 956 * 957 * Set up the DMA engines and enable them. 958 * Returns 0 for success, error for failure. 959 */ 960 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 961 uint32_t inst_mask, bool restore) 962 { 963 struct amdgpu_ring *ring; 964 uint32_t tmp_mask; 965 int i, r = 0; 966 967 if (amdgpu_sriov_vf(adev)) { 968 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 969 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 970 } else { 971 /* bypass sdma microcode loading on Gopher */ 972 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 973 adev->sdma.instance[0].fw) { 974 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 975 if (r) 976 return r; 977 } 978 979 /* unhalt the MEs */ 980 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 981 /* enable sdma ring preemption */ 982 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 983 } 984 985 /* start the gfx rings and rlc compute queues */ 986 tmp_mask = inst_mask; 987 for_each_inst(i, tmp_mask) { 988 uint32_t temp; 989 990 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 991 sdma_v4_4_2_gfx_resume(adev, i, restore); 992 if (adev->sdma.has_page_queue) 993 sdma_v4_4_2_page_resume(adev, i, restore); 994 995 /* set utc l1 enable flag always to 1 */ 996 temp = RREG32_SDMA(i, regSDMA_CNTL); 997 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 998 999 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 1000 /* enable context empty interrupt during initialization */ 1001 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 1002 WREG32_SDMA(i, regSDMA_CNTL, temp); 1003 } 1004 if (!amdgpu_sriov_vf(adev)) { 1005 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1006 /* unhalt engine */ 1007 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 1008 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 1009 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 1010 } 1011 } 1012 } 1013 1014 if (amdgpu_sriov_vf(adev)) { 1015 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 1016 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 1017 } else { 1018 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 1019 if (r) 1020 return r; 1021 } 1022 1023 tmp_mask = inst_mask; 1024 for_each_inst(i, tmp_mask) { 1025 ring = &adev->sdma.instance[i].ring; 1026 1027 r = amdgpu_ring_test_helper(ring); 1028 if (r) 1029 return r; 1030 1031 if (adev->sdma.has_page_queue) { 1032 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1033 1034 r = amdgpu_ring_test_helper(page); 1035 if (r) 1036 return r; 1037 } 1038 } 1039 1040 return r; 1041 } 1042 1043 /** 1044 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1045 * 1046 * @ring: amdgpu_ring structure holding ring information 1047 * 1048 * Test the DMA engine by writing using it to write an 1049 * value to memory. 1050 * Returns 0 for success, error for failure. 1051 */ 1052 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1053 { 1054 struct amdgpu_device *adev = ring->adev; 1055 unsigned i; 1056 unsigned index; 1057 int r; 1058 u32 tmp; 1059 u64 gpu_addr; 1060 1061 r = amdgpu_device_wb_get(adev, &index); 1062 if (r) 1063 return r; 1064 1065 gpu_addr = adev->wb.gpu_addr + (index * 4); 1066 tmp = 0xCAFEDEAD; 1067 adev->wb.wb[index] = cpu_to_le32(tmp); 1068 1069 r = amdgpu_ring_alloc(ring, 5); 1070 if (r) 1071 goto error_free_wb; 1072 1073 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1074 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1075 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1076 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1077 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1078 amdgpu_ring_write(ring, 0xDEADBEEF); 1079 amdgpu_ring_commit(ring); 1080 1081 for (i = 0; i < adev->usec_timeout; i++) { 1082 tmp = le32_to_cpu(adev->wb.wb[index]); 1083 if (tmp == 0xDEADBEEF) 1084 break; 1085 udelay(1); 1086 } 1087 1088 if (i >= adev->usec_timeout) 1089 r = -ETIMEDOUT; 1090 1091 error_free_wb: 1092 amdgpu_device_wb_free(adev, index); 1093 return r; 1094 } 1095 1096 /** 1097 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1098 * 1099 * @ring: amdgpu_ring structure holding ring information 1100 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1101 * 1102 * Test a simple IB in the DMA ring. 1103 * Returns 0 on success, error on failure. 1104 */ 1105 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1106 { 1107 struct amdgpu_device *adev = ring->adev; 1108 struct amdgpu_ib ib; 1109 struct dma_fence *f = NULL; 1110 unsigned index; 1111 long r; 1112 u32 tmp = 0; 1113 u64 gpu_addr; 1114 1115 r = amdgpu_device_wb_get(adev, &index); 1116 if (r) 1117 return r; 1118 1119 gpu_addr = adev->wb.gpu_addr + (index * 4); 1120 tmp = 0xCAFEDEAD; 1121 adev->wb.wb[index] = cpu_to_le32(tmp); 1122 memset(&ib, 0, sizeof(ib)); 1123 r = amdgpu_ib_get(adev, NULL, 256, 1124 AMDGPU_IB_POOL_DIRECT, &ib); 1125 if (r) 1126 goto err0; 1127 1128 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1129 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1130 ib.ptr[1] = lower_32_bits(gpu_addr); 1131 ib.ptr[2] = upper_32_bits(gpu_addr); 1132 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1133 ib.ptr[4] = 0xDEADBEEF; 1134 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1135 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1136 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1137 ib.length_dw = 8; 1138 1139 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1140 if (r) 1141 goto err1; 1142 1143 r = dma_fence_wait_timeout(f, false, timeout); 1144 if (r == 0) { 1145 r = -ETIMEDOUT; 1146 goto err1; 1147 } else if (r < 0) { 1148 goto err1; 1149 } 1150 tmp = le32_to_cpu(adev->wb.wb[index]); 1151 if (tmp == 0xDEADBEEF) 1152 r = 0; 1153 else 1154 r = -EINVAL; 1155 1156 err1: 1157 amdgpu_ib_free(&ib, NULL); 1158 dma_fence_put(f); 1159 err0: 1160 amdgpu_device_wb_free(adev, index); 1161 return r; 1162 } 1163 1164 1165 /** 1166 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1167 * 1168 * @ib: indirect buffer to fill with commands 1169 * @pe: addr of the page entry 1170 * @src: src addr to copy from 1171 * @count: number of page entries to update 1172 * 1173 * Update PTEs by copying them from the GART using sDMA. 1174 */ 1175 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1176 uint64_t pe, uint64_t src, 1177 unsigned count) 1178 { 1179 unsigned bytes = count * 8; 1180 1181 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1182 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1183 ib->ptr[ib->length_dw++] = bytes - 1; 1184 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1185 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1186 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1187 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1188 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1189 1190 } 1191 1192 /** 1193 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1194 * 1195 * @ib: indirect buffer to fill with commands 1196 * @pe: addr of the page entry 1197 * @value: dst addr to write into pe 1198 * @count: number of page entries to update 1199 * @incr: increase next addr by incr bytes 1200 * 1201 * Update PTEs by writing them manually using sDMA. 1202 */ 1203 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1204 uint64_t value, unsigned count, 1205 uint32_t incr) 1206 { 1207 unsigned ndw = count * 2; 1208 1209 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1210 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1211 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1212 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1213 ib->ptr[ib->length_dw++] = ndw - 1; 1214 for (; ndw > 0; ndw -= 2) { 1215 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1216 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1217 value += incr; 1218 } 1219 } 1220 1221 /** 1222 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1223 * 1224 * @ib: indirect buffer to fill with commands 1225 * @pe: addr of the page entry 1226 * @addr: dst addr to write into pe 1227 * @count: number of page entries to update 1228 * @incr: increase next addr by incr bytes 1229 * @flags: access flags 1230 * 1231 * Update the page tables using sDMA. 1232 */ 1233 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1234 uint64_t pe, 1235 uint64_t addr, unsigned count, 1236 uint32_t incr, uint64_t flags) 1237 { 1238 /* for physically contiguous pages (vram) */ 1239 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1240 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1241 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1242 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1243 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1244 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1245 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1246 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1247 ib->ptr[ib->length_dw++] = 0; 1248 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1249 } 1250 1251 /** 1252 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1253 * 1254 * @ring: amdgpu_ring structure holding ring information 1255 * @ib: indirect buffer to fill with padding 1256 */ 1257 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1258 { 1259 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1260 u32 pad_count; 1261 int i; 1262 1263 pad_count = (-ib->length_dw) & 7; 1264 for (i = 0; i < pad_count; i++) 1265 if (sdma && sdma->burst_nop && (i == 0)) 1266 ib->ptr[ib->length_dw++] = 1267 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1268 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1269 else 1270 ib->ptr[ib->length_dw++] = 1271 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1272 } 1273 1274 1275 /** 1276 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1277 * 1278 * @ring: amdgpu_ring pointer 1279 * 1280 * Make sure all previous operations are completed (CIK). 1281 */ 1282 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1283 { 1284 uint32_t seq = ring->fence_drv.sync_seq; 1285 uint64_t addr = ring->fence_drv.gpu_addr; 1286 1287 /* wait for idle */ 1288 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1289 addr & 0xfffffffc, 1290 upper_32_bits(addr) & 0xffffffff, 1291 seq, 0xffffffff, 4); 1292 } 1293 1294 /* 1295 * sdma_v4_4_2_get_invalidate_req - Construct the VM_INVALIDATE_ENG0_REQ register value 1296 * @vmid: The VMID to invalidate 1297 * @flush_type: The type of flush (0 = legacy, 1 = lightweight, 2 = heavyweight) 1298 * 1299 * This function constructs the VM_INVALIDATE_ENG0_REQ register value for the specified VMID 1300 * and flush type. It ensures that all relevant page table cache levels (L1 PTEs, L2 PTEs, and 1301 * L2 PDEs) are invalidated. 1302 */ 1303 static uint32_t sdma_v4_4_2_get_invalidate_req(unsigned int vmid, 1304 uint32_t flush_type) 1305 { 1306 u32 req = 0; 1307 1308 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 1309 PER_VMID_INVALIDATE_REQ, 1 << vmid); 1310 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 1311 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 1312 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 1313 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 1314 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 1315 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 1316 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 1317 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 1318 1319 return req; 1320 } 1321 1322 /* 1323 * sdma_v4_4_2_ring_emit_vm_flush - Emit VM flush commands for SDMA 1324 * @ring: The SDMA ring 1325 * @vmid: The VMID to flush 1326 * @pd_addr: The page directory address 1327 * 1328 * This function emits the necessary register writes and waits to perform a VM flush for the 1329 * specified VMID. It updates the PTB address registers and issues a VM invalidation request 1330 * using the specified VM invalidation engine. 1331 */ 1332 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1333 unsigned int vmid, uint64_t pd_addr) 1334 { 1335 struct amdgpu_device *adev = ring->adev; 1336 uint32_t req = sdma_v4_4_2_get_invalidate_req(vmid, 0); 1337 unsigned int eng = ring->vm_inv_eng; 1338 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 1339 1340 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1341 (hub->ctx_addr_distance * vmid), 1342 lower_32_bits(pd_addr)); 1343 1344 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1345 (hub->ctx_addr_distance * vmid), 1346 upper_32_bits(pd_addr)); 1347 /* 1348 * Construct and emit the VM invalidation packet 1349 */ 1350 amdgpu_ring_write(ring, 1351 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_VM_INVALIDATE) | 1352 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATE) | 1353 SDMA_PKT_VM_INVALIDATION_HEADER_XCC0_ENG_ID(0x1f) | 1354 SDMA_PKT_VM_INVALIDATION_HEADER_XCC1_ENG_ID(0x1f) | 1355 SDMA_PKT_VM_INVALIDATION_HEADER_MMHUB_ENG_ID(eng)); 1356 amdgpu_ring_write(ring, SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(req)); 1357 amdgpu_ring_write(ring, 0); 1358 amdgpu_ring_write(ring, SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(BIT(vmid))); 1359 } 1360 1361 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1362 uint32_t reg, uint32_t val) 1363 { 1364 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1365 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1366 amdgpu_ring_write(ring, reg); 1367 amdgpu_ring_write(ring, val); 1368 } 1369 1370 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1371 uint32_t val, uint32_t mask) 1372 { 1373 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1374 } 1375 1376 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1377 { 1378 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1379 case IP_VERSION(4, 4, 2): 1380 case IP_VERSION(4, 4, 5): 1381 return false; 1382 default: 1383 return false; 1384 } 1385 } 1386 1387 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1388 { 1389 struct amdgpu_device *adev = ip_block->adev; 1390 int r; 1391 1392 r = sdma_v4_4_2_init_microcode(adev); 1393 if (r) 1394 return r; 1395 1396 /* TODO: Page queue breaks driver reload under SRIOV */ 1397 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1398 adev->sdma.has_page_queue = true; 1399 1400 sdma_v4_4_2_set_ring_funcs(adev); 1401 sdma_v4_4_2_set_buffer_funcs(adev); 1402 sdma_v4_4_2_set_vm_pte_funcs(adev); 1403 sdma_v4_4_2_set_irq_funcs(adev); 1404 sdma_v4_4_2_set_ras_funcs(adev); 1405 sdma_v4_4_2_set_engine_reset_funcs(adev); 1406 1407 return 0; 1408 } 1409 1410 #if 0 1411 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1412 void *err_data, 1413 struct amdgpu_iv_entry *entry); 1414 #endif 1415 1416 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1417 { 1418 struct amdgpu_device *adev = ip_block->adev; 1419 #if 0 1420 struct ras_ih_if ih_info = { 1421 .cb = sdma_v4_4_2_process_ras_data_cb, 1422 }; 1423 #endif 1424 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1425 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1426 1427 /* The initialization is done in the late_init stage to ensure that the SMU 1428 * initialization and capability setup are completed before we check the SDMA 1429 * reset capability 1430 */ 1431 sdma_v4_4_2_update_reset_mask(adev); 1432 1433 return 0; 1434 } 1435 1436 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1437 { 1438 struct amdgpu_ring *ring; 1439 int r, i; 1440 struct amdgpu_device *adev = ip_block->adev; 1441 u32 aid_id; 1442 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1443 uint32_t *ptr; 1444 1445 /* SDMA trap event */ 1446 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1447 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1448 SDMA0_4_0__SRCID__SDMA_TRAP, 1449 &adev->sdma.trap_irq); 1450 if (r) 1451 return r; 1452 } 1453 1454 /* SDMA SRAM ECC event */ 1455 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1456 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1457 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1458 &adev->sdma.ecc_irq); 1459 if (r) 1460 return r; 1461 } 1462 1463 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1464 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1465 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1466 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1467 &adev->sdma.vm_hole_irq); 1468 if (r) 1469 return r; 1470 1471 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1472 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1473 &adev->sdma.doorbell_invalid_irq); 1474 if (r) 1475 return r; 1476 1477 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1478 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1479 &adev->sdma.pool_timeout_irq); 1480 if (r) 1481 return r; 1482 1483 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1484 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1485 &adev->sdma.srbm_write_irq); 1486 if (r) 1487 return r; 1488 1489 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1490 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1491 &adev->sdma.ctxt_empty_irq); 1492 if (r) 1493 return r; 1494 } 1495 1496 for (i = 0; i < adev->sdma.num_instances; i++) { 1497 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); 1498 /* Initialize guilty flags for GFX and PAGE queues */ 1499 adev->sdma.instance[i].gfx_guilty = false; 1500 adev->sdma.instance[i].page_guilty = false; 1501 1502 ring = &adev->sdma.instance[i].ring; 1503 ring->ring_obj = NULL; 1504 ring->use_doorbell = true; 1505 aid_id = adev->sdma.instance[i].aid_id; 1506 1507 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1508 ring->use_doorbell?"true":"false"); 1509 1510 /* doorbell size is 2 dwords, get DWORD offset */ 1511 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1512 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1513 1514 sprintf(ring->name, "sdma%d.%d", aid_id, 1515 i % adev->sdma.num_inst_per_aid); 1516 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1517 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1518 AMDGPU_RING_PRIO_DEFAULT, NULL); 1519 if (r) 1520 return r; 1521 1522 if (adev->sdma.has_page_queue) { 1523 ring = &adev->sdma.instance[i].page; 1524 ring->ring_obj = NULL; 1525 ring->use_doorbell = true; 1526 1527 /* doorbell index of page queue is assigned right after 1528 * gfx queue on the same instance 1529 */ 1530 ring->doorbell_index = 1531 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1532 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1533 1534 sprintf(ring->name, "page%d.%d", aid_id, 1535 i % adev->sdma.num_inst_per_aid); 1536 r = amdgpu_ring_init(adev, ring, 1024, 1537 &adev->sdma.trap_irq, 1538 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1539 AMDGPU_RING_PRIO_DEFAULT, NULL); 1540 if (r) 1541 return r; 1542 } 1543 } 1544 1545 adev->sdma.supported_reset = 1546 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1547 1548 if (amdgpu_sdma_ras_sw_init(adev)) { 1549 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1550 return -EINVAL; 1551 } 1552 1553 /* Allocate memory for SDMA IP Dump buffer */ 1554 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1555 if (ptr) 1556 adev->sdma.ip_dump = ptr; 1557 else 1558 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1559 1560 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1561 if (r) 1562 return r; 1563 1564 return r; 1565 } 1566 1567 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1568 { 1569 struct amdgpu_device *adev = ip_block->adev; 1570 int i; 1571 1572 for (i = 0; i < adev->sdma.num_instances; i++) { 1573 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1574 if (adev->sdma.has_page_queue) 1575 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1576 } 1577 1578 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1579 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1580 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1581 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1582 amdgpu_sdma_destroy_inst_ctx(adev, true); 1583 else 1584 amdgpu_sdma_destroy_inst_ctx(adev, false); 1585 1586 kfree(adev->sdma.ip_dump); 1587 1588 return 0; 1589 } 1590 1591 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1592 { 1593 int r; 1594 struct amdgpu_device *adev = ip_block->adev; 1595 uint32_t inst_mask; 1596 1597 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1598 if (!amdgpu_sriov_vf(adev)) 1599 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1600 1601 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1602 1603 return r; 1604 } 1605 1606 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1607 { 1608 struct amdgpu_device *adev = ip_block->adev; 1609 uint32_t inst_mask; 1610 int i; 1611 1612 if (amdgpu_sriov_vf(adev)) 1613 return 0; 1614 1615 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1616 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1617 for (i = 0; i < adev->sdma.num_instances; i++) { 1618 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1619 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1620 } 1621 } 1622 1623 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1624 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1625 1626 return 0; 1627 } 1628 1629 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1630 enum amd_clockgating_state state); 1631 1632 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1633 { 1634 struct amdgpu_device *adev = ip_block->adev; 1635 1636 if (amdgpu_in_reset(adev)) 1637 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1638 1639 return sdma_v4_4_2_hw_fini(ip_block); 1640 } 1641 1642 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1643 { 1644 return sdma_v4_4_2_hw_init(ip_block); 1645 } 1646 1647 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block) 1648 { 1649 struct amdgpu_device *adev = ip_block->adev; 1650 u32 i; 1651 1652 for (i = 0; i < adev->sdma.num_instances; i++) { 1653 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1654 1655 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1656 return false; 1657 } 1658 1659 return true; 1660 } 1661 1662 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1663 { 1664 unsigned i, j; 1665 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1666 struct amdgpu_device *adev = ip_block->adev; 1667 1668 for (i = 0; i < adev->usec_timeout; i++) { 1669 for (j = 0; j < adev->sdma.num_instances; j++) { 1670 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1671 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1672 break; 1673 } 1674 if (j == adev->sdma.num_instances) 1675 return 0; 1676 udelay(1); 1677 } 1678 return -ETIMEDOUT; 1679 } 1680 1681 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1682 { 1683 /* todo */ 1684 1685 return 0; 1686 } 1687 1688 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue) 1689 { 1690 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS; 1691 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset)); 1692 1693 /* Check if the SELECTED bit is set */ 1694 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0; 1695 } 1696 1697 static bool sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring *ring) 1698 { 1699 struct amdgpu_device *adev = ring->adev; 1700 uint32_t instance_id = ring->me; 1701 1702 return sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1703 } 1704 1705 static bool sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring *ring) 1706 { 1707 struct amdgpu_device *adev = ring->adev; 1708 uint32_t instance_id = ring->me; 1709 1710 if (!adev->sdma.has_page_queue) 1711 return false; 1712 1713 return sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1714 } 1715 1716 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1717 { 1718 struct amdgpu_device *adev = ring->adev; 1719 u32 id = GET_INST(SDMA0, ring->me); 1720 int r; 1721 1722 if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1723 return -EOPNOTSUPP; 1724 1725 amdgpu_amdkfd_suspend(adev, false); 1726 r = amdgpu_sdma_reset_engine(adev, id); 1727 amdgpu_amdkfd_resume(adev, false); 1728 1729 return r; 1730 } 1731 1732 static int sdma_v4_4_2_stop_queue(struct amdgpu_device *adev, uint32_t instance_id) 1733 { 1734 u32 inst_mask; 1735 uint64_t rptr; 1736 struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring; 1737 1738 if (amdgpu_sriov_vf(adev)) 1739 return -EINVAL; 1740 1741 /* Check if this queue is the guilty one */ 1742 adev->sdma.instance[instance_id].gfx_guilty = 1743 sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1744 if (adev->sdma.has_page_queue) 1745 adev->sdma.instance[instance_id].page_guilty = 1746 sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1747 1748 /* Cache the rptr before reset, after the reset, 1749 * all of the registers will be reset to 0 1750 */ 1751 rptr = amdgpu_ring_get_rptr(ring); 1752 ring->cached_rptr = rptr; 1753 /* Cache the rptr for the page queue if it exists */ 1754 if (adev->sdma.has_page_queue) { 1755 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page; 1756 rptr = amdgpu_ring_get_rptr(page_ring); 1757 page_ring->cached_rptr = rptr; 1758 } 1759 1760 /* stop queue */ 1761 inst_mask = 1 << ring->me; 1762 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1763 if (adev->sdma.has_page_queue) 1764 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1765 1766 return 0; 1767 } 1768 1769 static int sdma_v4_4_2_restore_queue(struct amdgpu_device *adev, uint32_t instance_id) 1770 { 1771 int i; 1772 u32 inst_mask; 1773 struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring; 1774 1775 inst_mask = 1 << ring->me; 1776 udelay(50); 1777 1778 for (i = 0; i < adev->usec_timeout; i++) { 1779 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1780 break; 1781 udelay(1); 1782 } 1783 1784 if (i == adev->usec_timeout) { 1785 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1786 ring->me); 1787 return -ETIMEDOUT; 1788 } 1789 1790 return sdma_v4_4_2_inst_start(adev, inst_mask, true); 1791 } 1792 1793 static struct sdma_on_reset_funcs sdma_v4_4_2_engine_reset_funcs = { 1794 .pre_reset = sdma_v4_4_2_stop_queue, 1795 .post_reset = sdma_v4_4_2_restore_queue, 1796 }; 1797 1798 static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev) 1799 { 1800 amdgpu_sdma_register_on_reset_callbacks(adev, &sdma_v4_4_2_engine_reset_funcs); 1801 } 1802 1803 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1804 struct amdgpu_irq_src *source, 1805 unsigned type, 1806 enum amdgpu_interrupt_state state) 1807 { 1808 u32 sdma_cntl; 1809 1810 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1811 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1812 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1813 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1814 1815 return 0; 1816 } 1817 1818 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1819 struct amdgpu_irq_src *source, 1820 struct amdgpu_iv_entry *entry) 1821 { 1822 uint32_t instance, i; 1823 1824 DRM_DEBUG("IH: SDMA trap\n"); 1825 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1826 1827 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1828 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1829 * Match node id with the AID id associated with the SDMA instance. */ 1830 for (i = instance; i < adev->sdma.num_instances; 1831 i += adev->sdma.num_inst_per_aid) { 1832 if (adev->sdma.instance[i].aid_id == 1833 node_id_to_phys_map[entry->node_id]) 1834 break; 1835 } 1836 1837 if (i >= adev->sdma.num_instances) { 1838 dev_WARN_ONCE( 1839 adev->dev, 1, 1840 "Couldn't find the right sdma instance in trap handler"); 1841 return 0; 1842 } 1843 1844 switch (entry->ring_id) { 1845 case 0: 1846 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1847 break; 1848 case 1: 1849 amdgpu_fence_process(&adev->sdma.instance[i].page); 1850 break; 1851 default: 1852 break; 1853 } 1854 return 0; 1855 } 1856 1857 #if 0 1858 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1859 void *err_data, 1860 struct amdgpu_iv_entry *entry) 1861 { 1862 int instance; 1863 1864 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1865 * be disabled and the driver should only look for the aggregated 1866 * interrupt via sync flood 1867 */ 1868 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1869 goto out; 1870 1871 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1872 if (instance < 0) 1873 goto out; 1874 1875 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1876 1877 out: 1878 return AMDGPU_RAS_SUCCESS; 1879 } 1880 #endif 1881 1882 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1883 struct amdgpu_irq_src *source, 1884 struct amdgpu_iv_entry *entry) 1885 { 1886 int instance; 1887 1888 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1889 1890 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1891 if (instance < 0) 1892 return 0; 1893 1894 switch (entry->ring_id) { 1895 case 0: 1896 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1897 break; 1898 } 1899 return 0; 1900 } 1901 1902 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1903 struct amdgpu_irq_src *source, 1904 unsigned type, 1905 enum amdgpu_interrupt_state state) 1906 { 1907 u32 sdma_cntl; 1908 1909 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1910 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1911 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1912 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1913 1914 return 0; 1915 } 1916 1917 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1918 struct amdgpu_iv_entry *entry) 1919 { 1920 int instance; 1921 struct amdgpu_task_info *task_info; 1922 u64 addr; 1923 1924 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1925 if (instance < 0 || instance >= adev->sdma.num_instances) { 1926 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1927 return -EINVAL; 1928 } 1929 1930 addr = (u64)entry->src_data[0] << 12; 1931 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1932 1933 dev_dbg_ratelimited(adev->dev, 1934 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1935 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1936 entry->pasid); 1937 1938 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1939 if (task_info) { 1940 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1941 task_info->process_name, task_info->tgid, 1942 task_info->task_name, task_info->pid); 1943 amdgpu_vm_put_task_info(task_info); 1944 } 1945 1946 return 0; 1947 } 1948 1949 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1950 struct amdgpu_irq_src *source, 1951 struct amdgpu_iv_entry *entry) 1952 { 1953 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1954 sdma_v4_4_2_print_iv_entry(adev, entry); 1955 return 0; 1956 } 1957 1958 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1959 struct amdgpu_irq_src *source, 1960 struct amdgpu_iv_entry *entry) 1961 { 1962 1963 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1964 sdma_v4_4_2_print_iv_entry(adev, entry); 1965 return 0; 1966 } 1967 1968 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1969 struct amdgpu_irq_src *source, 1970 struct amdgpu_iv_entry *entry) 1971 { 1972 dev_dbg_ratelimited(adev->dev, 1973 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1974 sdma_v4_4_2_print_iv_entry(adev, entry); 1975 return 0; 1976 } 1977 1978 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1979 struct amdgpu_irq_src *source, 1980 struct amdgpu_iv_entry *entry) 1981 { 1982 dev_dbg_ratelimited(adev->dev, 1983 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1984 sdma_v4_4_2_print_iv_entry(adev, entry); 1985 return 0; 1986 } 1987 1988 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1989 struct amdgpu_irq_src *source, 1990 struct amdgpu_iv_entry *entry) 1991 { 1992 /* There is nothing useful to be done here, only kept for debug */ 1993 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1994 sdma_v4_4_2_print_iv_entry(adev, entry); 1995 return 0; 1996 } 1997 1998 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1999 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 2000 { 2001 uint32_t data, def; 2002 int i; 2003 2004 /* leave as default if it is not driver controlled */ 2005 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 2006 return; 2007 2008 if (enable) { 2009 for_each_inst(i, inst_mask) { 2010 /* 1-not override: enable sdma mem light sleep */ 2011 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 2012 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2013 if (def != data) 2014 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 2015 } 2016 } else { 2017 for_each_inst(i, inst_mask) { 2018 /* 0-override:disable sdma mem light sleep */ 2019 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 2020 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2021 if (def != data) 2022 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 2023 } 2024 } 2025 } 2026 2027 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2028 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 2029 { 2030 uint32_t data, def; 2031 int i; 2032 2033 /* leave as default if it is not driver controlled */ 2034 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 2035 return; 2036 2037 if (enable) { 2038 for_each_inst(i, inst_mask) { 2039 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2040 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2041 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2042 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2043 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2044 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2045 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2046 if (def != data) 2047 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2048 } 2049 } else { 2050 for_each_inst(i, inst_mask) { 2051 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2052 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2053 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2054 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2055 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2056 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2057 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2058 if (def != data) 2059 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2060 } 2061 } 2062 } 2063 2064 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2065 enum amd_clockgating_state state) 2066 { 2067 struct amdgpu_device *adev = ip_block->adev; 2068 uint32_t inst_mask; 2069 2070 if (amdgpu_sriov_vf(adev)) 2071 return 0; 2072 2073 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2074 2075 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2076 adev, state == AMD_CG_STATE_GATE, inst_mask); 2077 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 2078 adev, state == AMD_CG_STATE_GATE, inst_mask); 2079 return 0; 2080 } 2081 2082 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 2083 enum amd_powergating_state state) 2084 { 2085 return 0; 2086 } 2087 2088 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2089 { 2090 struct amdgpu_device *adev = ip_block->adev; 2091 int data; 2092 2093 if (amdgpu_sriov_vf(adev)) 2094 *flags = 0; 2095 2096 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2097 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 2098 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 2099 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2100 2101 /* AMD_CG_SUPPORT_SDMA_LS */ 2102 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 2103 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2104 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2105 } 2106 2107 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2108 { 2109 struct amdgpu_device *adev = ip_block->adev; 2110 int i, j; 2111 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2112 uint32_t instance_offset; 2113 2114 if (!adev->sdma.ip_dump) 2115 return; 2116 2117 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2118 for (i = 0; i < adev->sdma.num_instances; i++) { 2119 instance_offset = i * reg_count; 2120 drm_printf(p, "\nInstance:%d\n", i); 2121 2122 for (j = 0; j < reg_count; j++) 2123 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 2124 adev->sdma.ip_dump[instance_offset + j]); 2125 } 2126 } 2127 2128 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 2129 { 2130 struct amdgpu_device *adev = ip_block->adev; 2131 int i, j; 2132 uint32_t instance_offset; 2133 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2134 2135 if (!adev->sdma.ip_dump) 2136 return; 2137 2138 for (i = 0; i < adev->sdma.num_instances; i++) { 2139 instance_offset = i * reg_count; 2140 for (j = 0; j < reg_count; j++) 2141 adev->sdma.ip_dump[instance_offset + j] = 2142 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 2143 sdma_reg_list_4_4_2[j].reg_offset)); 2144 } 2145 } 2146 2147 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 2148 .name = "sdma_v4_4_2", 2149 .early_init = sdma_v4_4_2_early_init, 2150 .late_init = sdma_v4_4_2_late_init, 2151 .sw_init = sdma_v4_4_2_sw_init, 2152 .sw_fini = sdma_v4_4_2_sw_fini, 2153 .hw_init = sdma_v4_4_2_hw_init, 2154 .hw_fini = sdma_v4_4_2_hw_fini, 2155 .suspend = sdma_v4_4_2_suspend, 2156 .resume = sdma_v4_4_2_resume, 2157 .is_idle = sdma_v4_4_2_is_idle, 2158 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 2159 .soft_reset = sdma_v4_4_2_soft_reset, 2160 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 2161 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 2162 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 2163 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 2164 .print_ip_state = sdma_v4_4_2_print_ip_state, 2165 }; 2166 2167 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 2168 .type = AMDGPU_RING_TYPE_SDMA, 2169 .align_mask = 0xff, 2170 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2171 .support_64bit_ptrs = true, 2172 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2173 .get_wptr = sdma_v4_4_2_ring_get_wptr, 2174 .set_wptr = sdma_v4_4_2_ring_set_wptr, 2175 .emit_frame_size = 2176 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2177 3 + /* hdp invalidate */ 2178 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2179 /* sdma_v4_4_2_ring_emit_vm_flush */ 2180 4 + 2 * 3 + 2181 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2182 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2183 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2184 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2185 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2186 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2187 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2188 .test_ring = sdma_v4_4_2_ring_test_ring, 2189 .test_ib = sdma_v4_4_2_ring_test_ib, 2190 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2191 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2192 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2193 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2194 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2195 .reset = sdma_v4_4_2_reset_queue, 2196 .is_guilty = sdma_v4_4_2_ring_is_guilty, 2197 }; 2198 2199 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2200 .type = AMDGPU_RING_TYPE_SDMA, 2201 .align_mask = 0xff, 2202 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2203 .support_64bit_ptrs = true, 2204 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2205 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2206 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2207 .emit_frame_size = 2208 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2209 3 + /* hdp invalidate */ 2210 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2211 /* sdma_v4_4_2_ring_emit_vm_flush */ 2212 4 + 2 * 3 + 2213 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2214 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2215 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2216 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2217 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2218 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2219 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2220 .test_ring = sdma_v4_4_2_ring_test_ring, 2221 .test_ib = sdma_v4_4_2_ring_test_ib, 2222 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2223 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2224 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2225 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2226 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2227 .reset = sdma_v4_4_2_reset_queue, 2228 .is_guilty = sdma_v4_4_2_page_ring_is_guilty, 2229 }; 2230 2231 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2232 { 2233 int i, dev_inst; 2234 2235 for (i = 0; i < adev->sdma.num_instances; i++) { 2236 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2237 adev->sdma.instance[i].ring.me = i; 2238 if (adev->sdma.has_page_queue) { 2239 adev->sdma.instance[i].page.funcs = 2240 &sdma_v4_4_2_page_ring_funcs; 2241 adev->sdma.instance[i].page.me = i; 2242 } 2243 2244 dev_inst = GET_INST(SDMA0, i); 2245 /* AID to which SDMA belongs depends on physical instance */ 2246 adev->sdma.instance[i].aid_id = 2247 dev_inst / adev->sdma.num_inst_per_aid; 2248 } 2249 } 2250 2251 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2252 .set = sdma_v4_4_2_set_trap_irq_state, 2253 .process = sdma_v4_4_2_process_trap_irq, 2254 }; 2255 2256 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2257 .process = sdma_v4_4_2_process_illegal_inst_irq, 2258 }; 2259 2260 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2261 .set = sdma_v4_4_2_set_ecc_irq_state, 2262 .process = amdgpu_sdma_process_ecc_irq, 2263 }; 2264 2265 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2266 .process = sdma_v4_4_2_process_vm_hole_irq, 2267 }; 2268 2269 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2270 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2271 }; 2272 2273 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2274 .process = sdma_v4_4_2_process_pool_timeout_irq, 2275 }; 2276 2277 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2278 .process = sdma_v4_4_2_process_srbm_write_irq, 2279 }; 2280 2281 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2282 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2283 }; 2284 2285 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2286 { 2287 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2288 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2289 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2290 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2291 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2292 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2293 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2294 2295 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2296 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2297 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2298 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2299 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2300 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2301 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2302 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2303 } 2304 2305 /** 2306 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2307 * 2308 * @ib: indirect buffer to copy to 2309 * @src_offset: src GPU address 2310 * @dst_offset: dst GPU address 2311 * @byte_count: number of bytes to xfer 2312 * @copy_flags: copy flags for the buffers 2313 * 2314 * Copy GPU buffers using the DMA engine. 2315 * Used by the amdgpu ttm implementation to move pages if 2316 * registered as the asic copy callback. 2317 */ 2318 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2319 uint64_t src_offset, 2320 uint64_t dst_offset, 2321 uint32_t byte_count, 2322 uint32_t copy_flags) 2323 { 2324 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2325 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2326 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2327 ib->ptr[ib->length_dw++] = byte_count - 1; 2328 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2329 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2330 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2331 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2332 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2333 } 2334 2335 /** 2336 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2337 * 2338 * @ib: indirect buffer to copy to 2339 * @src_data: value to write to buffer 2340 * @dst_offset: dst GPU address 2341 * @byte_count: number of bytes to xfer 2342 * 2343 * Fill GPU buffers using the DMA engine. 2344 */ 2345 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2346 uint32_t src_data, 2347 uint64_t dst_offset, 2348 uint32_t byte_count) 2349 { 2350 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2351 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2352 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2353 ib->ptr[ib->length_dw++] = src_data; 2354 ib->ptr[ib->length_dw++] = byte_count - 1; 2355 } 2356 2357 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2358 .copy_max_bytes = 0x400000, 2359 .copy_num_dw = 7, 2360 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2361 2362 .fill_max_bytes = 0x400000, 2363 .fill_num_dw = 5, 2364 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2365 }; 2366 2367 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2368 { 2369 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2370 if (adev->sdma.has_page_queue) 2371 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2372 else 2373 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2374 } 2375 2376 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2377 .copy_pte_num_dw = 7, 2378 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2379 2380 .write_pte = sdma_v4_4_2_vm_write_pte, 2381 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2382 }; 2383 2384 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2385 { 2386 struct drm_gpu_scheduler *sched; 2387 unsigned i; 2388 2389 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2390 for (i = 0; i < adev->sdma.num_instances; i++) { 2391 if (adev->sdma.has_page_queue) 2392 sched = &adev->sdma.instance[i].page.sched; 2393 else 2394 sched = &adev->sdma.instance[i].ring.sched; 2395 adev->vm_manager.vm_pte_scheds[i] = sched; 2396 } 2397 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2398 } 2399 2400 /** 2401 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2402 * @adev: Pointer to the AMDGPU device structure 2403 * 2404 * This function update reset mask for SDMA and sets the supported 2405 * reset types based on the IP version and firmware versions. 2406 * 2407 */ 2408 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2409 { 2410 /* per queue reset not supported for SRIOV */ 2411 if (amdgpu_sriov_vf(adev)) 2412 return; 2413 2414 /* 2415 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2416 * it needs to check both of them at here to skip old mec and pmfw. 2417 */ 2418 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2419 case IP_VERSION(9, 4, 3): 2420 case IP_VERSION(9, 4, 4): 2421 if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2422 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2423 break; 2424 case IP_VERSION(9, 5, 0): 2425 /*TODO: enable the queue reset flag until fw supported */ 2426 default: 2427 break; 2428 } 2429 2430 } 2431 2432 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2433 .type = AMD_IP_BLOCK_TYPE_SDMA, 2434 .major = 4, 2435 .minor = 4, 2436 .rev = 2, 2437 .funcs = &sdma_v4_4_2_ip_funcs, 2438 }; 2439 2440 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2441 { 2442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2443 int r; 2444 2445 if (!amdgpu_sriov_vf(adev)) 2446 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2447 2448 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2449 2450 return r; 2451 } 2452 2453 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2454 { 2455 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2456 uint32_t tmp_mask = inst_mask; 2457 int i; 2458 2459 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2460 for_each_inst(i, tmp_mask) { 2461 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2462 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2463 } 2464 } 2465 2466 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2467 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2468 2469 return 0; 2470 } 2471 2472 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2473 .suspend = &sdma_v4_4_2_xcp_suspend, 2474 .resume = &sdma_v4_4_2_xcp_resume 2475 }; 2476 2477 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2478 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2479 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2480 }; 2481 2482 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2483 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2484 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2485 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2486 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2487 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2488 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2489 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2490 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2491 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2492 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2493 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2494 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2495 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2496 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2497 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2498 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2499 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2500 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2501 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2502 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2503 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2504 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2505 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2506 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2507 }; 2508 2509 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2510 uint32_t sdma_inst, 2511 void *ras_err_status) 2512 { 2513 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2514 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2515 unsigned long ue_count = 0; 2516 struct amdgpu_smuio_mcm_config_info mcm_info = { 2517 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2518 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2519 }; 2520 2521 /* sdma v4_4_2 doesn't support query ce counts */ 2522 amdgpu_ras_inst_query_ras_error_count(adev, 2523 sdma_v4_2_2_ue_reg_list, 2524 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2525 sdma_v4_4_2_ras_memory_list, 2526 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2527 sdma_dev_inst, 2528 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2529 &ue_count); 2530 2531 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2532 } 2533 2534 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2535 void *ras_err_status) 2536 { 2537 uint32_t inst_mask; 2538 int i = 0; 2539 2540 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2541 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2542 for_each_inst(i, inst_mask) 2543 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2544 } else { 2545 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2546 } 2547 } 2548 2549 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2550 uint32_t sdma_inst) 2551 { 2552 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2553 2554 amdgpu_ras_inst_reset_ras_error_count(adev, 2555 sdma_v4_2_2_ue_reg_list, 2556 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2557 sdma_dev_inst); 2558 } 2559 2560 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2561 { 2562 uint32_t inst_mask; 2563 int i = 0; 2564 2565 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2566 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2567 for_each_inst(i, inst_mask) 2568 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2569 } else { 2570 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2571 } 2572 } 2573 2574 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2575 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2576 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2577 }; 2578 2579 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2580 enum aca_smu_type type, void *data) 2581 { 2582 struct aca_bank_info info; 2583 u64 misc0; 2584 int ret; 2585 2586 ret = aca_bank_info_decode(bank, &info); 2587 if (ret) 2588 return ret; 2589 2590 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2591 switch (type) { 2592 case ACA_SMU_TYPE_UE: 2593 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2594 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2595 1ULL); 2596 break; 2597 case ACA_SMU_TYPE_CE: 2598 bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank); 2599 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2600 ACA_REG__MISC0__ERRCNT(misc0)); 2601 break; 2602 default: 2603 return -EINVAL; 2604 } 2605 2606 return ret; 2607 } 2608 2609 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2610 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2611 2612 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2613 enum aca_smu_type type, void *data) 2614 { 2615 u32 instlo; 2616 2617 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2618 instlo &= GENMASK(31, 1); 2619 2620 if (instlo != mmSMNAID_AID0_MCA_SMU) 2621 return false; 2622 2623 if (aca_bank_check_error_codes(handle->adev, bank, 2624 sdma_v4_4_2_err_codes, 2625 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2626 return false; 2627 2628 return true; 2629 } 2630 2631 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2632 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2633 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2634 }; 2635 2636 static const struct aca_info sdma_v4_4_2_aca_info = { 2637 .hwip = ACA_HWIP_TYPE_SMU, 2638 .mask = ACA_ERROR_UE_MASK, 2639 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2640 }; 2641 2642 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2643 { 2644 int r; 2645 2646 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2647 if (r) 2648 return r; 2649 2650 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2651 &sdma_v4_4_2_aca_info, NULL); 2652 } 2653 2654 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2655 .ras_block = { 2656 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2657 .ras_late_init = sdma_v4_4_2_ras_late_init, 2658 }, 2659 }; 2660 2661 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2662 { 2663 adev->sdma.ras = &sdma_v4_4_2_ras; 2664 } 2665