1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_xcp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_trace.h"
33
34 #include "sdma/sdma_4_4_2_offset.h"
35 #include "sdma/sdma_4_4_2_sh_mask.h"
36
37 #include "soc15_common.h"
38 #include "soc15.h"
39 #include "vega10_sdma_pkt_open.h"
40
41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
43
44 #include "amdgpu_ras.h"
45
46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
47 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin");
48
49 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = {
50 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),
51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),
52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),
53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),
54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),
55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),
56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),
57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),
58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),
59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),
60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1),
61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI),
71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),
72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG),
75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),
76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI),
78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI),
80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET),
81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO),
82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI),
83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG),
84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL),
85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR),
86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI),
87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR),
88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI),
89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET),
90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO),
91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI),
92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG),
93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL)
94 };
95
96 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
97
98 #define WREG32_SDMA(instance, offset, value) \
99 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
100 #define RREG32_SDMA(instance, offset) \
101 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
102
103 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
104 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
105 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
106 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
107 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
108
sdma_v4_4_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 offset)109 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
110 u32 instance, u32 offset)
111 {
112 u32 dev_inst = GET_INST(SDMA0, instance);
113
114 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
115 }
116
sdma_v4_4_2_seq_to_irq_id(int seq_num)117 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
118 {
119 switch (seq_num) {
120 case 0:
121 return SOC15_IH_CLIENTID_SDMA0;
122 case 1:
123 return SOC15_IH_CLIENTID_SDMA1;
124 case 2:
125 return SOC15_IH_CLIENTID_SDMA2;
126 case 3:
127 return SOC15_IH_CLIENTID_SDMA3;
128 default:
129 return -EINVAL;
130 }
131 }
132
sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device * adev,unsigned client_id)133 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id)
134 {
135 switch (client_id) {
136 case SOC15_IH_CLIENTID_SDMA0:
137 return 0;
138 case SOC15_IH_CLIENTID_SDMA1:
139 return 1;
140 case SOC15_IH_CLIENTID_SDMA2:
141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
142 return 0;
143 else
144 return 2;
145 case SOC15_IH_CLIENTID_SDMA3:
146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
147 return 1;
148 else
149 return 3;
150 default:
151 return -EINVAL;
152 }
153 }
154
sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device * adev,uint32_t inst_mask)155 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
156 uint32_t inst_mask)
157 {
158 u32 val;
159 int i;
160
161 for (i = 0; i < adev->sdma.num_instances; i++) {
162 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
164 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
165 PIPE_INTERLEAVE_SIZE, 0);
166 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
167
168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
170 4);
171 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
172 PIPE_INTERLEAVE_SIZE, 0);
173 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
174 }
175 }
176
177 /**
178 * sdma_v4_4_2_init_microcode - load ucode images from disk
179 *
180 * @adev: amdgpu_device pointer
181 *
182 * Use the firmware interface to load the ucode images into
183 * the driver (not loaded into hw).
184 * Returns 0 on success, error on failure.
185 */
sdma_v4_4_2_init_microcode(struct amdgpu_device * adev)186 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
187 {
188 int ret, i;
189
190 for (i = 0; i < adev->sdma.num_instances; i++) {
191 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
192 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
193 ret = amdgpu_sdma_init_microcode(adev, 0, true);
194 break;
195 } else {
196 ret = amdgpu_sdma_init_microcode(adev, i, false);
197 if (ret)
198 return ret;
199 }
200 }
201
202 return ret;
203 }
204
205 /**
206 * sdma_v4_4_2_ring_get_rptr - get the current read pointer
207 *
208 * @ring: amdgpu ring pointer
209 *
210 * Get the current rptr from the hardware.
211 */
sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring * ring)212 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
213 {
214 u64 rptr;
215
216 /* XXX check if swapping is necessary on BE */
217 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
218
219 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
220 return rptr >> 2;
221 }
222
223 /**
224 * sdma_v4_4_2_ring_get_wptr - get the current write pointer
225 *
226 * @ring: amdgpu ring pointer
227 *
228 * Get the current wptr from the hardware.
229 */
sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring * ring)230 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
231 {
232 struct amdgpu_device *adev = ring->adev;
233 u64 wptr;
234
235 if (ring->use_doorbell) {
236 /* XXX check if swapping is necessary on BE */
237 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
238 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
239 } else {
240 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
241 wptr = wptr << 32;
242 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
243 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
244 ring->me, wptr);
245 }
246
247 return wptr >> 2;
248 }
249
250 /**
251 * sdma_v4_4_2_ring_set_wptr - commit the write pointer
252 *
253 * @ring: amdgpu ring pointer
254 *
255 * Write the wptr back to the hardware.
256 */
sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring * ring)257 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
258 {
259 struct amdgpu_device *adev = ring->adev;
260
261 DRM_DEBUG("Setting write pointer\n");
262 if (ring->use_doorbell) {
263 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
264
265 DRM_DEBUG("Using doorbell -- "
266 "wptr_offs == 0x%08x "
267 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
268 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
269 ring->wptr_offs,
270 lower_32_bits(ring->wptr << 2),
271 upper_32_bits(ring->wptr << 2));
272 /* XXX check if swapping is necessary on BE */
273 WRITE_ONCE(*wb, (ring->wptr << 2));
274 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
275 ring->doorbell_index, ring->wptr << 2);
276 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
277 } else {
278 DRM_DEBUG("Not using doorbell -- "
279 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
280 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
281 ring->me,
282 lower_32_bits(ring->wptr << 2),
283 ring->me,
284 upper_32_bits(ring->wptr << 2));
285 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
286 lower_32_bits(ring->wptr << 2));
287 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
288 upper_32_bits(ring->wptr << 2));
289 }
290 }
291
292 /**
293 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
294 *
295 * @ring: amdgpu ring pointer
296 *
297 * Get the current wptr from the hardware.
298 */
sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring * ring)299 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
300 {
301 struct amdgpu_device *adev = ring->adev;
302 u64 wptr;
303
304 if (ring->use_doorbell) {
305 /* XXX check if swapping is necessary on BE */
306 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
307 } else {
308 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
309 wptr = wptr << 32;
310 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
311 }
312
313 return wptr >> 2;
314 }
315
316 /**
317 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
318 *
319 * @ring: amdgpu ring pointer
320 *
321 * Write the wptr back to the hardware.
322 */
sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring * ring)323 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
324 {
325 struct amdgpu_device *adev = ring->adev;
326
327 if (ring->use_doorbell) {
328 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
329
330 /* XXX check if swapping is necessary on BE */
331 WRITE_ONCE(*wb, (ring->wptr << 2));
332 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
333 } else {
334 uint64_t wptr = ring->wptr << 2;
335
336 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
337 lower_32_bits(wptr));
338 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
339 upper_32_bits(wptr));
340 }
341 }
342
sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)343 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
344 {
345 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
346 int i;
347
348 for (i = 0; i < count; i++)
349 if (sdma && sdma->burst_nop && (i == 0))
350 amdgpu_ring_write(ring, ring->funcs->nop |
351 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
352 else
353 amdgpu_ring_write(ring, ring->funcs->nop);
354 }
355
356 /**
357 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
358 *
359 * @ring: amdgpu ring pointer
360 * @job: job to retrieve vmid from
361 * @ib: IB object to schedule
362 * @flags: unused
363 *
364 * Schedule an IB in the DMA ring.
365 */
sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)366 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
367 struct amdgpu_job *job,
368 struct amdgpu_ib *ib,
369 uint32_t flags)
370 {
371 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
372
373 /* IB packet must end on a 8 DW boundary */
374 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
375
376 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
377 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
378 /* base must be 32 byte aligned */
379 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
380 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
381 amdgpu_ring_write(ring, ib->length_dw);
382 amdgpu_ring_write(ring, 0);
383 amdgpu_ring_write(ring, 0);
384
385 }
386
sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring * ring,int mem_space,int hdp,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)387 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
388 int mem_space, int hdp,
389 uint32_t addr0, uint32_t addr1,
390 uint32_t ref, uint32_t mask,
391 uint32_t inv)
392 {
393 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
394 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
395 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
396 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
397 if (mem_space) {
398 /* memory */
399 amdgpu_ring_write(ring, addr0);
400 amdgpu_ring_write(ring, addr1);
401 } else {
402 /* registers */
403 amdgpu_ring_write(ring, addr0 << 2);
404 amdgpu_ring_write(ring, addr1 << 2);
405 }
406 amdgpu_ring_write(ring, ref); /* reference */
407 amdgpu_ring_write(ring, mask); /* mask */
408 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
409 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
410 }
411
412 /**
413 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
414 *
415 * @ring: amdgpu ring pointer
416 *
417 * Emit an hdp flush packet on the requested DMA ring.
418 */
sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)419 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
420 {
421 struct amdgpu_device *adev = ring->adev;
422 u32 ref_and_mask = 0;
423 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
424
425 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
426 << (ring->me % adev->sdma.num_inst_per_aid);
427
428 sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
429 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
430 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
431 ref_and_mask, ref_and_mask, 10);
432 }
433
434 /**
435 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
436 *
437 * @ring: amdgpu ring pointer
438 * @addr: address
439 * @seq: sequence number
440 * @flags: fence related flags
441 *
442 * Add a DMA fence packet to the ring to write
443 * the fence seq number and DMA trap packet to generate
444 * an interrupt if needed.
445 */
sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)446 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
447 unsigned flags)
448 {
449 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
450 /* write the fence */
451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
452 /* zero in first two bits */
453 BUG_ON(addr & 0x3);
454 amdgpu_ring_write(ring, lower_32_bits(addr));
455 amdgpu_ring_write(ring, upper_32_bits(addr));
456 amdgpu_ring_write(ring, lower_32_bits(seq));
457
458 /* optionally write high bits as well */
459 if (write64bit) {
460 addr += 4;
461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
462 /* zero in first two bits */
463 BUG_ON(addr & 0x3);
464 amdgpu_ring_write(ring, lower_32_bits(addr));
465 amdgpu_ring_write(ring, upper_32_bits(addr));
466 amdgpu_ring_write(ring, upper_32_bits(seq));
467 }
468
469 /* generate an interrupt */
470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
471 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
472 }
473
474
475 /**
476 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
477 *
478 * @adev: amdgpu_device pointer
479 * @inst_mask: mask of dma engine instances to be disabled
480 *
481 * Stop the gfx async dma ring buffers.
482 */
sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device * adev,uint32_t inst_mask)483 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
484 uint32_t inst_mask)
485 {
486 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
487 u32 doorbell_offset, doorbell;
488 u32 rb_cntl, ib_cntl;
489 int i;
490
491 for_each_inst(i, inst_mask) {
492 sdma[i] = &adev->sdma.instance[i].ring;
493
494 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
495 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
496 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
497 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
498 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
499 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
500
501 if (sdma[i]->use_doorbell) {
502 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
503 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
504
505 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
506 doorbell_offset = REG_SET_FIELD(doorbell_offset,
507 SDMA_GFX_DOORBELL_OFFSET,
508 OFFSET, 0);
509 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
510 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
511 }
512 }
513 }
514
515 /**
516 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 * @inst_mask: mask of dma engine instances to be disabled
520 *
521 * Stop the compute async dma queues.
522 */
sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device * adev,uint32_t inst_mask)523 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
524 uint32_t inst_mask)
525 {
526 /* XXX todo */
527 }
528
529 /**
530 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
531 *
532 * @adev: amdgpu_device pointer
533 * @inst_mask: mask of dma engine instances to be disabled
534 *
535 * Stop the page async dma ring buffers.
536 */
sdma_v4_4_2_inst_page_stop(struct amdgpu_device * adev,uint32_t inst_mask)537 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
538 uint32_t inst_mask)
539 {
540 u32 rb_cntl, ib_cntl;
541 int i;
542
543 for_each_inst(i, inst_mask) {
544 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
545 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
546 RB_ENABLE, 0);
547 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
548 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
549 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
550 IB_ENABLE, 0);
551 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
552 }
553 }
554
555 /**
556 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
557 *
558 * @adev: amdgpu_device pointer
559 * @enable: enable/disable the DMA MEs context switch.
560 * @inst_mask: mask of dma engine instances to be enabled
561 *
562 * Halt or unhalt the async dma engines context switch.
563 */
sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)564 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
565 bool enable, uint32_t inst_mask)
566 {
567 u32 f32_cntl, phase_quantum = 0;
568 int i;
569
570 if (amdgpu_sdma_phase_quantum) {
571 unsigned value = amdgpu_sdma_phase_quantum;
572 unsigned unit = 0;
573
574 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
575 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
576 value = (value + 1) >> 1;
577 unit++;
578 }
579 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
580 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
581 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
582 SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
583 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
584 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
585 WARN_ONCE(1,
586 "clamping sdma_phase_quantum to %uK clock cycles\n",
587 value << unit);
588 }
589 phase_quantum =
590 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
591 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
592 }
593
594 for_each_inst(i, inst_mask) {
595 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
597 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
598 if (enable && amdgpu_sdma_phase_quantum) {
599 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
600 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
601 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
602 }
603 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
604
605 /* Extend page fault timeout to avoid interrupt storm */
606 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
607 }
608 }
609
610 /**
611 * sdma_v4_4_2_inst_enable - stop the async dma engines
612 *
613 * @adev: amdgpu_device pointer
614 * @enable: enable/disable the DMA MEs.
615 * @inst_mask: mask of dma engine instances to be enabled
616 *
617 * Halt or unhalt the async dma engines.
618 */
sdma_v4_4_2_inst_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)619 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
620 uint32_t inst_mask)
621 {
622 u32 f32_cntl;
623 int i;
624
625 if (!enable) {
626 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
627 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
628 if (adev->sdma.has_page_queue)
629 sdma_v4_4_2_inst_page_stop(adev, inst_mask);
630
631 /* SDMA FW needs to respond to FREEZE requests during reset.
632 * Keep it running during reset */
633 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
634 return;
635 }
636
637 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
638 return;
639
640 for_each_inst(i, inst_mask) {
641 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
642 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
643 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
644 }
645 }
646
647 /*
648 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
649 */
sdma_v4_4_2_rb_cntl(struct amdgpu_ring * ring,uint32_t rb_cntl)650 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
651 {
652 /* Set ring buffer size in dwords */
653 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
654
655 barrier(); /* work around https://llvm.org/pr42576 */
656 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
657 #ifdef __BIG_ENDIAN
658 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
659 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
660 RPTR_WRITEBACK_SWAP_ENABLE, 1);
661 #endif
662 return rb_cntl;
663 }
664
665 /**
666 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
667 *
668 * @adev: amdgpu_device pointer
669 * @i: instance to resume
670 *
671 * Set up the gfx DMA ring buffers and enable them.
672 * Returns 0 for success, error for failure.
673 */
sdma_v4_4_2_gfx_resume(struct amdgpu_device * adev,unsigned int i)674 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
675 {
676 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
677 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
678 u32 wb_offset;
679 u32 doorbell;
680 u32 doorbell_offset;
681 u64 wptr_gpu_addr;
682
683 wb_offset = (ring->rptr_offs * 4);
684
685 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
686 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
687 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
688
689 /* set the wb address whether it's enabled or not */
690 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
691 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
692 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
693 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
694
695 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
696 RPTR_WRITEBACK_ENABLE, 1);
697
698 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
699 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
700
701 ring->wptr = 0;
702
703 /* before programing wptr to a less value, need set minor_ptr_update first */
704 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
705
706 /* Initialize the ring buffer's read and write pointers */
707 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
708 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
709 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
710 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
711
712 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
713 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
714
715 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
716 ring->use_doorbell);
717 doorbell_offset = REG_SET_FIELD(doorbell_offset,
718 SDMA_GFX_DOORBELL_OFFSET,
719 OFFSET, ring->doorbell_index);
720 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
721 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
722
723 sdma_v4_4_2_ring_set_wptr(ring);
724
725 /* set minor_ptr_update to 0 after wptr programed */
726 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
727
728 /* setup the wptr shadow polling */
729 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
730 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
731 lower_32_bits(wptr_gpu_addr));
732 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
733 upper_32_bits(wptr_gpu_addr));
734 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
735 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
736 SDMA_GFX_RB_WPTR_POLL_CNTL,
737 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
738 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
739
740 /* enable DMA RB */
741 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
742 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
743
744 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
745 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
746 #ifdef __BIG_ENDIAN
747 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
748 #endif
749 /* enable DMA IBs */
750 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
751 }
752
753 /**
754 * sdma_v4_4_2_page_resume - setup and start the async dma engines
755 *
756 * @adev: amdgpu_device pointer
757 * @i: instance to resume
758 *
759 * Set up the page DMA ring buffers and enable them.
760 * Returns 0 for success, error for failure.
761 */
sdma_v4_4_2_page_resume(struct amdgpu_device * adev,unsigned int i)762 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
763 {
764 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
765 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
766 u32 wb_offset;
767 u32 doorbell;
768 u32 doorbell_offset;
769 u64 wptr_gpu_addr;
770
771 wb_offset = (ring->rptr_offs * 4);
772
773 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
774 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
775 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
776
777 /* Initialize the ring buffer's read and write pointers */
778 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
779 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
780 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
781 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
782
783 /* set the wb address whether it's enabled or not */
784 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
785 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
786 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
787 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
788
789 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
790 RPTR_WRITEBACK_ENABLE, 1);
791
792 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
793 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
794
795 ring->wptr = 0;
796
797 /* before programing wptr to a less value, need set minor_ptr_update first */
798 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
799
800 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
801 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
802
803 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
804 ring->use_doorbell);
805 doorbell_offset = REG_SET_FIELD(doorbell_offset,
806 SDMA_PAGE_DOORBELL_OFFSET,
807 OFFSET, ring->doorbell_index);
808 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
809 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
810
811 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
812 sdma_v4_4_2_page_ring_set_wptr(ring);
813
814 /* set minor_ptr_update to 0 after wptr programed */
815 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
816
817 /* setup the wptr shadow polling */
818 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
819 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
820 lower_32_bits(wptr_gpu_addr));
821 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
822 upper_32_bits(wptr_gpu_addr));
823 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
824 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
825 SDMA_PAGE_RB_WPTR_POLL_CNTL,
826 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
827 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
828
829 /* enable DMA RB */
830 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
831 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
832
833 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
834 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
835 #ifdef __BIG_ENDIAN
836 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
837 #endif
838 /* enable DMA IBs */
839 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
840 }
841
sdma_v4_4_2_init_pg(struct amdgpu_device * adev)842 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
843 {
844
845 }
846
847 /**
848 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
849 *
850 * @adev: amdgpu_device pointer
851 * @inst_mask: mask of dma engine instances to be enabled
852 *
853 * Set up the compute DMA queues and enable them.
854 * Returns 0 for success, error for failure.
855 */
sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device * adev,uint32_t inst_mask)856 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
857 uint32_t inst_mask)
858 {
859 sdma_v4_4_2_init_pg(adev);
860
861 return 0;
862 }
863
864 /**
865 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
866 *
867 * @adev: amdgpu_device pointer
868 * @inst_mask: mask of dma engine instances to be enabled
869 *
870 * Loads the sDMA0/1 ucode.
871 * Returns 0 for success, -EINVAL if the ucode is not available.
872 */
sdma_v4_4_2_inst_load_microcode(struct amdgpu_device * adev,uint32_t inst_mask)873 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
874 uint32_t inst_mask)
875 {
876 const struct sdma_firmware_header_v1_0 *hdr;
877 const __le32 *fw_data;
878 u32 fw_size;
879 int i, j;
880
881 /* halt the MEs */
882 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
883
884 for_each_inst(i, inst_mask) {
885 if (!adev->sdma.instance[i].fw)
886 return -EINVAL;
887
888 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
889 amdgpu_ucode_print_sdma_hdr(&hdr->header);
890 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
891
892 fw_data = (const __le32 *)
893 (adev->sdma.instance[i].fw->data +
894 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
895
896 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
897
898 for (j = 0; j < fw_size; j++)
899 WREG32_SDMA(i, regSDMA_UCODE_DATA,
900 le32_to_cpup(fw_data++));
901
902 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
903 adev->sdma.instance[i].fw_version);
904 }
905
906 return 0;
907 }
908
909 /**
910 * sdma_v4_4_2_inst_start - setup and start the async dma engines
911 *
912 * @adev: amdgpu_device pointer
913 * @inst_mask: mask of dma engine instances to be enabled
914 *
915 * Set up the DMA engines and enable them.
916 * Returns 0 for success, error for failure.
917 */
sdma_v4_4_2_inst_start(struct amdgpu_device * adev,uint32_t inst_mask)918 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
919 uint32_t inst_mask)
920 {
921 struct amdgpu_ring *ring;
922 uint32_t tmp_mask;
923 int i, r = 0;
924
925 if (amdgpu_sriov_vf(adev)) {
926 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
927 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
928 } else {
929 /* bypass sdma microcode loading on Gopher */
930 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
931 adev->sdma.instance[0].fw) {
932 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
933 if (r)
934 return r;
935 }
936
937 /* unhalt the MEs */
938 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
939 /* enable sdma ring preemption */
940 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
941 }
942
943 /* start the gfx rings and rlc compute queues */
944 tmp_mask = inst_mask;
945 for_each_inst(i, tmp_mask) {
946 uint32_t temp;
947
948 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
949 sdma_v4_4_2_gfx_resume(adev, i);
950 if (adev->sdma.has_page_queue)
951 sdma_v4_4_2_page_resume(adev, i);
952
953 /* set utc l1 enable flag always to 1 */
954 temp = RREG32_SDMA(i, regSDMA_CNTL);
955 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
956 /* enable context empty interrupt during initialization */
957 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
958 WREG32_SDMA(i, regSDMA_CNTL, temp);
959
960 if (!amdgpu_sriov_vf(adev)) {
961 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
962 /* unhalt engine */
963 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
964 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
965 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
966 }
967 }
968 }
969
970 if (amdgpu_sriov_vf(adev)) {
971 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
972 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
973 } else {
974 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
975 if (r)
976 return r;
977 }
978
979 tmp_mask = inst_mask;
980 for_each_inst(i, tmp_mask) {
981 ring = &adev->sdma.instance[i].ring;
982
983 r = amdgpu_ring_test_helper(ring);
984 if (r)
985 return r;
986
987 if (adev->sdma.has_page_queue) {
988 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
989
990 r = amdgpu_ring_test_helper(page);
991 if (r)
992 return r;
993 }
994 }
995
996 return r;
997 }
998
999 /**
1000 * sdma_v4_4_2_ring_test_ring - simple async dma engine test
1001 *
1002 * @ring: amdgpu_ring structure holding ring information
1003 *
1004 * Test the DMA engine by writing using it to write an
1005 * value to memory.
1006 * Returns 0 for success, error for failure.
1007 */
sdma_v4_4_2_ring_test_ring(struct amdgpu_ring * ring)1008 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
1009 {
1010 struct amdgpu_device *adev = ring->adev;
1011 unsigned i;
1012 unsigned index;
1013 int r;
1014 u32 tmp;
1015 u64 gpu_addr;
1016
1017 r = amdgpu_device_wb_get(adev, &index);
1018 if (r)
1019 return r;
1020
1021 gpu_addr = adev->wb.gpu_addr + (index * 4);
1022 tmp = 0xCAFEDEAD;
1023 adev->wb.wb[index] = cpu_to_le32(tmp);
1024
1025 r = amdgpu_ring_alloc(ring, 5);
1026 if (r)
1027 goto error_free_wb;
1028
1029 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1030 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1031 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1032 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1033 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1034 amdgpu_ring_write(ring, 0xDEADBEEF);
1035 amdgpu_ring_commit(ring);
1036
1037 for (i = 0; i < adev->usec_timeout; i++) {
1038 tmp = le32_to_cpu(adev->wb.wb[index]);
1039 if (tmp == 0xDEADBEEF)
1040 break;
1041 udelay(1);
1042 }
1043
1044 if (i >= adev->usec_timeout)
1045 r = -ETIMEDOUT;
1046
1047 error_free_wb:
1048 amdgpu_device_wb_free(adev, index);
1049 return r;
1050 }
1051
1052 /**
1053 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1054 *
1055 * @ring: amdgpu_ring structure holding ring information
1056 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1057 *
1058 * Test a simple IB in the DMA ring.
1059 * Returns 0 on success, error on failure.
1060 */
sdma_v4_4_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)1061 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1062 {
1063 struct amdgpu_device *adev = ring->adev;
1064 struct amdgpu_ib ib;
1065 struct dma_fence *f = NULL;
1066 unsigned index;
1067 long r;
1068 u32 tmp = 0;
1069 u64 gpu_addr;
1070
1071 r = amdgpu_device_wb_get(adev, &index);
1072 if (r)
1073 return r;
1074
1075 gpu_addr = adev->wb.gpu_addr + (index * 4);
1076 tmp = 0xCAFEDEAD;
1077 adev->wb.wb[index] = cpu_to_le32(tmp);
1078 memset(&ib, 0, sizeof(ib));
1079 r = amdgpu_ib_get(adev, NULL, 256,
1080 AMDGPU_IB_POOL_DIRECT, &ib);
1081 if (r)
1082 goto err0;
1083
1084 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1085 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1086 ib.ptr[1] = lower_32_bits(gpu_addr);
1087 ib.ptr[2] = upper_32_bits(gpu_addr);
1088 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1089 ib.ptr[4] = 0xDEADBEEF;
1090 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1091 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1092 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1093 ib.length_dw = 8;
1094
1095 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1096 if (r)
1097 goto err1;
1098
1099 r = dma_fence_wait_timeout(f, false, timeout);
1100 if (r == 0) {
1101 r = -ETIMEDOUT;
1102 goto err1;
1103 } else if (r < 0) {
1104 goto err1;
1105 }
1106 tmp = le32_to_cpu(adev->wb.wb[index]);
1107 if (tmp == 0xDEADBEEF)
1108 r = 0;
1109 else
1110 r = -EINVAL;
1111
1112 err1:
1113 amdgpu_ib_free(adev, &ib, NULL);
1114 dma_fence_put(f);
1115 err0:
1116 amdgpu_device_wb_free(adev, index);
1117 return r;
1118 }
1119
1120
1121 /**
1122 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1123 *
1124 * @ib: indirect buffer to fill with commands
1125 * @pe: addr of the page entry
1126 * @src: src addr to copy from
1127 * @count: number of page entries to update
1128 *
1129 * Update PTEs by copying them from the GART using sDMA.
1130 */
sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1131 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1132 uint64_t pe, uint64_t src,
1133 unsigned count)
1134 {
1135 unsigned bytes = count * 8;
1136
1137 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1138 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1139 ib->ptr[ib->length_dw++] = bytes - 1;
1140 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1141 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1142 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1143 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1144 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1145
1146 }
1147
1148 /**
1149 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1150 *
1151 * @ib: indirect buffer to fill with commands
1152 * @pe: addr of the page entry
1153 * @value: dst addr to write into pe
1154 * @count: number of page entries to update
1155 * @incr: increase next addr by incr bytes
1156 *
1157 * Update PTEs by writing them manually using sDMA.
1158 */
sdma_v4_4_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1159 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1160 uint64_t value, unsigned count,
1161 uint32_t incr)
1162 {
1163 unsigned ndw = count * 2;
1164
1165 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1166 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1167 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1168 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1169 ib->ptr[ib->length_dw++] = ndw - 1;
1170 for (; ndw > 0; ndw -= 2) {
1171 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1172 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1173 value += incr;
1174 }
1175 }
1176
1177 /**
1178 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1179 *
1180 * @ib: indirect buffer to fill with commands
1181 * @pe: addr of the page entry
1182 * @addr: dst addr to write into pe
1183 * @count: number of page entries to update
1184 * @incr: increase next addr by incr bytes
1185 * @flags: access flags
1186 *
1187 * Update the page tables using sDMA.
1188 */
sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1189 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1190 uint64_t pe,
1191 uint64_t addr, unsigned count,
1192 uint32_t incr, uint64_t flags)
1193 {
1194 /* for physically contiguous pages (vram) */
1195 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1196 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1197 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1198 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1199 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1200 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1201 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1202 ib->ptr[ib->length_dw++] = incr; /* increment size */
1203 ib->ptr[ib->length_dw++] = 0;
1204 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1205 }
1206
1207 /**
1208 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1209 *
1210 * @ring: amdgpu_ring structure holding ring information
1211 * @ib: indirect buffer to fill with padding
1212 */
sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1213 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1214 {
1215 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1216 u32 pad_count;
1217 int i;
1218
1219 pad_count = (-ib->length_dw) & 7;
1220 for (i = 0; i < pad_count; i++)
1221 if (sdma && sdma->burst_nop && (i == 0))
1222 ib->ptr[ib->length_dw++] =
1223 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1224 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1225 else
1226 ib->ptr[ib->length_dw++] =
1227 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1228 }
1229
1230
1231 /**
1232 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1233 *
1234 * @ring: amdgpu_ring pointer
1235 *
1236 * Make sure all previous operations are completed (CIK).
1237 */
sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1238 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1239 {
1240 uint32_t seq = ring->fence_drv.sync_seq;
1241 uint64_t addr = ring->fence_drv.gpu_addr;
1242
1243 /* wait for idle */
1244 sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1245 addr & 0xfffffffc,
1246 upper_32_bits(addr) & 0xffffffff,
1247 seq, 0xffffffff, 4);
1248 }
1249
1250
1251 /**
1252 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1253 *
1254 * @ring: amdgpu_ring pointer
1255 * @vmid: vmid number to use
1256 * @pd_addr: address
1257 *
1258 * Update the page table base and flush the VM TLB
1259 * using sDMA.
1260 */
sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1261 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1262 unsigned vmid, uint64_t pd_addr)
1263 {
1264 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1265 }
1266
sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1267 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1268 uint32_t reg, uint32_t val)
1269 {
1270 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1271 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1272 amdgpu_ring_write(ring, reg);
1273 amdgpu_ring_write(ring, val);
1274 }
1275
sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1276 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1277 uint32_t val, uint32_t mask)
1278 {
1279 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1280 }
1281
sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device * adev)1282 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1283 {
1284 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1285 case IP_VERSION(4, 4, 2):
1286 case IP_VERSION(4, 4, 5):
1287 return false;
1288 default:
1289 return false;
1290 }
1291 }
1292
sdma_v4_4_2_early_init(void * handle)1293 static int sdma_v4_4_2_early_init(void *handle)
1294 {
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 int r;
1297
1298 r = sdma_v4_4_2_init_microcode(adev);
1299 if (r)
1300 return r;
1301
1302 /* TODO: Page queue breaks driver reload under SRIOV */
1303 if (sdma_v4_4_2_fw_support_paging_queue(adev))
1304 adev->sdma.has_page_queue = true;
1305
1306 sdma_v4_4_2_set_ring_funcs(adev);
1307 sdma_v4_4_2_set_buffer_funcs(adev);
1308 sdma_v4_4_2_set_vm_pte_funcs(adev);
1309 sdma_v4_4_2_set_irq_funcs(adev);
1310 sdma_v4_4_2_set_ras_funcs(adev);
1311
1312 return 0;
1313 }
1314
1315 #if 0
1316 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1317 void *err_data,
1318 struct amdgpu_iv_entry *entry);
1319 #endif
1320
sdma_v4_4_2_late_init(void * handle)1321 static int sdma_v4_4_2_late_init(void *handle)
1322 {
1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324 #if 0
1325 struct ras_ih_if ih_info = {
1326 .cb = sdma_v4_4_2_process_ras_data_cb,
1327 };
1328 #endif
1329 if (!amdgpu_persistent_edc_harvesting_supported(adev))
1330 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1331
1332 return 0;
1333 }
1334
sdma_v4_4_2_sw_init(void * handle)1335 static int sdma_v4_4_2_sw_init(void *handle)
1336 {
1337 struct amdgpu_ring *ring;
1338 int r, i;
1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340 u32 aid_id;
1341 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1342 uint32_t *ptr;
1343
1344 /* SDMA trap event */
1345 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1346 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1347 SDMA0_4_0__SRCID__SDMA_TRAP,
1348 &adev->sdma.trap_irq);
1349 if (r)
1350 return r;
1351 }
1352
1353 /* SDMA SRAM ECC event */
1354 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1355 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1356 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1357 &adev->sdma.ecc_irq);
1358 if (r)
1359 return r;
1360 }
1361
1362 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1363 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1364 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1365 SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1366 &adev->sdma.vm_hole_irq);
1367 if (r)
1368 return r;
1369
1370 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1371 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1372 &adev->sdma.doorbell_invalid_irq);
1373 if (r)
1374 return r;
1375
1376 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1377 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1378 &adev->sdma.pool_timeout_irq);
1379 if (r)
1380 return r;
1381
1382 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1383 SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1384 &adev->sdma.srbm_write_irq);
1385 if (r)
1386 return r;
1387 }
1388
1389 for (i = 0; i < adev->sdma.num_instances; i++) {
1390 ring = &adev->sdma.instance[i].ring;
1391 ring->ring_obj = NULL;
1392 ring->use_doorbell = true;
1393 aid_id = adev->sdma.instance[i].aid_id;
1394
1395 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1396 ring->use_doorbell?"true":"false");
1397
1398 /* doorbell size is 2 dwords, get DWORD offset */
1399 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1400 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1401
1402 sprintf(ring->name, "sdma%d.%d", aid_id,
1403 i % adev->sdma.num_inst_per_aid);
1404 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1405 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1406 AMDGPU_RING_PRIO_DEFAULT, NULL);
1407 if (r)
1408 return r;
1409
1410 if (adev->sdma.has_page_queue) {
1411 ring = &adev->sdma.instance[i].page;
1412 ring->ring_obj = NULL;
1413 ring->use_doorbell = true;
1414
1415 /* doorbell index of page queue is assigned right after
1416 * gfx queue on the same instance
1417 */
1418 ring->doorbell_index =
1419 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1420 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1421
1422 sprintf(ring->name, "page%d.%d", aid_id,
1423 i % adev->sdma.num_inst_per_aid);
1424 r = amdgpu_ring_init(adev, ring, 1024,
1425 &adev->sdma.trap_irq,
1426 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1427 AMDGPU_RING_PRIO_DEFAULT, NULL);
1428 if (r)
1429 return r;
1430 }
1431 }
1432
1433 if (amdgpu_sdma_ras_sw_init(adev)) {
1434 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1435 return -EINVAL;
1436 }
1437
1438 /* Allocate memory for SDMA IP Dump buffer */
1439 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1440 if (ptr)
1441 adev->sdma.ip_dump = ptr;
1442 else
1443 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1444
1445 return r;
1446 }
1447
sdma_v4_4_2_sw_fini(void * handle)1448 static int sdma_v4_4_2_sw_fini(void *handle)
1449 {
1450 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451 int i;
1452
1453 for (i = 0; i < adev->sdma.num_instances; i++) {
1454 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1455 if (adev->sdma.has_page_queue)
1456 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1457 }
1458
1459 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
1460 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5))
1461 amdgpu_sdma_destroy_inst_ctx(adev, true);
1462 else
1463 amdgpu_sdma_destroy_inst_ctx(adev, false);
1464
1465 kfree(adev->sdma.ip_dump);
1466
1467 return 0;
1468 }
1469
sdma_v4_4_2_hw_init(void * handle)1470 static int sdma_v4_4_2_hw_init(void *handle)
1471 {
1472 int r;
1473 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474 uint32_t inst_mask;
1475
1476 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1477 if (!amdgpu_sriov_vf(adev))
1478 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1479
1480 r = sdma_v4_4_2_inst_start(adev, inst_mask);
1481
1482 return r;
1483 }
1484
sdma_v4_4_2_hw_fini(void * handle)1485 static int sdma_v4_4_2_hw_fini(void *handle)
1486 {
1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1488 uint32_t inst_mask;
1489 int i;
1490
1491 if (amdgpu_sriov_vf(adev))
1492 return 0;
1493
1494 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1495 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1496 for (i = 0; i < adev->sdma.num_instances; i++) {
1497 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1498 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1499 }
1500 }
1501
1502 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1503 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1504
1505 return 0;
1506 }
1507
1508 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1509 enum amd_clockgating_state state);
1510
sdma_v4_4_2_suspend(void * handle)1511 static int sdma_v4_4_2_suspend(void *handle)
1512 {
1513 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1514
1515 if (amdgpu_in_reset(adev))
1516 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1517
1518 return sdma_v4_4_2_hw_fini(adev);
1519 }
1520
sdma_v4_4_2_resume(void * handle)1521 static int sdma_v4_4_2_resume(void *handle)
1522 {
1523 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1524
1525 return sdma_v4_4_2_hw_init(adev);
1526 }
1527
sdma_v4_4_2_is_idle(void * handle)1528 static bool sdma_v4_4_2_is_idle(void *handle)
1529 {
1530 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1531 u32 i;
1532
1533 for (i = 0; i < adev->sdma.num_instances; i++) {
1534 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1535
1536 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1537 return false;
1538 }
1539
1540 return true;
1541 }
1542
sdma_v4_4_2_wait_for_idle(void * handle)1543 static int sdma_v4_4_2_wait_for_idle(void *handle)
1544 {
1545 unsigned i, j;
1546 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1548
1549 for (i = 0; i < adev->usec_timeout; i++) {
1550 for (j = 0; j < adev->sdma.num_instances; j++) {
1551 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1552 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1553 break;
1554 }
1555 if (j == adev->sdma.num_instances)
1556 return 0;
1557 udelay(1);
1558 }
1559 return -ETIMEDOUT;
1560 }
1561
sdma_v4_4_2_soft_reset(void * handle)1562 static int sdma_v4_4_2_soft_reset(void *handle)
1563 {
1564 /* todo */
1565
1566 return 0;
1567 }
1568
sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1569 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1570 struct amdgpu_irq_src *source,
1571 unsigned type,
1572 enum amdgpu_interrupt_state state)
1573 {
1574 u32 sdma_cntl;
1575
1576 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1577 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1578 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1579 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1580
1581 return 0;
1582 }
1583
sdma_v4_4_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1584 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1585 struct amdgpu_irq_src *source,
1586 struct amdgpu_iv_entry *entry)
1587 {
1588 uint32_t instance, i;
1589
1590 DRM_DEBUG("IH: SDMA trap\n");
1591 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1592
1593 /* Client id gives the SDMA instance in AID. To know the exact SDMA
1594 * instance, interrupt entry gives the node id which corresponds to the AID instance.
1595 * Match node id with the AID id associated with the SDMA instance. */
1596 for (i = instance; i < adev->sdma.num_instances;
1597 i += adev->sdma.num_inst_per_aid) {
1598 if (adev->sdma.instance[i].aid_id ==
1599 node_id_to_phys_map[entry->node_id])
1600 break;
1601 }
1602
1603 if (i >= adev->sdma.num_instances) {
1604 dev_WARN_ONCE(
1605 adev->dev, 1,
1606 "Couldn't find the right sdma instance in trap handler");
1607 return 0;
1608 }
1609
1610 switch (entry->ring_id) {
1611 case 0:
1612 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1613 break;
1614 default:
1615 break;
1616 }
1617 return 0;
1618 }
1619
1620 #if 0
1621 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1622 void *err_data,
1623 struct amdgpu_iv_entry *entry)
1624 {
1625 int instance;
1626
1627 /* When “Full RAS” is enabled, the per-IP interrupt sources should
1628 * be disabled and the driver should only look for the aggregated
1629 * interrupt via sync flood
1630 */
1631 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1632 goto out;
1633
1634 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1635 if (instance < 0)
1636 goto out;
1637
1638 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1639
1640 out:
1641 return AMDGPU_RAS_SUCCESS;
1642 }
1643 #endif
1644
sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1645 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1646 struct amdgpu_irq_src *source,
1647 struct amdgpu_iv_entry *entry)
1648 {
1649 int instance;
1650
1651 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1652
1653 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1654 if (instance < 0)
1655 return 0;
1656
1657 switch (entry->ring_id) {
1658 case 0:
1659 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1660 break;
1661 }
1662 return 0;
1663 }
1664
sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1665 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1666 struct amdgpu_irq_src *source,
1667 unsigned type,
1668 enum amdgpu_interrupt_state state)
1669 {
1670 u32 sdma_cntl;
1671
1672 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1673 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1674 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1675 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1676
1677 return 0;
1678 }
1679
sdma_v4_4_2_print_iv_entry(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)1680 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1681 struct amdgpu_iv_entry *entry)
1682 {
1683 int instance;
1684 struct amdgpu_task_info *task_info;
1685 u64 addr;
1686
1687 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1688 if (instance < 0 || instance >= adev->sdma.num_instances) {
1689 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1690 return -EINVAL;
1691 }
1692
1693 addr = (u64)entry->src_data[0] << 12;
1694 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1695
1696 dev_dbg_ratelimited(adev->dev,
1697 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1698 instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1699 entry->pasid);
1700
1701 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1702 if (task_info) {
1703 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1704 task_info->process_name, task_info->tgid,
1705 task_info->task_name, task_info->pid);
1706 amdgpu_vm_put_task_info(task_info);
1707 }
1708
1709 return 0;
1710 }
1711
sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1712 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1713 struct amdgpu_irq_src *source,
1714 struct amdgpu_iv_entry *entry)
1715 {
1716 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1717 sdma_v4_4_2_print_iv_entry(adev, entry);
1718 return 0;
1719 }
1720
sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1721 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1722 struct amdgpu_irq_src *source,
1723 struct amdgpu_iv_entry *entry)
1724 {
1725
1726 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1727 sdma_v4_4_2_print_iv_entry(adev, entry);
1728 return 0;
1729 }
1730
sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1731 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1732 struct amdgpu_irq_src *source,
1733 struct amdgpu_iv_entry *entry)
1734 {
1735 dev_dbg_ratelimited(adev->dev,
1736 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1737 sdma_v4_4_2_print_iv_entry(adev, entry);
1738 return 0;
1739 }
1740
sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1741 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1742 struct amdgpu_irq_src *source,
1743 struct amdgpu_iv_entry *entry)
1744 {
1745 dev_dbg_ratelimited(adev->dev,
1746 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1747 sdma_v4_4_2_print_iv_entry(adev, entry);
1748 return 0;
1749 }
1750
sdma_v4_4_2_inst_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)1751 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1752 struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1753 {
1754 uint32_t data, def;
1755 int i;
1756
1757 /* leave as default if it is not driver controlled */
1758 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1759 return;
1760
1761 if (enable) {
1762 for_each_inst(i, inst_mask) {
1763 /* 1-not override: enable sdma mem light sleep */
1764 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1765 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1766 if (def != data)
1767 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1768 }
1769 } else {
1770 for_each_inst(i, inst_mask) {
1771 /* 0-override:disable sdma mem light sleep */
1772 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1773 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1774 if (def != data)
1775 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1776 }
1777 }
1778 }
1779
sdma_v4_4_2_inst_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)1780 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1781 struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1782 {
1783 uint32_t data, def;
1784 int i;
1785
1786 /* leave as default if it is not driver controlled */
1787 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1788 return;
1789
1790 if (enable) {
1791 for_each_inst(i, inst_mask) {
1792 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1793 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1794 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1795 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1796 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1797 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1798 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1799 if (def != data)
1800 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1801 }
1802 } else {
1803 for_each_inst(i, inst_mask) {
1804 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1805 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1806 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1807 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1808 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1809 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1810 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1811 if (def != data)
1812 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1813 }
1814 }
1815 }
1816
sdma_v4_4_2_set_clockgating_state(void * handle,enum amd_clockgating_state state)1817 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1818 enum amd_clockgating_state state)
1819 {
1820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1821 uint32_t inst_mask;
1822
1823 if (amdgpu_sriov_vf(adev))
1824 return 0;
1825
1826 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1827
1828 sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1829 adev, state == AMD_CG_STATE_GATE, inst_mask);
1830 sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1831 adev, state == AMD_CG_STATE_GATE, inst_mask);
1832 return 0;
1833 }
1834
sdma_v4_4_2_set_powergating_state(void * handle,enum amd_powergating_state state)1835 static int sdma_v4_4_2_set_powergating_state(void *handle,
1836 enum amd_powergating_state state)
1837 {
1838 return 0;
1839 }
1840
sdma_v4_4_2_get_clockgating_state(void * handle,u64 * flags)1841 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1842 {
1843 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1844 int data;
1845
1846 if (amdgpu_sriov_vf(adev))
1847 *flags = 0;
1848
1849 /* AMD_CG_SUPPORT_SDMA_MGCG */
1850 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1851 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1852 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1853
1854 /* AMD_CG_SUPPORT_SDMA_LS */
1855 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1856 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1857 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1858 }
1859
sdma_v4_4_2_print_ip_state(void * handle,struct drm_printer * p)1860 static void sdma_v4_4_2_print_ip_state(void *handle, struct drm_printer *p)
1861 {
1862 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1863 int i, j;
1864 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1865 uint32_t instance_offset;
1866
1867 if (!adev->sdma.ip_dump)
1868 return;
1869
1870 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1871 for (i = 0; i < adev->sdma.num_instances; i++) {
1872 instance_offset = i * reg_count;
1873 drm_printf(p, "\nInstance:%d\n", i);
1874
1875 for (j = 0; j < reg_count; j++)
1876 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name,
1877 adev->sdma.ip_dump[instance_offset + j]);
1878 }
1879 }
1880
sdma_v4_4_2_dump_ip_state(void * handle)1881 static void sdma_v4_4_2_dump_ip_state(void *handle)
1882 {
1883 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1884 int i, j;
1885 uint32_t instance_offset;
1886 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1887
1888 if (!adev->sdma.ip_dump)
1889 return;
1890
1891 amdgpu_gfx_off_ctrl(adev, false);
1892 for (i = 0; i < adev->sdma.num_instances; i++) {
1893 instance_offset = i * reg_count;
1894 for (j = 0; j < reg_count; j++)
1895 adev->sdma.ip_dump[instance_offset + j] =
1896 RREG32(sdma_v4_4_2_get_reg_offset(adev, i,
1897 sdma_reg_list_4_4_2[j].reg_offset));
1898 }
1899 amdgpu_gfx_off_ctrl(adev, true);
1900 }
1901
1902 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1903 .name = "sdma_v4_4_2",
1904 .early_init = sdma_v4_4_2_early_init,
1905 .late_init = sdma_v4_4_2_late_init,
1906 .sw_init = sdma_v4_4_2_sw_init,
1907 .sw_fini = sdma_v4_4_2_sw_fini,
1908 .hw_init = sdma_v4_4_2_hw_init,
1909 .hw_fini = sdma_v4_4_2_hw_fini,
1910 .suspend = sdma_v4_4_2_suspend,
1911 .resume = sdma_v4_4_2_resume,
1912 .is_idle = sdma_v4_4_2_is_idle,
1913 .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1914 .soft_reset = sdma_v4_4_2_soft_reset,
1915 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1916 .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1917 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1918 .dump_ip_state = sdma_v4_4_2_dump_ip_state,
1919 .print_ip_state = sdma_v4_4_2_print_ip_state,
1920 };
1921
1922 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1923 .type = AMDGPU_RING_TYPE_SDMA,
1924 .align_mask = 0xff,
1925 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1926 .support_64bit_ptrs = true,
1927 .get_rptr = sdma_v4_4_2_ring_get_rptr,
1928 .get_wptr = sdma_v4_4_2_ring_get_wptr,
1929 .set_wptr = sdma_v4_4_2_ring_set_wptr,
1930 .emit_frame_size =
1931 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1932 3 + /* hdp invalidate */
1933 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1934 /* sdma_v4_4_2_ring_emit_vm_flush */
1935 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1936 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1937 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1938 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1939 .emit_ib = sdma_v4_4_2_ring_emit_ib,
1940 .emit_fence = sdma_v4_4_2_ring_emit_fence,
1941 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1942 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1943 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1944 .test_ring = sdma_v4_4_2_ring_test_ring,
1945 .test_ib = sdma_v4_4_2_ring_test_ib,
1946 .insert_nop = sdma_v4_4_2_ring_insert_nop,
1947 .pad_ib = sdma_v4_4_2_ring_pad_ib,
1948 .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1949 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1950 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1951 };
1952
1953 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1954 .type = AMDGPU_RING_TYPE_SDMA,
1955 .align_mask = 0xff,
1956 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1957 .support_64bit_ptrs = true,
1958 .get_rptr = sdma_v4_4_2_ring_get_rptr,
1959 .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1960 .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1961 .emit_frame_size =
1962 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1963 3 + /* hdp invalidate */
1964 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1965 /* sdma_v4_4_2_ring_emit_vm_flush */
1966 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1967 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1968 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1969 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1970 .emit_ib = sdma_v4_4_2_ring_emit_ib,
1971 .emit_fence = sdma_v4_4_2_ring_emit_fence,
1972 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1973 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1974 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1975 .test_ring = sdma_v4_4_2_ring_test_ring,
1976 .test_ib = sdma_v4_4_2_ring_test_ib,
1977 .insert_nop = sdma_v4_4_2_ring_insert_nop,
1978 .pad_ib = sdma_v4_4_2_ring_pad_ib,
1979 .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1980 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1981 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1982 };
1983
sdma_v4_4_2_set_ring_funcs(struct amdgpu_device * adev)1984 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1985 {
1986 int i, dev_inst;
1987
1988 for (i = 0; i < adev->sdma.num_instances; i++) {
1989 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1990 adev->sdma.instance[i].ring.me = i;
1991 if (adev->sdma.has_page_queue) {
1992 adev->sdma.instance[i].page.funcs =
1993 &sdma_v4_4_2_page_ring_funcs;
1994 adev->sdma.instance[i].page.me = i;
1995 }
1996
1997 dev_inst = GET_INST(SDMA0, i);
1998 /* AID to which SDMA belongs depends on physical instance */
1999 adev->sdma.instance[i].aid_id =
2000 dev_inst / adev->sdma.num_inst_per_aid;
2001 }
2002 }
2003
2004 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
2005 .set = sdma_v4_4_2_set_trap_irq_state,
2006 .process = sdma_v4_4_2_process_trap_irq,
2007 };
2008
2009 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
2010 .process = sdma_v4_4_2_process_illegal_inst_irq,
2011 };
2012
2013 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
2014 .set = sdma_v4_4_2_set_ecc_irq_state,
2015 .process = amdgpu_sdma_process_ecc_irq,
2016 };
2017
2018 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
2019 .process = sdma_v4_4_2_process_vm_hole_irq,
2020 };
2021
2022 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
2023 .process = sdma_v4_4_2_process_doorbell_invalid_irq,
2024 };
2025
2026 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
2027 .process = sdma_v4_4_2_process_pool_timeout_irq,
2028 };
2029
2030 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
2031 .process = sdma_v4_4_2_process_srbm_write_irq,
2032 };
2033
sdma_v4_4_2_set_irq_funcs(struct amdgpu_device * adev)2034 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
2035 {
2036 adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2037 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2038 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2039 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2040 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2041 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2042
2043 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
2044 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
2045 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
2046 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
2047 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
2048 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
2049 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
2050 }
2051
2052 /**
2053 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
2054 *
2055 * @ib: indirect buffer to copy to
2056 * @src_offset: src GPU address
2057 * @dst_offset: dst GPU address
2058 * @byte_count: number of bytes to xfer
2059 * @copy_flags: copy flags for the buffers
2060 *
2061 * Copy GPU buffers using the DMA engine.
2062 * Used by the amdgpu ttm implementation to move pages if
2063 * registered as the asic copy callback.
2064 */
sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)2065 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
2066 uint64_t src_offset,
2067 uint64_t dst_offset,
2068 uint32_t byte_count,
2069 uint32_t copy_flags)
2070 {
2071 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2072 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2073 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
2074 ib->ptr[ib->length_dw++] = byte_count - 1;
2075 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2076 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2077 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2078 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2079 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2080 }
2081
2082 /**
2083 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
2084 *
2085 * @ib: indirect buffer to copy to
2086 * @src_data: value to write to buffer
2087 * @dst_offset: dst GPU address
2088 * @byte_count: number of bytes to xfer
2089 *
2090 * Fill GPU buffers using the DMA engine.
2091 */
sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)2092 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
2093 uint32_t src_data,
2094 uint64_t dst_offset,
2095 uint32_t byte_count)
2096 {
2097 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2098 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2099 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2100 ib->ptr[ib->length_dw++] = src_data;
2101 ib->ptr[ib->length_dw++] = byte_count - 1;
2102 }
2103
2104 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2105 .copy_max_bytes = 0x400000,
2106 .copy_num_dw = 7,
2107 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2108
2109 .fill_max_bytes = 0x400000,
2110 .fill_num_dw = 5,
2111 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2112 };
2113
sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device * adev)2114 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2115 {
2116 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2117 if (adev->sdma.has_page_queue)
2118 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2119 else
2120 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2121 }
2122
2123 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2124 .copy_pte_num_dw = 7,
2125 .copy_pte = sdma_v4_4_2_vm_copy_pte,
2126
2127 .write_pte = sdma_v4_4_2_vm_write_pte,
2128 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2129 };
2130
sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device * adev)2131 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2132 {
2133 struct drm_gpu_scheduler *sched;
2134 unsigned i;
2135
2136 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2137 for (i = 0; i < adev->sdma.num_instances; i++) {
2138 if (adev->sdma.has_page_queue)
2139 sched = &adev->sdma.instance[i].page.sched;
2140 else
2141 sched = &adev->sdma.instance[i].ring.sched;
2142 adev->vm_manager.vm_pte_scheds[i] = sched;
2143 }
2144 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2145 }
2146
2147 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2148 .type = AMD_IP_BLOCK_TYPE_SDMA,
2149 .major = 4,
2150 .minor = 4,
2151 .rev = 2,
2152 .funcs = &sdma_v4_4_2_ip_funcs,
2153 };
2154
sdma_v4_4_2_xcp_resume(void * handle,uint32_t inst_mask)2155 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2156 {
2157 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2158 int r;
2159
2160 if (!amdgpu_sriov_vf(adev))
2161 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2162
2163 r = sdma_v4_4_2_inst_start(adev, inst_mask);
2164
2165 return r;
2166 }
2167
sdma_v4_4_2_xcp_suspend(void * handle,uint32_t inst_mask)2168 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2169 {
2170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2171 uint32_t tmp_mask = inst_mask;
2172 int i;
2173
2174 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2175 for_each_inst(i, tmp_mask) {
2176 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2177 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2178 }
2179 }
2180
2181 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2182 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2183
2184 return 0;
2185 }
2186
2187 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2188 .suspend = &sdma_v4_4_2_xcp_suspend,
2189 .resume = &sdma_v4_4_2_xcp_resume
2190 };
2191
2192 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2193 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2194 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2195 };
2196
2197 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2198 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2199 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2200 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2201 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2202 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2203 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2204 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2205 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2206 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2207 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2208 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2209 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2210 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2211 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2212 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2213 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2214 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2215 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2216 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2217 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2218 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2219 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2220 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2221 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2222 };
2223
sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device * adev,uint32_t sdma_inst,void * ras_err_status)2224 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2225 uint32_t sdma_inst,
2226 void *ras_err_status)
2227 {
2228 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2229 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2230 unsigned long ue_count = 0;
2231 struct amdgpu_smuio_mcm_config_info mcm_info = {
2232 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2233 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2234 };
2235
2236 /* sdma v4_4_2 doesn't support query ce counts */
2237 amdgpu_ras_inst_query_ras_error_count(adev,
2238 sdma_v4_2_2_ue_reg_list,
2239 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2240 sdma_v4_4_2_ras_memory_list,
2241 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2242 sdma_dev_inst,
2243 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2244 &ue_count);
2245
2246 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
2247 }
2248
sdma_v4_4_2_query_ras_error_count(struct amdgpu_device * adev,void * ras_err_status)2249 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2250 void *ras_err_status)
2251 {
2252 uint32_t inst_mask;
2253 int i = 0;
2254
2255 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2256 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2257 for_each_inst(i, inst_mask)
2258 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2259 } else {
2260 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2261 }
2262 }
2263
sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device * adev,uint32_t sdma_inst)2264 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2265 uint32_t sdma_inst)
2266 {
2267 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2268
2269 amdgpu_ras_inst_reset_ras_error_count(adev,
2270 sdma_v4_2_2_ue_reg_list,
2271 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2272 sdma_dev_inst);
2273 }
2274
sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device * adev)2275 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2276 {
2277 uint32_t inst_mask;
2278 int i = 0;
2279
2280 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2281 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2282 for_each_inst(i, inst_mask)
2283 sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2284 } else {
2285 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2286 }
2287 }
2288
2289 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2290 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2291 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2292 };
2293
sdma_v4_4_2_aca_bank_parser(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)2294 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
2295 enum aca_smu_type type, void *data)
2296 {
2297 struct aca_bank_info info;
2298 u64 misc0;
2299 int ret;
2300
2301 ret = aca_bank_info_decode(bank, &info);
2302 if (ret)
2303 return ret;
2304
2305 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2306 switch (type) {
2307 case ACA_SMU_TYPE_UE:
2308 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
2309 1ULL);
2310 break;
2311 case ACA_SMU_TYPE_CE:
2312 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE,
2313 ACA_REG__MISC0__ERRCNT(misc0));
2314 break;
2315 default:
2316 return -EINVAL;
2317 }
2318
2319 return ret;
2320 }
2321
2322 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2323 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2324
sdma_v4_4_2_aca_bank_is_valid(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)2325 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2326 enum aca_smu_type type, void *data)
2327 {
2328 u32 instlo;
2329
2330 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2331 instlo &= GENMASK(31, 1);
2332
2333 if (instlo != mmSMNAID_AID0_MCA_SMU)
2334 return false;
2335
2336 if (aca_bank_check_error_codes(handle->adev, bank,
2337 sdma_v4_4_2_err_codes,
2338 ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2339 return false;
2340
2341 return true;
2342 }
2343
2344 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2345 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser,
2346 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2347 };
2348
2349 static const struct aca_info sdma_v4_4_2_aca_info = {
2350 .hwip = ACA_HWIP_TYPE_SMU,
2351 .mask = ACA_ERROR_UE_MASK,
2352 .bank_ops = &sdma_v4_4_2_aca_bank_ops,
2353 };
2354
sdma_v4_4_2_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)2355 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2356 {
2357 int r;
2358
2359 r = amdgpu_sdma_ras_late_init(adev, ras_block);
2360 if (r)
2361 return r;
2362
2363 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2364 &sdma_v4_4_2_aca_info, NULL);
2365 }
2366
2367 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2368 .ras_block = {
2369 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2370 .ras_late_init = sdma_v4_4_2_ras_late_init,
2371 },
2372 };
2373
sdma_v4_4_2_set_ras_funcs(struct amdgpu_device * adev)2374 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2375 {
2376 adev->sdma.ras = &sdma_v4_4_2_ras;
2377 }
2378