1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/of.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
16
17 #include "cqhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
20
21 /* CTL_CFG Registers */
22 #define CTL_CFG_2 0x14
23 #define CTL_CFG_3 0x18
24
25 #define SLOTTYPE_MASK GENMASK(31, 30)
26 #define SLOTTYPE_EMBEDDED BIT(30)
27 #define TUNINGFORSDR50_MASK BIT(13)
28
29 /* PHY Registers */
30 #define PHY_CTRL1 0x100
31 #define PHY_CTRL2 0x104
32 #define PHY_CTRL3 0x108
33 #define PHY_CTRL4 0x10C
34 #define PHY_CTRL5 0x110
35 #define PHY_CTRL6 0x114
36 #define PHY_STAT1 0x130
37 #define PHY_STAT2 0x134
38
39 #define IOMUX_ENABLE_SHIFT 31
40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41 #define OTAPDLYENA_SHIFT 20
42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43 #define OTAPDLYSEL_SHIFT 12
44 #define OTAPDLYSEL_MASK GENMASK(15, 12)
45 #define STRBSEL_SHIFT 24
46 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
47 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
48 #define SEL50_SHIFT 8
49 #define SEL50_MASK BIT(SEL50_SHIFT)
50 #define SEL100_SHIFT 9
51 #define SEL100_MASK BIT(SEL100_SHIFT)
52 #define FREQSEL_SHIFT 8
53 #define FREQSEL_MASK GENMASK(10, 8)
54 #define CLKBUFSEL_SHIFT 0
55 #define CLKBUFSEL_MASK GENMASK(2, 0)
56 #define DLL_TRIM_ICP_SHIFT 4
57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58 #define DR_TY_SHIFT 20
59 #define DR_TY_MASK GENMASK(22, 20)
60 #define ENDLL_SHIFT 1
61 #define ENDLL_MASK BIT(ENDLL_SHIFT)
62 #define DLLRDY_SHIFT 0
63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
64 #define PDB_SHIFT 0
65 #define PDB_MASK BIT(PDB_SHIFT)
66 #define CALDONE_SHIFT 1
67 #define CALDONE_MASK BIT(CALDONE_SHIFT)
68 #define RETRIM_SHIFT 17
69 #define RETRIM_MASK BIT(RETRIM_SHIFT)
70 #define SELDLYTXCLK_SHIFT 17
71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72 #define SELDLYRXCLK_SHIFT 16
73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74 #define ITAPDLYSEL_SHIFT 0
75 #define ITAPDLYSEL_MASK GENMASK(4, 0)
76 #define ITAPDLYENA_SHIFT 8
77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78 #define ITAPCHGWIN_SHIFT 9
79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
80
81 #define DRIVER_STRENGTH_50_OHM 0x0
82 #define DRIVER_STRENGTH_33_OHM 0x1
83 #define DRIVER_STRENGTH_66_OHM 0x2
84 #define DRIVER_STRENGTH_100_OHM 0x3
85 #define DRIVER_STRENGTH_40_OHM 0x4
86
87 #define CLOCK_TOO_SLOW_HZ 50000000
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
89 #define RETRY_TUNING_MAX 10
90
91 /* Command Queue Host Controller Interface Base address */
92 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
93
94 static const struct regmap_config sdhci_am654_regmap_config = {
95 .reg_bits = 32,
96 .val_bits = 32,
97 .reg_stride = 4,
98 .fast_io = true,
99 };
100
101 struct timing_data {
102 const char *otap_binding;
103 const char *itap_binding;
104 u32 capability;
105 };
106
107 static const struct timing_data td[] = {
108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
109 "ti,itap-del-sel-legacy",
110 0},
111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
112 "ti,itap-del-sel-mmc-hs",
113 MMC_CAP_MMC_HIGHSPEED},
114 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
115 "ti,itap-del-sel-sd-hs",
116 MMC_CAP_SD_HIGHSPEED},
117 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
118 "ti,itap-del-sel-sdr12",
119 MMC_CAP_UHS_SDR12},
120 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
121 "ti,itap-del-sel-sdr25",
122 MMC_CAP_UHS_SDR25},
123 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
124 NULL,
125 MMC_CAP_UHS_SDR50},
126 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
127 NULL,
128 MMC_CAP_UHS_SDR104},
129 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
130 NULL,
131 MMC_CAP_UHS_DDR50},
132 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
133 "ti,itap-del-sel-ddr52",
134 MMC_CAP_DDR},
135 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
136 NULL,
137 MMC_CAP2_HS200},
138 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
139 NULL,
140 MMC_CAP2_HS400},
141 };
142
143 struct sdhci_am654_data {
144 struct regmap *base;
145 u32 otap_del_sel[ARRAY_SIZE(td)];
146 u32 itap_del_sel[ARRAY_SIZE(td)];
147 u32 itap_del_ena[ARRAY_SIZE(td)];
148 int clkbuf_sel;
149 int trm_icp;
150 int drv_strength;
151 int strb_sel;
152 u32 flags;
153 u32 quirks;
154 bool dll_enable;
155 u32 tuning_loop;
156
157 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
158 #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1)
159 };
160
161 struct window {
162 u8 start;
163 u8 end;
164 u8 length;
165 };
166
167 struct sdhci_am654_driver_data {
168 const struct sdhci_pltfm_data *pdata;
169 u32 flags;
170 #define IOMUX_PRESENT (1 << 0)
171 #define FREQSEL_2_BIT (1 << 1)
172 #define STRBSEL_4_BIT (1 << 2)
173 #define DLL_PRESENT (1 << 3)
174 #define DLL_CALIB (1 << 4)
175 };
176
sdhci_am654_setup_dll(struct sdhci_host * host,unsigned int clock)177 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
178 {
179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
180 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
181 int sel50, sel100, freqsel;
182 u32 mask, val;
183 int ret;
184
185 /* Disable delay chain mode */
186 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
187 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
188
189 if (sdhci_am654->flags & FREQSEL_2_BIT) {
190 switch (clock) {
191 case 200000000:
192 sel50 = 0;
193 sel100 = 0;
194 break;
195 case 100000000:
196 sel50 = 0;
197 sel100 = 1;
198 break;
199 default:
200 sel50 = 1;
201 sel100 = 0;
202 }
203
204 /* Configure PHY DLL frequency */
205 mask = SEL50_MASK | SEL100_MASK;
206 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
208
209 } else {
210 switch (clock) {
211 case 200000000:
212 freqsel = 0x0;
213 break;
214 default:
215 freqsel = 0x4;
216 }
217
218 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
219 freqsel << FREQSEL_SHIFT);
220 }
221 /* Configure DLL TRIM */
222 mask = DLL_TRIM_ICP_MASK;
223 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
224
225 /* Configure DLL driver strength */
226 mask |= DR_TY_MASK;
227 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
229
230 /* Enable DLL */
231 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
232 0x1 << ENDLL_SHIFT);
233 /*
234 * Poll for DLL ready. Use a one second timeout.
235 * Works in all experiments done so far
236 */
237 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
238 val & DLLRDY_MASK, 1000, 1000000);
239 if (ret) {
240 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
241 return;
242 }
243 }
244
sdhci_am654_write_itapdly(struct sdhci_am654_data * sdhci_am654,u32 itapdly,u32 enable)245 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
246 u32 itapdly, u32 enable)
247 {
248 /* Set ITAPCHGWIN before writing to ITAPDLY */
249 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
250 1 << ITAPCHGWIN_SHIFT);
251 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
252 enable << ITAPDLYENA_SHIFT);
253 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
254 itapdly << ITAPDLYSEL_SHIFT);
255 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
256 }
257
sdhci_am654_setup_delay_chain(struct sdhci_am654_data * sdhci_am654,unsigned char timing)258 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
259 unsigned char timing)
260 {
261 u32 mask, val;
262
263 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
264
265 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
266 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
267 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
268
269 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
270 sdhci_am654->itap_del_ena[timing]);
271 }
272
sdhci_am654_set_clock(struct sdhci_host * host,unsigned int clock)273 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
274 {
275 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
276 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
277 unsigned char timing = host->mmc->ios.timing;
278 u32 otap_del_sel;
279 u32 mask, val;
280
281 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
282
283 sdhci_set_clock(host, clock);
284
285 /* Setup Output TAP delay */
286 otap_del_sel = sdhci_am654->otap_del_sel[timing];
287
288 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
289 val = (0x1 << OTAPDLYENA_SHIFT) |
290 (otap_del_sel << OTAPDLYSEL_SHIFT);
291
292 /* Write to STRBSEL for HS400 speed mode */
293 if (timing == MMC_TIMING_MMC_HS400) {
294 if (sdhci_am654->flags & STRBSEL_4_BIT)
295 mask |= STRBSEL_4BIT_MASK;
296 else
297 mask |= STRBSEL_8BIT_MASK;
298
299 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
300 }
301
302 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
303
304 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
305 sdhci_am654_setup_dll(host, clock);
306 sdhci_am654->dll_enable = true;
307
308 if (timing == MMC_TIMING_MMC_HS400) {
309 sdhci_am654->itap_del_ena[timing] = 0x1;
310 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
311 }
312
313 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
314 sdhci_am654->itap_del_ena[timing]);
315 } else {
316 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
317 sdhci_am654->dll_enable = false;
318 }
319
320 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
321 sdhci_am654->clkbuf_sel);
322 }
323
sdhci_j721e_4bit_set_clock(struct sdhci_host * host,unsigned int clock)324 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
325 unsigned int clock)
326 {
327 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
328 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
329 unsigned char timing = host->mmc->ios.timing;
330 u32 otap_del_sel;
331 u32 itap_del_ena;
332 u32 itap_del_sel;
333 u32 mask, val;
334
335 /* Setup Output TAP delay */
336 otap_del_sel = sdhci_am654->otap_del_sel[timing];
337
338 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
339 val = (0x1 << OTAPDLYENA_SHIFT) |
340 (otap_del_sel << OTAPDLYSEL_SHIFT);
341
342 /* Setup Input TAP delay */
343 itap_del_ena = sdhci_am654->itap_del_ena[timing];
344 itap_del_sel = sdhci_am654->itap_del_sel[timing];
345
346 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
347 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
348 (itap_del_sel << ITAPDLYSEL_SHIFT);
349
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
351 1 << ITAPCHGWIN_SHIFT);
352 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
353 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
354 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
355 sdhci_am654->clkbuf_sel);
356
357 sdhci_set_clock(host, clock);
358 }
359
sdhci_am654_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)360 static int sdhci_am654_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
361 {
362 struct sdhci_host *host = mmc_priv(mmc);
363 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
364 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
365 int ret;
366
367 if ((sdhci_am654->quirks & SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA) &&
368 ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
369 if (!IS_ERR(mmc->supply.vqmmc)) {
370 ret = mmc_regulator_set_vqmmc(mmc, ios);
371 if (ret < 0) {
372 pr_err("%s: Switching to 1.8V signalling voltage failed,\n",
373 mmc_hostname(mmc));
374 return -EIO;
375 }
376 }
377 return 0;
378 }
379
380 return sdhci_start_signal_voltage_switch(mmc, ios);
381 }
382
sdhci_am654_write_power_on(struct sdhci_host * host,u8 val,int reg)383 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
384 {
385 writeb(val, host->ioaddr + reg);
386 usleep_range(1000, 10000);
387 return readb(host->ioaddr + reg);
388 }
389
390 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
sdhci_am654_write_b(struct sdhci_host * host,u8 val,int reg)391 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
392 {
393 unsigned char timing = host->mmc->ios.timing;
394 u8 pwr;
395 int ret;
396
397 if (reg == SDHCI_HOST_CONTROL) {
398 switch (timing) {
399 /*
400 * According to the data manual, HISPD bit
401 * should not be set in these speed modes.
402 */
403 case MMC_TIMING_SD_HS:
404 case MMC_TIMING_MMC_HS:
405 val &= ~SDHCI_CTRL_HISPD;
406 }
407 }
408
409 writeb(val, host->ioaddr + reg);
410 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
411 /*
412 * Power on will not happen until the card detect debounce
413 * timer expires. Wait at least 1.5 seconds for the power on
414 * bit to be set
415 */
416 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
417 pwr & SDHCI_POWER_ON, 0,
418 MAX_POWER_ON_TIMEOUT, false, host, val,
419 reg);
420 if (ret)
421 dev_info(mmc_dev(host->mmc), "Power on failed\n");
422 }
423 }
424
sdhci_am654_reset(struct sdhci_host * host,u8 mask)425 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
426 {
427 u8 ctrl;
428 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
429 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
430
431 sdhci_and_cqhci_reset(host, mask);
432
433 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
434 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
435 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
436 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
437 }
438 }
439
sdhci_am654_execute_tuning(struct mmc_host * mmc,u32 opcode)440 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
441 {
442 struct sdhci_host *host = mmc_priv(mmc);
443 int err = sdhci_execute_tuning(mmc, opcode);
444
445 if (err)
446 return err;
447 /*
448 * Tuning data remains in the buffer after tuning.
449 * Do a command and data reset to get rid of it
450 */
451 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
452
453 return 0;
454 }
455
sdhci_am654_cqhci_irq(struct sdhci_host * host,u32 intmask)456 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
457 {
458 int cmd_error = 0;
459 int data_error = 0;
460
461 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
462 return intmask;
463
464 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
465
466 return 0;
467 }
468
469 #define ITAPDLY_LENGTH 32
470 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
471
sdhci_am654_calculate_itap(struct sdhci_host * host,struct window * fail_window,u8 num_fails,bool circular_buffer)472 static int sdhci_am654_calculate_itap(struct sdhci_host *host, struct window
473 *fail_window, u8 num_fails, bool circular_buffer)
474 {
475 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
476 u8 first_fail_start = 0, last_fail_end = 0;
477 struct device *dev = mmc_dev(host->mmc);
478 struct window pass_window = {0, 0, 0};
479 int prev_fail_end = -1;
480 u8 i;
481
482 if (!num_fails) {
483 /* Retry tuning */
484 dev_dbg(dev, "No failing region found, retry tuning\n");
485 return -1;
486 }
487
488 if (fail_window->length == ITAPDLY_LENGTH) {
489 /* Retry tuning */
490 dev_dbg(dev, "No passing itapdly, retry tuning\n");
491 return -1;
492 }
493
494 first_fail_start = fail_window->start;
495 last_fail_end = fail_window[num_fails - 1].end;
496
497 for (i = 0; i < num_fails; i++) {
498 start_fail = fail_window[i].start;
499 end_fail = fail_window[i].end;
500 pass_length = start_fail - (prev_fail_end + 1);
501
502 if (pass_length > pass_window.length) {
503 pass_window.start = prev_fail_end + 1;
504 pass_window.length = pass_length;
505 }
506 prev_fail_end = end_fail;
507 }
508
509 if (!circular_buffer)
510 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
511 else
512 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
513
514 if (pass_length > pass_window.length) {
515 pass_window.start = last_fail_end + 1;
516 pass_window.length = pass_length;
517 }
518
519 if (!circular_buffer)
520 itap = pass_window.start + (pass_window.length >> 1);
521 else
522 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
523
524 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
525 }
526
sdhci_am654_do_tuning(struct sdhci_host * host,u32 opcode)527 static int sdhci_am654_do_tuning(struct sdhci_host *host,
528 u32 opcode)
529 {
530 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
531 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
532 unsigned char timing = host->mmc->ios.timing;
533 struct window fail_window[ITAPDLY_LENGTH];
534 struct device *dev = mmc_dev(host->mmc);
535 u8 curr_pass, itap;
536 u8 fail_index = 0;
537 u8 prev_pass = 1;
538
539 memset(fail_window, 0, sizeof(fail_window));
540
541 /* Enable ITAPDLY */
542 sdhci_am654->itap_del_ena[timing] = 0x1;
543
544 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
545 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
546
547 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL);
548
549 if (!curr_pass && prev_pass)
550 fail_window[fail_index].start = itap;
551
552 if (!curr_pass) {
553 fail_window[fail_index].end = itap;
554 fail_window[fail_index].length++;
555 dev_dbg(dev, "Failed itapdly=%d\n", itap);
556 }
557
558 if (curr_pass && !prev_pass)
559 fail_index++;
560
561 prev_pass = curr_pass;
562 }
563
564 if (fail_window[fail_index].length != 0)
565 fail_index++;
566
567 return sdhci_am654_calculate_itap(host, fail_window, fail_index,
568 sdhci_am654->dll_enable);
569 }
570
sdhci_am654_platform_execute_tuning(struct sdhci_host * host,u32 opcode)571 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
572 u32 opcode)
573 {
574 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
575 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
576 unsigned char timing = host->mmc->ios.timing;
577 struct device *dev = mmc_dev(host->mmc);
578 int itapdly;
579
580 do {
581 itapdly = sdhci_am654_do_tuning(host, opcode);
582 if (itapdly >= 0)
583 break;
584 } while (++sdhci_am654->tuning_loop < RETRY_TUNING_MAX);
585
586 if (itapdly < 0) {
587 dev_err(dev, "Failed to find itapdly, fail tuning\n");
588 return -1;
589 }
590
591 dev_dbg(dev, "Passed tuning, final itapdly=%d\n", itapdly);
592 sdhci_am654_write_itapdly(sdhci_am654, itapdly, sdhci_am654->itap_del_ena[timing]);
593 /* Save ITAPDLY */
594 sdhci_am654->itap_del_sel[timing] = itapdly;
595
596 return 0;
597 }
598
599 static const struct sdhci_ops sdhci_am654_ops = {
600 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
601 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
602 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
603 .set_uhs_signaling = sdhci_set_uhs_signaling,
604 .set_bus_width = sdhci_set_bus_width,
605 .set_power = sdhci_set_power_and_bus_voltage,
606 .set_clock = sdhci_am654_set_clock,
607 .write_b = sdhci_am654_write_b,
608 .irq = sdhci_am654_cqhci_irq,
609 .reset = sdhci_and_cqhci_reset,
610 };
611
612 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
613 .ops = &sdhci_am654_ops,
614 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
615 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
616 };
617
618 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
619 .pdata = &sdhci_am654_pdata,
620 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
621 DLL_CALIB,
622 };
623
624 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
625 .pdata = &sdhci_am654_pdata,
626 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
627 };
628
629 static const struct sdhci_ops sdhci_j721e_8bit_ops = {
630 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
631 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
632 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
633 .set_uhs_signaling = sdhci_set_uhs_signaling,
634 .set_bus_width = sdhci_set_bus_width,
635 .set_power = sdhci_set_power_and_bus_voltage,
636 .set_clock = sdhci_am654_set_clock,
637 .write_b = sdhci_am654_write_b,
638 .irq = sdhci_am654_cqhci_irq,
639 .reset = sdhci_and_cqhci_reset,
640 };
641
642 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
643 .ops = &sdhci_j721e_8bit_ops,
644 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
645 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
646 };
647
648 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
649 .pdata = &sdhci_j721e_8bit_pdata,
650 .flags = DLL_PRESENT | DLL_CALIB,
651 };
652
653 static const struct sdhci_ops sdhci_j721e_4bit_ops = {
654 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
655 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
656 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
657 .set_uhs_signaling = sdhci_set_uhs_signaling,
658 .set_bus_width = sdhci_set_bus_width,
659 .set_power = sdhci_set_power_and_bus_voltage,
660 .set_clock = sdhci_j721e_4bit_set_clock,
661 .write_b = sdhci_am654_write_b,
662 .irq = sdhci_am654_cqhci_irq,
663 .reset = sdhci_am654_reset,
664 };
665
666 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
667 .ops = &sdhci_j721e_4bit_ops,
668 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
669 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
670 };
671
672 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
673 .pdata = &sdhci_j721e_4bit_pdata,
674 .flags = IOMUX_PRESENT,
675 };
676
677 static const struct soc_device_attribute sdhci_am654_devices[] = {
678 { .family = "AM65X",
679 .revision = "SR1.0",
680 .data = &sdhci_am654_sr1_drvdata
681 },
682 {/* sentinel */}
683 };
684
sdhci_am654_dumpregs(struct mmc_host * mmc)685 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
686 {
687 sdhci_dumpregs(mmc_priv(mmc));
688 }
689
690 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
691 .enable = sdhci_cqe_enable,
692 .disable = sdhci_cqe_disable,
693 .dumpregs = sdhci_am654_dumpregs,
694 };
695
sdhci_am654_cqe_add_host(struct sdhci_host * host)696 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
697 {
698 struct cqhci_host *cq_host;
699
700 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
701 GFP_KERNEL);
702 if (!cq_host)
703 return -ENOMEM;
704
705 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
706 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
707 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
708 cq_host->ops = &sdhci_am654_cqhci_ops;
709
710 host->mmc->caps2 |= MMC_CAP2_CQE;
711
712 return cqhci_init(cq_host, host->mmc, 1);
713 }
714
sdhci_am654_get_otap_delay(struct sdhci_host * host,struct sdhci_am654_data * sdhci_am654)715 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
716 struct sdhci_am654_data *sdhci_am654)
717 {
718 struct device *dev = mmc_dev(host->mmc);
719 int i;
720 int ret;
721
722 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
723
724 ret = device_property_read_u32(dev, td[i].otap_binding,
725 &sdhci_am654->otap_del_sel[i]);
726 if (ret) {
727 if (i == MMC_TIMING_LEGACY) {
728 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
729 return ret;
730 }
731 dev_dbg(dev, "Couldn't find %s\n",
732 td[i].otap_binding);
733 /*
734 * Remove the corresponding capability
735 * if an otap-del-sel value is not found
736 */
737 if (i <= MMC_TIMING_MMC_DDR52)
738 host->mmc->caps &= ~td[i].capability;
739 else
740 host->mmc->caps2 &= ~td[i].capability;
741 }
742
743 if (td[i].itap_binding) {
744 ret = device_property_read_u32(dev, td[i].itap_binding,
745 &sdhci_am654->itap_del_sel[i]);
746 if (!ret)
747 sdhci_am654->itap_del_ena[i] = 0x1;
748 }
749 }
750
751 return 0;
752 }
753
sdhci_am654_init(struct sdhci_host * host)754 static int sdhci_am654_init(struct sdhci_host *host)
755 {
756 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
757 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
758 u32 ctl_cfg_2 = 0;
759 u32 mask;
760 u32 val;
761 int ret;
762
763 /* Reset OTAP to default value */
764 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
765 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
766
767 if (sdhci_am654->flags & DLL_CALIB) {
768 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
769 if (~val & CALDONE_MASK) {
770 /* Calibrate IO lines */
771 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
772 PDB_MASK, PDB_MASK);
773 ret = regmap_read_poll_timeout(sdhci_am654->base,
774 PHY_STAT1, val,
775 val & CALDONE_MASK,
776 1, 20);
777 if (ret)
778 return ret;
779 }
780 }
781
782 /* Enable pins by setting IO mux to 0 */
783 if (sdhci_am654->flags & IOMUX_PRESENT)
784 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
785 IOMUX_ENABLE_MASK, 0);
786
787 /* Set slot type based on SD or eMMC */
788 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
789 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
790
791 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
792 ctl_cfg_2);
793
794 /* Enable tuning for SDR50 */
795 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
796 TUNINGFORSDR50_MASK);
797
798 /* Use to re-execute tuning */
799 sdhci_am654->tuning_loop = 0;
800
801 ret = sdhci_setup_host(host);
802 if (ret)
803 return ret;
804
805 ret = sdhci_am654_cqe_add_host(host);
806 if (ret)
807 goto err_cleanup_host;
808
809 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
810 if (ret)
811 goto err_cleanup_host;
812
813 ret = __sdhci_add_host(host);
814 if (ret)
815 goto err_cleanup_host;
816
817 return 0;
818
819 err_cleanup_host:
820 sdhci_cleanup_host(host);
821 return ret;
822 }
823
sdhci_am654_get_of_property(struct platform_device * pdev,struct sdhci_am654_data * sdhci_am654)824 static int sdhci_am654_get_of_property(struct platform_device *pdev,
825 struct sdhci_am654_data *sdhci_am654)
826 {
827 struct device *dev = &pdev->dev;
828 int drv_strength;
829 int ret;
830
831 if (sdhci_am654->flags & DLL_PRESENT) {
832 ret = device_property_read_u32(dev, "ti,trm-icp",
833 &sdhci_am654->trm_icp);
834 if (ret)
835 return ret;
836
837 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
838 &drv_strength);
839 if (ret)
840 return ret;
841
842 switch (drv_strength) {
843 case 50:
844 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
845 break;
846 case 33:
847 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
848 break;
849 case 66:
850 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
851 break;
852 case 100:
853 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
854 break;
855 case 40:
856 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
857 break;
858 default:
859 dev_err(dev, "Invalid driver strength\n");
860 return -EINVAL;
861 }
862 }
863
864 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
865 device_property_read_u32(dev, "ti,clkbuf-sel",
866 &sdhci_am654->clkbuf_sel);
867
868 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
869 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
870
871 /* Suppress v1p8 ena for eMMC and SD with vqmmc supply */
872 if (!!of_parse_phandle(dev->of_node, "vmmc-supply", 0) ==
873 !!of_parse_phandle(dev->of_node, "vqmmc-supply", 0))
874 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA;
875
876 sdhci_get_of_property(pdev);
877
878 return 0;
879 }
880
881 static const struct of_device_id sdhci_am654_of_match[] = {
882 {
883 .compatible = "ti,am654-sdhci-5.1",
884 .data = &sdhci_am654_drvdata,
885 },
886 {
887 .compatible = "ti,j721e-sdhci-8bit",
888 .data = &sdhci_j721e_8bit_drvdata,
889 },
890 {
891 .compatible = "ti,j721e-sdhci-4bit",
892 .data = &sdhci_j721e_4bit_drvdata,
893 },
894 {
895 .compatible = "ti,am64-sdhci-8bit",
896 .data = &sdhci_j721e_8bit_drvdata,
897 },
898 {
899 .compatible = "ti,am64-sdhci-4bit",
900 .data = &sdhci_j721e_4bit_drvdata,
901 },
902 {
903 .compatible = "ti,am62-sdhci",
904 .data = &sdhci_j721e_4bit_drvdata,
905 },
906 { /* sentinel */ }
907 };
908 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
909
sdhci_am654_probe(struct platform_device * pdev)910 static int sdhci_am654_probe(struct platform_device *pdev)
911 {
912 const struct sdhci_am654_driver_data *drvdata;
913 const struct soc_device_attribute *soc;
914 struct sdhci_pltfm_host *pltfm_host;
915 struct sdhci_am654_data *sdhci_am654;
916 const struct of_device_id *match;
917 struct sdhci_host *host;
918 struct clk *clk_xin;
919 struct device *dev = &pdev->dev;
920 void __iomem *base;
921 int ret;
922
923 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
924 drvdata = match->data;
925
926 /* Update drvdata based on SoC revision */
927 soc = soc_device_match(sdhci_am654_devices);
928 if (soc && soc->data)
929 drvdata = soc->data;
930
931 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
932 if (IS_ERR(host))
933 return PTR_ERR(host);
934
935 pltfm_host = sdhci_priv(host);
936 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
937 sdhci_am654->flags = drvdata->flags;
938
939 clk_xin = devm_clk_get(dev, "clk_xin");
940 if (IS_ERR(clk_xin)) {
941 dev_err(dev, "clk_xin clock not found.\n");
942 ret = PTR_ERR(clk_xin);
943 goto err_pltfm_free;
944 }
945
946 pltfm_host->clk = clk_xin;
947
948 base = devm_platform_ioremap_resource(pdev, 1);
949 if (IS_ERR(base)) {
950 ret = PTR_ERR(base);
951 goto err_pltfm_free;
952 }
953
954 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
955 &sdhci_am654_regmap_config);
956 if (IS_ERR(sdhci_am654->base)) {
957 dev_err(dev, "Failed to initialize regmap\n");
958 ret = PTR_ERR(sdhci_am654->base);
959 goto err_pltfm_free;
960 }
961
962 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
963 if (ret)
964 goto err_pltfm_free;
965
966 ret = mmc_of_parse(host->mmc);
967 if (ret) {
968 dev_err_probe(dev, ret, "parsing dt failed\n");
969 goto err_pltfm_free;
970 }
971
972 host->mmc_host_ops.start_signal_voltage_switch = sdhci_am654_start_signal_voltage_switch;
973 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
974
975 pm_runtime_get_noresume(dev);
976 ret = pm_runtime_set_active(dev);
977 if (ret)
978 goto pm_put;
979 pm_runtime_enable(dev);
980 ret = clk_prepare_enable(pltfm_host->clk);
981 if (ret)
982 goto pm_disable;
983
984 ret = sdhci_am654_init(host);
985 if (ret)
986 goto clk_disable;
987
988 /* Setting up autosuspend */
989 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
990 pm_runtime_use_autosuspend(dev);
991 pm_runtime_mark_last_busy(dev);
992 pm_runtime_put_autosuspend(dev);
993 return 0;
994
995 clk_disable:
996 clk_disable_unprepare(pltfm_host->clk);
997 pm_disable:
998 pm_runtime_disable(dev);
999 pm_put:
1000 pm_runtime_put_noidle(dev);
1001 err_pltfm_free:
1002 sdhci_pltfm_free(pdev);
1003 return ret;
1004 }
1005
sdhci_am654_remove(struct platform_device * pdev)1006 static void sdhci_am654_remove(struct platform_device *pdev)
1007 {
1008 struct sdhci_host *host = platform_get_drvdata(pdev);
1009 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1010 struct device *dev = &pdev->dev;
1011 int ret;
1012
1013 ret = pm_runtime_get_sync(dev);
1014 if (ret < 0)
1015 dev_err(dev, "pm_runtime_get_sync() Failed\n");
1016
1017 sdhci_remove_host(host, true);
1018 clk_disable_unprepare(pltfm_host->clk);
1019 pm_runtime_disable(dev);
1020 pm_runtime_put_noidle(dev);
1021 sdhci_pltfm_free(pdev);
1022 }
1023
1024 #ifdef CONFIG_PM
sdhci_am654_restore(struct sdhci_host * host)1025 static int sdhci_am654_restore(struct sdhci_host *host)
1026 {
1027 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1028 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
1029 u32 ctl_cfg_2 = 0;
1030 u32 val;
1031 int ret;
1032
1033 if (sdhci_am654->flags & DLL_CALIB) {
1034 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
1035 if (~val & CALDONE_MASK) {
1036 /* Calibrate IO lines */
1037 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1038 PDB_MASK, PDB_MASK);
1039 ret = regmap_read_poll_timeout(sdhci_am654->base,
1040 PHY_STAT1, val,
1041 val & CALDONE_MASK,
1042 1, 20);
1043 if (ret)
1044 return ret;
1045 }
1046 }
1047
1048 /* Enable pins by setting IO mux to 0 */
1049 if (sdhci_am654->flags & IOMUX_PRESENT)
1050 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
1051 IOMUX_ENABLE_MASK, 0);
1052
1053 /* Set slot type based on SD or eMMC */
1054 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1055 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
1056
1057 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
1058 ctl_cfg_2);
1059
1060 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
1061 if (~val & TUNINGFORSDR50_MASK)
1062 /* Enable tuning for SDR50 */
1063 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
1064 TUNINGFORSDR50_MASK);
1065
1066 return 0;
1067 }
1068
sdhci_am654_runtime_suspend(struct device * dev)1069 static int sdhci_am654_runtime_suspend(struct device *dev)
1070 {
1071 struct sdhci_host *host = dev_get_drvdata(dev);
1072 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1073 int ret;
1074
1075 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1076 mmc_retune_needed(host->mmc);
1077
1078 ret = cqhci_suspend(host->mmc);
1079 if (ret)
1080 return ret;
1081
1082 ret = sdhci_runtime_suspend_host(host);
1083 if (ret)
1084 return ret;
1085
1086 /* disable the clock */
1087 clk_disable_unprepare(pltfm_host->clk);
1088 return 0;
1089 }
1090
sdhci_am654_runtime_resume(struct device * dev)1091 static int sdhci_am654_runtime_resume(struct device *dev)
1092 {
1093 struct sdhci_host *host = dev_get_drvdata(dev);
1094 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1095 int ret;
1096
1097 /* Enable the clock */
1098 ret = clk_prepare_enable(pltfm_host->clk);
1099 if (ret)
1100 return ret;
1101
1102 ret = sdhci_am654_restore(host);
1103 if (ret)
1104 return ret;
1105
1106 ret = sdhci_runtime_resume_host(host, 0);
1107 if (ret)
1108 return ret;
1109
1110 ret = cqhci_resume(host->mmc);
1111 if (ret)
1112 return ret;
1113
1114 return 0;
1115 }
1116 #endif
1117
1118 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
1119 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend,
1120 sdhci_am654_runtime_resume, NULL)
1121 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1122 pm_runtime_force_resume)
1123 };
1124
1125 static struct platform_driver sdhci_am654_driver = {
1126 .driver = {
1127 .name = "sdhci-am654",
1128 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1129 .pm = &sdhci_am654_dev_pm_ops,
1130 .of_match_table = sdhci_am654_of_match,
1131 },
1132 .probe = sdhci_am654_probe,
1133 .remove = sdhci_am654_remove,
1134 };
1135
1136 module_platform_driver(sdhci_am654_driver);
1137
1138 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
1139 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
1140 MODULE_LICENSE("GPL");
1141